( DOC No.

HX8861-H11-DS )

HX8861-H11
TFT LCD Timing controller
with LVDS input and
mini-LVDS output
Version 03 May, 2014
 HX8861-H11
TFT LCD Timing controller
with LVDS input and mini-LVDS output

Version 03 May, 2014

1. General Description
The HX8861-H11 is a timing controller embedded with a single pixel LVDS receiver
and a 3-pair mini-LVDS transmitter for TFT LCD panel. The mini-LVDS is a low EMI
and low voltage swing interface that transmits data between the timing controller and
source drivers. The HX8861-H11 supports WXGA (1366X768) and other resolutions
with EEPROM.

2. Features
 Input frequency range from 25MHz to 110MHz
 mini-LVDS frequency range from 50MHz to 300MHz
 Support WXGA (1366X768) and other resolutions with EEPROM
 Built-in single pixel LVDS receiver
 Built-in mini-LVDS transmitter for low power consumption and low EMI
 Built-in single port 6-bit mini-LVDS 3-pair differential bus interface output
 Support both 6/8 bit inputs. 8-bit input and 6-bit output with FRC mode (16.7M colors)
 Embedded with aging generator for simplifying TFT LCD panel dynamic burn-in test
 Support DE mode only
 Support serial bus programming
 Support dual-gate panel structure
 Support gamma correction function
 Support POL 1, 1+2n, 2n, 2+2n (n=1 ~ 8) line, column inversion by ROM code setting
 Support LVDS input port mirror function by ROM code setting
 Support LVDS VESA/JEIDA format by ROM code setting
 Support mini-LVDS output skew control with EEPROM
 Support CE (hue/saturation, brightness/contrast, sharpness adjustment) function
 Support CABC (Content Adaptive Brightness Control) function
 Support SDRRS (Seamless Dynamic Refresh Rate Switching) function
 Support 5V tolerance input pads: CABC_EN, COLOR_EN, AGMODE, PWMI
 Supply voltage: VDD=2.5V/3.3V (2.3V~3.6V)
 46-pin QFN package with E-PAD
 HX8861-H11DDKG: support ≧ 32K bit EEPROM only
 HX8861-H11DDKG-E: support 2K to 16K bit EEPROM only

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

3. Block Diagram

LV0P/N

Aging Generator
LVDS Receiver

Data Re-order
LV1P/N ML0P/N

Transmitter
mini-LVDS
Image Data
Processing
ML1P/N
LV2P/N

ML2P/N
LV3P/N

MLCLKP/N
LVCLKP/N

To All Blocks
To All Blocks To All Blocks

POL, TP1
System
SCLK Serial ROM Pin/Register Control & STV, CPV, OE1, OE2
Bus/ROM Download Setting Gate/Source
SDAT
Control Registers Processing Control
ROM

Miscellaneous Control

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 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

4. Pin Assignment

VDDM
PWMI
SDAT
SCLK
TEST

VDD
CPV
N.C.

OE2
OE1

POL
VSS

STV

TP1
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDA 1 32 ML2P

LV0N 2 31 ML2N
LV0P 3 30 ML1P
LV1N 4 29 ML1N
LV1P 5 28 ML0P
LV2N 6 27 ML0N

LV2P 7 26 MLCLKP
LVCLKN 8 25 MLCLKN
LVCLKP 9 24 VSSM
10
11
12
13
14
15
16
17
18
19
20
21
22
23
/HWRSTZ
LV3N

N.C.

CABC_EN

COLOR_EN

PI
N.C.
N.C.
LV3P
VSSA

VSS
PWMO

AGMODE
VDD

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

5. Pin Description
Pin name Pin no. I/O Description
LVDS input signals
LV0P/N 3,2
LV1P/N 5,4
In LVDS differential data pairs.
LV2P/N 7,6
LV3P/N 11,10
LVCLKP/N 9,8 In LVDS differential clock pairs.
mini-LVDS output signals
ML0P/N 28,27
ML1P/N 30,29 Out mini-LVDS outputs to source drivers.
ML2P/N 32,31
MLCLKP/N 26,25 Out mini-LVDS clock outputs to source drivers.
PI 21 In External resistor input for mini-LVDS output swing control.
Gate/Source driver control signals-for normal or dual-gate mode
15,22
N.C. Out No connection pin. It should be floating.
23,46
TP1 35 Out Data latch output to source driver.
POL 36 Out Polarity inversion output to source driver.
STV 37 Out Start pulse to gate driver.
CPV 38 Out Gate driver clock.
OE1 39 Out Output enable signal to gate driver.
OE2 40 Out Gate pulse modulation signal.
Miscellaneous control signals
PWMO 13 Out Backlight control output.
CABC function selection, default CABC_EN=L.
CABC_EN(1) 17 In CABC_EN=H: Enable CABC function.
CABC_EN=L: Disable CABC function.
/HWRSTZ 18 In Reset input (low active).
Color engine function selection, default COLOR_EN=L.
COLOR_EN(1) 19 In COLOR_EN=H: Enable color engine function.
COLOR_EN=L: Disable color engine function.
Aging pattern selection, default AGMODE=L.
AGMODE(1) 20 In AGMODE=H and no clock in: BIST pattern.
AGMODE=L and no clock in: Black pattern.
Test mode selection, default TEST=L.
TEST 41 In TEST=H: Test mode.
TEST=L: Normal operation.
SCLK 42 In/Out Control register input clock (using EEPROM).
SDAT 43 In/Out Control register input data (using EEPROM).
PWMI(1) 44 In Backlight control input.
Power supply
VDD 16,34 In Digital power supply.
VDDA 1 In Power supply for analog.
VDDM 33 In mini-LVDS power supply.
VSS 14,45 In Grounding for VDD.
VSSA 12 In Grounding for VDDA.
VSSM 24 In Grounding for VDDM.
Exposed pad is connected to VSS internally, the soldering coverage
E-Pad - -
rate should be over 75%.
Note: (1) 5V tolerance input pads.

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 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

6. Function Description
6.1 LVDS receiver

The HX8861-H11 has a built-in single pixel LVDS receiver that converts data from
differential serialized format to parallel output.

Ideal strobe position for LVDS input

T
LVCLKP
LVCLKN

LV0P
R[1] R[0] G[0] R[5] R[4] R[3] R[2]
LV0N
0.5T/7
1.5T/7
2.5T/7
3.5T/7
4.5T/7
5.5T/7
6.5T/7
Figure 6.1: LVDS input data ideal strobe position

LVDS input data mapping

Figure 6.2: LVDS input data mapping (VESA format)

Figure 6.3: LVDS input data mapping (JEIDA format)

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
6.2 Aging function

The HX8861-H11 is embedded with an aging generator for simplifying TFT LCD
model dynamic burn-in test. When AGMODE pin is pulled to VDD and no clock is
detected, the HX8861-H11 will operate at aging mode and generate BIST (Built-In Self
Test) patterns as Figure 6.4. When AGMODE pin is low or open, and no clock is
detected, the HX8861-H11 will generate black pattern.

Figure 6.4: BIST patterns

Figure 6.5: Free run timing

Spec.
Symbol Parameter Unit
Min. Typ. Max.
tF Detection time 50 - 100 ms

6.3 Serial bus configuration

The HX8861-H11 can easily adjust parameter by serial bus including source/gate
control timing, output data mapping, etc.
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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
6.4 CABC function

The CABC function generates a PWM signal to control backlight modulation. The
duty ratio of PWM is generated by image histogram and works with gamma
correction. PWMO frequency will follow PWMI frequency when PWMI is a modulation
signal. PWMO frequency can generate specific frequency (refer to below table) by
internal setting if the PWMI is DC level.
Spec.
Symbol Parameter Condition Unit
Min. Typ. Max.
CABC
FI Backlight control input Frequency 100 - 30K Hz
Enable/Disable
CABC
DI Backlight control input Duty 1 - 100 %
Enable/Disable
(1)
30K
CABC Disable 100 - Hz
STV*2n(2)
FO Backlight control output Frequency STV*2n(2)
CABC Enable 100 - 100K(3) Hz
30K(4)
DO Backlight control output Duty CABC Disable 1 - 100 %
Note: (1) PWMO frequency will follow PWMI
(2) PWMO is the multiple of STV frequency (n=0~10, n is integer) and independent of PWMI.
(3) When PWMI frequency is always DC level.
(4) When PWMI frequency is not DC level and PWMO frequency will follow PWMI.

6.5 Color engine function

The HX8861-H11 with color engine IP can support hue/saturation, brightness/

contrast, sharpness adjustment function.

6.6 Gate/source control timing

The HX8861-H11 generates control signals for source and gate drivers according to
the settings in EEPROM. Examples of timing specifications are shown as below.

Description Symbol WXGA Unit

Reset pulse leading to TP1 td1 2064 mini-LVDS Clock
High duration of TP1 tw1 99 mini-LVDS Clock
Reset pulse leading to POL (1+2 line) td2 900 mini-LVDS Clock
High/Low duration of POL (1+2 line) tw2 2 Line
Reset pulse leading to CPV rising td3 2064 mini-LVDS Clock
High duration of CPV tw3 1167 mini-LVDS Clock
Reset pulse leading to STV rising td4 900 mini-LVDS Clock
High duration of STV tw4 1 Line
Reset pulse leading to OE1/OE2 rising td5 1728/1389 mini-LVDS Clock
High duration of OE1/OE2 tw5 450/429 mini-LVDS Clock
Note: (1) The timing can be customized by different panel characteristics through ROM code.

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

MLCLKP/N

Internal DE

mini-LVDS data

TP1

POL (1+2Line)

CPV

STV

OE1/2

MLCLKP/N

Internal DE

mini-LVDS data
Reset Pulse
ML0P/N
~

ML2P/N
td1
TP1
tw1

td2
POL(1+ 2 line) tw2
td3

CPV
tw3

td4
STV tw4
td5

OE1/2 tw5

Figure 6.6: Control signal output timing characteristic

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
6.7 POL inversion

Figure 6.7: POL 1+2 line frame inversion

6.8 Input signal timing

Parameter Symbol Condition WXGA Unit

Min. 1420 Clock
Horizontal total timing HT Typ. 1526 Clock
Max. 2047 Clock
Horizontal active timing HVD Typ. 1366 Clock
Min. 771 Line
Vertical total timing VT Typ. 790 Line
Max. 2047 Line
Vertical active timing VVD Typ. 768 Line

Figure 6.8: Input video signal format

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
6.9 Seamless Dynamic Refresh Rate Switching (SDRRS)

Seamless Dynamic Refresh Rate Switching (SDRRS) is a power saving technology that
lowers the pixel clock frequency and frame rate to TFT LCD in response to power
policy, and display activity. The HX8861-H11 will detect the loss of signals and drive
the panel into a safe refresh mode. As a result of the actions of the HX8861-H11, the
switch between refresh rates will not cause a noticeable impact on display quality.

SDRRS response time

T2

LVDS Clock Clock refresh rate 1 LVDS clock differential pair Clock refresh rate 2
held at logical 0 value

LVDS Data Data at clock rate 1 LVDS data differential pairs Data at clock rate 2
held at logical 0 value

Blanking Blanking
DE Last active T1 T4 First active
line line
T3

mini-LVDS Clock Clock refresh rate 1 Clock refresh rate 2

mini-LVDS Data Data at clock rate 1 Invalid data Data at clock rate 2

Figure 6.9: TCON receive lock time at switching refresh rates

Spec.
Symbol Parameter Unit
Min. Typ. Max.
T1 VBlank at refresh rate 1 2 - 3 Line
T2 LVDS clock differential pair held at logical 0 value 50 - 100 µs
T3 TCON receive lock time - - 200 µs
T4 Refresh rate 2 to first active line 200 - - µs

6.10 Spread Spectrum Clock Generator (SSCG)

The SSCG function is used for reducing EMI. The modulation of SSCG IP is
symmetrically centered and triangular on the output frequency. The specifications are
detailed listed at section 8.4.

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 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
6.11 EEPROM mapping memory

6.11.1 TCON only: 4K bit memory space

Block Address 000 001

Word Address 00---FF 00---FF
Function Timing Timing

6.11.2 TCON + color engine: 6K bit memory space

Block Address 000 001 010

Word Address 00---FF 00---FF 00---FF
Function Timing Timing Color engine

6.11.3 TCON + CABC: 8K bit memory space

Block Address 000 001 010 011

Word Address 00---FF 00---FF 00---FF 00---FF
Function Timing Timing CABC

6.11.4 TCON + CABC + color engine: 10K bit memory space

Block Address 000 001 010 011 100

Word Address 00---FF 00---FF 00---FF 00---FF 00---FF
Function Timing Timing Color engine CABC

6.11.5 TCON + DGC: 10K bit memory space

Block Address 000 001 010 011 100

Word Address 00---FF 00---FF 00---FF 00---FF 00-00---FF F
Red Green Blue
Function Timing Timing Gamma Gamma Gamma
(DGC) (DGC) (DGC)

6.11.6 TCON + color engine + DGC: 12K bit memory space

Block Address 000 001 010 011 100 101

Word Address 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF
Red Green Blue
Function Timing Timing Color engine Gamma Gamma Gamma
(DGC) (DGC) (DGC)

6.11.7 TCON + DGC + CABC: 14K bit memory space

Block Address 000 001 010 011 100 101 110

Word Address 00---FF 00---FF 00---FF 00---FF 00-00---FF F 00---FF 00---FF
Red Green Blue
Function Timing Timing Gamma Gamma Gamma CABC
(DGC) (DGC) (DGC)

6.11.8 TCON + color engine + DGC + CABC: 16K bit memory space

Block Address 000 001 010 011 100 101 110 111
Word Address 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF 00---FF
Red Green Blue
Function Timing Timing Color engine Gamma Gamma Gamma CABC
(DGC) (DGC) (DGC)

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in whole or in part without prior written permission of Himax. May, 2014
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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

7. DC Characteristics
7.1 Absolute maximum ratings

Spec.
Parameter Symbol Unit
Min. Typ. Max.
Supply voltage VDD -0.3 - +4.0 V
CMOS/TTL input voltage VIN -0.3 - VDD V
CMOS/TTL output voltage VOUT -0.3 - VDD V
LVDS receiver input voltage VIN -0.3 - VDD V
Storage temperature TSTG -40 - 125 ℃
Junction temperature TJ - - 125 ℃
Thermal resistance (junction ambient) ΘJA - - 100(1) ℃/W
Note: (1) For 2-layer standard JEDEC PCB.

7.2 Recommended operating conditions

Spec.
Parameter Symbol Unit
Min. Typ. Max.
3.0(1) 3.3(1) 3.6(1) V
Supply voltage VDD
2.3(2) 2.5(2) 2.7(2) V
Operating temperature TA 0 25 70 ℃
LVDS receiver input voltage VIN 0 - 2.4 V
Note: (1) For +3.3V operation.
(2) For +2.5V operation.

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
7.3 DC electrical characteristics

Spec.
Symbol Parameter Condition Unit
Min. Typ. Max.
F=75MHz,
IDD Supply current PI=14KΩ, RL=100Ω - 54 - mA
pixel checker pattern
CMOS/TTL DC Specifications
VIH High level input voltage - 0.7VDD - VDD V
VIL Low level input voltage - VSS - 0.3VDD V
VOH High level output voltage - 0.8VDD - VDD V
VOL Low level output voltage - VSS - 0.2VDD V
IIN Input current - -10 - 10 A
CABC_EN (Pin 17)
VDD=3.3V COLOR_EN (Pin 19) 50 100 150 KΩ
RPD Pull low resistance AGMODE (Pin 20)
VDD=2.5V TEST (Pin 41) 75 150 225 KΩ
PWMI (Pin 44)
LVDS DC Specifications
VTH Differential input high threshold - - +100 mV
VIC=1.2V
VTL Differential input low threshold -100 - - mV
VIC LVDS common mode voltage - 0.7 - 1.6 V
VID LVDS swing voltage - 100 - 600 mV
mini-LVDS DC Specifications
Output differential voltage range 100 - 600 mV
VOD
VOD_CODE VOD_CODE
Output differential voltage deviation - mV
RL=100Ω *0.85(1) *1.15(1)
(TA=25℃)
Output offset voltage range 0.6 - 1.3 V
VOS
VOS_CODE VOS_CODE
Output offset voltage deviation - V
-0.2(1) +0.2(1)
DCLK Output clock duty - 45 50 55 %
Note: (1) The VOD_CODE and VOS_CODE can be programmable by different panel characteristics through ROM code.

LVCLKN
VID VID
LVCLKP
VIC

GND

VID
LVCLKP-LVCLKN 0V
VID

Figure 7.1: LVDS VID and VIC definition

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

Figure 7.2: mini-LVDS VOD and VOS definition

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

VOD (mV) PI vs. VOD (RL=100Ω)

800

600

400

200

0
5 7 9 11 13 15
PI(KΩ)

Figure 7.3: PI and VOD relation curve

7.4 ESD parameters

Parameter Symbol Spec. Unit

Human Body Model HBM 2000 V
Machine Model (C=200pF, R=0Ω) MM 200 V

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

8. AC Characteristics
8.1 LVDS AC electrical characteristics

Figure 8.1: LVDS channel to channel skew

Figure 8.2: LVDS input SSC

Spec.
Symbol Parameter Condition Unit
Min. Typ. Max.
F LVDS Input frequency - 25 - 110 MHz
F=65MHz
TLVSK LVDS channel to channel skew VIC=1.2V -600 - +600 ps
VID=200mV
Modulating frequency of input
FLVMOD 10 - 300 KHz
clock during SSC F=85MHz
Maximum deviation of input clock VIC=1.2V
FLVDEV -3 - +3 %
frequency during SSC VID=200mV
TCY-CY Cycle to cycle jitter - - 200 ps

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
Phase Lock Loop wake-up time

VTH

VDD
10ms

LVCLKP/N

Internal CLK Invalid

Invalid

Figure 8.3: PLL wake up time

Power up sequence

VHYS
VTH
VDD

0V

Internal Reset

TRST TRST

Figure 8.4: Power on reset

Spec.
Symbol Parameter Condition Unit
Min. Typ. Max.
VTH Reset threshold voltage - 1.7 1.9 2.1 V
VHYS Hysteresis voltage - 200 - - mV
TRST Time constant of RC - - 0.8RC - s

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

VDD
T2(1)
LVDS

/HWRSTZ
TRC(1)
EEPROM
Download
STV

CPV

OE1

TP1/POL/OE2

PWMO

MLCLKP/N

1 frame
Data Out

1 2 3 4 5 6

Note: (1) 0ms < T2 < 50ms, T2 <TRC

Figure 8.5: Power up sequence

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
8.2 mini-LVDS AC electrical characteristics

8.2.1 mini-LVDS output data format

0v 0v
MLCLKP/N
Tst1 Thd1 Tst1 Thd1
ML0P/N
b0 b1 b2 b3 b4 b5


ML2P/N

Figure 8.6: mini-LVDS output data format

mini-LVDS skew control

mini-LVDS output skew can be adjusted by ROM code setting

SKEW Setup time(Tst1) Hold time(Thd1) Unit
0 4T/16 4T/16
1 3T/16 5T/16
2 2T/16 6T/16
T
3 1T/16 7T/16 (mini-LVDS clock cycle)
4 5T/16 3T/16
5 6T/16 2T/16
6 7T/16 1T/16

mini-LVDS reset pulse

Starting Data Sampling
1 2

MLCLKP/N 0V

ML0P/N Data Data Data

Data


ML5P/N 11.5 clocks “H” 1.5 clock “L”

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
8.2.2 mini-LVDS output data mapping @ WXGA (1366X768)

8.2.2.1 Normal mode

Single port 3-pair

Data pair One line data

ML0P/N 1R 2R 3R 4R 5R 6R 7R 8R --- 1365R 1366R
ML1P/N 1G 2G 3G 4G 5G 6G 7G 8G --- 1365G 1366G
ML2P/N 1B 2B 3B 4B 5B 6B 7B 8B --- 1365B 1366B

8.2.2.2 Dual-gate mode

Support four types of dual gate mapping

Pattern A

Dual gate data mapping ML0 ML1 ML2

Odd line 1R 1B 2G
Type 0
Even line 1G 2R 2B
Odd line 1R 2R 2G
Type 1
Even line 1G 1B 2B
Odd line 1G 1B 2G
Type 2
Even line 1R 2R 2B
Odd line 1R 2R 2B
Type3
Even line 1G 1B 2G

Pattern B

Dual gate data mapping ML0 ML1 ML2

Odd line 1G 2R 2B
Type 0
Even line 1R 1B 2G
Odd line 1G 1B 2B
Type 1
Even line 1R 2R 2G
Odd line 1R 2R 2B
Type 2
Even line 1G 1B 2G
Odd line 1G 1B 2G
Type3
Even line 1R 2R 2B

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TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
8.3 mini-LVDS output data swap by ROM code setting

The HX8861-H11 supports 2 swap types for 3-pair mini-LVDS output, including PN
and Port swap. All these swapping settings are independent. Users can combine
each swapping setting.

8.3.1 3-pair mini-LVDS data swap

SWAP SWAP
Pin no. Pin name V PN PN
Port V Port
28 ML0P ML0N ML2P
27 ML0N ML0P ML2N
30 ML1P ML1N ML1P
29 ML1N ML1P ML1N
32 ML2P ML2N ML0P
31 ML2N ML2P ML0N
26 MLCLKP MLCLKN MLCLKP
25 MLCLKN MLCLKP MLCLKN

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03
8.4 SSCG AC electrical characteristics

Spec.
Symbol Parameter Condition Unit
Min. Typ. Max.
FMOD Modulation frequency LVDS input frequency=80MHz - 125 - KHz
LVDS input frequency=80MHz
ROM code Setting 0
- 1 -
LVDS input frequency=80MHz
FDEV Spread range
ROM code Setting 1
- 2 - %
LVDS input frequency=80MHz
- 3 -
ROM code Setting 3

Figure 8.7: SSCG profile

8.5 Oscillator AC electrical characteristics

Spec.
Symbol Parameter Condition Unit
Min. Typ. Max.
FOSC Oscillator frequency - FOSC*0.85 FOSC FOSC*1.15 MHz

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in whole or in part without prior written permission of Himax. May, 2014
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

9. Package Outline Dimension

Himax Confidential -P.24-

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in whole or in part without prior written permission of Himax. May, 2014
 May, 2014
-P.25-
DATA SHEET V03

R19 22 OE2
R18 22 OE1
HX8861-H11DDKG : EEPROM 24LC32 R17 22 CPV
R16 22 STV
VDD R12 22 POL

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
R13 22 TP
4.7K

4.7K

C1
0.1uF
U1 C3 0.1uF
1 8 VDD
A0 VCC
2 7
R1

R2

A1 WP C4 0.1uF
3 6 SCLK VDDM

PWMI

SDAT

SCLK

TEST
A2 SCL
4 5 SDAT
VSS SDA
EEPROM

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33
VSS

SCLK

CPV

STV
E-pad

OE2

OE1

POL

TP1
SDAT

TEST

VDDM
N.C.

PWMI

VDD
C16 0.1uF
VDDA 1 32 R4 100 ML2P
CN1 VDDA ML2P
LV0N LV0N 2 31 ML2N
1 R3 100 LV0N ML2N
LV0N 2 LV0P LV0P 3 30 R6 100 ML1P
LV0P LV0P ML1P
TFT LCD Timing controller with LVDS input and mini-LVDS output

3
LV1N 4 LV1N LV1N 4 29 ML1N
LV1P
LV2N
LV2P
5
6
R5 100
LV1P LV1P 5
LV1N
LV1P
HX8861-H11DDKG ML1N
ML0P
28 R9 100 ML0P
7
GND
LVCLKN
LVCLKP
8
9 R7 100
LV2N
LV2P

LV2N
LV2P

6
LV2N (QFN46) ML0N
27 ML0N
MLCLKP
10 7 26 R10 100
LV3N 11 LV2P MLCLKP
LV3P 12 LVCLKN LVCLKN 8 25 MLCLKN
NC 13 R8 100 LVCLKN MLCLKN
NC 14 LVCLKP LVCLKP 9 24

COLOR_EN
GND 15 LVCLKP VSSM

/HWRSTZ
CABC_EN

AGMODE
NC 16 LV3N LV3N

PWMO
NC 17 R15 100

VSSA
LV3N

LV3P

N.C.

VDD

N.C.

N.C.
GND

VSS
18 LV3P LV3P
NC

PI
19
NC 20
NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23
21
NC 22
NC 23
NC

COLOR_EN
24

CABC_EN
GND

AGMODE
25

HWRST
TST_PG

PWMO
26

in whole or in part without prior written permission of Himax.

NC

PI_A
VDD
27 VIN(5V) VCC VDD
SELLVDS 28
Vin 29 F1 U3 LDO L1 BEAD
Vin 30 VDD C5 R14
Vin Vin Vout

Gnd
0.1uF 14K
FI-X30S-HF C6 C7 C8 C9 C10
10. Reference Circuit
HX8861-H11

VDDA Reset DC setting Pin CABC function

10.1 HX8861-H11DDKG

L2 BEAD
VDDA VDD
VDD VDD VDD VDD VDD VDD
C12 C13
JP1 JP4 JP6 JP5 JP2 JP3
R11
100k COLOR_EN AGMODE TEST CABC_EN PWMI PWMO
HWRST

Himax Confidential
VDDM
C11
L3 BEAD
VDDM 0.1uF
C14 C15
 May, 2014
-P.26-
DATA SHEET V03

R19 22 OE2
R18 22 OE1
HX8861-H11DDKG-E : EEPROM 24LC16 R17 22 CPV
R16 22 STV
VDD R12 22 POL
R13 22 TP

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
4.7K

4.7K

C1
0.1uF
U1 C3 0.1uF
1 8 VDD
A0 VCC
R1

R2

2 7
A1 WP C4 0.1uF
3 6 SCLK VDDM

PWMI

SDAT

SCLK

TEST
A2 SCL
4 5 SDAT
VSS SDA
EEPROM

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33
VSS

SCLK

CPV

STV
E-pad

OE2

OE1

POL

TP1
SDAT

TEST

VDDM
N.C.

PWMI

VDD
C16 0.1uF
VDDA 1 32 R4 100 ML2P
CN1 VDDA ML2P
LV0N LV0N 2 31 ML2N
1 R3 100 LV0N ML2N
LV0N 2 LV0P LV0P 3 30 R6 100 ML1P
LV0P 3 LV0P ML1P
TFT LCD Timing controller with LVDS input and mini-LVDS output

LV1N 4 LV1N LV1N 4 29 ML1N

LV1P
LV2N
LV2P
5
6
R5 100
LV1P LV1P 5
LV1N
LV1P
HX8861-H11DDKG-E ML1N
ML0P
28 R9 100 ML0P
7
GND
LVCLKN
LVCLKP
8
9 R7 100
LV2N
LV2P

LV2N
LV2P

6
LV2N (QFN46) ML0N
27 ML0N
MLCLKP
10 7 26 R10 100
LV3N 11 LV2P MLCLKP
LV3P 12 LVCLKN LVCLKN 8 25 MLCLKN
NC 13 R8 100 LVCLKN MLCLKN
NC 14 LVCLKP LVCLKP 9 24

COLOR_EN
GND 15 LVCLKP VSSM

CABC_EN

/HWRSTZ

AGMODE
NC 16 LV3N LV3N

PWMO
NC 17 R15 100

VSSA
LV3N

LV3P

N.C.

VDD

N.C.

N.C.
GND

VSS
18 LV3P LV3P
NC

PI
19
NC 20
NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23
21
NC 22
NC 23
NC

COLOR_EN
24

CABC_EN
GND

AGMODE
25

HWRST
TST_PG

PWMO

in whole or in part without prior written permission of Himax.

26
NC

PI_A
VDD
27 VIN(5V) VCC VDD
SELLVDS 28
Vin 29 F1 U3 LDO L1 BEAD
Vin 30 VDD C5 R14
Vin Vin Vout

Gnd
0.1uF 14K
FI-X30S-HF C6 C7 C8 C9 C10
10.2 HX8861-H11DDKG-E
HX8861-H11

VDDA Reset DC setting Pin CABC function

L2 BEAD
VDDA VDD
VDD VDD VDD VDD VDD VDD
C12 C13
JP1 JP4 JP6 JP5 JP2 JP3
R11
100k COLOR_EN AGMODE TEST CABC_EN PWMI PWMO

Himax Confidential
HWRST
VDDM
C11
L3 BEAD
VDDM 0.1uF
C14 C15
 HX8861-H11
TFT LCD Timing controller with LVDS input and mini-LVDS output
DATA SHEET V03

11. Ordering Information

Device Package Description
HX8861-H11DDKG 46-pin QFN green package Support ≧32K bit EEPROM only
HX8861-H11DDKG-E 46-pin QFN green package Support 2K to 16K bit EEPROM only

12. Revision History

Version Date Description of Changes
01 2012/01/16 New setup.
02 2012/06/19 Page 2, 24, 25
Add HX8861-H11DDKG-E: support 2K to 16K bit EEPROM
only.
03 2014/05/27 All pages
Remove ‘preliminary’ wording.
Page 14
Fill spec. in “Supply current (IDD)“
Modify “mini-LVDS DC specifications”.
Page 23
Modify spec. of “Oscillator frequency(FOSC)”

Himax Confidential -P.27-

This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax. May, 2014