Task 4-5

Embedded Systems Laboratory (EE 3704)

Aim:
Develop RTOS–with FIFO structure for signal access–to realize
the filters in the circuit developed in Task-1-2.

Software used :-
1. Proteus 8 Professional.
2. Keil uVision.
3. MATLAB R2021a

Theory :-
The most commonly used IIR filter design method uses reference analog
prototype filter. It is the best method to use when designing standard filters
such as low-pass, high-pass, bandpass and band-stop filters it is important
class of linear time-invariant discrete-time systems characterized by the general
linear constant-coefficient difference equation.

By means of Z transform it is characterized by the rational system function,

H(z)=

The filter design process starts with specifications and requirements of the
desirable IIR filter. A type of reference analog prototype filter to be used is
specified according to the specifications and after that everything is ready for
analog prototype filter design.

The next step in the design process is scaling of the frequency range of analog
prototype filter into desirable frequency range. This is how an analog prototype
filter is converted into an analog filter.
After the analog filter is designed, it is time to go through the last step in the
digital IIR filter design process. It is conversion from analog to digital filter. The
most popular and most commonly used converting method is bilinear
transformation method. The resulting filter, obtained in this way, is always
stable. However, instability of the resulting filter, when bilinear transformation
is used, may be caused only by the finite word-length side-effect.

. Schematic diagram:-

Procedure :-
1. Initially the filter coefficients were calculated using the MATLAB filter
designer toolbox.
2. The cut-off frequency is 373Hz and the sampling frequency must be
greater than the twice of the cut-off frequency sampling
frequency=2100Hz.
The circuit is the same as the one designed in Task 1. The code has been
altered to implement the Low-pass FIR filter.

The coefficients are in the range of 0-1 so they are converted 0.8 notation of
fixed precision point and the samples are already in 0.8 notation, so the output
which is:
 Is in the form of 0.8*0.8 = 0.16, lower 8 bits are ignored, hence we are left with
0.8 output which is sent to the DAC

Assembly code :
;================================================================
====
; Main.asm file generated by New Project wizard
;
; Created: Thu Mar 20 2022
; Processor: AT89C52
; Compiler: ASEM-51 (Proteus)
;================================================================
====
 CLR PSW.3
CLR PSW.4 ;SELECT REGISTER BANK 0
MOV R0,Pl ;MOVE CONVERTED DATA FROM ADC TO RO
MOV A,#32H ;a0 MOVED TO ACCUMULATOR
MOV B,R0 ;x[n] SAMPLE FROM RO MOVED TOB
MUL AB ;a0*x[n]
MOV R6,B ;ABOVE MULTIPICATION RESULT MOVED TO
R6
MOV A,#64H ;al MOVED TO ACCUMULATOR
MOV B,Rl ;x[n-1] SAMPLE FROM Rl MOVED TOB
MUL AB ;al*x[n-1]
MOV R7,B ;ABOVE MULTIPICATION RESULT MOVED TO
R6
MOV A,#32H ;a2 MOVED TO ACCUMULATOR
MOV B,R2 ;x[n-2] SAMPLE FROM R2 MOVED TOB
MUL AB ;a2*x[n-2]
MOV A,B ;ABOVE MULTIPICATION RESULT MOVED TO
ACCUMULATOR

ADDC A,R6 ;a2*x[n-2]+a0*x[n]

ADDC A,R7
MOV R3,A ;a0*x[n]+a1*x[n-1]+a2*x[n-2]
R3 ;ABOVE SUM FROM ACCUMULATOR MOVED TO

MOV A,Rl
MOV R2,A
MOV A,R0 ;TRANSFER x[n-1] SAMPLE TO R2
MOV Rl,A

;TRANSFER x[n] SAMPLE TO Rl

MOV A,#94H
MOV B,R4
MUL AB ;bl MOVED TO ACCUMULATOR
ACCUMULATOR MOV A,B
;y[n-1] SAMPLE FROM RO MOVED TO B
1] ;bl*y[n-1]
ADDC A,R3
;ABOVE MULTIPICATION RESULT MOVED TO

MOV R6,A ;a0*x[n]+a1*x[n-1]+a2*x[n-2]-bl*y[n-

MOV A,#6CH
MOV B,R5
R7 MUL AB ;ABOVE SUM MOVED TO R6
MOV R7,B ;b2 MOVED TO ACCUMULATOR
;y[n-2] SAMPLE FROM R0 MOVED TO B
MOV A,R6
;b2*y[n-2]
;ABOVE MULTIPICATION RESULT MOVED TO

;a0*x[n]+a1*x[n-1]+a2*x[n-2]-bl*y[n-
1] SUM MOVED TO ACCUMULATOR SUBB A,R7
r CLR P SW • 0
 ;a0*x[n]+a1*x[n-1]+a2*x[n-2]-bl*y[n-

1]-b2*y[n-2]
 MOV R6,A ;ABOVE SUM MOVED FROM ACCUMULATOR TO
R6

MOV A,R4
MOV R5,A ;TRANSFER y[n-1] SAMPLE TO
R5 MOV A,R6
MOV R4,A ;TRANSFER y[n] SAMPLE TO R4

r SECTION 2 (SECOND II ORDER FILTER)

CLR PSW.3
SETB PSW.4 ;CHANGE THE REGISTER BANK TO BANK 2
FOR SECTION
2
MOV R0,A
MOV A,#25H
MOV B,R0
MUL AB
MOV R6,B
MOV A,#50H
MOV B,Rl
MUL AB
MOV R7,B
MOV A,#25H
MOV B,R2
MUL AB
MOV A,B
ADDC A,R6
ADDC A,R7
MOV R3,A

MOV A,Rl
MOV R2,A
MOV A,R0
MOV Rl,A

MOV A,#97H
MOV B,R4
MUL AB
MOV A,B
ADDC A,R3
MOV R6,A
MOV A,#2DH
MOV B,R5
MUL AB
MOV
R7,B
MOV
A,R6
/ CFR PSW 0
 SUBB A,R7
MOV R6,A

MOV A,R4
MOV R5,A
MOV A,R6
MOV R4,A

r SECTION I ORDER FILTER)

SETB PSW.3
SETB PSW.4 ;CHANGE THE REGISTER BANK TO BANK 3
FOR SECTION
3
MOV R0,A
MOV A,#5DH
MOV B,R0
MUL AB
MOV R6,B
MOV
A,#5DH
MOV B,Rl
MUL AB
MOV A,B
ADDC A,R6
MOV R3,A

MOV A,R0
MOV Rl,A

MOV
A,#45H
MOV B,R4
MUL AB
MOV A,B
ADDC
A,R3 MOV
R6,A

MOVED TO P2 MOV A,R6

MOV R4,A

MOV P2,A ;OUTPUT y[n] OF STH ORDER FILTER

SETB ALE
SETB START
CLR ALE
CLR START
RETI
;================================================================
====
END

Observations:
Table-1: Table showing the Output Amplitudes of IIR filter for various
Input frequencies.
Frequen Input Output Gain
cy Amplitude Amplitude Latency Gain in
(ms)
(Hz) (V) (V) dB
50 4 3.8 1.3 0.95 -0.44
100 4 3.8 1.15 0.95 -0.44
200 4 3.7 1.3 0.925 -0.625
300 4 2.4 1.2 0.6 -4.436
334 4 2.275 1.2 0.568 -4.91
500 4 0.975 2.05 0.237 -12.48
5
800 4 0.720 - 0.180 -14.89
1000 4 0.185 - 0.046 -
26.744

Results :-

Fig 1. The output at 50Hz and 2.5V Amplitude (Input in Blue and
Output in yellow)
 Fig 2. The output at 200Hz and 2.5V Amplitude (Input in Blue and
Output in yellow)

Fig 3. The output at 500Hz and 2.5V Amplitude (Input in Blue and
Output in yellow)

Fig 4. The output at 1000Hz and 2.5V Amplitude (Input in Blue and
Output in yellow)

Conclusion :-

1. Due to the higher number of coefficients and past values of input

and output that had to be stored, a single register bank was not
 enough. We had to use a second bank as well. This led to increased
complexity of the code.
2. Distortions were higher as compared to the FIR filter, causing
problems while taking readings. There were especially large
distortions at f = 200 Hz. Even at the other frequencies, the
distorted sinusoids were interspersed by flat lines in between.

3. They are harder to implement using fixed-point arithmetic.

4. Clock frequency of ADC0808 should not be less like 2KHz,
instead it should be like 640kHz or 1MHz.

5. Output filtered signal was similar to the input signal for low
frequency signals and for higher frequency signals output
amplitude is attenuated according to the frequency response

Karri Teja

Group: S2

Roll No :119EE0610