FPGA UG 02001 1 2 ICE40 UltraPlus Breakout Board

iCE40 UltraPlus Breakout Board
User Guide
FPGA-UG-02001-1.2
April 2022
User Guide
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.
© 2016-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-UG-02001-1.2
User Guide
Contents
Acronyms in This Document ................................................................................................................................................. 5
1. Introduction .................................................................................................................................................................. 6
2. Features ........................................................................................................................................................................ 7
3. iCE40 UltraPlus Device .................................................................................................................................................. 8
4. Software Requirements ................................................................................................................................................ 9
5. Demonstration Design Shunts .................................................................................................................................... 10
6. Clock Sources .............................................................................................................................................................. 11
7. Board Power ............................................................................................................................................................... 12
8. Board Configuration and Programming....................................................................................................................... 13
9. Test Points .................................................................................................................................................................. 16
10. RGB LED Demonstration Design and Software User Interface ............................................................................... 18
11. Serial Communication Interface ............................................................................................................................. 21
11.1. LED Control through SPI .................................................................................................................................... 21
11.2. SPI Protocol ....................................................................................................................................................... 21
11.3. Register Definitions ........................................................................................................................................... 22
12. Ordering Information.............................................................................................................................................. 24
Appendix A. Schematic Diagrams ....................................................................................................................................... 25
Appendix B. Bill of Materials............................................................................................................................................... 31
References .......................................................................................................................................................................... 35
Technical Support Assistance ............................................................................................................................................. 36
Revision History................................................................................................................................................................... 37
FPGA-UG-02001-1.2 3
User Guide
Figures
Figure 2.1. iCE40 UltraPlus Breakout Board (Top Side) ........................................................................................................7
Figure 5.1. Default Shunt Locations ....................................................................................................................................10
Figure 8.1. Board Configuration for Programming Flash ....................................................................................................13
Figure 8.2. Device Property Settings for Programming Flash .............................................................................................14
Figure 8.3. Setting Status in Diamond Programmer for Programming Flash ......................................................................14
Figure 8.4. Device Property Settings for Programming iCE40 UltraPlus .............................................................................15
Figure 9.1. J52 Header ‘A’ Breakouts ..................................................................................................................................16
Figure 9.2. J2 Header ‘B’ Breakouts ....................................................................................................................................16
Figure 9.3. J3 Header ‘C’ Breakouts ....................................................................................................................................16
Figure 9.4. U6 PMOD Connector.........................................................................................................................................17
Figure 9.5. J1 Adardvark Connector ....................................................................................................................................17
Figure 9.6. Breakout Headers .............................................................................................................................................17
Figure 10.1. SPI Flash Selection (Horizontal) for J6 .............................................................................................................18
Figure 10.2. iCE40 UltraPlus Selection (Vertical) for J6.......................................................................................................19
Figure 10.3. iCE40 UltraPlus LED Demonstration Interface ................................................................................................19
Figure 11.1. SPI Physical Transaction ..................................................................................................................................21
Figure A.1. Block Diagram ...................................................................................................................................................25
Figure A.2. FTDI Connection ...............................................................................................................................................26
Figure A.3. DUT Connection ................................................................................................................................................27
Figure A.4. RGB,PMOD and HEADERS .................................................................................................................................28
Figure A.5. Regulator Connection .......................................................................................................................................29
Figure A.6. SPI .....................................................................................................................................................................30
Tables
Table 11.1. Register Address and Bit Field Allocation.........................................................................................................21
Table 11.2. Bit Field Functionality Definition ......................................................................................................................21
Table 11.3. RGB Color Code Definition ...............................................................................................................................22
Table 11.4. LED Brightness Code Definition .......................................................................................................................22
Table 11.5. Breathe Ramp Code Definition ........................................................................................................................23
Table 11.6. Blink Rate Code Definition ...............................................................................................................................23
Table 12.1. Ordering Information .......................................................................................................................................24
4 FPGA-UG-02001-1.2
User Guide
Acronyms in This Document

A list of acronyms used in this document.
Acronym Definition
CMOS Complementary Metal-Oxide Semiconductor
FPGA Field Programmable Gate Array
FTDI Future Technology Devices International
I/O Input/Output
LED Light-emitting Diode
SPI Serial Peripheral Interface
FPGA-UG-02001-1.2 5
User Guide
1. Introduction
Thank you for choosing the Lattice iCE40 UltraPlus™ Breakout Board.
This guide describes how to begin using the iCE40 UltraPlus Breakout Board, an easy-to-use platform for demonstrating
the high-current LED drive capabilities of the iCE40 UltraPlus, which has more memory to achieve functions mainly
required in the customer mobile market. Along with the evaluation board and accessories, this kit includes a pre-loaded
LED Driver Demo that demonstrates driving the RGB LEDs with a PWM circuit. In addition, most of the device's I/O pins
are accessible through one of the several header locations on the board, facilitating rapid prototyping of user functions.
The contents of this user guide include demo operation, top-level functional descriptions of the various portions of the
evaluation board, descriptions of the onboard connectors, shunts, and a complete set of schematics and the bill of
materials for the iCE40 UltraPlus Breakout Board.
Note: Static electricity can severely shorten the lifespan of electronic components. Be careful when handling the iCE40
UltraPlus Breakout Board as to not damage it from ESD.
6 FPGA-UG-02001-1.2
User Guide
2. Features
The iCE40 UltraPlus Breakout Board includes:
 iCE40 UltraPlus Breakout Board – The iCE40 UltraPlus Breakout Board features the following on-board components
and circuits:
 iCE40 UltraPlus (iCE40UP5K-SG48) device in a 48-PIN QFN package.
 Example of a board using this 0.5mm pitch QFN package.
 High-current LED output
 iCE40 UltraPlus Current Measurements
 Standard USB cable for device programming.
 RoHS-compliant packaging and process
 Pre-loaded Demo – The kit includes a pre-loaded demo to control the onboard RGB LED in conjunction with a
software run user interface.
 USB Connector Cable – A mini B USB port provides power, a programming interface and communication for the
software RGB LED user interface to the iCE40 UltraPlus SPI port.
Figure 2.1 shows the top side of the iCE40 UltraPlus Breakout Board indicating the specific features that are designed on
the board.
D13 USB
Power Interface
LED Socket
iCE40UP5K-
SG48
RGB
LED
Figure 2.1. iCE40 UltraPlus Breakout Board (Top Side)
FPGA-UG-02001-1.2 7
User Guide
3. iCE40 UltraPlus Device

The board features an iCE40UP5K FPGA with a 1.2 V core supply. The device package is 48-PIN QFN. For a complete
description of this device, see iCE40 UltraPlus Family Data Sheet (FPGA-DS-02008).
8 FPGA-UG-02001-1.2
User Guide
4. Software Requirements
You should install the following software before you begin developing designs for the board:
 Lattice iCEcube2 2017.01 (or higher)
 Diamond Programmer 3. 9 (or higher)
These software are available at the Lattice website Design Software and IP page. Make sure you log in to
www.latticesemi.com, otherwise these software downloads are not visible. It is also recommended to download the
RGB LED software user interface which interfaces with the iCE40 UltraPlus Breakout Board. This user interface allows
you to control the RGB LED for color, brightness, blinking and breathing. Download the PC or MAC version of the user
interface at www.latticesemi.com.
FPGA-UG-02001-1.2 9
User Guide
5. Demonstration Design Shunts

Lattice provides the RGB LED Driver Demo design programmed on the board. The RGB LED Driver Demo used in
conjunction with the software user interface illustrates the use of a PWM driver controlling the LEDs on the board.
Below is a description of the control jumpers for each LED.
 The RGB LED transitions colors.
 J27 can be used to probe RGB LED (Default shunted). If you remove J27, the RGB LED does not light up.
Figure 5.1 shows the default board shunt locations.
J28 – Enable DONE LED
J6 – Program SPI
Flash or iCE40UP
J7 – Isolate
J51 – Enable SPI Flash CSn
12 MHz clock
J27 - RGB Shunts

Figure 5.1. Default Shunt Locations
10 FPGA-UG-02001-1.2
User Guide
6. Clock Sources
The board has a single 12 MHz clock source. The 12 MHz clock drives both the FTDI USB interface device, and the
iCE40UP5K device. The iCE40UP5K can be disconnected from the 12 MHz oscillator using J51. This is necessary, for
example, when iCE40UP5K device pin35 is mistakenly programmed as an output and prevents the FTDI USB interface
from operating.
FPGA-UG-02001-1.2 11
User Guide
7. Board Power
There are two versions of the Bill of Materials (BOM). Early versions have D11 populated with a CDBU0520 Schottky.
Later versions populate D11 with a CDSU4148. The later version diode complies with the voltage requirements on the
Vpp_2V5 pin for NVCM programming/configuration.
The board provides the following power features:
 Board Power
 Board power is derived from the USB connection.
 D13 Blue LED indicates Board Power
 iCE40 UltraPlus VCC/VCC_PLL
 Onboard 1.2 V supply
 ICC can be measured across the series resistor R76 (1 Ω) at TP11 and TP12
 ICC_PLL can be measured across the series resistor R77 (1 Ω) at TP13 and TP14
 iCE40 UltraPlus VCCIO
 Onboard 3.3 V supply
 ICC0 can be measured across the series resistor R73 (1 Ω) at TP5 and TP6
The power supplies on the iCE40 UltraPlus Breakout Board are simplified and suitable for booting from the external SPI
flash. The power supply sequencing does not conform to the NVCM boot requirements as specified in iCE40 UltraPlus
Family Data Sheet (FPGA-DS-02008). You may encounter intermittent boot success and/or higher than specified
startup currents when attempting to boot from NVCM.
12 FPGA-UG-02001-1.2
User Guide
8. Board Configuration and Programming

The board allows for programming of the iCE40 UltraPlus or the SPI Flash:
 SPI Flash Programming J6 shunt pins 1-3 and 2-4 (Default shunted)
 U5 Micron Technology Inc. part number N25Q032A13ESC40F
 iCE40 UltraPlus Configuration or Programming J6 shunt pins 1-2 and 3-4
 U1 iCE40UP5K – SG48
 CRESETB can be asserted by pushing SW1
 Can be probed with J11
 Done LED D2
 Can be probed with J28 (Default shunted)
The details of the iCE40 UltraPlus Board for SPI flash programming are shown in Figure 8.1.
J11 – CRESETB Probe
CRESETB Push-Button
J28 – Enable DONE LED
USB Interface
Socket
U5 – N25Q032A13ESC40F
J6 – Program SPI
Flash or iCE40 UltraPlus
J51 – Enable J7 – Isolate SPI Flash CSn

12 MHz clock
U1 –
iCE40UP5K-SG48
Figure 8.1. Board Configuration for Programming Flash
To program SPI flash in Diamond Programmer:

1. Make sure that the Standalone Diamond Programmer is installed.
2. Connect the iCE40 UltraPlus breakout board through the USB cable to a PC or MAC.
3. Start Diamond Programmer.
4. Set Device Family to iCE40 UltraPlus” and Device to “iCE40UP5K”. Refer to Figure 8.3.
5. Open the Device Properties dialog. Apply the settings highlighted in Figure 8.2.
 Programming file is the bitmap file that will be programmed into the iCE40 UltraPlus breakout board.
 Load from File button should be used to refresh fields such as “Data file size” and “End address(Hex)”.
FPGA-UG-02001-1.2 13
User Guide
6. Click OK to exit Device Properties dialog.

7. Click the Program button in Diamond Programmer to download the bitstream file.
Figure 8.2. Device Property Settings for Programming Flash
Double-click to Double-click to Double-click to

set Device set Device type open the Device
Program button Family to iCE40 to iCE40UP5K Properties dialog
UltraPlus
Figure 8.3. Setting Status in Diamond Programmer for Programming Flash
14 FPGA-UG-02001-1.2
User Guide
The differences between programming ICE40 UltraPlus and programming flash are described below.
To program ICE40 UltraPlus in Diamond Programmer:
1. Change jumpers on J6, shunt pins 1-2 and 3-4.
2. Apply the settings in the Device Properties dialog as shown in Figure 8.4.
Figure 8.4. Device Property Settings for Programming iCE40 UltraPlus
For more information on Diamond Programmer, please refer to its user guide.
FPGA-UG-02001-1.2 15
User Guide
9. Test Points
The board features a number of headers and test connections which provide access to the iCE40 UltraPlus I/Os:
Figure 9.1. J52 Header ‘A’ Breakouts
Figure 9.2. J2 Header ‘B’ Breakouts
Figure 9.3. J3 Header ‘C’ Breakouts
16 FPGA-UG-02001-1.2
User Guide
Figure 9.4. U6 PMOD Connector
Figure 9.5. J1 Adardvark Connector
The break-out headers and test connectors are shown in Figure 9.6.
U6 - "PMOD SOCKET"
J3 - "Header C" J2 - "Header B"
J1 - "Aardvark SPI
emulator connector
J52 - "Header A"
Figure 9.6. Breakout Headers
FPGA-UG-02001-1.2 17
User Guide
10. RGB LED Demonstration Design and Software User Interface

The iCE40 UltraPlus Breakout Board can demonstrate a complete controller for an RGB LED. Following are the steps to
run the demonstration. The software user interface tool used here is the same as the one used with the iCE40 Ultra
Breakout Board. You can refer to the Lattice website iCE40 Ultra Breakout Board page.
To run the demonstration:
1. Ensure that the RGB LED user interface is installed.
2. Make sure the jumpers on J6 are both in the horizontal position. This is the default pins 1-3 and 2-4 shorted
together.
Figure 10.1. SPI Flash Selection (Horizontal) for J6
3. Connect the iCE40 UltraPlus breakout board through the USB cable to a PC or MAC.
4. After the iCE40 UltraPlus device has initialized and the RGB LED is illuminated RED, change the J6 jumper positions
to vertical, shorting pins 1-2 and 3-4. This is required to allow the USB port to communicate with the iCE40UP5K
device.
18 FPGA-UG-02001-1.2
User Guide
Figure 10.2. iCE40 UltraPlus Selection (Vertical) for J6
5. Start the RGB user interface on the PC or MAC.
Figure 10.3. iCE40 UltraPlus LED Demonstration Interface
FPGA-UG-02001-1.2 19
User Guide
Now you can control the RGB LED on the iCE40 UltraPlus Breakout Board. You can set the color, brightness, blinking
rate as well as breathing.
Note: The RGB user interface is the same demo tool used with iCE40 Ultra Breakout board.
20 FPGA-UG-02001-1.2
User Guide
11. Serial Communication Interface
11.1. LED Control through SPI

The Software user interface demonstration program communicates with the iCE40 UltraPlus device using an SPI serial
communication channel. The SPI interface (mode 0) control link is implemented using a simple write-only protocol (see
Figure 11.1.)
CSn
SCK
MOSI
ADDR[7:0] REG[15:8] REG[7:0]
Figure 11.1. SPI Physical Transaction
11.2. SPI Protocol

Data on the MOSI serial line is transmitted MSB first.
Addr[7:0] – Controls which of the 16 bits are updated with REG data.
Note that Unspecified REG bits must be written, but are ignored.
Table 11.1. Register Address and Bit Field Allocation
Addr Bits Written Bit Position
0x13 REG[3:0] ------------dddd
0x14 REG[7:4] --------cccc----
0x15 REG[11:8] ----bbbb--------
0x16 REG[15:12] aaaa------------
0x19 REG[15:0] aaaabbbbccccdddd
REG[15:0] – Consists of four control fields.

Table 11.2. Bit Field Functionality Definition
Field Bit Positions Function
aaaa REG[15:12] RGB Color[3:0]
bbbb REG[11:8] Brightness[3:0]
cccc REG[7:4] Breathe Ramp [3:0]
dddd REG[3:0] Blink Rate [3:0]
FPGA-UG-02001-1.2 21
User Guide
11.3. Register Definitions

Table 11.3. RGB Color Code Definition
Default setting (hardware, software) is denoted by (*).
RGB Color[3:0] Color Color Code
0000* Red #FF0000
0001 Orange #FF7F00
0010 Yellow #FFFF00
0011 Chartreuse #7FFF00
0100 Green #00FF00
0101 Spring Green #00FF7F
0110 Cyan #00FFFF
0111 Azure #007FFF
1000 Blue #0000FF
1001 Violet #7F00FF
1010 Magenta #FF00FF
1011 Rose #FF007F
1100 — —
1101 — —
1110 — —
1111 White #FFFFFF
Table 11.4. LED Brightness Code Definition

Brightness[3:0] Level (%)
0000 6.25 (dim)
0001 12.5
0010 18.78
0011 25
0100 31.25
0101 37.5
0110 43.75
0111* 50
1000 56.25
1001 62.5
1010 68.75
1011 75
1100 81.25
1101 87.5
1110 93.75
1111 100 (bright)
22 FPGA-UG-02001-1.2
User Guide
Table 11.5. Breathe Ramp Code Definition

Breathe Ramp[3:0] Level (%)
0000* .0x (fast)
0001 .063x
0010 .125x
0011 .25x
0100 .5x
0101 1x
0110 2x
0111 4x (slow)
1000 —
1001 —
1010 —
1011 —
1100 —
1101 —
1110 —
1111 —
Table 11.6. Blink Rate Code Definition

Blink Rate[3:0] Level (%)
0000 Always On
0001 1/16 (fast)
0010 1/8
0011 1/4
0100 1/2
0101* 1
0110 2
0111 4
1000 Always Off
1001 —
1010 —
1011 —
1100 —
1101 —
1110 —
1111 —
FPGA-UG-02001-1.2 23
User Guide
12. Ordering Information

Table 12.1. Ordering Information
Description Ordering Part Number China RoHS Environment- Friendly
Use Period (EFUP)
iCE40 UltraPlus Breakout Board iCE40UP5K-B-EVN
24 FPGA-UG-02001-1.2
User Guide
Appendix A. Schematic Diagrams

5 4 3 2 1
Page : 4
BLOCK DIAGRAM
Header C
D D
Page : 4
BANK 1 & 2
Switches
Page : 4
Aardvark Connector
RGB
Lattice Semiconductor FPGA
BANK 1
C C
BANK 0
Header A
SPI
Page : 4
USB
Connector USB to SPI SPI
iCE40UP5K-SG48
Page : 5 Page : 6
Page : 2
BANK 0
B B
Page : 3
Header B
Page : 4
A A
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Title
Block Diagram
Size Project Schematic Rev A

B iCE40 UltraPlus Breakout Board
Board Rev A
Date: 6-DEC-2015 Sheet 1 of 6
5 4 3 2 1
Figure A.1. Block Diagram
FPGA-UG-02001-1.2 25
User Guide
5 4 3 2 1
+3.3V
FB4 FTDI CONNECTION
FB_60ohm C1 C2
PART_NUMBER = HI0603P600R-10
Manufacturer = Laird-signal 4.7uF 0.1uF
D +3.3V D
FB5
VBUS_5V
R54
FB_60ohm C3 C4
PART_NUMBER = HI0603P600R-10
1
1K
D13 Manufacturer = Laird-signal 4.7uF 0.1uF VCC1_8FT +3.3V
C64 Green
L4
0.1uF
600 OHM 800MA
2
J5
1
VCC 2 U2
D- 3 FT2232HL
12
37
64
20
31
42
56
4
9
D+ 4 R49 0
ID 5
VPLL
VCCIO
VCCIO
VCCIO
VCCIO
VPHY
VCORE
VCORE
VCORE
GND C66 0.1uF +3.3V
SKT_MINIUSB_B_RA 16 SCK 0 R5
VCC1_8FT ADBUS0 ICE_SCK 3,4,6
50 17 SI 0 R6
VREGIN ADBUS1 FLASH_MOSI 6
C PART_NUMBER = 5075BMR-05-SM-CR 18 SO 0 R7 C
ADBUS2 FLASH_MISO 6
Manufacturer = Neltron 49 19
VREGOUT ADBUS3 21 SS 0 R8
ADBUS4 ICE_SS 3,4,6
22
+3.3V 7 ADBUS5 23 0 R70
DM ADBUS6 CDONE 3
8 24 0 R71
DP ADBUS7 CRESET_B 3
C10 C11 R9 2.2K 26
14 ACBUS0 27
+3.3V 10uF 0.1uF RESET# ACBUS1 28
R11 R12 R13 R10 12K ACBUS2 29
6 ACBUS3 30
10K 10K 10K REF ACBUS4 32
U2 ACBUS5 33
ACBUS6 34
8 1 FT_EECS 63 ACBUS7
7 VCC CS 2 FT_EECLK 62 EECS 38
6 NU CLK 3 FT_EEDATA 61 EECLK BDBUS0 39
5 ORG DI 4 EEDATA BDBUS1 40
C12 VSS DO BDBUS2 41
93LC56-SO8 R19 2.2K 2 BDBUS3 43
0.1uF OSCI BDBUS4 44
PART_NUMBER = 93LC56CT-I/SN BDBUS5 45
Manufacturer = Microchip BDBUS6 46
+3.3V
B 3 BDBUS7 B
OSCO 48
BCBUS0 52
X1 C53 BCBUS1 53
13 BCBUS2 54
1 4 0.1uF TEST BCBUS3 55
OE_ST# VDD BCBUS4 57
BCBUS5 58
2 3
FTDI High-Speed USB BCBUS6 59
GND OUTPUT BCBUS7
FT2232H PWREN#
60
12.0000MHZ J51
2 1 ICE_CLK 3,4 36
SUSPEND#
AGND
GND
GND
GND
GND
GND
GND
GND
GND
PART_NUMBER = SiT1602AC-12-33E-12.000 2 PIN JPR
Manufacturer = SiTime
10
1
5
11
15
25
35
47
51
PART_NUMBER = FT2232HL-REEL
+3.3V Manufacturer = FTDI
C5 C6 C7 C8 C9
A 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A
Title
FTDI Connection

Board Rev A
5 4 3 2 1
Figure A.2. FTDI Connection
26 FPGA-UG-02001-1.2
User Guide
5 4 3 2 1
DUT CONNECTION
+1.2V TP11 TP12 VCC
DNI DNI
R76
1
D D
1 C95 C94 C98
1uF 0.1uF 10nF
TP10 TP9 +3.3V

VCCIO_1 DNI DNI
U1
+1.2V TP13 TP14 VCC_PLL R75
DNI DNI
R77 5 22
R14
1
VCC SPI_VCCIO1
30 16 ICE_SS C99 C91 C92 1
1
1 VCC IOB_35B_SPI_SS ICE_SS 2,4,6

100 15 ICE_SCK
1 C97 C96 IOB_34A_SPI_SCK ICE_SCK 2,4,6 10nF
17 ICE_MOSI 1uF 0.1uF
IOB_33B_SPI_SI ICE_MOSI 4,6
14 ICE_MISO
10uF 100nF IOB_32A_SPI_SO ICE_MISO 4,6
+3.3V 29 8 CRESET_B
VCCPLL CRESET_B CRESET_B 2
7 CDONE
D11 CDONE CDONE 2
Bank1
1 2 24 12 IOB_22A
VPP_2V5 IOB_22A IOB_22A 4
21 IOB_23B
C93 IOB_23B IOB_23B 4
CDSU4148 13 IOB_24A
iCE40UP5K - SG48
IOB_24A IOB_24A 4
20 IOB_25B_G3
0.1uF IOB_25B_G3 IOB_25B_G3 4
19 IOB_29B
C IOB_29B IOB_29B 4 C
18 IOB_31B
IOB_31B IOB_31B 4
11 IOB_20A
IOB_20A IOB_20A 4
33 10 IOB_18A
VCCIO_0 IOB_18A IOB_18A 4
9 IOB_16A
IOB_16A IOB_16A 4
IOT_37A 23 6 IOB_13B
4 IOT_37A IOT_37A IOB_13B IOB_13B 4
IOT_36B 25
4 IOT_36B IOT_36B
IOT_39A 26
4 IOT_39A IOT_39A
IOT_38B 27
4 IOT_38B IOT_38B VCCIO_2 TP8 TP7 +3.3V
IOT_43A 32 DNI DNI
4 IOT_43A IOT_43A R74
IOT_42B 31
4 IOT_42B IOT_42B
IOT_45A_G1 37 1
4 IOT_345A_G1
1
IOT_44B 34 IOT_45A_G1 VCCIO_2
4 IOT_44B IOT_44B
IOT_49A 43 4 IOB_8A C100 C89 C90 1
4 IOT_49A IOT_49A IOB_8A IOB_8A 4
IOT_48B 36 3 IOB_9B
Bank0
Bank2
4 IOT_48B IOT_48B IOB_9B IOB_9B 4
IOT_51A 42 48 IOB_4A 1uF 0.1uF 10nF
4 IOT_51A IOB_4A 4
+3.3V TP5 TP6 VCCIO_0 IOT_50B 38 IOT_51A IOB_4A 45 IOB_5B
DNI DNI 4 IOT_50B IOT_50B IOB_5B IOB_5B 4
4 IOT_41A IOT_41A 28 47 IOB_2A
R73 IOT_41A IOB_2A IOB_2A 4
2,4 ICE_CLK IOT_46B_G0 35 44 IOB_3B_G6
IOT_46B_G0 IOB_3B_G6 IOB_3B_G6 4
46 IOB_0A
IOB_0A 4
1
IOB_0A 2 IOB_6A
C101 IOB_6A IOB_6A 4
1 C88 C87 39
4 LED_BLUE 40 RGB0
1uF 0.1uF 10nF 4 LED_GREEN 41 RGB1
B B
4 LED_RED RGB2
GND
Paddle
iCE40UP5K- SG48
+3.3V
Done LED
+3.3V
R34
10k
CRESETB Button J11
SW1
Default: Open R35
2k2
J28
CRESET_B 2 CRESET_B
1
CRST
A 1 A
PART_NUMBER = TL1015AF160QG 2 CDONE Lattice Semiconductor Applications
Manufacturer = E-Switch D3 PART_NUMBER = LG L29K-G2J1-24-Z Email: techsupport@Latticesemi.com
CRST Green Manufacturer = Osram
PART_NUMBER = 77311-801-02LF
DONE Title
Manufacturer = FCI
PART_NUMBER = 77311-801-02LF DUT Connection
Manufacturer = FCI
Board Rev A
5 4 3 2 1
Figure A.3. DUT Connection
FPGA-UG-02001-1.2 27
User Guide
5 4 3 2 1
RGB, PMOD and HEADERS
RGB LED
D
PMOD Socket D
VBUS_5V +3.3V
U10 +3.3V U11
D8
J27 R97 110 3 4 2 1 ICE_SS 1 7 IOT_38B
SM_R_0603 DI CDBU0520 ICE_MOSI 2 8 IOT_39A
D9
LED_RED 2 1 ICE_MISO 3 9 IOT_43A
3,4 LED_RED LED_GREEN 4 3 R94 62 2 5 2 1 ICE_SCK 4 10 IOT_42B
3,4 LED_GREEN LED_BLUE 6 5 SM_R_0603 DI CDBU0520
D10 5 11
3,4 LED_BLUE
6 12
Default: Shunt R95 62 1 6 2 1
HEADER 3X2 SM_R_0603 DI CDBU0520 (Bank 0)
PMOD socket
DNI
Manufacturer = Seoul Semiconductor Inc
PART_NUMBER = SFT722N-S
LED TRI-COLOUR_1
C C
+3.3V
+3.3V +3.3V +3.3V
+3.3V
MAKE PWR TRACES
CAPABLE OF 1A
C76
C73 C75 C74 0.1uF
0.1uF C72 0.1uF 0.1uF
0.1uF
J52 J2 J3
1 2 1 2
IOB_22A 3
2 1 IOT_37A 3 4 3 4
3 IOT_37A 3 IOB_8A IOB_23B 3
3,4,6 ICE_MOSI ICE_MOSI 4 3 LED_BLUE IOT_36B 5 6 5 6
3 IOT_36B 3 IOB_9B IOB_24A 3
3,4,6 ICE_MISO ICE_MISO 6 5 LED_GREEN IOT_39A 7 8 7 8
3,4 IOT_39A IOT_48B 3 3 IOB_4A IOB_25B_G3 3
2,3,4,6 ICE_SCK ICE_SCK 8 7 IOT_38B 9 10 9 10
3,4 IOT_38B IOT_51A 3 3 IOB_5B IOB_29B 3
2,3,4,6 ICE_SS ICE_SS 10 9 LED_RED IOT_43A 11 12 11 12
3,4 IOT_43A IOT_50B 3 3 IOB_2A IOB_31B 3
11 12 IOT_42B 13 14 IOT_41A 3 13 14
3,4 IOT_42B 3 IOB_3B_G6 IOB_20A 3
15 16 ICE_CLK 2,3 3 IOB_0A 15 16
3 IOT_345A_G1 IOB_18A 3
IOT_44B 17 18 3 IOB_6A 17 18
3 IOT_44B IOB_16A 3
IOT_49A 19 20 19 20
B 3 IOT_49A IOB_13B 3 B
HEADER 5X2_0
DNI
Header2x10 Header2x10
DNI DNI
(Bank 0) (Bank 2) (Bank 1)

HEADER A HEADER B HEADER C
VCCIO_0 PLACE THE RESISTORS ON THE TOP LAYER
R80 R79 R78 R72
DNI DNI DNI DNI
A 4.7K 4.7K 4.7K 4.7K SW2 A

IOT_37A 1 8 Lattice Semiconductor Applications
IOT_36B 2 1 8 7
2 7 Email: techsupport@Latticesemi.com
IOT_44B 3 6
IOT_49A 4 3 6 5
4 5 Title
SW-DIP4 RGB, PMOD and HEADERS

Board Rev A
5 4 3 2 1
Figure A.4. RGB,PMOD and HEADERS
28 FPGA-UG-02001-1.2
User Guide
5 4 3 2 1
REGULATOR CONNECTION
D D
VBUS_5V Part Reference = U7 +3.31V VCC_3.3V +3.3V
R68 L6
18 3
17 IN1_1 OUT1_1
14 IN1_2 4 C46 0.1 600 OHM 800MA
13 IN2_1 OUT1_2 R64 C47 R66 C84 C49
IN2_2 0.01uF
C65 R63 R62 20 2 357K 10uF 100 22uF 0.1uF
SHDN1 BYP1 R65 210K
10uF 1M 1M 11 1
SHDN2 ADJ1
+1.22V VCC_1.2V +1.2V +3.3V
19 R69 L7
PWRGD1 7
12 OUT2_1
PWRGD2 8 C48 0.1 600 OHM 800MA C42 C43 C44 C45
OUT2_2 C67 R67 C85
0.01uF 10uF 1uF 0.1uF 0.01uF
21 9 4.7uF 100 22uF
C THERMPAD BYP2 C
10
ADJ2
GND1
GND2
GND3
GND4
+1.2V
16
15
LT3030EFE#TRPBF
PART_NUMBER = LT3030EFE#TRPBF
Manufacturer = Linear C35 C36 C37 C38 C39 C40 C41
10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF
DNI DNI DNI
TP1 TP2 TP3
+3.3V +1.2V
1
1
B B
A A
Title
Regulator Connection

Board Rev A
5 4 3 2 1
Figure A.5. Regulator Connection
FPGA-UG-02001-1.2 29
User Guide
5 4 3 2 1
+3.3V
SPI
R25
10K
D D
C63
Aardvark Connector 0.1uF

C15
1 2
3 SS2 GND1 4 0.1uF
FLASH_MISO 5 SS3 NC2 6
2,6 FLASH_MISO MISO NC1
2,3,4 ICE_SCK ICE_SCK 7 8 FLASH_MOSI R58 R59 R60
SCLK MOSI FLASH_MOSI 2,6
2,3,4,6 ICE_SS ICE_SS 9 10
SS1 GND2 10K 10K 10K
J1 U5
8
SPI PGM
PART_NUMBER = 77313-801-10LF
VCC
FLASH_MOSI 5 2 FLASH_MISO
Manufacturer = FCI SDI SDO
2,3,4 ICE_SCK 6
SCK
J7 3
WP
1 2 1 7
GND
2,3,4,6 ICE_SS CS HOLD
C C
4
N25Q032A13ESC40F
Short-circuit Jumper
JU1 JU2 JU3
J9: Remove shunt only for Programming iCE.

Replace shunt for programming Flash and for normal operation.
63429-202LF 63429-202LF 63429-202LF
J6
2,6 FLASH_MOSI 3 1 ICE_MISO 3,4
3,4 ICE_MOSI 4 2 FLASH_MISO 2,6

B B
For programming Flash - Shunt 1,3 and 2,4 (default)
For programming iCE - Shunt 3,4 and 1,2
A A
Title
SPI

Board Rev A
5 4 3 2 1
Figure A.6. SPI
30 FPGA-UG-02001-1.2
User Guide
Appendix B. Bill of Materials

Item Reference Qty Part PCB Footprint Part Number Manufacturer Description
CAP CER 4.7UF 6.3V

1 C1,C3,C67 3 4.7uF cc0603 ECJ-1VB0J475K Panasonic
10% X5R 0603
C2,C4,C5,C6,C7, C8,C9,C11,C12,
C0402C104K4RAC CAP CER 0.1UF 16V
2 C15,C37,C38,C39,C40,C44,C49,C53,C63,C64,C66,C87,C89,C91, 25 0.1uF cc0402 Kemet
TU 10% X7R 0402
C93,C94
LMK107BJ106MAL CAP CER 10UF 10V
3 C10,C35,C42,C47,C65 5 10uF cc0603 Taiyo Yuden
TD 20% X5R 0603
C0402C105K9PAC CAP CER 1UF 6.3V
4 C36,C43 2 1uF cc0402 Kemet
TU 10% X5R 0402
C0402C103J4RACT CAP CER 10000PF
5 C41,C45,C46,C48 4 0.01uF cc0402 Kemet
U 16V 5% X7R 0402
6 C72,C73,C74,C75,C76 5 0.1uF cc0603 Kemet
TU 10% X7R 0603
LMK212BJ226MG- CAP CER 22UF 10V
7 C84,C85 2 22uF cc0805 Taiyo Yuden
T 20% X5R 0805
C0402C105K4PAC CAP CER 1UF 16V
8 C88, C95, C99, C100 4 1uF cc0402 Kemet
7867 10% X5R 0402
C0402C103J4RACT CAP CER 10000PF
9 C90, C92, C98, C101 4 10nF cc0402 Kemet
U 16V 5% X7R 0402
10 C96 1 100nF cc0402 Kemet
TU 10% X7R 0402
CL05A106MP5NU CAP CER 10UF 10V
11 C97 1 10uF cc0402 Samsung
NC X5R 0402
LED SMARTLED
12 D3 1 Green SM_D_0603 LG L29K-G2J1-24-Z Osram GREEN 570NM
0603
DIODE SCHOTTKY
13 D8,D9,D10 3 CDBU0130R diode_sod523f CDBU0130R Comchip
30V 100MA 0603
DIODE SCHOTTKY
14 D11 (Older Version) 1 CDBU0520 diode_sod523f CDBU0520 Comchip
30V 100MA 0603
DIODE SCHOTTKY
15 D11 (Later Version) 1 CDSU4148 diode_sod523f CDSU4148 Compchip
30V 150MA 0603
LED BLUE CLEAR
16 D13 1 Blue led_0603 LTST-C190TBKT LITE-On Inc.
0603 SMD
FPGA-UG-02001-1.2 31
User Guide
FERRITE CHIP
17 FB4,FB5 2 FB_60ohm L0603 HI0603P600R-10 Laird-signal
POWER 60 Ω SMD
CONN HEADER .100
18 J1 1 SPI PGM hdr5x2 77313-801-10LF FCI
DUAL STR 10POS
CONN HEADER
hdr_samtec_m MTSW-110-08-T-
19 J2,J3 2 Header2x10 Samtec 20POS .100" TH
tsw_2x10_100 D-300
DUAL
CONN MINI USB
SKT_MINIUS skt_miniusb_b 5075BMR-05-SM-
20 J5 1 Neltron RCPT RA TYPE B
B_B_RA _ra CR
SMD
TSW-102-07- hdr_samtec_ts CONN HEADER
21 J6 1 TSW-102-07-F-D Samtec
F-D w_2x2_100 4POS .100" DBL
CONN HEADER
TSW-102-07- hdr_samtec_ts
22 J7 1 TSW-102-07-G-S Samtec 2POS .100" SGL
G-S w_1x2_100
GOLD
CONN HEADER .100
23 J11 1 CRST HDR1X2-40 77311-801-02LF FCI
SINGL STR 2POS
24 J27 1 HEADER 3X2 HDR3x2 — — —
CONN HEADER .100
25 J28 1 DONE HDR1X2-40 77311-801-02LF FCI
SINGL STR 2POS
26 J51 1 2 PIN JPR 2PIN_100MIL — — —
HEADER
27 J52 1 HDR_6X2 — — —
6X2_0
600 OHM BLM18HE601SN1 FERRITE CHIP 600 Ω
28 L4,L6,L7 3 fb0603 Murata
800MA D 800MA 0603
RES 0.0 Ω 1/10W
29 R5,R6,R7,R8,R49,R70,R71 7 0 cr0603 RC0603JR-070RL Yageo
JUMP 0603 SMD
RES 2.20 K Ω 1/16W
30 R9,R19 2 2.2K cr0402 RC0402FR-072K2L Yageo
1% 0402 SMD
RES 12.0 K Ω 1/16W
31 R10 1 12K cr0402 RC0402FR-0712KL Yageo
1% 0402 SMD
RES 10.0 K Ω 1/16W
32 R11,R12,R13,R25,R58,R59,R60 7 10K cr0402 RC0402FR-0710KL Yageo
1% 0402 SMD
CRCW0603100RFK RES 100 Ω 0.25W
33 R14 1 100 R0603 Vishay
EAHP 1% 0603 SMD
32 FPGA-UG-02001-1.2
User Guide
RES 10 K Ω 1/10W
34 R34 1 10k R0603 ERJ-3EKF1002V Panasonic
1% 0603 SMD
RES 2.2 K Ω 1/10W
35 R35 1 2k2 R0603 ERJ-3EKF2201V Panasonic
1% 0603 SMD
RES SMD 1 K Ω 5%
36 R54 1 1K cr0402 ERJ-2GEJ102X Panasonic
1/10W 0402
RES 1.0M Ω 1/16W
37 R62,R63 2 1M cr0402 RC0402JR-071ML Yageo
5% 0402 SMD
RES SMD 357 K Ω
38 R64 1 357K cr0603 ERJ-3EKF3573V Panasonic
1% 1/10W 0603
RES SMD 210 K Ω
39 R65 1 210K cr0402 ERJ-2RKF2103X Panasonic
1% 1/10W 0402
RC0603FR- RES 100 Ω 1/10W
40 R66,R67 2 100 cr0603 Yageo
07100RL 1% 0603 SMD
RES .10 Ω 1/10W
41 R68,R69 2 0.1 cr0603 ERJ-3RSFR10V Panasonic
1% 0603 SMD
CRCW06034K70FK RES 4.70 K Ω 1/10W
42 R72,R78,R79,R80 4 4.7K cr0603 Vishay
EA 1% 0603 SMD
RES SMD 1 Ω 1%
43 R73,R74,R75,R76,R77 5 1 cr0603 RC0603FR-071RL Yageo
1/10W 0603
RES 62 Ω 1/10W 1%
44 R94,R95 2 62 SM_R_0603 ERJ-3EKF62R0V Panasonic
0603 SMD
RES 110 Ω 1/10W
45 R97 1 110 SM_R_0603 ERJ-3EKF1100V Panasonic
1% 0603 SMD
2psmd_eswitc SWITCH TACTILE
46 SW1 1 CRST TL1015AF160QG E-Switch
h SPST-NO 0.05 A 12V
CTS SWITCH SIDE
sw_sp_st_cts_
47 SW2 1 SW-DIP4 195-4MST Electrocompo ACTUATED 4 SEC
195-4mst
nents 50V
Square test point,
40mil inner
48 TP1,TP2,TP3 3 TP_S_40_63 tp_s_40_63 — — diameter,
63mil outer
diameter
Square test point,
49 TP5,TP6,TP7,TP8,TP9,TP10,TP11,TP12,TP13,TP14 10 DNI tp_s_40_63 — — 40mil inner
diameter,
FPGA-UG-02001-1.2 33
User Guide
63mil outer
diameter
iCE40UP5K/ iCE40UP5K_SG
50 U1 1 — — —
3K- SG48 48
tqfp64_0p5_12 IC USB HS DUAL
51 U2 1 FT2232HL FT2232HL-REEL FTDI
p2x12p2_h1p6 UART/FIFO 64-LQFP
IC EEPROM 2KBIT
52 U3 1 93LC56-SO8 so8_50_244 93LC56CT-I/SN Microchip
3MHZ 8SOIC
Seoul
LED TRI- LED RED/GRN/BLU
53 U4 1 6-PLCC SFT722N-S Semiconducto
COLOUR_1 CLEAR LENS 6PLCC
r Inc.
IC Flash Mem Serial-
N25Q032A1 N25Q032A13ESC4 SPI 3V/3.3V 32M-Bit
54 U5 1 so8_50_244 Micron
3ESC40F 0F 4M 7ns 8-Pin SO
T/R
PMOD
55 U6 1 HDR_2X6 — — —
socket
LT3030EFE# tssop20_26_26 IC REG LDO ADJ
56 U7 1 LT3030EFE#TRPBF Linear
TRPBF 0_thrm_pad 20TSSOP
SiT1602AC-12- OSC MEMS 12MHZ
57 X1 1 12.0000MHZ 2_5mmx2mm SiTime
33E-12.000 H/LV-CMOS SMD
58 iCE40 ULTRAPLUS BREAKOUT BOARD PCB 1 — — 305-PD-16-0084 PACTRON —
34 FPGA-UG-02001-1.2
User Guide
References
The standards used in this document and their abbreviations are listed on the table below.
Abbreviation Standards Publication, Organization, and Date
HDMI High Definition Multimedia Interface, Revision 1.4a, HDMI Licensing LLC., March 2010
HCTS HDMI Compliance Test Specification, Revision 1.4a, HDMI Licensing LLC., March 2010
High-bandwidth Digital Content Protection, Revision 2.2, Digital Content Protection, LLC; February 2013
HDCP
High-bandwidth Digital Content Protection, Revision 1.4, Digital Content Protection, LLC; July 2009
DVI Digital Visual Interface, Revision 1.0, Digital Display Working Group, April 1999
E-EDID Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; February 2000
CEA-861-D A DTV Profile For Uncompressed High Speed Digital Interfaces, EIA/CEA, July 2006
EDDC Enhanced Display Data Channel Standard, Version 1, VESA, September 1999
MHL MHL (Mobile High-definition Link) Specification, Version 3.0, MHL, LLC, August 2013
For more information on the specifications that are applied in this document, contact the responsible standards groups
listed on the table below.
Standards Group Web URL
ANSI/EIA/CEA http://global.ihs.com
VESA http://www.vesa.org
HDCP http://www.digital-cp.com
DVI http://www.ddwg.org
HDMI http://www.hdmi.org
MHL http://www.mhlconsortium.org
FPGA-UG-02001-1.2 35
User Guide
Technical Support Assistance

Submit a technical support case through www.latticesemi.com/techsupport.
36 FPGA-UG-02001-1.2
User Guide
Revision History
Revision 1.2 April 2022
Section Change Summary
All  Adjustments in formatting across the document.
 Updated document ID of reference document iCE40 UltraPlus Family Datasheet from
DS1056 to FPGA-DS-02008.
 Updated last page of the document.
Acronyms in This Document Added this section.
Disclaimers Added this section.
Board Power Added a paragraph regarding BOM.
Serial Communication Interface Changed section name form GUI Serial Communication Interface to Serial Communication
Interface.
Appendix A. Schematic Diagram Updated Figure A.3. DUT Connection to change CDBU0520 to CDSU4148.
Appendix B. Bill of Materials Updated table to create two new rows for D11.
Revision History Updated table to new template.
Revision 1.1, March 2017

All  Corrected document status; removed “Preliminary”.
 iCE40 UtraPlus Family Datasheet document number changed to DS1056.
Software Requirements Updated Lattice iCEcube2 to version 2017.01 and Diamond Programmer version to 3.9.
Appendix A. Schematic Diagram Updated figures.
Lattice Semiconductor Removed this section.
Documents
Revision 1.0, September 2016

All Initial release.
FPGA-UG-02001-1.2 37
www.latticesemi.com

FPGA UG 02001 1 2 ICE40 UltraPlus Breakout Board

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

FPGA UG 02001 1 2 ICE40 UltraPlus Breakout Board

Uploaded by

Copyright:

Available Formats

iCE40 UltraPlus Breakout Board

Acronyms in This Document

3. iCE40 UltraPlus Device

5. Demonstration Design Shunts

J28 – Enable DONE LED

J27 - RGB Shunts

8. Board Configuration and Programming

J28 – Enable DONE LED

J51 – Enable J7 – Isolate SPI Flash CSn

Figure 8.1. Board Configuration for Programming Flash

To program SPI flash in Diamond Programmer:

6. Click OK to exit Device Properties dialog.

Figure 8.2. Device Property Settings for Programming Flash

Double-click to Double-click to Double-click to

Figure 8.3. Setting Status in Diamond Programmer for Programming Flash

Figure 8.4. Device Property Settings for Programming iCE40 UltraPlus

Figure 9.1. J52 Header ‘A’ Breakouts

Figure 9.2. J2 Header ‘B’ Breakouts

Figure 9.3. J3 Header ‘C’ Breakouts

Figure 9.4. U6 PMOD Connector

Figure 9.5. J1 Adardvark Connector

J3 - "Header C" J2 - "Header B"

J52 - "Header A"

Figure 9.6. Breakout Headers

10. RGB LED Demonstration Design and Software User Interface

Figure 10.1. SPI Flash Selection (Horizontal) for J6

Figure 10.2. iCE40 UltraPlus Selection (Vertical) for J6

5. Start the RGB user interface on the PC or MAC.

Figure 10.3. iCE40 UltraPlus LED Demonstration Interface

11. Serial Communication Interface

11.1. LED Control through SPI

Figure 11.1. SPI Physical Transaction

11.2. SPI Protocol

REG[15:0] – Consists of four control fields.

11.3. Register Definitions

Table 11.4. LED Brightness Code Definition

Table 11.5. Breathe Ramp Code Definition

Table 11.6. Blink Rate Code Definition

12. Ordering Information

iCE40 UltraPlus Breakout Board iCE40UP5K-B-EVN

Appendix A. Schematic Diagrams

Size Project Schematic Rev A

Figure A.1. Block Diagram

Size Project Schematic Rev A

Figure A.2. FTDI Connection

1uF 0.1uF 10nF

TP10 TP9 +3.3V

1 VCC IOB_35B_SPI_SS ICE_SS 2,4,6

Figure A.3. DUT Connection

RGB, PMOD and HEADERS

(Bank 0) (Bank 2) (Bank 1)

VCCIO_0 PLACE THE RESISTORS ON THE TOP LAYER

R80 R79 R78 R72

DNI DNI DNI DNI

A 4.7K 4.7K 4.7K 4.7K SW2 A

Size Project Schematic Rev A

Figure A.4. RGB,PMOD and HEADERS

VBUS_5V Part Reference = U7 +3.31V VCC_3.3V +3.3V

10uF 1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF

DNI DNI DNI

TP1 TP2 TP3

Size Project Schematic Rev A

Figure A.5. Regulator Connection

Aardvark Connector 0.1uF