B.M.

S COLLEGE OF ENGINEERING
(Autonomous College Affiliated to Visvesvaraya Technological University, Belgaum)
Bull Temple Road, Basavanagudi, Bangalore-560019

Course Title: System Verilog & Verification

Course code: 19EC6PE3SV

AAT - I
Simulation of System Verilog programs and Coverage
Analysis using Cadence Tools

Submitted by
SANJANA VK 1BM19EC141

Course Instructor
Dr. Kiran Bailey
Assistant Professor

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
EVEN SEM (2021-22)
 CONTENTS

1. Implement JK flipflop with asynchronous active low reset and test the
design using interface block and modport

2. Design mod 9 Up/Down counter with asynchronous active high reset and test
the design using interface block and modport

3. Design a mod 6 synchronous Up/Down counter and test the design

using SV test bench architecture with interface, clocking block and
modports

4. Simulation of programs relating to OOPs concepts

5. For a 4- bit shift register, randomize the following inputs using

transactor class:
- Serial input
- Parallel load
- Direction pins
Use virtual interface to drive the inputs to the design using driver class
and thus develop the System Verilog test bench environment.
1. Implement JK flipflop with asynchronous active low reset and test the design
using interface block and modport

Block diagram:

System Verilog Code:

//Interface

//RTL design

//Test bench
 //Top module

Simulation waveforms:
Coverage Reports:
2. Design a mod 9 Up/Down counter with asynchronous active high reset and test
the design using interface block and modport

Block diagram:

System Verilog Code:

//RTL design
//Interface

//Test bench

//Top module
Simulation waveforms:
Coverage Reports:
3. Design a mod 6 synchronous Up/Down counter and test the design using
SV test bench architecture with interface, clocking block and modports

Block diagram:

System Verilog Code:

//RTL design
//Interface

//Test bench
Simulation waveforms:
Coverage Reports:
4. Simulation of programs relating to OOPs concepts

a. Overriding – without using super keyword

Using super keyword

b. Polymorphism – without using virtual keyword
Using virtual keyword
5. For a 4- bit shift register, randomize the following inputs using
transactor class:
- Serial input
- Parallel load
- Direction pins
Use virtual interface to drive the inputs to the design using driver class
and thus develop the System Verilog test bench environment.

Block diagram:

System Verilog Code:

//RTL design
//Interface

//transactor class, driver class and test bench were defined in the same file
//Top module
Simulation waveforms:
Coverage Reports: