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BANK 2 BANK 3
JP6 JP18
JP2
BIOS
MH0407
BANK 1 BANK 0
P-1 P-0
JP3
JP4
J19
JP5
JP14
JP8 CON1 JP15
JP12 JP9
CON2 JP16 JP1
KBD
CPU
JP7 JP10
J18
JP11 JP20
NPU JP19
CONNECTIONS
Purpose Location Purpose Location
IDE interface CON1 Turbo switch JP5
Floppy drive interface CON2 Turbo LED JP8
Speaker JP2 External battery JP9
IDE LED JP3 Reset switch JP12
Power LED & keylock JP4
Copyright © 1992, Micro House International (303) 443-3388. All rights reserved. Including the right of reproduction in any form.
380 The Micro House Encyclopedia of Main Boards
MORSE TECHNOLOGIES, INC.
KP 286HF
. . . continued from previous page
DRAM CONFIGURATION
Size Bank 0 Parity (P-0) Bank 1 Parity (P-1) Bank 2 Bank 3
512KB (4) 44256 (2) 41256 NONE NONE NONE NONE
1MB (4) 44256 (2) 41256 (4) 44256 (2) 41256 NONE NONE
1.5MB (4) 44256 (2) 41256 (4) 44256 (2) 41256 (2) 256K x 9 NONE
2MB (4) 44256 (2) 41256 (4) 44256 (2) 41256 (2) 256K x 9 (2) 256K x 9
3MB (4) 44256 (2) 41256 (4) 44256 (2) 41256 (2) 1M x 9 NONE
5MB (4) 44256 (2) 41256 (4) 44256 (2) 41256 (2) 1M x 9 (2) 1M x 9
IDE CONFIGURATION
Setting JP14 JP15
Enabled Closed Closed
Disabled Open Open
NPU CONFIGURATION
Setting JP19 JP20
Asynchronous pins 1 & 2 closed pins 1 & 2 closed
Synchronous pins 2 & 3 closed pins 2 & 3 closed
Copyright © 1992, Micro House International (303) 443-3388. All rights reserved. Including the right of reproduction in any form.