I N A RspY icat

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MITSUBISHI SOUND PROCESSOR ICS
I M inal ject
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P R E; This iisc nlimo its are M65831AP/FP
ice tr
Not parame
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e DIGITAL ECHO (DIGITAL DELAY)
DESCRIPTION
The M65831A is an IC developed for producing echo effects added to voice signals
picked up by microphone for karaoke applications.
The IC has the largest memory among the digital delay series. As it’s design is aimed
at high performance, it is best suited to provide radio cassette tape recorders and
miniature unit audio system with quality echo function.
Being pin compatible with the M65830CP / FP and M65843AP / FP, the M65831AP / FP is
suitable for upgrading the series.
Outline
FEATURES
•Built-in input / output filters, A-D and D-A conver ters, and
memory realize a delay system with only a single chip
•Capable of composing low-noise and low-distortion delay
system at low cost by ADM system
(No=-92dB typ, THD=0.5% typ) Outline 24P4 (AP)
•Control mode selections available from 2 kinds : easy mode 2.54mm pitch 600mil DIP
using parallel data and microcomputer mode using serial (13.0mm X 31.1mm X 3.8mm)
data
•Sleep mode can be selected to stop IC functions
•Built-in automatic reset circuit

RECOMMENDED OPERATING CONDITIONS

Outline 24P2W-A(AFP)
Supply voltage range VCC,VDD=4.5 to 5.5V
1.27mm pitch 450mil SOP
Rated supply voltage VCC,VDD=5.0V (8.4mm X15.0mm X2.0mm)

SYSTEM CONFIGURATION
RAM

L HPF MIX BASS MIX L

VOCAL
LPF KEY CONTROL
CUT

R HPF MIX BASS MIX R

CTL

NORM SEARCH VISS VISS

MIC1 MIC VOL M65381AP/FP

MIC AMP MIX MIX

MIC2 MIC VOL ECHO ECHO VOL

MIC AMP

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Pin Configuration

VDD 1 24 Vcc
XIN 2 23 LPF1 IN
XOUT 3 22 LPF1 OUT
D1/REQ 4 21 OP1 OUT
M65831AP/FP

D2/SCK 5 20 OP1 IN
D3/DATA 6 19 REF
D4/IDSW 7 18 CC1
TEST 8 17 CC2
EASY/µ -COM 9 16 OP2 IN
SLEEP 10 15 OP2 OUT
D-GND 11 14 LPF2 IN
A-GND 12 13 LPF2 OUT

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BLOCK DIAGRAM
LPF1 LPF1 OP1 OP1 OP2 OP2 LPF2 LPF2
IN OUT OUT IN CC1 CC2 IN OUT IN OUT
23 22 21 4.7k
20 18 17 16 15 14 13
4.7k

MOD DEM

OP1 OP2 LPF2

LPF1
COMP
REF 19
1/2 Vcc
D1 DO0 DO1
RESET MAIN CONTROL
MO 48K-bit
AUTO
CLOCK DELC MI SRAM
RESET

DELAY TIME
OSCILLATOR
CONTROL

2 3 4 5 6 7 8 9 10 11 12 1 24
XIN XOUT D1/REQ D3/DATA TEST SLEEP D-GND A-GND VDD Vcc
D2/SCK D4/IDSW EASY/µ -COM

Unit Resistance:Ω

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PIN DESCRIPTION

No. Symbol Name I/O Function

1 VDD Digital VDD Supply voltage

2 XIN Oscillator input I

3 XOUT Oscillator output O Connects to 2MHz ceramic filter
Easy mode:inputs D1 data
4 D1/REQ Delay1/Request I µ -COM mode:inputs request data

Easy mode:inputs D2 data

5 D2/SCK Delay2/Shift clock I µ -COM mode:inputs shift clock

Easy mode:inputs D3 data

6 D3/DATA Delay3/Serial data I µ -COM mode:inputs serial data

Easy mode:inputs D4 data

7 D4/IDSW Delay4/ID switch I µ -COM mode:controls ID code

8 TEST Test I L=normal mode

H=easy mode
9 EASY/ µ -COM Easy/ µ -COM I L=µ -COM mode

H=sleep mode
10 SLEEP Sleep I L=normal mode
11 D GND Digital GND Connects to analog GND at one point
12 A GND Analog GND Connects to analog GND
13 LPF2 OUT Low pass filter2 output O Forms low pass filter with external C.R
14 LPF2 IN Low pass filter2 input I
15 OP2 OUT OP-AMP2 output O Forms integrator with external C.R
16 OP2 IN OP-AMP2 input I
17 CC2 Current control 2
18 CC1 Current control 1
19 REF Reference =1/2VCC
20 OP1 IN OP-AMP1 input I Forms integrator with external C.R
21 OP1 OUT OP-AMP1 output O
22 LPF1 OUT Low pass filter1 output O Forms low pass filter with external C.R
23 LPF1 IN Low pass filter1 input I
24 VCC Analog VCC Supply voltage

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ABSOLUTE MAXIMUM RATINGS
(Vcc=5V,f=1kHz,Vi=100mVrms,Ta=25°C,unless otherwise noted)
Symbol Parameter Conditions Ratings Units
Vcc Supply voltage 6.5 V
Icc Circuit cuurent 100 mA
M65831AP 1 W
Pd Power dissipation M65831AFP 650 mW
Topr Operating temperature -20~+75 °C
Tstg Storage temperature -40~+125 °C

THERMAL DERATING
POWER DISSIPATION Pd (mW)

(MAXIMUM RATING)
1000
AP

800

650 AFP
600

400
325

200

0
0 25 50 75 100 125

AMBIENT TEMPERATURE Ta (°C )

RECOMMENDED OPERATING CONDITIONS

Limits
Symbol Parameter Conditions Units
Min Typ Max
Vcc Supply voltage 4.5 5 5.5 V
VDD Supply voltage 4.5 5 5.5 V
Vcc-VDD Difference voltage -0.3 0 0.3 V
fck Clock frequency 1 2 3 MHz
VIH High input voltage 0.7VDD VDD V
VIL Low input voltage 0 0.3VDD V

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ELECTRICAL CHARACTERISTICS
(Vcc=5V,f=1kHz,Vi=100mVrms,Ta=25°C,unless otherwise noted)
Symbol Parameter Limits
Test conditions Units
Min Typ Max
Icc Circuit current No signal 18.0 40.0 mA

Gv Voltage gain RL=47kΩ -3.5 -0.5 2.5 dB

Vomax Maximum output voltage THD=10% 0.7 1 Vrms

fs=500kHz 0.3 1.0

THD Output distortion 30kHz LPF %
fs=250kHz 0.5 1.5

No Output noise voltage DIN-AUDIO -92 -75 dBV

(fs=250kHz)
Supply voltage rejection
SVRR ratio
∆Vcc=-20dBV,f=100Hz -40 -25 dB
Upon changing Delay
Time 508 528 548
TMUTE Mute time ms
Upon canceling Sleep
Mode
508 528 548
Circuit current
Iccs (Sleep mode) Sleep Mode 14.0 30.0 mA

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OPERATION
1) DELAY TIME

D4 D3 D2 D1 fs Td
L 12.3
L
H 24.6
L
L 36.9
H
H 49.2
L 500
L 61.4
L
H 73.7
H
L 86.0
H
H 98.3

L 110.6
L
H 122.9
L
L 135.2
H
H 147.5
H 250
L 159.7
L
H 172.0
H
L 184.3
H
H 196.6

fs=sampling frequency(kHz)
Td=delay time(msec)

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2) EASY MODE(EASY / µ -COM=H)

D1,D2,D3,D4 and sleep are for easy mode

D1
D2 delay time cf 11-1)
D3
D4
SLEEP cf 11-5)

3) µ -COM MODE(EASY / µ -COM=L)

REQ

SCK

DATA SLEEP D1 D2 D3 D4 MUTE ID1 ID2 ID3 ID4

DELAY TIME cf 11-1) ID CODES

H=SLEEP MODE cf 11-5) H=MUTE cf 11-4)

TIMING DIAGRAM

This Timing chart shows that delay time is set by serial data from µ -COM.
DATA signal is latched at the falling edge of SCK signal,the last ten data are set at
the rising edge of REQ signal when ID codes are satisfied.
ID1,ID3:L *
ID2 :H
*
ID4 :equal to IDSW

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REQ,SCK,DATA INPUT TIMING

t5

REQ
t1 t4

SCK
t2 t3
ds
DATA SLEEP D1 D2 D3 D4 MUTE ID1 ID2 ID3 ID4

Symbol Parameter min typ max Units

t1 SCK pulse width 250 nsec

ds SCK pulse duty 50 %

t2 DATA setup time 100 t1/2 nsec

t3 DATA hold time 100 t1/2 nsec

t4 REQ hold time 100 nsec

t5 REQ pulse width 250 nsec

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4) MUTING
(1)Easy mode
Automatic mute upon changing delay time,cancelling SLEEP mode
and power-on.

(2)µ -COM mode

MUTE=H:mute
MUTE=L:automatic mute

AUTOMATIC MUTE
DELAY SIGNAL BEFORE DELAY SIGNAL AFTER
CHANGE MODE CHANGE MODE

MUTE TIME

(a) UPON CHANGING DELAY TIME

DELAY SIGNAL

MUTE TIME
CANCEL
SLEEP MODE
(b) UPON CANCELLING SLEEP MODE
DELAY SIGNAL

120msec MUTE TIME

POWER ON
(c) UPON POWER-ON

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5) SLEEP MODE

SLEEP data is

H:clock and RAM stop to reduce circuit current (SLEEP mode)

L:normal operation

6) SYSTEM RESET
Automatically reset power-on. The reset time is about
120msec.
Delay time is set at 147.5msec.

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S30 1
ice
Vi
2 1µ 5600p
50
Not parame

5600p 0.01µ
tr

15k 15k 15k

0.1µ Vo
I

15k 0.1µ 10k 1µ 2.7k

10k 47k
100µ 47µ 0.1µ 0.1µ
N

0.1µ 30
30
P R E; This iisc nlimo its are

Vcc 560p 560p

A
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A RspY

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2 VCC 4.7k 4.7k

icat
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OP1 LPF2
1/2 Vcc LPF1 OP2

12
COMP
TEST CIRCUIT

D1 DO0 DO1

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ELECTRIC
RESET MO 48K-bit
MAIN CONTROL SRAM
CLK DELC MI
AUTO
RESET

DELAY TIME
OSCILLATOR CONTROL
DIG.GND
ANG.GND

VDD

1 2 3 4 5 6 7 8 9 10 11 12
1M S4 S5 S6 S7 S10
0.1µ
DIGITAL ECHO (DIGITAL DELAY)

2 1 2 1 2 1 2 1 2 1
M65831AP/FP

2MHz GND
Units : Resistance Ω 100p 100p VDD
Capacitance F
MITSUBISHI SOUND PROCESSOR ICS
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TEST METHODS
Switch condition * 1 or 2
Sampling S S S S S S S
No Parameter frequency Symbol 4 5 6 7 10 24 30
notes
1 Current circuit Icc 1 1 1 1 1 2 2 No signal
Gv1
2 Voltage gain
500kHz * * * 1 1 1 1
250kHz Gv2 * * * 2 1 1 1
Tda 1 1 1 1 1 1 1
Tdb 2 1 1 1
Tdc 1 2 1 1
Tdd 2 2 1 1
500kHz
Tde 1 1 2 1
Tdf 2 1 2 1
Tdg 1 2 2 1
Tdh 2 2 2 1 cf. 11-1)
3 Delay time
Tdi 1 1 1 2
Tdj 2 1 1 2
Tdk 1 2 1 2
Tdl 2 2 1 2
250kHz
Tdm 1 1 2 2
Tdn 2 1 2 2
Tdo 1 2 2 2
Tdp 2 2 2 2 1 1 1
Output voltage 500kHz Vomax 1 * * * 1 1 1 1 30kHz L.P.F.
4 (max) 250kHz Vomax 2 * * * 2 1 1 1 THD=10%
Total harmonic 500kHz THD 1 * * * 1 1 1 1 30kHz L.P.F.
5 distortion
250kHz THD 2 * * * 2 1 1 1
Output noise DIN AUDIO
6 voltage 250kHz No * * * 2 1 1 1 Vi=0mVrms

Supply voltage ∆Vcc=-20dBv,

7 rejection ratio SVRR * * * * 1 1 2 f=100Hz

MUTE T 2 1 * * * 1 1 1
Upon changing Delay Time
8 Mute time 2 Upon cancelling Sleep Mode
MUTE S * * * * 1 1 1

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APPLICATION EXAMPLE
1.EASY MODE
1µ 30k 3k
IN non-porlar 0.01µ
1µ 15k 5600p 0.01µ
5600p 15k
0.1µ
15k 15k 1µ 2.7k
10k 0.1µ 47µ 0.1µ 0.1µ 10k OUT
30
560p 30 560p
24 23 22 21 20 19 18 17 16 15 14 13
OP1 OUT

OP1 IN

CC1
LPF1 OUT

CC2
LPF1 IN

OP2 OUT

LPF2 OUT
EASY/µ-COM OP2 IN

LPF2 IN
REF
Vcc

SLEEP

DGND

AGND
XOUT

TEST
VDD

XIN

D1

D2

D3

D4

1 2 3 4 5 6 7 8 9 10 11 12
SLEEP SW
1M

100µ 0.1µ
2MHz
100p 100p
SETTING DELAY TIME

2.µ -COM MODE 1µ 30k 3k

IN non-porlar 0.01µ
1µ 15k 5600p 0.01µ
5600p 15k
0.1µ
15k 0.1µ 10k 15k 1µ 2.7k
10k 47µ 0.1µ 0.1µ OUT
30
560p 30 560p
24 23 22 21 20 19 18 17 16 15 14 13
LPF1 OUT

OP1 OUT

CC1

OP2 OUT
EASY/ µ -COM OP2 IN
OP1 IN

LPF2 OUT
CC2
LPF1 IN

LPF2 IN
REF
Vcc

SLEEP

DGND

AGND
XOUT

DATA

IDSW

TEST
REQ

SCK
VDD

XIN

1 2 3 4 5 6 7 8 9 10 11 12
SLEEP SW

1M

100µ 0.1µ
2MHz
100p 100p
µ -COM Units Resistance Ω
Capacitance F
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