MP172

MP172
700 V Non-Isolated Off-Line Regulator

Up to 120 mA Output Current
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NOT RECOMMENDED FOR NEW DESIGNS. REFER TO MP172A
DESCRIPTION FEATURES
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MP172 is a primary-side regulator that provides  Primary-Side CV Control, Supporting Buck,
accurate constant voltage (CV) regulation Boost, Buck-Boost, and Flyback Topologies

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without an opto-coupler. It supports buck, boost, Integrated 700 V MOSFET and Current
buck-boost, and flyback topologies. It has an Source
integrated 700 V MOSFET to simplify the  < 30 mW No-Load Power Consumption
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structure and reduce costs. These features  Up to 3 W Output Power
make it an ideal regulator for off-line, low-power  Maximum DCM Output Current Less than
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applications, such as home appliances and 80 mA
standby power.  Maximum CCM Output Current Less than
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MP172 is a green-mode-operation regulator. 120 mA
Both the peak current and the switching  Low VCC Operating Current
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frequency decrease as the load decreases.  Frequency Foldback
This feature provides excellent efficiency at light  Limited Maximum Frequency
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
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load and improves the overall average Peak-Current Compression
efficiency.  Internally Biased VCC
 TSD, UVLO, OLP, SCP, Open-Loop
MP172 has various protection features
Protection
including thermal shutdown (TSD), VCC under-
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voltage lockout (UVLO), overload protection APPLICATIONS

(OLP), short-circuit protection (SCP), and open-

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Home Appliances, White Goods, and
loop protection.
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Consumer Electronics
MP172 is available in a small TSOT23-5  Industrial Controls
package and SOIC-8 package.  Standby Power
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All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance. “MPS”
and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
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TYPICAL APPLICATION
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DRAIN VCC D2
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C2 R1
FB C3
MP172
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R2
L1
SOURCE SOURCE
VOUT
Input C1
D1 C4
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MP172 Rev. 1.01 www.MonolithicPower.com 1

9/17/2018 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2021 MPS. All Rights Reserved.
MP172– NON-ISOLATED OFF-LINE REGULATOR
ORDERING INFORMATION
Part Number Package Top Marking
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MP172GJ* TSOT23-5 See Below
MP172GS** SOIC-8 See Below
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* For Tape & Reel, add suffix –Z (e.g. MP172GJ–Z).
** For Tape & Reel, add suffix –Z (e.g. MP172GS–Z).
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TOP MARKING (TSOT23-5)
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APK: product code of MP172GJ;
Y: year code;
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TOP MARKING (SOIC-8)
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MP172: part number;

LLLLLLLL: lot number;
MPS: MPS prefix:
Y: year code;
WW: week code:
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PACKAGE REFERENCE
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TOP VIEW TOP VIEW

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VCC 1 8 NC
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FB 2 7 DRAIN
SOURCE 3 6 NC
SOURCE 4 5 NC
TSOT23-5 SOIC-8

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC

DRAIN to SOURCE (TJ=+25°C) . -0.3 V to 700 V TSOT23-5 .............................. 100 ..... 55... °C/W
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All other pins ................................ -0.3 V to 6.5 V SOIC-8 .................................... 96 ...... 45... °C/W
Continuous power dissipation ..... (TA = +25°C)(2) NOTES:
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TSOT23-5 .................................................... 1 W 1) Exceeding these ratings may damage the device.
SOIC-8 ......................................................... 1 W 2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
Junction temperature ................................150°C
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ambient thermal resistance θJA, and the ambient temperature
Lead temperature .....................................260°C TA. The maximum allowance continuous power dissipation at
Storage temperature ................ -60°C to +150°C any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/θJA. Exceeding the maximum allowance power dissipation
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will produce an excessive die temperature, causing the
Recommended Operating Conditions (3) regulator to go into thermal shutdown. Internal thermal
Operating junction temp (TJ). ... -40°C to +125°C shutdown circuit protects the device from permanent damage.
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3) The device is not guaranteed to function outside of its
Operating VCC range ................... 5.5 V to 5.7 V operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
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ELECTRICAL CHARACTERISTICS
VCC = 5.5 V, TJ = -40°C~125°C, min and max are guaranteed by characterization, typical is tested
under 25°C, unless otherwise specified.
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Parameter Symbol Condition Min Typ Max Units
Start-up Current Source and Internal MOSFET (DRAIN)
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Internal regulator supply current Iregulator VCC = 4 V; VDrain = 100 V 2.2 4.1 6 mA
VCC = 5.8 V; VDrain = 400
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DRAIN leakage current ILeak 10 17 μA
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Breakdown voltage V(BR)DSS TJ = 25°C 700 V
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On resistance Ron TJ = 25°C 16 20 Ω
Supply Voltage Management (VCC)
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VCC level (increasing) where the internal
VCCOFF 5.4 5.7 6 V
regulator stops
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VCC level (decreasing) where the
VCCON 5.1 5.5 5.8 V
internal regulator turns on
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VCC regulator on and off hysteresis 130 250 mV
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VCC level (decreasing) where the IC
VCCstop 3 3.4 3.6 V
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stops
VCC level (decreasing) where the
VCCpro 2 2.5 2.8 V
protection phase ends
Internal IC consumption ICC fs = 36 kHz, D = 64% 720 μA
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Internal IC consumption (no switching) ICC 200 µA

μA
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Internal IC consumption, latch-off phase ICCLATCH VCC = 5.3 V 16 24
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Internal Current Sense

Peak current limit ILimit TJ = 25°C 188 210 232 mA
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Leading-edge blanking τLEB1 350 ns

SCP threshold ISCP TJ = 25°C 330 400 510 mA
Leading-edge blanking for SCP (1)
τLEB2 180 ns
Feedback Input (FB)
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Minimum off time τminoff 7.5 10 12.5 μs

Maximum on time τmanon 13 18 23 μs
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Primary MOSFET feedback turn-on

VFB 2.45 2.55 2.65 V
threshold
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OLP feedback trigger threshold VFB_OLP 1.64 1.74 1.84 V

OLP delay time τOLP fs = 36 kHz 175 ms
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Open-loop detection VOLD 0.4 0.5 0.6 V

Thermal Shutdown
Thermal shutdown threshold (1) 150 °C
Thermal shutdown recovery hysteresis (1) 30 °C
NOTE:
1) This parameter is guaranteed by design.

TYPICAL CHARACTERISTICS
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TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 230 VAC, VOUT = 5 V, IOUT = 120 mA, L = 1 mH, COUT = 47 μF, TA = +25°C, unless otherwise
noted.
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PIN FUNCTIONS
Pin # Pin #
Name Description
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TSOT23-5 SOIC8
1 1 VCC Control circuit power supply.
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2 2 FB Regulator feedback.
3,4 3,4 SOURCE Internal power MOSFET source and ground reference for VCC and FB.
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5 7 DRAIN Internal power MOSFET drain and high-voltage current source input.
5,6,8 NC No connection.
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FUNCTIONAL BLOCK DIAGRAM
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VCC Power Start-Up Unit DRAIN
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Management
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Driving Signal
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Management
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Feedback Control
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Peak Current
Limitation
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FB Protection Unit SOURCE
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Figure 1—Functional block diagram

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OPERATION  48us 18 us 10 us
MP172 is a green-mode-operation regulator: The Driver
peak current and the switching frequency both
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decrease with a decreasing load. As a result, it
offers excellent light-load efficiency and improves 128 Switching cycle 128 Switching cycle
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overall average efficiency. Also, the regulator Figure 2— min off at start-up
incorporates multiple features and operates with
Constant Voltage (CV) Operation
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a minimum number of external components.
The MP172 regulates the output voltage by
The MP172 acts as a fully integrated regulator
monitoring the sampling capacitor.
when used in buck topology (see Typical
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Application on page 1). At the beginning of each cycle, the integrated
MOSFET turns on while the feedback voltage
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Start-Up and Under-Voltage Lockout
drops below the 2.55 V reference voltage, which
The internal high-voltage regulator self-supplies indicates insufficient output voltage. The peak
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the IC from DRAIN. When VCC voltage reaches current limitation determines the on period. After
VCCOFF, the IC starts switching, and the internal the on period elapses, the integrated MOSFET
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high-voltage regulator turns off. The internal high- turns off. The sampling capacitor (C3) voltage is
voltage regulator turns on to charge the external charged to the output voltage when the
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VCC capacitor when the VCC voltage falls below
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freewheeling diode (D1) turns on. This way, the
VCCON. A small capacitor (in the low μF range) sampling capacitor (C3) samples and holds the
maintains the VCC voltage and thus lowers the output voltage for output regulation. The
capacitor cost. sampling capacitor (C3) voltage decreases when
The IC stops switching when the VCC voltage the L1 inductor current falls below the output
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drops blow VCCstop. current. When the feedback voltage falls below
the 2.55 V reference voltage, a new switching
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Under fault conditions—such as OLP, SCP, and
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cycle begins. Figure 3 shows this operation in

TSD—the IC stops switching and an internal continuous conduction mode (CCM).
current source discharges the VCC capacitor.
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The internal high-voltage regulator will not charge

the VCC capacitor until the VCC voltage drops MOSFET
below VCCpro. The re-start time can be estimated
using Equation (1). Diode
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 VCC  VCCpro VCCOFF  VCCPRO  (1)

restart  CVCC    
 ICCLATCH Iregulator
IL Ipeak Io
 
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Vo
Soft Start (SS)
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The IC stops operation when the VCC voltage V FB

drops below VCCstop; the IC begins operation 2.55V
when VCC charges to VCCOFF. Every time the

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chip starts operation, there is a soft-start period. Figure 3— VFB vs. VO

The soft start prevents the inductor current from
overshooting by limiting the minimum off time. Equation (2) determines the output voltage:
R1  R2
MP172 adopts a 2 phase minimum off time limit Vo  2.55V  (2)
soft start. Each soft-start phase retains 128 R2
switching cycles. During the soft start, the off
time limit gradually shortens from 48 μs to 18 μs
and finally reaches the normal operation off time
limit (see Figure 2).

Frequency Foldback and Peak Current Ramp Compensation
Compression An internal ramp compensation circuit improves
The MP172 remains highly efficient at light-load the load regulation. As shown in Figure 4, a
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conditions by reducing the switching frequency voltage sinking source is added to pull down the
automatically. reference voltage of the feedback comparator.
The ramp compensation is relative to the
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Under light-load or no-load conditions, the output
MOSFET off time, and increases exponentially
voltage drops very slowly, which increases the
as the off time increases. The compensation is
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MOSFET off time. Thus, the frequency
about 1mV/µs under min off time switching
decreases along with the load.
condition.
The switching frequency is determined with
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Over-Load Protection (OLP)
Equation (3) and Equation (4):
The maximum output power of the MP172 is
(Vin  Vo ) Vo
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fs   , for CCM (3) limited by the maximum switching frequency and
2L(Ipeak  Io ) Vin the peak current limit. If the load current is too
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large, the output voltage drops, causing the FB
2(Vin  VO ) Io Vo voltage to drop.
fs  
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, for DCM (4)
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2
LI peak Vin When the FB voltage drops below VFB_OLP, it is
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considered an error flag, and the timer starts. If
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As the peak current limit decreases from 210 mA, the timer reaches 170 ms (fS = 36 kHz), OLP
the off time increases. In standby mode, the occurs. This timer duration avoids triggering OLP
frequency and the peak current are both when the power supply starts up or the load
minimized, allowing for a smaller dummy load. As transitions. The power supply should start up in
a result, the peak current compression helps
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less than 170 ms (fS = 36 kHz). The OLP delay

reduce no-load consumption. The peak current time is calculated using Equation (6):
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limit can be estimated from Equation (5) where
τoff is the off time of the power module:
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36kHz
Delay  170ms  (6)
IPeak  210mA  (0.8mA / s)  ( off  10s) (5) fs
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EA Compensation Short-Circuit Protection (SCP)

FB The MP172 monitors the peak current and shuts
Comparator
down when the peak current rises above the
SCP threshold through short-circuit protection.
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The power supply resumes operation with the
+
EA
removal of the fault.
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VFB - Thermal Shutdown (TSD)

+
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To prevent thermal induced damage, the MP172
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Vramp
+ +
Vramp stops switching when the junction temperature
exceeds 150°C. During thermal shutdown (TSD),
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+ V
-
ref
Ipeak
the VCC capacitor is discharged to VCCpro, and
2.55V
the internal high-voltage regulator re-charges.
The MP172 recovers when the junction
Figure 4—EA and ramp compensation
temperature drops below 120°C.
MP172 has an internal error amplifier (EA)
Open-Loop Detection
compensation loop. It samples the feedback
voltage 6 µs after the MOSFET turns off and If VFB is less than 0.5 V, the IC stops switching,
regulates the output based on the 2.55 V and a re-start cycle begins. During a soft start,
reference voltage. the open-loop detection is blanked.

Leading-Edge Blanking
An internal leading-edge blanking (LEB) unit
avoids premature switching pulse termination
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due to a turn-on spike. A turn-on spike is caused
by parasitic capacitance and reverse recovery of
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the freewheeling diode. During the blanking time,
the current comparator is disabled and cannot
turn off the external MOSFET. Figure 5 shows
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the leading-edge blanking.
IDS
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350ns
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ILIMIT
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Figure 5—Leading-edge blanking
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APPLICATION INFORMATION
Table 1—Common topologies using MP172
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Topology Circuit Schematic Features
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DRAIN
5 1
VCC 1. No isolation
2. Positive output
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FB
MP172 2 3. Low cost
High-side 4. Direct feedback
SOURCE SOURCE
4 3
buck
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Vin
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Vo
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DRAIN
5 1
VCC 1. No isolation
2. Negative output
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FB
MP172 2 3. Low cost
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High-side 4. Direct feedback
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SOURCE SOURCE
4 3
buck-boost
Vin
Vo
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1. No isolation
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2. Positive output
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VCC
DRAIN
5 1
3. Low cost
4. Direct feedback
Boost
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FB
Vin MP172 2 Vo
SOURCE SOURCE
4 3
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T 1. Isolation
Vin * 2. Positive output
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3. Low cost
* 4. Indirect feedback
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Flyback
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DRAIN VCC
5 1
FB
MP172 2
*
SOURCE SOURCE
4 3

Topology Options maximum power using Equation (7) and Equation
The MP172 can be used in common topologies (8):
such as buck, boost, buck-boost, and flyback V
Po max  Vo (Ipeak  o min off ) , for CCM (7)
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(see Table 1). 2L
Component selection below is based on the 1 2 1
Pomax  LIpeak  , for DCM (8)
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typical application of MP173 (see it on page 1). 2  minoff
Component Selection For mass production, tolerance on the
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Input Capacitor parameters (such as peak current limitation and
the minimum off time) should be taken into
The input capacitor supplies the DC input voltage consideration.
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for the converter. Figure 6 shows the typical DC
bus voltage waveform of a half-wave rectifier and Freewheeling Diode
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a full-wave rectifier. Select a diode with a maximum reverse-voltage
VDC(max) rating greater than the maximum input voltage
Vin
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DC input voltage and a current rating determined by the output
current.
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The reverse recovery of the freewheeling diode
VDC(min) affects the efficiency and circuit operation during
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AC input voltage
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a CCM condition, so use an ultra-fast diode such
t as the EGC10JH.
Vin VDC(max) Output Capacitor
DC input voltage
The output capacitor is required to maintain the
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DC output voltage. Estimate the output voltage

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VDC( min) ripple using Equation (9) and Equation (10):
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AC input voltage
i
VCCM _ ripple   i  RESR , for CCM (9)
t 8fsCo
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Figure 6—Input voltage waveform 2

Io I I 
Typically, the use of a half-wave rectifier requires VDCM _ ripple    pk o   Ipk  RESR , for DCM (10)
fsCo  I 
an input capacitor rated at 3 µF/W for the  pk 
universal input condition. When using a full-wave
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It is recommended to use ceramic, tantalum, or

rectifier, an input capacitor is chosen between
low ESR electrolytic capacitors to reduce the
1.5~2 µF/W for the universal input condition. A
output voltage ripple.
half-wave rectifier is recommended for a < 2 W output
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application, otherwise use a full-wave rectifier. Feedback Resistors

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Under very low input voltage, the inductor current The resistor divider determines the output
ramps up slowly; it may not reach the current voltage. Choose appropriate R1 and R2 values to
limit during τmanon, so the MOSFET on time maintain VFB at 2.55 V. An excessively large
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should be less than the minimum value of τmanon. value for R2 should be avoided.
Inductor Sampling Capacitor
The MP172 has a minimum off-time limit that The sampling capacitor (C3) samples and holds
determines the maximum power output. A power the output voltage for feedback. With R1 and R2
inductor with a larger inductance increases the fixed, a small sampling capacitor result in poor
maximum power. Using a very small inductor regulation at light loads, and large sampling
may cause failure at full load. Estimate the capacitor affect the circuit operation. Roughly
estimate an optimal capacitor value using
Equation (11):

1 Vo C Vo C Surge Performance
 o  CFB   o (11)
2 R1  R2 Io R1  R2 Io An appropriate input capacitor value should be
chosen to obtain good surge performance. Figure
Dummy Load
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8 shows the half-wave rectifier. Table 2 shows
A dummy load is required to maintain the load the capacitance required under normal conditions
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regulation. This ensures there is sufficient for different surge voltages. FR1 is a 20 Ω/2 W
inductor energy to charge the sample and hold fused resistor, and L1 is 1 mH for this
capacitor to detect the output voltage. Normally a recommendation.
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3 mA dummy load is needed and can be
FR1 L1
adjusted according to the regulated voltage. L
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There is a compromise between small, no-load
consumption and good, no-load regulation,
especially for applications that require 30 mW no-
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load consumption. Use a Zener to reduce no- C1 C2
load consumption if no-load regulation is not a
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concern.
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Auxiliary VCC Supply N
R3 D3
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Figure 8—Half-wave rectifier
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VCC D2
C2
Table 2—Recommended capacitance
R1
MP172 FB Surge
C3 500 V 1000 V 2000 V
R2
Voltage
SOURCE SOURCE L1 C1 1 μF 2.2 μF 3.3 μF
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VOUT
C2 1 μF 2.2 μF 3.3 μF
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PCB Layout Guidelines
Figure 7—Auxiliary VCC supply circuit
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Efficient PCB layout is critical for reliable

For applications with VO above 7 V, the MP172 operation, good EMI, and thermal performance.
achieves the 30 mW no-load power requirement.
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Please follow the guidelines below to optimize

In order to do this, the chip requires an external performance.
VCC supply to reduce overall power consumption
(see Figure 7). 1) Minimize the loop area formed by the input
capacitor, IC, freewheeling diode, inductor,
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This auxiliary VCC supply is derived from the and output capacitor.
resistor connected between C2 and C3. C3
should be set larger than the value 2) Place the power inductor far away from the
input filter while keeping the loop area to the
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recommended above. D3 is used in case VCC

interferes with FB. R3 is determined using inductor at a minimum (see example below).
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Equation (12): 3) Place a capacitor valued at several hundred

Vo  VFW  5.8V pF between FB and SOURCE as close to the
R3  (12)
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IC as possible.
IS
Where IS is the VCC consumption under a no- 4) Connect the exposed pads or large copper
load condition, and VFW is the forward voltage area with DRAIN to improve thermal
drop of D3. Because IS varies in different performance.
applications, R3 should be adjusted to meet the
application’s specific IS. In a particular
configuration, IS is measured at about 200 µA.

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Top layer
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Bottom layer
Design Example
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Table 3 shows a design example for the following
application guideline specifications:
Table 3—Design example
VIN 85 VAC to 265 VAC
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VOUT 5V
IOUT 120 mA
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The detailed application schematic is shown in

Figure 9. The typical performance and circuit
waveforms have been shown in the “Typical
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Performance Characteristics” section. For

additional device applications, please refer to the
related evaluation board datasheets.
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TYPICAL APPLICATION CIRCUITS
Figure 9 shows a typical application example of a 5 V, 120 mA non-isolated power supply using the
MP172.
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D1
SRGC10JH
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R1
41.2 K C1
22 nF
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U1
8 1
NC VCC
RF1 D2 L1
7 2 C2 C7 R2
DRAIN FB 2.2 µF 470 pF 39.2 K
1 mH L2 5 V/120 mA
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L 39 SRGC10JH
6 SOURC 3
NC
E 1 mH Vout
5 SOURC 4
NC
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C3 C4 E
MP172GS
85 VAC~265VAC 2.2 µF/400 V 2.2 µF/400 V
D3
C5 C6 R3
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STTH1R06
600 V/1 A 1 µF 47 µF 1.2 K
A
D4
N SRJC10JH
N GND
GND
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Figure 9—Typical application at 5 V, 120 mA
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FLOW CHART
Power On
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Internal High Voltage Vcc Decrease
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Regulator On to VCCPRO
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Stop Operation
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Shut Down Y N
Internal High Voltage VCC>VCCOFF
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Regulator N Y
VCC>VCCSTOP Y
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Fault Logic N
Soft Start Monitor VCC High?
TO S D
A
N
Shuts Down Y N N
Internal High Voltage VCC>VCCOFF VCC<VCCON
Regulator
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TSD, SCP
Y and Open-Loop
Monitor
Internal High Voltage
Regulator On
Monitor FB Voltage
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Open-Loop Logic High Y

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N N N Y
< VFB < VFB_OLP < VOLD Counts to 6144 N
Switching
Cycle?
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Y Y
Turn On the OLP Fault Count Switching Y OLP Fault

MOSFET Logic High Cycle Logic High?
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Reset Counter
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UVLO, SCP, OLP, OTP and Open-Loop Protections are Auto Restart
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Figure 10—Control flow chart

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Unplug from
Normal 16µA Discharge Main Input
Start Up Operation Current
VCCOFF
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VCCON
VCC
VCCSTOP
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VCCPRO
Start-Up
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Driver Blanking
Pluses Time
Driver
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Internal
Regulator
Supply
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Current
On and Off
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Fault Flag
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Open-Loop Fault Over-Load Over-Load Short Circuit Thermal Shutdown
Fault Fault Fault Fault
Counter<6144 Counter=6144
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Figure 11—Signal evolution in the presence of a fault

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MP172 –NON-ISOLATED OFF-LINE REGULATOR
PACKAGE INFORMATION
TSOT23-5
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0.60 0.95
2.80 TYP BSC
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3.00
5 4
P1 S F
1.20
TYP
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1.50 2.60 2.60
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1.70 3.00 TYP
TO S D
A
1
N 3
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TOP VIEW RECOMMENDED LAND PATTERN
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0.70
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0.90 1.00 MAX

0.09
SEATING PLANE 0.20
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0.30 0.00
0.95 BSC
0.50 0.10 SEE DETAIL "A"
FRONT VIEW SIDE VIEW

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NOTE:
T
GAUGE PLANE 1) ALL DIMENSIONS ARE IN MILLIMETERS.

O
0.25 BSC 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,

PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
N
OR PROTRUSION.
0.30 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
0o-8o 0.50 SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-193, VARIATION AA.
DETAIL “A” 6) DRAWING IS NOT TO SCALE.

MP172 –NON-ISOLATED OFF-LINE REGULATOR
PACKAGE INFORMATION
SOIC-8
R
0.189(4.80) 0.050(1.27)
0.024(0.61)
0.197(5.00)
8 5
O
0.063(1.60)
P1 S F
0.150(3.80) 0.228(5.80)
0.157(4.00) 0.213(5.40)
PIN 1 ID 0.244(6.20)
M N D
IG E
1 4
TO S D
TOP VIEW RECOMMENDED LAND PATTERN
A
N
72
ER D ME
0.053(1.35)
0.069(1.75)
0.0075(0.19)
SEATING PLANE
0.0098(0.25)
0.004(0.10)
EF W M
0.013(0.33) 0.010(0.25)
0.020(0.51) SEE DETAIL "A"
0.050(1.27)
E
BSC
R NE O
FRONT VIEW SIDE VIEW

EC
0.010(0.25)
x 45o NOTE:
0.020(0.50)
R
GAUGE PLANE 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN

0.010(0.25) BSC BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH ,
T
PROTRUSIONS OR GATE BURRS.

3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
0.016(0.41) OR PROTRUSIONS.
O
0o-8o 0.050(1.27) 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING)

SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
N
DETAIL "A" 6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.


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MP172

700 V Non-Isolated Off-Line Regulator

voltage lockout (UVLO), overload protection APPLICATIONS

MP172 Rev. 1.01 www.MonolithicPower.com 1

MP172: part number;

TOP VIEW TOP VIEW

MP172 Rev. 1.01 www.MonolithicPower.com 2

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance (4) θJA θJC

MP172 Rev. 1.01 www.MonolithicPower.com 3

Internal IC consumption (no switching) ICC 200 µA

Internal Current Sense

Leading-edge blanking τLEB1 350 ns

Minimum off time τminoff 7.5 10 12.5 μs

Primary MOSFET feedback turn-on

OLP feedback trigger threshold VFB_OLP 1.64 1.74 1.84 V

Open-loop detection VOLD 0.4 0.5 0.6 V

MP172 Rev. 1.01 www.MonolithicPower.com 4

MP172 Rev. 1.01 www.MonolithicPower.com 5

MP172 Rev. 1.01 www.MonolithicPower.com 6

MP172 Rev. 1.01 www.MonolithicPower.com 7

Figure 1—Functional block diagram

MP172 Rev. 1.01 www.MonolithicPower.com 8

cycle begins. Figure 3 shows this operation in

The internal high-voltage regulator will not charge

 VCC  VCCpro VCCOFF  VCCPRO  (1)

The IC stops operation when the VCC voltage V FB

when VCC charges to VCCOFF. Every time the

chip starts operation, there is a soft-start period. Figure 3— VFB vs. VO

MP172 Rev. 1.01 www.MonolithicPower.com 9

less than 170 ms (fS = 36 kHz). The OLP delay

EA Compensation Short-Circuit Protection (SCP)

VFB - Thermal Shutdown (TSD)

MP172 Rev. 1.01 www.MonolithicPower.com 10

MP172 Rev. 1.01 www.MonolithicPower.com 11

MP172 Rev. 1.01 www.MonolithicPower.com 12

Component Selection For mass production, tolerance on the

DC output voltage. Estimate the output voltage

Figure 6—Input voltage waveform 2

It is recommended to use ceramic, tantalum, or

application, otherwise use a full-wave rectifier. Feedback Resistors

MP172 Rev. 1.01 www.MonolithicPower.com 13

Efficient PCB layout is critical for reliable

Please follow the guidelines below to optimize

recommended above. D3 is used in case VCC

Equation (12): 3) Place a capacitor valued at several hundred

MP172 Rev. 1.01 www.MonolithicPower.com 14

The detailed application schematic is shown in

Performance Characteristics” section. For

MP172 Rev. 1.01 www.MonolithicPower.com 15

MP172 Rev. 1.01 www.MonolithicPower.com 16

Open-Loop Logic High Y

Turn On the OLP Fault Count Switching Y OLP Fault

Figure 10—Control flow chart

MP172 Rev. 1.01 www.MonolithicPower.com 17

Figure 11—Signal evolution in the presence of a fault

MP172 Rev. 1.01 www.MonolithicPower.com 18

0.90 1.00 MAX

FRONT VIEW SIDE VIEW

GAUGE PLANE 1) ALL DIMENSIONS ARE IN MILLIMETERS.

0.25 BSC 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,

MP172 Rev. 1.01 www.MonolithicPower.com 19

FRONT VIEW SIDE VIEW

GAUGE PLANE 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN

PROTRUSIONS OR GATE BURRS.