PD - 96216

IRFB4115GPbF
HEXFET® Power MOSFET
Applications D
l High Efficiency Synchronous Rectification in SMPS
VDSS 150V
l Uninterruptible Power Supply RDS(on) typ. 9.3mΩ
l High Speed Power Switching G max. 11mΩ
l Hard Switched and High Frequency Circuits
S ID (Silicon Limited) 104A
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability S
D
G
l Lead-Free
l Halogen-Free
TO-220AB
IRFB4115GPbF

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 104
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 74 A
IDM Pulsed Drain Currentc 420
PD @TC = 25°C Maximum Power Dissipation 380 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery e 18 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range
°C
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw x
10lbf in (1.1N m) x
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 220 mJ
IAR Avalanche Currentc See Fig. 14, 15, 22a, 22b A
EAR Repetitive Avalanche Energy c mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Casei ––– 0.40
RθCS Case-to-Sink, Flat Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62

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IRFB4115GPbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.18 ––– V/°C Reference to 25°C, ID = 3.5mA c
RDS(on) Static Drain-to-Source On-Resistance ––– 9.3 11 mΩ VGS = 10V, ID = 62A f
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 150V, VGS = 0V
––– ––– 250 VDS = 150V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Internal Gate Resistance ––– 2.3 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 97 ––– ––– S VDS = 50V, ID = 62A
Qg Total Gate Charge ––– 77 120 nC ID = 62A
Qgs Gate-to-Source Charge ––– 28 ––– VDS = 75V
Qgd Gate-to-Drain ("Miller") Charge ––– 26 ––– VGS = 10V f
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 51 ––– ID = 62A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time ––– 18 ––– ns VDD = 98V
tr Rise Time ––– 73 ––– ID = 62A
td(off) Turn-Off Delay Time ––– 41 ––– RG = 2.2Ω
tf Fall Time ––– 39 ––– VGS = 10V f
Ciss Input Capacitance ––– 5270 ––– pF VGS = 0V
Coss Output Capacitance ––– 490 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 105 ––– ƒ = 1.0 MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance (Energy Related) ––– 460 ––– VGS = 0V, VDS = 0V to 120V h, See Fig. 11
Coss eff. (TR) Effective Output Capacitance (Time Related) ––– 530 ––– VGS = 0V, VDS = 0V to 120V g
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 104 A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 420 A integral reverse G

(Body Diode) d p-n junction diode.

f
S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 62A, VGS = 0V
trr Reverse Recovery Time ––– 86 ––– ns TJ = 25°C VR = 130V,
––– 110 ––– TJ = 125°C IF = 62A
Qrr Reverse Recovery Charge ––– 300 ––– nC TJ = 25°C di/dt = 100A/µs f
––– 450 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 6.5 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by TJmax, starting TJ = 25°C, L = 0.11mH
RG = 25Ω, IAS = 62A, VGS =10V. Part not recommended for use
above this value.
ƒ ISD ≤ 62A, di/dt ≤ 1040A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
… Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
† Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
‡ Rθ is measured at TJ approximately 90°C.

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 IRFB4115GPbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
100 6.5V 6.5V
6.0V 6.0V
5.5V 100 5.5V
BOTTOM 5.0V BOTTOM 5.0V

10

5.0V
10
1

5.0V ≤60µs PULSE WIDTH

≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1 1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0
ID = 62A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

T J = 175°C 2.5
100

2.0
(Normalized)

T J = 25°C
10

1.5

1
1.0
VDS = 50V
≤60µs PULSE WIDTH
0.1 0.5
2 4 6 8 10 12 14 16 -60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 14.0
VGS = 0V, f = 1 MHZ
ID= 62A
C iss = C gs + C gd, C ds SHORTED
12.0 VDS= 120V
C rss = C gd
VGS, Gate-to-Source Voltage (V)

VDS= 75V
C oss = C ds + C gd
10000 VDS= 30V
Ciss 10.0
C, Capacitance (pF)

8.0
Coss
1000
6.0
Crss
4.0
100

2.0

10 0.0
1 10 100 1000 0 20 40 60 80 100
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFB4115GPbF
1000 10000

OPERATION IN THIS AREA

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

LIMITED BY R DS(on)
100 T J = 175°C 1000

100µsec
10 100
DC 1msec
T J = 25°C
10msec
1 10
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

120 200
Id = 3.5mA

100 190
ID, Drain Current (A)

80 180

60 170

40 160

20 150

0 140
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
6.0 900
EAS , Single Pulse Avalanche Energy (mJ)

ID
800
TOP 10A
5.0
700 22A
BOTTOM 62A
4.0 600
Energy (µJ)

500
3.0
400

2.0 300

200
1.0
100

0.0 0
-20 0 20 40 60 80 100 120 140 160 25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRFB4115GPbF
1

Thermal Response ( Z thJC ) °C/W D = 0.50

0.1 0.20
0.10
0.05
R1 R2 R3
0.01 0.02 R1 R2 R3 Ri (°C/W) τi (sec)
τJ
0.01 τJ
τC
τ 0.0500 0.000052
τ1 τ2 τ3
τ1 τ2 τ3 0.1461 0.000468
Ci= τi/Ri 0.2041 0.004702
0.001 SINGLE PULSE
Ci i/Ri

( THERMAL RESPONSE ) Notes:

1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche
100 pulsewidth, tav, assuming ∆Tj = 150°C and
Avalanche Current (A)

Tstart =25°C (Single Pulse)

0.01

10 0.05
0.10

1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth

250 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
200 ID = 62A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
150 4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
100 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
50
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFB4115GPbF
6.0 50
IF = 42A
VGS(th) , Gate threshold Voltage (V)

V R = 130V
5.0 40
TJ = 25°C
TJ = 125°C
4.0 30

IRR (A)
ID = 250µA
3.0 ID = 1.0mA 20
ID = 1.0A

2.0 10

1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
TJ , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

50 2500
IF = 62A IF = 42A
V R = 130V V R = 130V
40 2000
TJ = 25°C TJ = 25°C
TJ = 125°C TJ = 125°C
30 1500
QRR (A)
IRR (A)

20 1000

10 500

0 0
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

3000
IF = 62A
V R = 130V
2400
TJ = 25°C
TJ = 125°C
1800
QRR (A)

1200

600

0
0 200 400 600 800 1000
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFB4115GPbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRFB4115GPbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

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TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.01/2009
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