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IRFP4668PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
D
VDSS 200V
l Uninterruptible Power Supply
l High Speed Power Switching
RDS(on) typ. 8.0m:
l Hard Switched and High Frequency Circuits G max. 9.7m:
Benefits S ID 130A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability S
D
l Lead-Free G
TO-247AC
G D S
Gate Drain Source
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 760 mJ
IAR Avalanche Current c See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy f mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case j ––– 0.29
RθCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RθJA Junction-to-Ambient ij ––– 40
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IRFP4668PbF
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 130 A MOSFET symbol
D
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 520 integral reverse
G
Notes:
Repetitive rating; pulse width limited by max. junction
Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. as Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax, starting TJ = 25°C, L = 0.23mH Coss eff. (ER) is a fixed capacitance that gives the same energy as
RG = 25Ω, IAS = 81A, VGS =10V. Part not recommended for Coss while VDS is rising from 0 to 80% VDSS.
use above this value. When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
ISD ≤ 81A, di/dt ≤ 520A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. mended footprint and soldering techniques refer to application note #AN-994.
Pulse width ≤ 400μs; duty cycle ≤ 2%. Rθ is measured at TJ approximately 90°C.
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IRFP4668PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)
0.1 4.5V
4.5V ≤60μs PULSE WIDTH
Tj = 175°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000
VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)
100
TJ = 175°C (Normalized) 2.5
2.0
10
TJ = 25°C 1.5
1 1.0
VDS = 50V
≤ 60μs PULSE WIDTH 0.5
0.1
3.0 4.0 5.0 6.0 7.0 8.0 9.0 0.0
-60 -40 -20 0 20 40 60 80 100120140160180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
16000 16
VGS = 0V, f = 1 MHZ ID= 81A
Ciss = Cgs + Cgd, Cds SHORTED
VDS = 160V
VGS, Gate-to-Source Voltage (V)
Crss = Cgd
Coss = Cds + Cgd VDS = 100V
12000 12
Ciss VDS = 40V
C, Capacitance (pF)
8000 8
4
4000
Coss
Crss 0
0 0 40 80 120 160 200
1 10 100
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFP4668PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
TJ = 175°C
100
100μsec
100
10 TJ = 25°C 10msec
10
1msec
1
1 Tc = 25°C
Tj = 175°C DC
VGS = 0V Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 0.1 1 10 100 1000
100
230
80
220
60
210
40
20 200
0 190
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
TC , CaseTemperature (°C) TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
14 2500
EAS, Single Pulse Avalanche Energy (mJ)
ID
12 TOP 18A
2000 24A
BOTTOM 81A
10
1500
Energy (μJ)
6 1000
4
500
2
0 0
0 40 80 120 160 200 25 50 75 100 125 150 175
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFP4668PbF
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20
0.10
0.01
0.05 R1
R1
R2
R2
R3
R3 Ri (°C/W) τι (sec)
τJ
0.02 τJ
τC
τ 0.063359 0.000278
τ1 τ2 τ3
τ1
0.01 τ2 τ3
0.110878 0.005836
Ci= τi/Ri
Ci= τi/Ri 0.114838 0.053606
0.001
100
0.01
0.05
10
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
5.0 ID = 1.0mA 60
ID = 250μA
50
4.0
IRRM - (A)
40
3.0
30
2.0
20 IF = 52A
VR = 100V
1.0
10 TJ = 125°C
TJ = 25°C
0.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000
TJ , Temperature ( °C ) dif / dt - (A / μs)
Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt
70 5000
60
4000
50
QRR - (nC)
3000
IRRM - (A)
40
30
2000
20 IF = 81A IF = 52A
VR = 100V 1000 VR = 100V
10 TJ = 125°C TJ = 125°C
TJ = 25°C TJ = 25°C
0 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt
5000
4000
QRR - (nC)
3000
2000
IF = 81A
1000 VR = 100V
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS
VGS
90%
D.U.T.
RG
+
- VDD
V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds
Vgs
50KΩ
12V .2μF
.3μF
+
V
D.U.T. - DS
Vgs(th)
VGS
3mA
IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRFP4668PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/08
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Mouser Electronics
Authorized Distributor
Infineon:
IRFP4668PBF