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PD -97140

IRFP4668PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
D
VDSS 200V
l Uninterruptible Power Supply
l High Speed Power Switching
RDS(on) typ. 8.0m:
l Hard Switched and High Frequency Circuits G max. 9.7m:
Benefits S ID 130A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability S
D
l Lead-Free G

TO-247AC

G D S
Gate Drain Source

Absolute Maximum Ratings


Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 130
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 92 A
IDM Pulsed Drain Current c 520
PD @TC = 25°C Maximum Power Dissipation 520 W
Linear Derating Factor 3.5 W/°C
VGS Gate-to-Source Voltage ± 30 V
dv/dt Peak Diode Recovery e 57 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbxin (1.1Nxm)

Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 760 mJ
IAR Avalanche Current c See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy f mJ

Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case j ––– 0.29
RθCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RθJA Junction-to-Ambient ij ––– 40
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IRFP4668PbF

Static @ TJ = 25°C (unless otherwise specified)


Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 200 ––– ––– V VGS = 0V, ID = 250μA
ΔV(BR)DSS/ΔTJ Breakdown Voltage Temp. Coefficient ––– 0.21 ––– V/°C Reference to 25°C, ID = 5mAc
RDS(on) Static Drain-to-Source On-Resistance ––– 8.0 9.7 mΩ VGS = 10V, ID = 81A f
VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250μA
IDSS Drain-to-Source Leakage Current ––– ––– 20 μA VDS = 200V, VGS = 0V
––– ––– 250 VDS = 200V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Internal Gate Resistance ––– 1.0 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 150 ––– ––– S VDS = 50V, ID = 81A
Qg Total Gate Charge ––– 161 241 nC ID = 81A
Qgs Gate-to-Source Charge ––– 54 ––– VDS = 100V
Qgd Gate-to-Drain ("Miller") Charge ––– 52 ––– VGS = 10V f
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 109 ––– ID = 81A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time ––– 41 ––– ns VDD = 130V
tr Rise Time ––– 105 ––– ID = 81A
td(off) Turn-Off Delay Time ––– 64 ––– RG = 2.7Ω
tf Fall Time ––– 74 ––– VGS = 10V f
Ciss Input Capacitance ––– 10720 ––– VGS = 0V
Coss Output Capacitance ––– 810 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 160 ––– pF ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)h ––– 630 ––– VGS = 0V, VDS = 0V to 160V h
Coss eff. (TR) Effective Output Capacitance (Time Related)g ––– 790 ––– VGS = 0V, VDS = 0V to 160V g

Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 130 A MOSFET symbol
D
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 520 integral reverse
G

(Body Diode)c p-n junction diode. S


VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 81A, VGS = 0V f
trr Reverse Recovery Time ––– 130 ––– ns TJ = 25°C VR = 100V,
––– 155 ––– TJ = 125°C IF = 81A
Qrr Reverse Recovery Charge ––– 633 ––– nC TJ = 25°C di/dt = 100A/μs f
––– 944 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 8.7 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction … Coss eff. (TR) is a fixed capacitance that gives the same charging time
temperature. as Coss while VDS is rising from 0 to 80% VDSS.
‚ Limited by TJmax, starting TJ = 25°C, L = 0.23mH † Coss eff. (ER) is a fixed capacitance that gives the same energy as
RG = 25Ω, IAS = 81A, VGS =10V. Part not recommended for Coss while VDS is rising from 0 to 80% VDSS.
use above this value. ‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
ƒ ISD ≤ 81A, di/dt ≤ 520A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. mended footprint and soldering techniques refer to application note #AN-994.
„ Pulse width ≤ 400μs; duty cycle ≤ 2%. ˆ Rθ is measured at TJ approximately 90°C.

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IRFP4668PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)


100 7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 100 5.0V
BOTTOM 4.5V BOTTOM 4.5V
10

≤60μs PULSE WIDTH


1 Tj = 25°C
10

0.1 4.5V
4.5V ≤60μs PULSE WIDTH
Tj = 175°C
0.01 1
0.1 1 10 100 1000 0.1 1 10 100 1000
VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics


1000 3.5
ID = 81A

RDS(on) , Drain-to-Source On Resistance


3.0 VGS = 10V
ID, Drain-to-Source Current(Α)

100
TJ = 175°C (Normalized) 2.5

2.0
10

TJ = 25°C 1.5

1 1.0
VDS = 50V
≤ 60μs PULSE WIDTH 0.5
0.1
3.0 4.0 5.0 6.0 7.0 8.0 9.0 0.0
-60 -40 -20 0 20 40 60 80 100120140160180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

16000 16
VGS = 0V, f = 1 MHZ ID= 81A
Ciss = Cgs + Cgd, Cds SHORTED
VDS = 160V
VGS, Gate-to-Source Voltage (V)

Crss = Cgd
Coss = Cds + Cgd VDS = 100V
12000 12
Ciss VDS = 40V
C, Capacitance (pF)

8000 8

4
4000
Coss

Crss 0
0 0 40 80 120 160 200
1 10 100
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRFP4668PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS (on)

ID, Drain-to-Source Current (A)


ISD, Reverse Drain Current (A)

1000
TJ = 175°C
100
100μsec
100

10 TJ = 25°C 10msec
10

1msec
1
1 Tc = 25°C
Tj = 175°C DC
VGS = 0V Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 0.1 1 10 100 1000

VSD , Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area


Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)


140 250
Id = 5mA
120
240
ID , Drain Current (A)

100
230
80
220
60

210
40

20 200

0 190
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
TC , CaseTemperature (°C) TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
14 2500
EAS, Single Pulse Avalanche Energy (mJ)

ID
12 TOP 18A
2000 24A
BOTTOM 81A
10

1500
Energy (μJ)

6 1000

4
500
2

0 0
0 40 80 120 160 200 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFP4668PbF
1

D = 0.50
Thermal Response ( Z thJC )

0.1
0.20
0.10

0.01
0.05 R1
R1
R2
R2
R3
R3 Ri (°C/W) τι (sec)
τJ
0.02 τJ
τC
τ 0.063359 0.000278
τ1 τ2 τ3
τ1
0.01 τ2 τ3
0.110878 0.005836
Ci= τi/Ri
Ci= τi/Ri 0.114838 0.053606
0.001

SINGLE PULSE Notes:


( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1 1

t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case


1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Duty Cycle = Single Pulse
Avalanche Current (A)

100

0.01

0.05
10

0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 14. Typical Avalanche Current vs.Pulsewidth


800 Notes on Repetitive Avalanche Curves , Figures 14, 15:
TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1% Duty Cycle 1. Avalanche failures assumption:
ID = 81A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

600 excess of Tjmax. This is validated for every part type.


2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
400 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
200 25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
Starting TJ , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature


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IRFP4668PbF
6.0 70
ID = 1.0A
VGS(th) Gate threshold Voltage (V)

5.0 ID = 1.0mA 60
ID = 250μA
50
4.0

IRRM - (A)
40
3.0
30
2.0
20 IF = 52A
VR = 100V
1.0
10 TJ = 125°C
TJ = 25°C
0.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000
TJ , Temperature ( °C ) dif / dt - (A / μs)

Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

70 5000

60
4000

50
QRR - (nC)
3000
IRRM - (A)

40

30
2000

20 IF = 81A IF = 52A
VR = 100V 1000 VR = 100V
10 TJ = 125°C TJ = 125°C
TJ = 25°C TJ = 25°C
0 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs) dif / dt - (A / μs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

5000

4000
QRR - (nC)

3000

2000

IF = 81A

1000 VR = 100V
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000

dif / dt - (A / μs)

Fig. 20 - Typical Stored Charge vs. dif/dt


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IRFP4668PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied


• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2μF
.3μF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRFP4668PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information


EXAMPLE: THIS IS AN IRFPE30
WIT H AS S EMBLY PART NUMBER
LOT CODE 5657 INTERNATIONAL
AS S EMBLED ON WW 35, 2001 RECT IFIER IRFPE30

IN T HE AS S EMBLY LINE "H" LOGO 135H


56 57
DAT E CODE
AS S EMBLY YEAR 1 = 2001
Note: "P" in ass embly line pos ition
indicates "Lead-Free" LOT CODE WEEK 35
LINE H

TO-247AC packages are not recommended for Surface Mount Application.


Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.


This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/08
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Mouser Electronics

Authorized Distributor

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Infineon:
IRFP4668PBF

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