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IRFP4468PbF
HEXFET® Power MOSFET
Applications D VDSS 100V
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
RDS(on) typ. 2.0m:
l High Speed Power Switching max. 2.6m:
l Hard Switched and High Frequency Circuits G ID (Silicon Limited) 290A c
Benefits S ID (Package Limited) 195A
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability S
D
l Lead-Free G
TO-247AC
G D S
Gate Drain Source
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 740 mJ
IAR Avalanche Currentd See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy g mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k ––– 0.29
RθCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RθJA Junction-to-Ambient jk ––– 40
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IRFP4468PbF
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 290c A MOSFET symbol
D
(Body Diode) showing the
ISM Pulsed Source Current ––– ––– 1120 A integral reverse G
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 180A, VGS = 0V g
trr Reverse Recovery Time ––– 100 ns TJ = 25°C VR = 85V,
––– 110 TJ = 125°C IF = 180A
Qrr Reverse Recovery Charge ––– 370 nC TJ = 25°C di/dt = 100A/μs g
––– 420 TJ = 125°C
IRRM Reverse Recovery Current ––– 6.9 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction ISD ≤ 180A, di/dt ≤ 600A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
temperature. Bond wire current limit is 195A. Note that current Pulse width ≤ 400μs; duty cycle ≤ 2%.
limitations arising from heating of the device leads may occur with Coss eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. (Refer to AN-1140) as Coss while VDS is rising from 0 to 80% VDSS.
Repetitive rating; pulse width limited by max. junction Coss eff. (ER) is a fixed capacitance that gives the same energy as
temperature. Coss while VDS is rising from 0 to 80% VDSS.
Limited by TJmax, starting TJ = 25°C, L = 0.045mH When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
RG = 25Ω, IAS = 180A, VGS =10V. Part not recommended for use mended footprint and soldering techniques refer to application note #AN-994.
above this value . Rθ is measured at TJ approximately 90°C
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100
10 4.0V
2.0
100 TJ = 175°C (Normalized)
1.5
TJ = 25°C
10
1.0
VDS = 25V
≤ 60μs PULSE WIDTH
1
2.0 3.0 4.0 5.0 6.0 7.0 0.5
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
35000 16
VGS = 0V, f = 100 kHz
ID= 180A
Ciss = Cgs + Cgd, Cds SHORTED
VGS, Gate-to-Source Voltage (V)
Ciss
20000
8
15000
10000 4
Coss
5000
Crss 0
0
0 50 100 150 200 250 300 350 400 450
1 10 100
QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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1000
100 100μsec
100
10 1msec
TJ = 25°C
LIMITED BY PACKAGE
10
10msec
1
1 Tc = 25°C
Tj = 175°C DC
VGS = 0V Single Pulse
0.1 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.1 1 10 100
200 110
150
100
100
50
0
90
25 50 75 100 125 150 175
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
TC , Case Temperature (°C)
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
7.0 3000
EAS, Single Pulse Avalanche Energy (mJ)
ID
6.0 2500
TOP 30A
41A
BOTTOM 180A
5.0
2000
Energy (μJ)
4.0
1500
3.0
1000
2.0
500
1.0
0.0 0
0 20 40 60 80 100 25 50 75 100 125 150 175
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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D = 0.50
Thermal Response ( Z thJC )
0.1
0.20
0.10
0.01
0.05 R1
R1
R2
R2
R3
R3 Ri (°C/W) τι (sec)
τJ τC
0.02 τJ τ 0.063359 0.000278
τ1 τ2 τ3
τ1 τ2 τ3
0.01 0.110878 0.005836
Ci= τi/Ri
Ci= τi/Ri 0.114838 0.053606
0.001
100
0.01
0.05
10
0.10
tav (sec)
ID = 1.0A
VGS(th) Gate threshold Voltage (V)
4.0 ID = 1.0mA
ID = 250μA 24
3.5
IRRM - (A)
3.0
16
2.5
2.0 IF = 72A
8
VR = 85V
1.5 TJ = 125°C
TJ = 25°C
1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 100 200 300 400 500 600 700 800 900 1000
Fig 16. Threshold Voltage Vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt
40 1500
32
24
16
500
IF = 108A IF = 72A
8 VR = 85V VR = 85V
TJ = 125°C TJ = 125°C
TJ = 25°C TJ = 25°C
0 0
100 200 300 400 500 600 700 800 900 1000 100 200 300 400 500 600 700 800 900 1000
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt
2000
IF = 108A
VR = 85V
TJ = 125°C
1500 TJ = 25°C
QRR - (nC)
1000
500
0
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
Recovery Body Diode Forward
-
+ Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD
Ripple ≤ 5% ISD
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS
Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS
VGS
90%
D.U.T.
RG
+
- VDD
V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds
Vgs
50KΩ
12V .2μF
.3μF
+
V
D.U.T. - DS
Vgs(th)
VGS
3mA
IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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