PD - 97369

IRLB4030PbF
Applications
l DC Motor Drive HEXFET® Power MOSFET
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
D
VDSS 100V
l High Speed Power Switching RDS(on) typ. 3.4mΩ
l Hard Switched and High Frequency Circuits G
max. 4.3mΩ
Benefits S ID 180A
l Optimized for Logic Level Drive
l Very Low RDS(ON) at 4.5V VGS
l Superior R*Q at 4.5V VGS
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche S
D
SOA G
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free TO-220AB

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 180
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 130 A
IDM Pulsed Drain Current c 730
PD @TC = 25°C Maximum Power Dissipation 370 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ± 16 V
dv/dt Peak Diode Recovery e 21 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw x x
10lb in (1.1N m)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 305 mJ
IAR Avalanche Current c See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy f mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case j ––– 0.40 °C/W
RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––
RθJA Junction-to-Ambient ij ––– 62

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IRLB4030PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.10 ––– V/°C Reference to 25°C, ID = 5mA c
RDS(on) Static Drain-to-Source On-Resistance ––– 3.4 4.3 mΩ VGS = 10V, ID = 110A f
––– 3.6 4.5 VGS = 4.5V, ID = 92A f
VGS(th) Gate Threshold Voltage 1.0 ––– 2.5 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 VDS = 100V, VGS = 0V
µA
––– ––– 250 VDS = 100V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
RG(int) Internal Gate Resistance ––– 2.1 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 320 ––– ––– S VDS = 25V, ID = 110A
Qg Total Gate Charge ––– 87 130 ID = 110A
Qgs Gate-to-Source Charge ––– 27 ––– VDS = 50V
Qgd Gate-to-Drain ("Miller") Charge ––– 45 –––
nC
VGS = 4.5V f
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 42 ––– ID = 110A, VDS =0V, VGS = 4.5V
td(on) Turn-On Delay Time ––– 74 ––– VDD = 65V
tr Rise Time ––– 330 ––– ID = 110A
ns
td(off) Turn-Off Delay Time ––– 110 ––– RG = 2.7Ω
tf Fall Time ––– 170 ––– VGS = 4.5V f
Ciss Input Capacitance ––– 11360 ––– VGS = 0V
Coss Output Capacitance ––– 670 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 290 ––– pF ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related) h ––– 760 ––– VGS = 0V, VDS = 0V to 80V h
Coss eff. (TR) Effective Output Capacitance (Time Related) g ––– 1140 ––– VGS = 0V, VDS = 0V to 80V g
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D
––– ––– 180
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

(Body Diode)c ––– ––– 730

p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 110A, VGS = 0V f
trr Reverse Recovery Time ––– 50 ––– TJ = 25°C VR = 85V,
ns
––– 60 ––– TJ = 125°C IF = 110A
Qrr Reverse Recovery Charge ––– 88 ––– TJ = 25°C di/dt = 100A/µs f
nC
––– 130 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 3.3 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by TJmax, starting TJ = 25°C, L = 0.05mH
RG = 25Ω, IAS = 110A, VGS =10V. Part not recommended for use
above this value .
ƒ ISD ≤ 110A, di/dt ≤ 1330A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
… Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
† Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
ˆ Rθ is measured at TJ approximately 90°C.

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 IRLB4030PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

4.5V 4.5V
3.5V 3.5V
3.0V 3.0V
100 2.7V 2.7V
BOTTOM 2.5V BOTTOM 2.5V

100

10 2.5V

2.5V
≤60µs PULSE WIDTH ≤60µs PULSE WIDTH
Tj = 25°C Tj = 175°C
1 10
0.1 1 10 100 1000 0.1 1 10 100 1000
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
ID = 110A

RDS(on) , Drain-to-Source On Resistance

V GS = 10V
ID, Drain-to-Source Current (A)

2.0

TJ = 175°C
100
1.5
(Normalized)

TJ = 25°C

1.0
10

0.5
V DS = 50V
≤60µs PULSE WIDTH
1.0 0.0
1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
V GS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 5.0
VGS = 0V, f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
ID= 110A V DS= 80V
C rss = C gd V DS= 50V
V GS, Gate-to-Source Voltage (V)

4.0
C oss = C ds + C gd
Ciss
C, Capacitance (pF)

10000
3.0

Coss
2.0
1000
Crss
1.0

100 0.0
1 10 100 0 20 40 60 80 100
V DS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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IRLB4030PbF
1000 10000

OPERATION IN THIS AREA

TJ = 175°C LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

100 1000
100µsec
TJ = 25°C
10 100
10msec
1msec
DC
1 10
Tc = 25°C
Tj = 175°C
V GS = 0V
Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 0 1 10 100 1000
V SD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage

V (BR)DSS, Drain-to-Source Breakdown Voltage (V)

200 125
Id = 5mA
180
120
160

140 115
ID, Drain Current (A)

120
110
100
105
80

60 100
40
95
20

0 90
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
TC , Case Temperature (°C) TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
4.5 1400
EAS , Single Pulse Avalanche Energy (mJ)

ID
4.0
1200 TOP 17A
3.5 40A
1000 BOTTOM 110A
3.0
Energy (µJ)

2.5 800

2.0 600
1.5
400
1.0
200
0.5

0.0 0
-20 0 20 40 60 80 100 120 25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRLB4030PbF
1

Thermal Response ( Z thJC ) °C/W

D = 0.50
0.1 0.20
0.10
0.05 R1 R2 R3
R1 R2 R3 Ri (°C/W) τi (sec)
0.01 0.02 τJ
τJ
τC
τ
0.0477 0.000071
0.01 τ1 τ2 τ3
τ1 τ2 τ3 0.1631 0.000881
Ci= τi/Ri 0.1893 0.007457
0.001 Ci i/Ri
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
Avalanche Current (A)

0.05
10 0.10

1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

350 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
300 BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
ID = 110A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

250 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
200 4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
150 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
100 25°C in Figure 14, 15).
tav = Average time in avalanche.
50 D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRLB4030PbF
2.5 40
IF = 73A
35
VGS(th), Gate threshold Voltage (V)

V R = 85V
2.0
30 TJ = 25°C
TJ = 125°C
25
1.5

IRRM (A)
ID = 250µA 20

1.0 ID = 1.0mA
15
ID = 1.0A
10
0.5
5

0.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

35 800
IF = 110A IF = 73A
720
30 V R = 85V V R = 85V
TJ = 25°C 640 TJ = 25°C
25 TJ = 125°C TJ = 125°C
560
IRRM (A)

20
QRR (A)

480

15 400

320
10
240
5
160

0 80
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

880
IF = 110A
800
V R = 85V
720
TJ = 25°C
640 TJ = 125°C
560
QRR (A)

480

400

320

240

160

80
0 200 400 600 800 1000
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRLB4030PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRLB4030PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

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TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 02/09
8 www.irf.com
IMPORTANT NOTICE
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event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
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values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
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applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
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contain dangerous substances. For information on
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