PD - 96213

IRFB4410ZGPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
D
VDSS 100V
l Uninterruptible Power Supply RDS(on) typ. 7.2m:
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G max. 9.0m:
S ID (Silicon Limited) 97A
Benefits
D
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
S
SOA D
G
l Enhanced body diode dV/dt and dI/dt Capability
TO-220AB
l Lead-Free
IRFB4410ZGPbF
l Halogen-Free

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 97
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 69 A
IDM Pulsed Drain Current c 390
PD @TC = 25°C Maximum Power Dissipation 230 W
Linear Derating Factor 1.5 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery e 16 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range
°C
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw x
10lbf in (1.1N m) x
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 242 mJ
IAR Avalanche Current c See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy c mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case i ––– 0.65
RθCS Case-to-Sink, Flat Greased Surface , TO-220 0.50 ––– °C/W
RθJA Junction-to-Ambient, TO-220 ––– 62

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 IRFB4410ZGPbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.12 ––– V/°C Reference to 25°C, ID = 5mA c
RDS(on) Static Drain-to-Source On-Resistance ––– 7.2 9.0 mΩ VGS = 10V, ID = 58A f
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 150µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG Internal Gate Resistance ––– 0.70 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 140 ––– ––– S VDS = 10V, ID = 58A
Qg Total Gate Charge ––– 83 120 nC ID = 58A
Qgs Gate-to-Source Charge ––– 19 ––– VDS =50V
Qgd Gate-to-Drain ("Miller") Charge ––– 27 VGS = 10V f
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 56 ––– ID = 58A, VDS =0V, VGS = 10V f
td(on) Turn-On Delay Time ––– 16 ––– ns VDD = 65V
tr Rise Time ––– 52 ––– ID = 58A
td(off) Turn-Off Delay Time ––– 43 ––– RG =2.7Ω
tf Fall Time ––– 57 ––– VGS = 10V f
Ciss Input Capacitance ––– 4820 ––– pF VGS = 0V
Coss Output Capacitance ––– 340 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 170 ––– ƒ = 1.0MHz, See Fig.5
Coss eff. (ER) Effective Output Capacitance (Energy Related) h––– 420 ––– h
VGS = 0V, VDS = 0V to 80V , See Fig.11
Coss eff. (TR) Effective Output Capacitance (Time Related) g ––– 690 ––– VGS = 0V, VDS = 0V to 80V g
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 97 A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 390 A integral reverse G

(Body Diode)c p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 58A, VGS = 0V f
trr Reverse Recovery Time ––– 38 57 ns TJ = 25°C VR = 85V,
––– 46 69 TJ = 125°C IF = 58A
Qrr Reverse Recovery Charge ––– 53 80 nC TJ = 25°C di/dt = 100A/µs f
––– 82 120 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.5 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by TJmax, starting TJ = 25°C, L = 0.143mH
RG = 25Ω, IAS = 58A, VGS =10V. Part not recommended for use
above this value.
ƒ ISD ≤ 58A, di/dt ≤ 610A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
… Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
† Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS .
‡ Rθ is measured at TJ approximately 90°C.

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 IRFB4410ZGPbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
100 4.8V 100 4.8V
BOTTOM 4.5V BOTTOM 4.5V
4.5V

4.5V
10 10

≤60µs PULSE WIDTH ≤60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
VDS = 50V ID = 58A

RDS(on) , Drain-to-Source On Resistance

≤60µs PULSE WIDTH VGS = 10V
ID, Drain-to-Source Current (A)

100 2.0
(Normalized)

10 T J = 25°C 1.5
TJ = 175°C

1 1.0

0.1 0.5
2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 12.0
VGS = 0V, f = 1 MHZ
ID= 58A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VDS= 80V
10.0
VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd VDS= 40V

VDS= 20V
C, Capacitance (pF)

10000 8.0
Ciss
6.0
Coss
1000 4.0
Crss

2.0

100 0.0
1 10 100 0 20 40 60 80 100
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFB4410ZGPbF
1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD, Reverse Drain Current (A)

ID, Drain-to-Source Current (A)

100µsec
100 T J = 175°C
100 1msec

10 10msec
T J = 25°C DC

10
1
Tc = 25°C
Tj = 175°C
VGS = 0V
Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

100 125
Id = 5mA
120
80
115
ID, Drain Current (A)

60
110

40 105

100
20
95

0 90
25 50 75 100 125 150 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
2.0 1000
EAS , Single Pulse Avalanche Energy (mJ)

ID
1.8 900
TOP 6.4A
1.6 800 9.4A
1.4 BOTTOM 58A
700
1.2
Energy (µJ)

600
1.0 500
0.8 400
0.6 300
0.4 200
0.2 100
0.0 0
-10 0 10 20 30 40 50 60 70 80 90 100 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRFB4410ZGPbF
1

Thermal Response ( Z thJC ) °C/W

D = 0.50

0.20
0.1
0.10
R1 R2
0.05 R1 R2 Ri (°C/W) τi (sec)
τJ τC
τJ τ 0.237 0.000178
τ1 τ2
0.02 τ1 τ2 0.413 0.003772
0.01 0.01
Ci= τi/Ri
Ci i/Ri

SINGLE PULSE Notes:

( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

100
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming ∆ Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
Avalanche Current (A)

10 0.05
0.10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
150 Notes on Repetitive Avalanche Curves , Figures 14, 15:
TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
ID = 58A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
100
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
50 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFB4410ZGPbF
4.5 20
I = 39A
F
V = 85V
R
VGS(th), Gate threshold Voltage (V)

4.0
TJ = 25°C _____

15 TJ = 125°C ----------
3.5

IRRM (A)
3.0
10
2.5

ID = 150µA
2.0
ID = 250µA 5
ID = 1.0mA
1.5
ID = 1.0A

1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 200 100 200 300 400 500 600 700
T J , Temperature ( °C ) dif/dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

20 400
IF = 58A I = 39A
F
V = 85V 350 V = 85V
R R
T = 25°C _____ TJ = 25°C _____
J
15 TJ = 125°C ---------- 300 TJ = 125°C ----------

250
IRRM (A)

Qrr (nC)

10 200

150

5 100

50

0 0
100 200 300 400 500 600 700 100 200 300 400 500 600 700
dif/dt (A/µs) dif/dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

450
I = 58A
F
400 V = 85V
R
TJ = 25°C _____
350 TJ = 125°C
----------
300
Qrr (nC)

250

200

150

100

50

0
100 200 300 400 500 600 700
dif/dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFB4410ZGPbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
20V
tp 0.01Ω I AS
Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms

LD
VDS
VGS
+ 90%
VDD -

D.U.T
10%
VGS
VDS
Second Pulse Width < 1µs
Duty Factor < 0.1%
td(off) tf td(on) tr

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms

Id
Vds

Vgs

L
VCC
DUT
0
Vgs(th)
1K
S
20K

Qgodr Qgd Qgs2 Qgs1

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRFB4410ZGPbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

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TO-220AB packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.01/2009
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