L4971

1.5A STEP DOWN SWITCHING REGULATOR

1 FEATURES Figure 1. Package

■ UP TO 1.5A STEP DOWN CONVERTER
■ OPERATING INPUT VOLTAGE FROM 8V TO
55V
■ PRECISE 3.3V (±1%) INTERNAL DIP8 SO16W
REFERENCE VOLTAGE
■ OUTPUT VOLTAGE ADJUSTABLE FROM Table 1. Order Codes
3.3V TO 50V
■ SWITCHING FREQUENCY ADJUSTABLE UP Part Number Package
TO 300KHz L4971 DIP8
■ VOLTAGE FEEDFORWARD L4971D SO16W
■ ZERO LOAD CURRENT OPERATION L4971D013TR SO16 in Tape & Reel
■ INTERNAL CURRENT LIMITING (PULSE-
BYPULSE AND HICCUP MODE)
■ INHIBIT FOR ZERO CURRENT A switching frequency up to 300KHz is achievable
CONSUMPTION (the maximum power dissipation of the packages
■ PROTECTION AGAINST FEEDBACK must be observed).
DISCONNECTION A wide input voltage range between 8V to 55V and
■ THERMAL SHUTDOWN output voltages regulated from 3.3V to 50V cover
■ SOFT START FUNCTION the majority of today’s applications.
Features of this new generations of DC-DC con-
2 DESCRIPTION verter include pulse-by-pulse current limit, hiccup
mode for short circuit protection, voltage feedfor-
The L4971 is a step down monolithic power
ward regulation, soft-start, protection against feed-
switching regulator delivering 1.5A at a voltage be-
back loop disconnection, inhibit for zero current
tween 3.3V and 50V (selected by a simple external
consumption and thermal shutdown.
divider). Realized in BCD mixed technology, the
The device is available in plastic dual in line, DIP8
device uses an internal power D-MOS transistor
for standard assembly, and SO16W for SMD as-
(with a typical Rdson of 0.25Ω) to obtain very high
sembly.
efficency and high switching speed.

Figure 1. Block Diagram

Vi=8V to 55V
5
8
R1
20K
3
L4971
4
C1 C7 C2 L1
220µF 220nF 2.7nF 2 7 1 6 VO=3.3V/1.5A
126µH
63V (77120)
C6
R2 100nF D1
9.1K STPS C8
C5 330µF
3L60U
100nF C4
22nF

D97IN748A

Rev. 11
May 2005 1/13
L4971

Figure 2. Block Diagram

VCC
5

THERMAL VOLTAGES
SHUTDOWN MONITOR
CBOOT
CHARGE
2 INTERNAL INTERNAL
SS_INH INHIBIT SOFTSTART
REFERENCE SUPPLY 5.1V
3.3V
7
COMP 6
BOOT
8 E/A
FB PWM
R
Q CBOOT
3.3V S CHARGE
DRIVE AT LIGHT
LOADS
OSCILLATOR

3 1 4
OSC GND OUT D97IN594

Figure 3. Pin Connections

N.C. 1 16 N.C.
GND 2 15 N.C.

GND 1 8 FB SS_INH 3 14 FB

SS_INH 2 7 COMP OSC 4 13 COMP

OSC 3 6 BOOT OUT 5 12 BOOT

OUT 4 5 VCC OUT 6 11 VCC

D97IN595 N.C. 7 10 N.C.

N.C. 8 9 N.C.
D97IN596

DIP8 SO16

Table 2. Pin Description

DIP SO (*) Name Function
1 2 GND Ground
2 3 SS_INH A logic signal (active low) disables the device (sleep mode operation).
A capacitor connected between this pin and ground determines the soft start time.
When this pin is grounded disabled the device (driven by open collector/drain).
3 4 OSC An external resistor connected between the unregulated input voltage and this pin and
a capacitor connected from this pin to ground fix the switching frequency. (Line feed
forward is automatically obtained)
4 5, 6 OUT Stepdown regulator output
5 11 VCC Unregulated DC input voltage
6 12 BOOT A capacitor connected between this pin and OUT allows to drive the internal DMOS
Transistor
7 13 COMP E/A output to be used for frequency compensation
8 14 FB Stepdown feedback input. Connecting directly to this pin results in an output voltage of
3.3V. An external resistive divider is required for higher output voltages.
(*) Pins 1, 7, 8, 9, 10, 15 and 16 are not internally, electrically connected to the die.

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 L4971

Table 3. Absolute Maximum Ratings

Symbol
Parameter Value Unit
Minidip S016
V5 V11 Input voltage 58 V
V4 V5,V6 Output DC voltage -1 V
Output peak voltage at t = 0.1µs f=200KHz -5 V
I4 I5,I6 Maximum output current int. limit.
V6-V5 V12-V11 14 V
V6 V12 Bootstrap voltage 70 V
V7 V13 Analogs input voltage (VCC = 24V 12 V
V2 V3 Analogs input voltage (VCC = 24V) 13 V
V8 V14 (VCC = 20V) 6 V
-0.3 V
Ptot Power dissipation a Tamb ≤60°C DIP8 1 W
SO16 0.8 W
Tj,Tstg Junction and storage temperature -40 to 150 °C

Table 4. Thermal Data

Symbol Parameter DIP8 SO16 Unit

Rth(j-amb) Thermal Resistance Junction to ambient Max. 90 (*) 110 (*) °C/W

(*) Package mounted on board.

3 ELECTRICAL CHARACTERISTCS
Table 5. (Tj = 25°C, Cosc = 2.7nF, Rosc = 20kΩ, VCC = 24V, unless otherwise specified.)
* Specification Refered to Tj from 0 to 125°C
Symbol Parameter Test Condition Min. Typ. Max. Unit
DYNAMIC CHARACTERISTIC
VI Operating input voltage range Vo = 3.3 to 50V; Io = 1.5A * 8 55 V
Vo Output voltage Io = 0.5A 3.33 3.36 3.39 V
Io = 0.2 to 1.5A 3.292 3.36 3.427 V
Vcc = 8 to 55V * 3.22 3.36 3.5 V
Vd Dropout voltage Vcc = 10V; Io = 1.5A 0.44 0.55 V
* 0.88 V
Il Maximum limiting current Vcc = 8 to 55V * 2 2.5 3 A
Efficiency
Vo = 3.3V; Io = 1.5A 85 %
fs Switching frequency * 90 100 110 KHz
SVRR Supply voltage ripple rejection Vi = Vcc+2VRMS; Vo = Vref; 60 dB
Io = 1.5A; f ripple = 100Hz
Voltage stability of switching Vcc = 8 to 55V 3 6 %
frequency
Temp. stability of switching Tj = 0 to 125°C 4 %
frequency

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L4971

Table 5. (Tj = 25°C, Cosc = 2.7nF, Rosc = 20kΩ, VCC = 24V, unless otherwise specified.)
* Specification Refered to Tj from 0 to 125°C
Soft Start
Soft start charge current 30 40 50 µA
Soft start discharge current 6 10 14 µA
Inhibit
VLL Low level voltage * 0.9 V
IsLL Isource Low level * 5 15 µA
DC Characteristics
Iqop Total operating quiescent 4 6 mA
current
Iq Quiescent current Duty Cycle = 0; VFB = 3.8V 2.5 3.5 mA

Iqst-by Total stand-by quiescent Vinh <0.9V 100 200 µA

current
Vcc = 55V; Vinh<0.9V 150 300 µA
Error Amplifier
VFB Voltage Feedback Input 3.33 3.36 3.39 V
RL Line regulation Vcc = 8 to 55V 5 10 mV
Ref. voltage stability vs * 0.4 mV/°C
temperature
VoH High level output voltage VFB = 2.5V 10.3 V
VoL Low level output voltage VFB = 3.8V 0.65 V

Io source Source output current Vcomp = 6V; VFB = 2.5V 200 300 µA

Io sink Sink output current Vcomp = 6V; VFB= 3.8V 200 300 µA

Ib Source bias current 2 3 µA

SVRR E/A Supply voltage ripple rejection Vcomp = Vfb; Vcc = 8 to 55V 60 80 dB
DC open loop gain RL = ∞ 50 57 dB

gm Transconductance Icomp = -0.1 to 0.1mA 2.5 ms

Vcomp = 6V
Oscillator Section
Ramp Valley 0.78 0.85 0.92 V
Ramp peak Vcc = 8V 2 2.15 2.3 V
Vcc = 55V 9 9.6 10.2 V
Maximum duty cycle 95 97 %
Maximum Frequency Duty Cycle = 0% ; 300 kHz
Rosc = 13kΩ, Cosc = 820pF

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 L4971

Table 6. Typical Performance (Using Evaluation Board) fsw = 100kHz

Output Output Efficiency Line Regulation Load Regulation

Voltage Ripple VCC =35V IO = 1.5A Io = 1.5A VCC = 8 to 55V VCC =35V IO = 0.5 to 1.5A

3.3V 10mV 84 (%) 3mV 6mV

5.1V 10mV 86 (%) 3mV 6mV

12V 12mV 93 (%) 3mV (VCC =15 to 55V) 4mV

Figure 4. Test and valuation board circuit.

Vi=8V to 55V
5
8
R1
20K
3
L4971 VO=3.3V/1.5A
4
C1 C7 C2 L1
220µF 220nF 2.7nF 2 7 1 6
126µH
63V (77120) R3
C6
R2 100nF D1
C5 9.1K ST C8
100nF PS3L60U 330µF
C4 R4
22nF

D97IN749A

L4971
C1=220µF/63V EKE
C2=2.7nF VO(V) R3(KΩ) R4(KΩ)
C5=100nF 3.3 0
C6=100nF
C7=220nF/63V 5.1 2.7 4.7
C8=330µF/35V CG Sanyo 12 12 4.7
L1=126µH KoolMu 77120 - 65 Turns - 0.5mm
R1=20K 15 16 4.7
R2=9.1K 18 20 4.7
D1=STPS3L60U
24 30 4.7

Figure 5. PCB and component layout of the figure 4.

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L4971

Figure 6. Quiescent drain current vs. input Figure 9. Line Regulation

voltage.
VO D97IN733
Iq D97IN724 (V)
(mA)
200KHz 3.377
Tj=125˚C
R1=22K
5 C2=1.2nF 3.376

100KHz 3.375
R1=20K
4 Tj=25˚C
C2=2.7nF
3.374

3 3.373
0Hz

3.372
2
3.371
Tamb=25˚C
0% DC
3.370
1
0 5 10 15 20 25 30 35 40 45 50 VCC(V)
0 5 10 15 20 25 30 35 40 45 50 Vcc(V)

Figure 7. Quiescent current vs. junction Figure 10. Line Regulation

temperature
VO D97IN734
D97IN731
Iq (V)
(mA) 3.378 VCC=35V

200KHz 3.376
5 R1=22K
C2=1.2nF 3.374
Tj=25˚C
3.372
4 100KHz
R1=20K 3.370 Tj=125˚C
C2=2.7nF

3 3.368
0Hz
3.366
VCC=35V
2 0% DC 3.364
3.362
1 3.360
-50 -30 -10 10 30 50 70 90 110 Tj(˚C) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)

Figure 8. Stand-by drain current vs. input Figure 11. Switching frquency vs. R1 and C2
voltage

Ibias D97IN732 fsw D97IN784

(µA) (KHz)
150 Vss=GND
500 Tamb=25˚C

140 Tj=25˚C
0.8
2nF
130 200
1.2
nF
120 100
2.2
110 nF

50 3.3n
100 Tj=125˚C F

90 4.7n
F
20
5.6n
80 F

10
70
60 5
0 5 10 15 20 25 30 35 40 45 50 VCC(V) 0 20 40 60 80 R1(KΩ)

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 L4971

Figure 12. Switching Frequency vs. input Figure 15. Efficiency vs output voltage.
voltage.
η
D97IN737
fsw D97IN735 (%)
(KHz)
96 100KHz
107.5
94 200KHz
105.0
92
102.5 Tj=25˚C

90
100.0
VCC=35V
88 IO=1.5A
97.5

95.0
86

92.5 84

90.0 82
0 5 10 15 20 25 30 35 40 45 50 VCC(V) 0 5 10 15 20 25 VO(V)

Figure 13. Switching frequency vs. junction Figure 16. Efficiency vs. output current.
temperature.

fsw D97IN785
η D97IN738

(KHz) (%)
VCC=8V

90 VCC=12V

105
85
VCC=24V
80
100
75 VCC=48V

fsw=100KHz
70 VO=5.1V
95
65

90 60
-50 0 50 100 Tj(˚C) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)

Figure 17. Efficiency vs. output current.

Figure 14. Dropout voltage between pin 5 and 4

∆V D97IN736 η D97IN739
(V) (%)
VCC=8V
0.5 Tj=125˚C 90

0.4 85 VCC=12V
C
2 5˚ VCC=24V
Tj=
80
0.3
75 VCC=48V
0.2 Tj=-25˚C

70 fsw=100KHz
0.1 VO=3.36V
65
0.0
60
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)

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L4971

Figure 18. Efficiency vs. output current. Figure 21. Power dissipation vs. Vcc.
D97IN740 Pdiss D97IN743
η
VCC=8V
(mW)
(%)
VO=5.1V
90 fsw=100KHz
VCC=12V
800
85 VCC=24V

600 IO=1.5A
80
VCC=48V IO=1A

75
400
70 IO=0.5A
fsw=200KHz
VO=5.1V 200
65

60 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A) 0 10 20 30 40 50 VCC(V)

Figure 19. Efficiency vs. output current. Figure 22. Efficiency vs. VO

η D97IN741 Pdiss D97IN744

(%) (mW)
VCC=35V
90 VCC=8V fsw=100KHz
800
85 VCC=12V
IO=1.5A
80 VCC=24V 600

75
IO=1A
400
70
VCC=48V
IO=0.5A
65 fsw=200KHz 200
VO=3.36V
60
0
55 0 5 10 15 20 25 30 V0(V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 IO(A)

Figure 20. Efficiency vs. VCC. Figure 23. Pulse by pulse limiting current vs.
junction temperature.
η D97IN742
(%) Ilim D97IN747
V0 =5 (A)
.1V-f
SW =1
00KH fsw=100KHz
z
2.9 VCC=35V
V0
85 =5
.1V
-fS
W=
20 2.8
0K
Hz
V0 = 2.7
3.36
80 V-f
V SW =
0 =3 100
KHz
.36 2.6
V-
fS
W=
20
0K 2.5
75 Hz
IO=1.5A
2.4

2.3
70
0 10 20 30 40 50 VCC(V) -50 -25 0 25 50 75 100 125 Tj(˚C)

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 L4971

Figure 24. Load transient. Figure 27. Soft start capacitor selection vs.
Inductor and Vccmax

L D97IN746
(µH)
fsw=200KHz 56nF

300 47nF

200 33nF

22nF
100

0
15 20 25 30 35 40 45 50 VCCmax(V)

Figure 25. Line transient. Figure 28. Open loop frequency and phase of
error amplifier
VCC D97IN786
(V)
GAIN D97IN787
30 (dB) Phase

20 50
GAIN

10 0 0
VO
1
(mV) -50 45
IO = 1A
fsw = 100KHz
100
-100 90
2 0 Phase

-150 135
-100
1ms/DIV
-200
10 102 103 104 105 106 107 108 f(Hz)

Figure 26. Soft start capacitor selection Vs

inductor and Vccmax.

D97IN745
L 680nF
(µH) 470nF
fsw=100KHz
400

330nF
300

200 220nF

100
100nF

0
15 20 25 30 35 40 45 50 VCCmax(V)

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L4971

Figure 29. DIP8 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 3.32 0.131

a1 0.51 0.020

B 1.15 1.65 0.045 0.065

b 0.356 0.55 0.014 0.022

b1 0.204 0.304 0.008 0.012

D 10.92 0.430

E 7.95 9.75 0.313 0.384

e 2.54 0.100

e3 7.62 0.300

e4 7.62 0.300

F 6.6 0.260

I 5.08 0.200

L 3.18 3.81 0.125 0.150 DIP-8

Z 1.52 0.060

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 L4971

Figure 30. SO16 Mechanical Data & Package Dimensions

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.200

C 0.23 0.32 0.009 0.013

D (1) 10.10 10.50 0.398 0.413

E 7.40 7.60 0.291 0.299

e 1.27 0.050

H 10.0 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

k 0˚ (min.), 8˚ (max.)

ddd 0.10 0.004

(1) “D” dimension does not include mold flash, protusions or gate SO16 (Wide)
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.

0016021 C

11/13
L4971

4 REVISION HISTORY

Table 7. Revision History

Date Revision Description of Changes

October 2004 10 First Issue in EDOCS

May 2005 11 Updated the Layout look & feel.

Changed name of the D1 on the figs. 1 and 4.

12/13
 L4971

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