UNIT II

1. Demonstrate multiplication of two numbers with an example. Design an arithmetic

element to perform this multiplication.
 Signed multiplication
 Booth algorithm
 Booth algorithm for Signed multiplication
 Faster Multiplication
 Multiply in MIPS

2. Describe non restoring division with an example.

 If the sign of A is shift A and Q left one bit position and subtract divisor from A;
otherwise shift A and Q left and add divisor to A. if the sign of A is 0, set q0 to 1,
otherwise , set q0 to 0.
 Repeat steps 1 and 2 for n times.
 If the sign of A is 1, add divisor to A.

3. Design an arithmetic element to perform the basic floating point operations.

Consider two floating point number:
A=m1.r and B=m2.re2
e1

Rules for addition and subtraction

 Select the number with a smaller exponent and shift its mantissa right, a number of
steps equal to the difference in exponents.
 Set the exponent to the lower
 Determine the sign of the result
 Normalize the result
 Overflow and underflow in mantissa and exponent
 Flow chart for addition and subtraction

4. What is meant by sub word parallelism? Explain.

A processor can use parallelism to perform simultaneous operations on short vectors of
sixteen 8 bit operands eight 16 bit operands, four 32 bit operands or two 64 bit operands.
Such parallelism which occurs within a wide word is known as sub word parallelism
 Data level parallelism
 Vector
 SIMD.

5. Discuss in detail about division algorithm in detail with diagram and examples.
 Signed division
 Faster division
 Division in MIPS
 Step 1: Test divisor<dividend.
 Step 2: if divisor<dividend.
 Step 1: shift the divisor right by 1 bit

6. Define booth multiplication algorithm with suitable example.

(Or)
Explain booth’s algorithm for the multiplication of signed two’s complement numbers.
7. What is the disadvantage of ripple carry addition and how it is overcome in carry
look ahead adder and draws the logic circuit CLA?
 There are two techniques to speed up the multiplication process:
 The first technique guarantees that the maximum number of summands that must be
added is n/2 for n-bit operands.
 The second technique reduces the time needed to add the summands.
 The input carry needed by a stage is directly computed from carry signals obtained
from all the preceding stages i-1,i-2,…..0, rather than waiting for normal carries to
supply slowly from stage to stage.
 An added that uses this principle is a called carry look-ahead adder.
 It handles both positive and negative multipliers uniformly.
 It achieves some efficiency in the number of addition required when the multiplier has
a few large blocks of 1s.
 Instead of letting the carries ripple along the rows, they can be saved and introduced
into the next roe at the correct weighted position. Delay in CSA is less than delay
through the ripple carry adder.

8. Explain briefly about floating point addition and subtraction algorithm.

Consider two floating point number:
A=m1.r e1 and B=m2.re2
Rules for addition and subtraction
 Select the number with a smaller exponent and shift its mantissa right, a number of
steps equal to the difference in exponents.
 Set the exponent to the lower
 Determine the sign of the result
 Normalize the result
 Overflow and underflow in mantissa and exponent
 Flow chart for addition and subtraction

9. Explain the Multiplication algorithm in detail with diagram and examples.

 Signed multiplication
 Booth algorithm
 Booth algorithm for Signed multiplication
  Faster Multiplication
 Multiply in MIPS

10. Explain the sequential version of multiplication algorithm and its hardware.
 Multiplication is a complex operation then addition and subtraction it can be
performed in hardware
 Hardware implementation of unsigned binary multiplication
 Flowchart for multiplication operation
 Multiplication process.

11. Explain how floating point addition is carried out in a computer system. Give an
example for a binary floating point addition
Consider two floating point number:
A=m1.r e1 and B=m2.re2
Rules for addition and subtraction
 Select the number with a smaller exponent and shift its mantissa right, a number of
steps equal to the difference in exponents.
 Set the exponent to the lower
 Determine the sign of the result
 Normalize the result
 Overflow and underflow in mantissa and exponent
 Flow chart for addition and subtraction

12. Briefly explain carry look ahead adder.

 Carry propagation delay
 Carry generate
 Full adder circuit
 Multilevel generate and propagate functions.

13. Explain in detail about floating point representation

 IEEE 754 standard
 Scientific notation in binary
 Single precision floating point IEEE 754 standard
 Double precision floating point IEEE 754 standard
 Normalization representation
 Sizes
 Sign bit o Exponent
 Special values
 Denormalized representation
 Floating point under flow and over flow
 Guard and rounding.

16. Explain in detail about floating point arithmetic operation.

 Floating point addition and subtraction
 Floating point addition
 Procedure
 Example
 Floating point Multiplication o Procedure
 Example
 Floating point in MIPS

17. Explain in detail about basic concepts of ALU design

 1-bit ALU design
 Full adder
 32-bit ALU design
  MIPS ALU design
 Arithmetic for multimedia

18. Explain in detail about arithmetic operation

 Boolean addition
 Boolean subtraction
 Overflow
 MIPS Overflow handling
 Ripple carry adder
 Fast adder circuit
 Carry look ahead adder

19. Explain how can we speed up the multiplication process?

 There are two techniques to speed up the multiplication process:
 The first technique guarantees that the maximum number of summands that must be
added is n/2 for n-bit operands.
 The second technique reduces the time needed to add the summands.
 Bit pair recoding halves the maximum number of summands. Group the Booth-
recoded multiplier bits in pairs and observe the following: The pair (+1 -1) is
equivalent to to the pair (0 +1).
 That is instead of adding -1 times the multiplicand m at shift position i to +1 M at
position i+1, the same result is obtained by adding +1  M at position i.

20. Explain the two methods of achieving the 2’s complement?

 Take the 1’s complement of the number and add 1.
 Leave all least significant 0’s and the first unchanged and then complement the
remaining bits.
 It handles both positive and negative multiplier uniformly.
 It achieves efficiency in the number of additions required when the multiplier has a
few large blocks of 1’s.

21. Write the multiply rule for floating point numbers and explain detail.
 Add the exponent and subtract 127.
 Multiply the mantissa and determine the sign of the result.
 Normalize the resulting value, if necessary.
 Although the mantissas of initial operands are limited to 24 bits, it is important to
retain extra bits, called as guard bits.

22. Write the Add/Subtract rule for floating point numbers?

 Choose the number with the smaller exponent and shift its mantissa right a number of
steps equal to the difference in exponent
 Set the exponent of the result equal the larger exponent
 Perform addition/subtraction on the mantissa and determine. The sign of the result.
 In floating point numbers when do you say that an underflow or overflow has
occurred.
 In single precision numbers when an exponent is less than -126 then we say that an
underflow has occurred .In single precision numbers when an exponent is less than
=127 then we say that an overflow has occurred.

23. Explain in detail floating point numbers when so you say that an underflow or
overflow has occurred?
  In single precision numbers when an exponent is less than -126 then we say that an
underflow has occurred.
 In single precision numbers when an exponent is less than +127 then we say that an
overflow has occurred.
Cn-1 – 2(n-1)
Sn-1 – 2(n-1)+1
Cn – 2n

24. What is a carry look-ahead adder and explain it.

 The input carry needed by a stage is directly computed from carry signals obtained
from all the preceding stages i-1,i-2,…..0, rather than waiting for normal carries to
supply slowly from stage to stage.
 An added that uses this principle is a called carry look-ahead adder.
 It handles both positive and negative multipliers uniformly.
 It achieves some efficiency in the number of addition required when the multiplier has
a few large blocks of 1s.
 Instead of letting the carries ripple along the rows, they can be saved and introduced
into the next roe at the correct weighted position. Delay in CSA is less than delay
through the ripple carry adder.

25. Explain the ways to truncate the guard bits.

 There are several ways to truncate the guard bits:
 Chopping
 Von Neumann rounding
 Rounding

UNEXPECTED QUESTIONS AND ANSWERS

26. Define carry save addition (CSA) process in detail.

 Instead of letting the carries ripple along the rows, they can be saved and introduced
into the next roe at the correct weighted position. Delay in CSA is less than delay
through the ripple carry adder.
 The generate function is given by Gi=xiyi and The propagate function is given as
Pi=xi+yi.
 The Transformation 011… 110= +100…0 – 10 is called skipping over one’s.In his
case multiplier has its ones grouped into a few contiguous blocks.

27. Briefly describe about the two attractive features of Booth Algorithm?
 It handles both positive and negative multipliers uniformly
 It achieves some efficiency in the number of additions required when the multiplier
has a few large blocks of ones
 The worst case is shown as below
010101010
+1 -1 +1 -1 +1 -1 +1 -1 +1

28. Write down the steps for restoring division and non-restoring division and explain
in detail.

Non Restoring:
Step1: Do the following n times
 1.If the sign of A is 0, shift A and Q left one bit position and subtract M from
A otherwise shift A and Q left and add M to A.
2.Now if the sign of A is 0, set Q0 to 1; otherwise set Q0 to 0
Step 2: If the sign of A is 1, add M to A
Restoring:
Shift A and Q left one binary position
Subtract M from A
If the sign of A is one , set Q0 to 0, add M back to A otherwise set Q0 to 1

29. Briefly describe about the hardwired control?

 Hardwired control is a implemented with gates, flip-flops, decodes and other digital
circuit .The goal in hardwired design is to generate the control signals with minimum
number of components and maximize the speed of operation.
 Complex sequencing and micro operation logic.
 Difficult to design and test
 Inflexible design
 Difficult to add new instructions.

30. Write the algorithm for restoring division and explain.

Do the following for n times:

 Shift A and Q left one binary position.
 Subtract M and A and place the answer back in A.
 If the sign of A is 1, set q0 to 0 and add M back to A.
 Where A- Accumulator, M- Divisor, Q- Dividend.