Nexys4 DDR™ FPGA Board Reference Manual

3.3V
H17 LD0
P17
BTNL LD1
K15
M17 LD2
Buttons BTNR J13
LD3
M18 N14
BTNU LD4
R18
P18 V17 LD5
BTND
LD6
N17 U17
BTNC LD7
U16 LEDs
V16 LD8
LD9
T15
3.3V LD10
U14
LD11
SW0 J15 T16
V15 LD12
SW1 L16 V14 LD13
LD14
SW2 M13 V12
LD15
V11 7-seg
SW3 R15 3.3V Display

SW4 R17 U13 AN7

Slide K2 AN6
Switches
SW5 T18 T14 AN5
P14 AN4
SW6 U18 J14 AN3
1.8V SW7 R13 T9 AN2
J18 AN1
SW8 T8 J17 AN0

SW9 U8
SW10 R16 T10 CA
SW11 T13 R10 CB
K16 CC
SW12 H6 K13 CD
P15 CE
SW13 U12 T11 CF
SW14 U11 L18 CG
H15 DP
SW15 V10 5.0V

Tri-Color LD17 LD16

LEDs
3.3V N16 R17
R11 G17
G14 B17
CPU Reset C12 N15 R16
BTNRES
M16 G16
Artix-7 R12 B16

Figure 16. General Purpose I/O devices on the Nexys4 DDR.

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