Freescale Semiconductor Technical Data H-Bridge Driver ‘The 33186 is a monolithic H-Bridge ideal fr fractional horsepower D¢-motor and bi-directional thrust solenoid control. The IC incorporates internal contol logic, charge pump, gate drive, and low Rogion) MOSFET output circuitry: The 33186 is able to control continuous inductive DC load currants up to 6.0 A. Output loads can 'be pulse width modulated (PWM-od) at frequencias up to 10 KHz, ‘The 33186 is paramettcally spectfied over a temperature range of “40°C = Ty = 125°C, 5.0 V = V+ = 28 V. The IC can also be operated Up to.40 V with de-rating ofthe specifications, The IC is available in a surface mount power package with exposed pad for heat sinking Features + Overtemperature, Shor-Circuit Protection, and Overvattage Protection against Transients up to 40 V at VBAT Typical + RDSon = 150 m@ for each output Transistor at 25°C + Continuous DC Load Current § A (TC < 100°C) + Output Current Limitation at typ 6,5 A */- 20% + Short-Circuit Shutdown for Output Currents over B A, + Logic Inputs TTLICMOS Compatible * Operating Frequency up to 20 kHz + Undervoltage Disable Function + Diagnostic Output, 2 Disable Input *+ Coding Input for Altemative Functions * Stable Operation with an External Capacitance of Maximum 47 uF at BAT + Po.Free Packaging Designated by Suffix Code VW soy 33186 Document Number: MC33186 Rev. 6.0, 10/2006 33186 H-BRIDGE MOTOR DRIVER DH SUFFIX ‘VW SUFFIX (PB-FREE) PLASTIC PACKAGE, ‘98ASH7O7O2A 20-PIN HOP ‘ORDERING INFORMATION Figure 1. 33186 Simplified Block Diagram Freescale Somiconductor, In. reserves the ight to change the deta specifications, « a5 may be required, fo petit improvements in the design of is products © Freescale Semiconductor, In., 2007, All rights reserved. Temperature Device Range (Ta) Package MessTe8oHURe ~«0'Gto 1256 | 20HSOP CsSTBEMWHIRE Vee 2e. 7 freescale ‘semiconductorINTERNAL BLOCK DIAGRAM ce BAT VBAT VBAT to ee cree Pom ag oe . ee ee fet ¥al wot >| {Jour vege) gf onc cn 2 eae on Tt sal Over i] [Ecront tn op | befovicrieatve ae oud Fp coo] afore ar hho Figure 2. 33186 Simplified internal Block Diagram “Rralog Integrated Greuk Davice Data 2 Freescale SemiconductorLL PIN CONNECTIONS PIN CONNECTIONS. PIN CONNECTIONS Aa) ne ™ on veat e our on our an oo oe Poo 2] row ono Fe pow ‘Metal slug is connected to power ground (Top View) Figure 3, 33186 Pin Locations Table 1. 33186 Pin Description Pin Name Deseription 910, 14,12 PGND Power Ground Alline ground are connected together, they should be conneciog as short as Metal siug possible on the PCB 1 ‘AGND ‘Analog ground. Allthe ground are connecied together, they should be connected as short es possible on the PCB 2 Output | Open drain ouput, active low. eset accorcing to the nuh table When a feu appears, SF changes: ‘status tag (SF) | {Pilly in less than 100 ms. 313 Inguls Nt, IN2, | Votage controled inputs with hysteresis 18,19 it, pi, coo @ ‘cop \wmen not connected or connected fo GND, a stored false wil be reset by change ofthe vollgs level on Dit or 12 \Wnen connected te VCC, tho disable Pin DIY and DI2 ae inactive, A stored failure il be reset by change ofthe vote ievel on INT oF IN2. 6,7,14,15 | OUT, OUT2 | H-Bndge outputs with integrated free-wheeling diodes 33106 “fnalog Integrated Creu Device Data Freescale Semiconductor 3PIN CONNECTIONS Table 1. 39186 Pin Description(continued) Pin Name Description 4.5.16 veaT ‘The Pins 4 and Sars intemally connaced, Theses Pins supply the left high side and the analog/ogc pattof the device The Pin 16 supplies the rit high side and the charge pump. ‘The Pin 4, Sand 16 should be connected together on the printed excuit board wth connections as short as possible Supervision and protection functions 6) Supply vottage supervision ‘The supply voltage is supervised fits below ts specific thneshald, the power stages are swiched in stato and th status ag is switched low. tthe supply voltage is over tne pectic resold again, the power stage swicnes indopendontty inte narmal operetion, according to tne input Pins andthe status agi reset. ) Thomnal supervision In case of overtemporatute, tho power stages ar switched in tistate independent ofthe inputs signa and the status fag is surtoned low. I the level changes fem high to low on DI (INT) or low to high on DI2 (IN), the output stage ‘witos on again ifthe tomporatu is below the specified mi Tho status-1ag i eset to high lovel (Pin names in brackets refer to coding Pin = VEC) ©) Supervision of overcurent on high sies ani ow sides Incase ofover-current dotocton the power stages ae switcnedin state independent ofthe inputs signals and the status Nag is set Ifthe level changes fom nigh to ow on DI (IN1) or low to high an O12 (IN2) the output stage ‘wits on again and he status fag is reset to high level (Pn nares in brackets refer to coding Pin = vec) The output stage svitches int the mode defined by te inputs Pins provided, andi he temperature Is balow ne specie tts, 6) Current imiing on low sides The maximum current which can flow under normal operating Condtions is inted to imax = 6,5 A 7208. When the maximum current value s reached, the output stages are swiched tnstaa for ‘ged te. According tothe ume constant ine current decreases unt he next swan on accu. See age 8 for schematics v oP (Charge Pump output Pin ‘Atitering capactor (upto 33 nF) can be connected between Pin 17 and Gnd. Devieo can operate ‘without external capacitor, although Pin 17 decoupling capacitor help in noise reducton and alows, the davies to perform a maximum speed, tmng and PWM frequency. 33106 “Rralog Integrated Greuk Davice Data Freescale SemiconductorELECTRICAL CHARACTERISTICS, Table 2. MAXIMUM RATINGS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS. All voltages are with respect to ground unless otherwise noted, Exceeding these ratings may cause a malfunction or ‘permanent damage to the device, Notes Ratings Symbol Min WP Max Unit ELECTRICAL RATINGS Supply Vorege v Stic Destruction Proot Vex “10 - Ey Dynamic Destruction Proof < 0.5 Von “20 - 40 Legis Inputs (IN, IN2, DI, D2, GODE) u 0s. - 70 ‘Outout Siaius- Flag SF Use -05 - 70 v THERMAL RATINGS on —— rere SARIS an f . Gontrot A, Sonal > Status A Flog > Detail © Overcurrent detection 1 \ i oss ca hfe US eS . | L Z { - t= swteof time in currant imation I 13 = current imitation banking time | Figure 8. Current Limitation on Low Side 33106 “fnalog Integrated Creu Device Data Freescale Semiconductor "ELECTRICAL CHARACTERISTICS 2s 135) +7 ‘a 2m 125| 201 _8 280 Eng E79 a" E278 2 105} oon ‘o al ale Sos ss 2s. 250 25S] “TEMPERATURE ¢C) 1, TEMPERATURE (¢) Figure 9. Stand-by Current vs. Temperature Figure 12, High Threshold input Voltage vs. Temperature 5m 45 2a “[Gaabencabre 4.80/ — such on Vol — 5a Lt 470 = 0 = 460| ° 7 z +o = asl oa g 450 & 20] ‘4 40|__Sihich off Votage| | —4 ae 4.30 —t | 10 40 ‘sy 250 e780) 8 5 “TEMPERATURE CC) al Figure 10, VBAT Undervotage vs, Temperature oF eee tes Figure 13. vep vs. Batery Voltage o oa . say 7 ano fan a 1,86} 180) Fras 4 170 a E tad = 100 +,83| j 150] te 10 S 120 25025 807510018 ‘2 7. TEMPERATURE (C) 19 Sy sos 78 Figure 11, Low Threshold input Voltage vs. Temperature 33106 1, TEMPERATURE (°C) Figure 14, RDSON vs. Temperature 12 “Rralog Integrated Greuk Davice Data Freescale SemiconductorELECTRICAL CHARACTERISTICS t2-205u0 = motor (Ale) a oe out (svi) 5o 3 660 os : 2 eviet) 040 a 620 50 ee 1, TEMPERATURE (°C) Figure 15. Switch off Current vs. Temperature Figure 18, Switch off Time 1150 1700 tes} —}—_} |} | |_| 1600 z psi Ftch out gid 1550 = 8 15.00 ©1450 +400 / 1350 s balm! 13,00 a a re 7, TEMPERATURE (16) Figure 16, Overcurrent Detection vs. Temperature Figure 19. Output Switching Time: Tr § Hout) max 7A fe ete (| ai ate bt — feb Figure 17, Current Limitation Figure 20. Output Switching Time: 11 33106 “fnalog Integrated Creu Device Data Freescale Semiconductor 13ELECTRICAL CHARACTERISTICS loche= 168 Figure 21. Output OFF Delay Figure 24. High Side Overcurrent High Side Detection ib dhvidivy Q Figure 22. Output ON Delay =] aid (ava Note Curent rougn eral secretion doe, @125°C n case ot agate votage a OUTS Figure 25. Maximum Di2 Input Current vs. lout2, current Figure 23. Disable Delay Time 33106 “Rralog Integrated Greuk Davice Data 14 Freescale SemiconductorPACKAGING SOLDERING PACKAGING SOLDERING The 20 HSOP package is designed for enhanced thermal performance. The particularity of this packagais its copper base plate on which the power dias soldered. The base plato is soldered on a PCB to provide heat flow to the ambient and algo to provide a large thermal capacitance. Of course, the more copper area on the PCB, the better the power dissipation and transient behavior. We characterized the 20 HSOP on a double side PCB, The bottom side area of the copper is 7.8 cm?. The top. surface is 2.7 om, see Figure 28. Top Side Bottom Side Figure 26. PCB Test Layout Figure 27. PHSOP20 Thermal Response igure 27 shows the thermal response with the device ‘soldered on to the test PCB described on Figure 26. 33106 “fnalog Integrated Creu Device Data Freescale SemiconductorPACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS Important: For the most current revision of the package, vist ynywu{reescale.com and perform a keyword search on the 984, umber listed below. Ey SuSE. Seewbumcoa Samira 6: GAT 0-4 TOBE DEEMED AT el ee sorrow view ae ltt , vow Lae al ie [teas aie <7 ¢ «BRE ee “i Hea tes Hae wage] area wt SECTION Ww betas eeu tess [es] bb] eae a i ‘t = @ rm und vera ow sure wn eee) suse coe Seuseaie seer 33106 16 “Rralog Integrated Greuk Davice Data Freescale SemiconductorADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) Introduction This thermal addendum is provided as a supplement to the MC33188 technical datasheet, The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, pplication, and packaging information is provided in the datasheet. Package and Thermal Considerations. ‘The MC33186 is offered in a 20 pin HSOP exposed pad, single die package. ‘There is a single heat source (P), a single junction temperature (T,), and thermal resistance (Ra). {T)} = [Raw] {P } The stated values are solely for a thermal performance comparison of one package to another in a standardized environment, This methodology is not ‘meant to and will not predict the performance of a package in an application- ‘specific environment. Stated values were obtained by measurement and simulation according to the standards listad balow. ‘Sonar Table 5. Thermal Performance Comparison “Thermal Resistance rem Rate Fy Rag 20 Rea @ Rac) 20 Notes — “1 Per JEDEG.JESD51-2 at natal convection, si ae cnction 2 2s2p thommal test board por JEDEC JESO51-5 and JESDSt7. 3. PerJEDEG JESOS-8, vith the board temperature on the canter trace near the center lad, 4. Single layer thrmal test board per JEDEC JESDS1-3 and JESDStS 5. Thermal esistance betwoen the die junction and the exposed ad surface, cold pate attached tothe package bottom side, Femaining surfaces insulated [ADDITIONAL DOCUMENTATION ‘THERMAL ADDENDUM (REV 2.0) 33186DW 33186VW 20-PIN HSOP-EP DH SUFFIX VW SUFFIX (PD-FREE) ‘98ASH70273A 20-PIN HSOP-EP Note For package dimensions, rafor to the 33186 data shoot. = al measurements “~ Soldermast openings Thermal vias 20Pin HSOP-EP connected to top 1.6mm Pitch utd plana 160mm x11.0 mm Body 12. mm:x7 1 mm Exposed Pad Figure 28. Thermal Land Pattern for Direct Thermal ‘Attachment According to JESD51-5 33106 “fnalog Integrated Creu Device Data Freescale Semiconductor 7Fe ‘ADDITIONAL DOCUMENTATION See AReROUT Vo ~ 80 - t (in pa Agno] 1 0, _ 2o/2No sed 2 Vg come ‘ — wis 3 teson veated4 | larfSce 8 = : al veaTo|5 | | 16) vat 2| oui) 6 | | 18 sour ouney | Moun coo 8 [S00 PGNOI a | 12)" PGND pone 10 © = — — 4 | ypenp RORORSRORRORONOR ROROMRSRORCR. 33186DH1 Pin Connections 5 20PNHSOP-cP T ‘vemm Pics 2 46.0 mmx 11,0mm Bosy 1 123x'7'1 mm exposed pad Figure 29. Thermal Test Board Device on Thermal Test Board ‘Table 6. Thermal Resistance Performance Materia Single layer prntes circuit board ‘Atmel Rua rowd FR4, 1.6 mm thicknoss 5 Cutraces, 0.07 mm thicknoss ‘80 mm x 100 mm board area, 300 “ including edge connector for 600 47 thermal festng area Cuheat-sroading aroas on board Fesnis the thermal resistance between die junction and Gunes ambit ai ‘Ambiont Conditions: Natural convection, stil air 33106 “Rralog Integrated Greuk Davice Data 18 Freescale Semiconductor[ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0) 0 rm} x 2 eo . g 9 a es § 3 0 £ x» 5 2 wo] [Fe Raaromm ° 3 ate oo Heat Spreading Area A (rn?) Figure 30. Device on Thermal Test Board Ria 100 0 Fe Rassiroon ‘Thermal Resistance [°CAN 04 1006-03 1006-02 1.006-01 1.00600 100601 1.00E+02 100E+02 1 00E+O4 Times} Figure 31. Transient Thermal Resistance Ri, ‘1 W Step Response, Device on Thermal Test Board Area A = 600 (mm?) 33106 “fnalog Integrated Creu Device Data Freescale Semiconductor 19| REVISION HISTORY REVISION HISTORY [REVISION [DATE [DESCRIPTION OF CHANGES so | 52008 Implemented Revision History page {Added Lead Free (Pb-Free) Pat Number MC331B6VWt 30 roam06 Updated data shest formal ‘+ Romoved Peak Package Retlow Temperature During Refow (solder rofow) parameter fiom MAXIMUM RATINGS on page 5. Added noto with instructions to obtain this information fom we reescale cam. 33106 “Rralog Integrated Greuk Davice Data 20 Freescale SemiconductorHow to Reach Us: Home Page: ‘won roaseale.com Web Support hp awan teescalocomysupport USAlEurope or Locations Not Listed: Frestcals Semiconductor. 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