Black Miner

F1/F1+ FPGA Development Board User Guide

for third-part Support
User Guide
APP-D0001-1 Rev. A
April 22, 2019
 Revision history

Revision Date Description

A April 2019 Initial release

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 Contents

1 Introduction ....................................................................................................................... 4
1.1 Purpose ..................................................................................................................................................... 4

2 Hardware Information ....................................................................................................... 5

2.1 CPU Interface ............................................................................................................................................ 5
2.2 FPGA PIN Assignment .............................................................................................................................. 6

3 Block Diagram ................................................................................................................... 7

4 JTAG Interface .................................................................................................................. 8

Figures

Figure 3-1 HW Block Diagram........................................................................................................................................ 7

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 1 Introduction

1.1 Purpose
This document provides the information for third-party development on F1/F1+ board.

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 2 Hardware Information

This chapter describes the hardware interface information for proper setup.

2.1 CPU Interface

Following list is the pin information for HOST interface.

Table 2-1Pinlis for the HOST interface

Pin
Pin Name Direction Function Description Level
#
1 VCC3V3_Int Power Power This supply is from FPGA on board 3.3V regulator 3.3V
2 TEMP_ADDR1 Input Strap FPGA on board Temp sensor address setting 3.3V
3 UART_RXD Output UART FPGA output to CPU UART receive pin. 3.3V
4 UART_TXD Input UART FPGA output to CPU UART transimit pin. 3.3V
5 TEMP_ADDR0 Input Strap FPGA on board Temp sensor address setting 3.3V
6 RESET Input Control CPU reset signal to FPGAs 3.3V
7 CCLK Input Configuration FPGA Slave Serial mode configuration, CCLK 3.3V
8 GND Power Power Ground PIN 0V
9 GND Power Power Ground PIN 0V
10 DATA_DIN Input Configuration FPGA Slave Serial mode configuration, DIN 3.3V
FPGA Slave Serial mode configuration,
11 PROGM_B Input Configuration 3.3V
PROGRAM_B
12 RSVD RSVD RSVD Default to GND 0V
Board attached information to CPU, when FPGA
13 PLUG Output Control board attached to CPU interface, CPU will detect 3.3V
as High level
14 DONE OD Configuration FPGA Slave Serial mode configuration, DONE 3.3V
15 TEMP_SDA BI I2C I2C interface to on board Temp Sensor 3.3V
16 INIT_B OD Configuration FPGA Slave Serial mode configuration, Init_b 3.3V
17 VCC3V3_BB Power Power Power supply from external control board 3.3V
18 TEMP_SCL Input I2C I2C interface to on board Temp Sensor 3.3V

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<F1/F1+ FPGA Development Board User Guide for third-part Support><User Guide>

2.2 FPGA PIN Assignment

The following table list the PIN assignment for FPGA.

Table 2-2FPGAPINAssignment

PIN# PIN NAME Direction Description Standard

AB11 CLK_IN input 25MHz Clock input for FPGA from onboard Oscillator LVCOM18
P26 RESET_N input Reset signal input LVCOM33
Y26 OUT_1 output FPGA COMM Chain 1, ouput LVCOM33
AC26 IN_1 input FPGA COMM Chain 1, input LVCOM33
AB26 OUT_2 output FPGA COMM Chain 2, ouput LVCOM33
W26 IN_2 input FPGA COMM Chain 2, input LVCOM33
AD26 OUT_3 output FPGA COMM Chain 3, ouput LVCOM33
K26 IN_3 input FPGA COMM Chain 3, input LVCOM33
M26 LED_R output User LED indicator, Red LVCOM33
N26 LED_G output User LED indicator, Green LVCOM33
A17 ADDR[0] input FPGA Chip ID setting LVCOM33
A18 ADDR[1] input FPGA Chip ID setting LVCOM33
A19 ADDR[2] input FPGA Chip ID setting LVCOM33

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3 Block Diagram

Below is Block Diagram for the FPGA board for the commnunication port.

Figure 3-1 HW Block Diagram

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 4 JTAG Interface

JTAG is available on the board with 14-pin Molex socket, which is mated with the Xilinx USB
download cable.
To enalble the JTAG configuration for the FPGA bitstream, plese install the cap on J11 to short
the mode pin. As blow:

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