19-203-0806 LOW POWER VLSI DESIGN

Course Outcome:
On successful completion of teaching-learning and valuation activities, a student would be able
1. Identify the source of power dissipation.
2. Understanding low power design methodologies
3. Application of low power design principles in combinational and sequential circuit
design.

Module I
Power dissipation in CMOS VLSI Circuits,Need for low power VLSI chips, MOS Transistor
structure and device modelling, Dynamic Power Dissipation-Short Circuit Power-Switching
Power- Gliching Power, Static Power Dissipation, Degrees of Freedom, Scaling of device
dimensions , Impact of technology Scaling.

Module II
Leakage power minimization and supply voltage scaling Variable-threshold-voltage CMOS
(VTCMOS) approach, Multi-threshold-voltage CMOS (MTCMOS) approach, Power gating,
Transistor stacking, Dual-Vt assignment approach (DTCMOS), Dynamic voltage scaling, Impact
of supply voltage scaling on parallel and pipelined architectures.

Module III
Circuit and logic level power reduction techniques, Circuit level: Transistor and gate sizing,
network restructuring and Reorganization. Special Flip Flops & Latches design, high
capacitance nodes, low power digital cells library. Logic level: Gate reorganization, signal
gating, logic encoding, state machine encoding, pre-computation logic.

Module IV
Architecture level power reduction techniques and clock distribution, Power & performance
management, switching activity reduction, parallel architecture with voltage reduction, flow
graph transformation, low power arithmetic components, Adaptive filter design.
Low power Clock Distribution: Clock gating, Power dissipation in clock distribution, single
driver vs. distributed buffers, Zero skew vs. tolerable skew, chip & package co design of clock
network.

References:
1. Neil H. E. Weste, DavidHaris and Ayan Banerjee, CMOS VLSI Design, A circuits
and Systems perspective, fourth edition.
2. Pal, Ajit. Low-Power VLSI Circuits and Systems. Springer, 2015 edition.
3. Gary K. Yeap, Practical Low Power Digital VLSI Design, KAP, 2002,ISBN 981-02-
2518-0
4. Kaushik Roy,Sharat Prasad, Low-Power CMOS VLSI Circuit DesignWiley,2009
edition.

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