ARM PROGRAMMING

Bùi Quốc Bảo

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Assembly Programming
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AREA subrout, CODE, READONLY

; Name this block of code
u

ENTRY ; Mark first instruction to execute

cu

start MOV r0, #10 ; Set up parameters

MOV r1, #3
BL doadd ; Call subroutine
stop MOV r0, #0x18 ; angel_SWIreason_ReportException
LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit
SVC #0x123456 ; ARM semihosting (formerly SWI)
doadd ADD r0, r0, r1 ; Subroutine code
BX lr ; Return from subroutine
END ; Mark end of file

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 Define constant
NVIC_IRQ_SETEN0 EQU 0xE000E100
NVIC_IRQ0_ENABLE EQU 0x1
LDR R0,=NVIC_IRQ_SETEN0
MOV R1,#NVIC_IRQ0_ENABLE
STR R1, [R0]

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MY_NUMBER
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DCD 0x12345678
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HELLO_TXT
DCB “Hello\n”,0

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 {label} {instruction|directive|pseudo-instruction} {;comment}

Label: identify the location of program counter, can not

start by a number
Comment: any thing that follow a semicolon “;” “@” or C
style comment (/* */)

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Addressing mode
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MOV R0,#1234
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MOV R0,R1
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LDR R0,[R1]

LDR R0,[R1,#4]

LDR R0,[R1,R2]

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 The condition

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Instruction with condition

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All instruction contain a

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condition field which determines

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whether the CPU will execute

them

ADD R0, R1,R2 ;R0 =R1+R2

ADDEQ R0,R1,R2 ;R0 = R1+R2 if zero flag is set

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For ARM Cortex M3, the conditional
execution suffixes are usually used for
branch instructions.

However, other instructions can also be

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used with the conditional execution
suffixes if they are inside an IF-THEN

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instruction block

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By default, data processing operations

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do not affect the condition flags (apart from

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the comparisons where this is the only

effect).
To cause the condition flags to be
updated, the S bit of the instruction needs to
be set by postfixing the instruction (and any
condition code) with an “S”.
ADD R0,R1,R2 ;R0=R1+R2, flag will not affected
ADDS R0,R1,R2 ;R0=R1+R2, flag will be affected

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 Thumb2 instruction set

Thumb-2 is a superset of the Thumb

instruction set

Thumb-2 introduces 32-bit instructions
that are intermixed with the 16-bit

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instructions.

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Thumb2 instruction set

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Some of the operations can be handled by

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either a Thumb instruction or a Thumb-2

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instruction

ADDS R0, #1 ; Use 16-bit Thumb instruction
;by default

ADDS.N R0, #1 ; Use 16-bit Thumb
;instruction (N=Narrow)

ADDS.W R0, #1 ; Use 32-bit Thumb-2
;instruction (W=wide)

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 Data Processing Instruction

All sharing the same instruction format.

Contains:
 • Arithmetic operations
 • Comparisons (no results - just set condition codes)
 • Logical operations
 • Data movement between registers

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Remember, this is a load / store architecture
 These instruction only work on registers, NOT memory.
 They each perform a specific operation on one or two

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operands.
 First operand always a register - Rn
Second operand sent to the ALU via barrel shifter.

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Arithmetic
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Operations are:
 ADD operand1 + operand2
u

 ADC operand1 + operand2 + carry

 SUB operand1 - operand2
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 SBC operand1 - operand2 + carry -1

 RSB operand2 - operand1
 RSC operand2 - operand1 + carry – 1
 MUL operand1 * operand2
 UDIV operand1 / operand2 (unsigned)
 SDIV operand1 / operand2 (signed)

Syntax:
<Operation>{<cond>}{S} Rd, Rn, Operand2

Examples:
ADD r0, r1
SUB.N r3, #1
SUBS.W r3, r3, #1

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 Using the suffix

When 16-bit Thumb code is used, an ADD

instruction changes the flags in the PSR.

32-bit Thumb-2 code can either change a flag
or keep it unchanged.

To separate the two different operations, the S

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suffix should be used if the following operation
depends on the flags:

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ADD.W R0, R1, R2 ; Flag unchanged
ADDS.W R0, R1, R2 ; Flag change

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Comparisons
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The only effect of the comparisons is to UPDATE

THE CONDITION FLAGS. Thus no need to set S bit.
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Operations are:
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• CMP operand1 - operand2, but result not written

• CMN operand1 + operand2 (signed), but result not written
• TST operand1 AND operand2, but result not written
• TEQ operand1 EOR operand2, but result not written

Syntax:

<Operation>{<cond>} Rn, Operand2

Examples:
• CMP r0, r1
• TSTEQ r2, #5

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 Logical Operations

Operations are:
AND operand1 AND operand2
EOR operand1 EOR operand2
ORR operand1 OR operand2
BIC operand1 AND NOT operand2 [ie bit clear]

Syntax:

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<Operation>{<cond>}{S} Rd, Rn,operand2

Examples:

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AND r0, r1, r2
BICEQ r2, r3, #7

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EORS r1,r3,r0
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Data Movement
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Operations are:
u

MOV{S}{cond} Rd, Operand2

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MOV{cond} Rd, #imm16

MVN{S}{cond} Rd, Operand2
Examples:
• MOV r0, r1
• MOVS r2, #10
• MVNEQ r1,#0

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 Loading full 32 bit

Instead of MOV, this instruction is

prefered:

LDR Rd, =numeric constant

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Ex:
LDR R0,=0x42

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Commonly Used Memory Access

Instructions
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LDRB Rd, [Rn, #offset] Read byte from memory location Rn+ offset
u

LDRH Rd, [Rn, #offset] Read half-word from memory location Rn+
offset
cu

LDR Rd, [Rn, #offset]
LDRD Rd1,Rd2, [Rn, #offset]
STRB Rd, [Rn, #offset]
STRH Rd, [Rn, #offset]
STR Rd, [Rn, #offset]
STRD Rd1,Rd2, [Rn, #offset]
Read word from memory location Rn+offset
Read double word from memory location
Rn+offset
Store byte to memory location Rn+offset
Store half word to memory location
Rn+offset
Store word to memory location Rn+offset
Store double word to memory location
Rn+offset

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 Multiple Memory Access Instructions

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The exclamation mark (!) in the instruction specifi es

whether the register Rd should be updated after the
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instruction is completed. For example, if R8 equals

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0x8000:

STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after store

; (increment by 4 words)
STMIA.W R8 , {R0-R3} ; R8 unchanged after store

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 Pre-index Addressing

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Post-index addressing
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 om
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Pre-index addressing
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R0  [R1+4]

LDR R0,[R1,#4]! R1 = R1 + 4
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LDR R0,[R1,R2]
cu

LDR R0,[R1,R2,LSL # 2]!

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 Post-index addressing
R0  [R1]

LDR R0, [R1], #4 R1 = R1 + 4

LDR R0,[R1],R2

LDR R0,[R1],R2,LSL # 2

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Branch instruction
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The BL and BLX command will save
return address into the LR of current
bank

To return from subroutine, restore the

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PC from LR:
 MOV PC,LR

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 Another instruction to return is: BX LR

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Nested function call

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main
...
BL functionA
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...
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functionA
PUSH {LR} ; Save LR content to stack
...
BL functionB
...
POP {PC} ; Use stacked LR content to return to main
functionB
PUSH {LR}
...
POP {PC} ; Use stacked LR content to return to functionA

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 If-then instruction (IT block)
IT<x><y><z> <cond>
instr1<cond> <operands>
instr2<cond or not cond> <operands>
instr3<cond or not cond> <operands>
; IT instruction (<x>, <y>,
; <z> can be T or E)
; 1st instruction (<cond>
; must be same as IT)
; 2nd instruction (can be
; <cond> or <!cond>
; 3rd instruction (can be
; <cond> or <!cond>

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instr4<cond or not cond> <operands> ; 4th instruction (can be
; <cond> or <!cond>

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If-then instruction (IT block)

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if (R1<R2) then
R2=R2-R1 and R2=R2/2
else
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R1=R1-R2 and R1=R1/2

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CMP R1, R2 ; If R1 < R2 (less then)

ITTEE LT ; then execute instruction 1 and 2
; (indicated by T)
; else execute instruction 3 and 4
; (indicated by E)
SUBLT.W R2,R1 ; 1st instruction
LSRLT.W R2,#1 ; 2nd instruction
SUBGE.W R1,R2 ; 3rd instruction (notice the GE is
; opposite of LT)
LSRGE.W R1,#1 ; 4th instruction

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 PUSH and POP
PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into
; stack memory
POP {R2,R3} ; Pop R2 and R3 from stack

Use POP as function return:

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PUSH {R0-R3, LR} ; Save register contents at beginning of
; subroutine
.... ; Processing

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POP {R0-R3, PC} ; restore registers and return

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Special register
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Program Status Registers (PSRs)

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Application PSR (APSR)

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Interrupt PSR (IPSR)

Execution PSR (EPSR)

Interrupt Mask Registers

PRIMASK

FAULTMASK

BASEPRI)

Control Register (Control)

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 Access the special registers

To access the special register, one can use MRS and
MSR command:
MRS r0, APSR ; Read Flag state into R0
MRS r0, IPSR ; Read Exception/Interrupt state
MRS r0, EPSR ; Read Execution state
MSR APSR, r0 ; Write Flag state
MRS r0, PSR ; Read the combined program status word
MSR PSR, r0 ; Write combined program state word

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MRS r0, CONTROL ; Read CONTROL register into R0
MSR CONTROL, r0 ; Write R0 into CONTROL register
MRS r0, BASEPRI ; Read BASEPRI register into R0

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MRS r0, PRIMASK ; Read PRIMASK register into R0
MRS r0, FAULTMASK ; Read FAULTMASK register into R0
MSR BASEPRI, r0 ; Write R0 into BASEPRI register

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MSR PRIMASK, r0 ; Write R0 into PRIMASK register
MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register
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Block Data Transfer

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