\worwchipdoes.com HD6321/HD6821 PIA (Peripheral Interface Adapter) ‘The HD6321/HD6821 Peripheral Interface Adapter provides the universal means of interfacing peripheral equipment to the [HD6800 Microprocessing. Unit (MPU). This device is capable of interfacing the MPU to peripherals through two &bit bt irectional peripheral datz buses ané four conteol lines. No external logic is requited for interfacing to most peripheral devices The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be programmed to act aan input or output, and cach of the four contrlfinterrup lines may be programmed for fone of several control modes. This allows a high degree of Aexibity in the overall operation of the interface. FEATURES © Two Bidirectional 8.it Peripheral Data Bus for interface to Peripheral devices 1 Two programmable control, Data Direction Registers © Four individually Controled Interrupt Input Lines: Two Usable as Peripheral Contro! Outputs © Handshake Control Logic for Input and Output Peripheral Operation Ay, CA: Port A (PAy ~ PA;) cA;, cB, Port 8 (P&) ~ PB.) © High-Impedance 3State and Direet Transistor Drive Periohe ral Lines © Two TTL Drive Capability on All A and B Side Butters 106321- Low-Power, High Speed, High-Density CMOS. 1 Wise Range Operating Voltage (Vee = SV * 10%) © Compatibie with NMOS PIA (HD6B21) (Refer to Electrical Specification as to Minor sifference] =HDs821— ' Compatible with MCB821, MCSBAZ1 and MC68B21 TYPE OF PRODUCTS Moea21P, Ho6e21P (wP-40) HDe32FP (FP say ‘Tha specifications of the HO6I21 ae for preliminary and may ‘change hereafter. Please make an inquire at sale office upon adoption of the HOS321 Type No. | Process | Giock Frequency | Package HOS321P 1OMH2 HOBSARTP 1sMHe | DP.40 HD63821P 20MM —HDeIBRIP_| cyos | —20MHe_ HOSS2TFP +0MHe HDSSARIFP 15MM | FPS HD63B21FP 20MM? HD6821P 0 MHz HOBSAZIP 1SMHz | BPO Ho6sEZIP | aig | _20 Mie HDsE21 1OMH HDseAzI asMHz | 06-40 HD6EB21 20MHz | @HITACHI 660 Hitachi America, Ld. * Hitachi Plaza © 2000 Siera Point Pkwy. « Brisbane, CA 94006-1819 « (415) 589-8300 Be sure to vist ChipDocs web site for more information.HD6321/HD6821 = ABSOLUTE MAXIMUM RATINGS tm Syme —_ _ nit Sassy Voie ve" “aa~ 1710 [ 03~ 70 v Input Vote Vin ~aa~710 [0370 v Taxon Output Curent Tal 70 = ma Waximum Tot Output Caren’ | 131g 00 na Operating Temperature Toor =20~ +75 =20~ 375 °C. ‘Storage Temperature Tso “35 ~ +180 =55~ +160 °C. Wits pect vo Vg (SYSTEM GND} “+ Maxenom output current he maximum crret wich ea low na flow out rom one out terminal and 1/0 common terminal, (PAg=PAy, Cag. PO ‘Op-Oa1 ‘++ Maxima tot) output currant ithe orl wom of output currant whic cn low no low out simultaneously from outout {teminls ond /S como twimiai, BA Phy, Car, Pg PB4, CBs, 0007! (NOTE) Purmenent LS} damage may ocur if maximum rings a4 axeaadad. Norma operation snout be under recommndad ‘perating condone, thes condition are exceed, Ke coud eect voloity of (St ‘= RECOMMENDED OPERATING CONDITIONS I 06321 06821 fem Symbol rin] yp [max [min] we [omen | Ut Supply Voroge Vee* | 48 | 50 | 55 | 475] 80 | 525 | v ngut “Low” vortage vur [0 os {-o3 | - | os Tv 0,~05. PA } Ps, Car, CAs Input “High” | pe. pay 22 Yee voltage” | Poe Pr . | vin - bf | - | ve] v CS, C3,,AS0 a0" Vee As, RES | ‘Operating Temperature [tor [-% | » | w= | -% | w | | % + wie pect to Vag (SYSTEM GND) ++ chasctritin l bm ieroved @HITACHI Hitachi America, Ltd, © Hitachi Plaza © 2000 Sierra Point Pkwy. » Brisbane, CA 94006-1619 « (416) 589-8300 661 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 = PIN ARRANGEMENT © HD6321P, HD8871P ss2 Eda. (Top View) (Top View) (0P-40, 0¢-40) (P54) @HITACHI 662 Hitachi America, Lid. « Hitachi Plaza + 2000 Siera Point Pkwy, » Brisbane, CA 94005-1819 + (415) 589-6900 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 1 BLOCK DIAGRAM @HITACHI Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8300 663 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 = ELECTRICAL CHARACTERISTICS © DC CHARACTERISTICS (HOG32 -20 ~ 475°C, unless otherwise noted.) /ec™ BV *10%, HDB8Z1: Voc * BV 25%, Vas * OV, we a ro oat ad “Test Condition | min. [tye |wax | Test Condition | min [eve* [maw O"* 35-8; Pae=Pay 7 eh Gin Page a2 | — ve | Input “igh Voitage | C81 C82. yy, + 0 | = fvee| v eR m Z , | Traore Votes | Ai ioe vi =oa_|— [oa =a |- eal y | RC REE As a, i Ieour emanecrrnt | 9,681,081. | tin |VinO~Vee |-28 |= )28 |Vmeonvee [as | |25) un * cae ‘hase Sue (OH aw) | PAO-PAD CAD Tees 0 test | vqro4-vee| 10 | - | 10 |[vanoe-zayins 7 int "gh Sart mL Vinee [me |=) - Toa Inne “Low Curant | yPRo, CAs rn" vu-ow | - =a ma Dy 0s j eS ee ign = BOA fon 6a Toustemn | = [~ [ea fior=na ut “Low” Vtg vor figteaam | |- | og [ouztena v _ toys 32mA Von=24v - vous wor cnet | Phys, Cas ton Vou = 240 7 «| pae=ras. ces Vow 18 ma up Lanne Guar] re man T tm Sel | TON om fvowsvee | - |= | 1] vone2ev | = | - 5 10) ua | Yvmeov [= [= |usfvmrov | — | - las nov apace J em we ~ | nol ~ | a vu casctence | ROE DR | ou ~ |= 106 ——t 1 1 he Par, CAs, Po | ral C8, weowectiog | senoienot cad, | | Seve ot \" a Vin min = Vee - 0.8 a | Sey Caran vit 0 , | “WP Ag~ Pay, CA ane 1 | sured ve mut na Ser Oa 008 [coer For Dapaton Fo SE Ta 28°C, Veo = 50V HO6B821; Voy =22V min IPAp~ PA, CAs) area eu wm ue. Ate rt il once cyy ard bara cpt nea he @ HITACHI 664 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 ‘* AC CHARACTERISTICS (HD6321; Veg SV # 10%, HDGB21; Vee SV + 5X, Vos * OV, Ta ~20 ~ 478°C unless otherwise noted) 1. PERIPHERAL TIMING = Pros [rc one aim ea Tages. Troma Tessas, Tego Da romp on Tecra tex [wo = [oo = [wo] foo t-te] fort to robe on "in eee tote ee eel eld olde ne SEVER TE wn scam [can [roms | - [ae] - [ae] - [xe] = foe] [om | fm] reed Reet TE [owen oem [a | ve? |= [=|] - =~ fl lel bel Meetteramr™eucen [uw | reo [lu ~ [welll huol ~ hoo] - fel ‘eer Te rom ca i Sim ectorw ch, oa som wwe | a | |200) — [200] = 200] - jano0} - fraso] — froco} me SEehors ENN |encerwinet cre pom | Me ras | - [am |= | 200] - |200] ~ froco] ~ Jer ) - ] 00 | me ‘ay Tir, Raia mane | Eni Poart Vee_30% Von Boe Se vais PitLas.cay ra ‘Daur Tine, ease Sree cease” | entice, tear | reatar | - [200] - [20] - |am] - froo0} - [ero] - | 100] me ‘ei Ting. Ppt Ooms T Gai G8, "ette | peipnert one vcs, | toc | fas | | - | | - | [| a] - | 20] - | m) - | Ganon cbs scam” | Eraie + 085 ast ra.6 | = |200| - | 200] - | 200] ~ |r000] - | 670 | ~ | soo} me Prot! Convo! Out Risin easicar [cas os icy | Fo.2.F0.6 | 80 | - |ars| - |250| - | oxo -|m ie paral To for CB |, ver | -|wo]- rm} - |r| - rool ees ure 1 te | 0 oe ‘Datey Time, CB wet | Fantion €8;‘pntiwe |B: =c8 tasz | 27 | ~ [200] - [m0] - j200] — foooo) - [rsso} — fro00| RGR ona ROS ROR, TRB tm | rae | - [000] - [mo] - [ooo] - fseoo] - [sr00} — | eo m Inarupt Reson Tie | ROK OW ‘asa_|__rae | = [ao] — [wo — [co] — [roo] — [roo] — [ro00[ ‘marvtrow Pol Wath [CAs,CAa,CB.6e | rm | ree fetta] ~ [ala] — late] - om] — [poor] - for] — [me Rowton Tne [RES vai | wt [mo] = [x0] —] x0 |= [ooo] — fom] — Tom] — Tw “rhe tina must be “High amnion dein th PUA ‘+ Ate ove Erle "ph pula hod be ned nh aod @HITACHI Hitachi America, Ltd.» Hitachi Piaza * 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 665 wwchipdocs.com Be sure fo visit ChipDocs website for more information.#HD6321/HD6821 2. BUS TIMING 1)_READ weaai_[ womans | woeveni | woseni_[ Hoseaat | Wommazt ‘on [trentot | Tox Consion ro [man [win Joon [in [max] min [oon [mn [rar] ein [ro | “tea cree Te Reet Fete] 68} Te foo eee] Pe Erb ui Wh, Lo re) | «s0] - 200] - [20 | - Jew) — ooo - [20] - | Erbium Rin wd Fotis [ter] Fo | -| | -] *[-|]-] [-] ||] sap tine [Action affine [tas] fmt? | 0] - | eo] - 140 | ~]ro) - [mo -| mf - [ow Tres Hee fam | fe? | 0] - | | -)w[-] w]-] w]-| wl -|w “bet uty Fine oon] fas | -|20| - [rw] - [roo] - [amo] - [xo] - [roo] w Bw Wald Tine fonn | ta12 | z0[ 10] 20] 100] = |r] | - | | -| | - | 2) ware T ‘wossazi | woesent | _wousat | woseazt | woeeeat ten lm | Ter Condon * ee noe | Meee notte ane Erie oven Tine fact | Furr [roo] - foos) — [soo] - from] - foo] - [om] - [o Enable ut Wath Pen | Fe | aso] - [200] - [2m | - | aso - [200] - [po] - tw Eni ut Wi, “Low” me, | ran | oo] - [am - [no] | «ol - || - [a] -]~ Enable Pula Rene fu Tirws [enter] ra | -| | -| | -] =] -[ | -] | -| =) sp To Mas [ore fmt - | eo fo] - fol -[ et Assen Hid Fie [ Aion, RAE yy | Fata | 10} - | 10 es ‘ei Sup Tone iow | rata | ves! -| | -| | -| ws -|@[-|@|- |» et ot Tie how | ren | of -[ | -] | -] o[-| «[-[~]-]™ @HITACHI 666 Hitachi America, Ltd. » Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 + (415) 589-8300 \worwchipdoes.com Be sure to vist ChipDocs web site for more information.ata Setup and Hold Times (Read Mode} Figure 1 Periphe able cay Figure 3 CA; Delay Time (Revd Move: CRAS=1, CRA3*CRAS=0) ce, Vee-20v"** (note) C8, gon “Low” ana rent oh Soertransonot Eno. Figure § Peripheral Data and CB, Delay Times (Write Mode; CRBE=CRBI*1, CRBE=O} bie TN ~——_——— “ Tannov"** 8, Vou ma + Aummes part as devel ing Figure 7 CBy Delay Time (Wriwe Mode; CRBS=1, CRB3-CRA40) ++ 0.8 for HD6921, 0.4V for HOSE2! s+ 2AV for HO6821 @HITACHI Hitachi America, Ltd. « Hitachi Plaza + 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 \worwchipdoes.com nie __HD6321/HD6821 Figure 2 CA; Delay Time {Read Mode; CRAS*CRA3=1, CRA4=0} Figure 4 Peripheral Data Delay Tiras (Write Mode! CRAS*CRA3=1, CRAS=0) rae * haus para nce ring he Figure 6 CB, Delay Time (write Mode; CRBS=CRB3=1, CRB4=0) ©A,.cA, 8,08, THOR ROB + Asses vert Enable Bt ar Figure & Intevrupt Pulse Width and TAG Response 667 Be sure to vist ChipDocs web site for more information.HD6321/HD6821 Tw ue wo _ ke The RES line rust be # Vi94 for 8 minimum of TBusbatore aorerung the POA Figure 9 TAG Ret Time Figure 10 RES Low Time me aus Yee -20¥ Vec-20V"*" Owe Bus Yon ia Yin in av oav viene yi ex Figure 12. Bus Read Timing Characteristics Figure 13. Bus Write Timing Characterstics (Read Information trom PIA) (Write Information into PIA) Loan 8 A, .¢8,) ones, AL +240 “Tex Point estar Rong (408921), 12ke. (HOSEN) oo 300 A lode 0152074" equivalent Retoer osr2n, 110 o6821) ‘Asisat R10 that LoL = 1.8m, then wt Vou ‘Adjort a0 thet Igy © 3.2m, then tert VO soa c a , ARE ony Loo 0 woee21) gsov (©MOS Lond) Tes Point an Ton Point 209 " in Figure 14 Bus Timing Test Load @ HITACHI 668 Hitachi America, L1d. » Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 * (415) 589-6300 wwchipdocs.com Be sure fo visit ChipDocs website for more information.\worwchipdoes.com © PIA INTERFACE SIGNALS FOR MPU ‘The PIA interfaces to the HD6800 MPU with an eight bit bidirectional data bus, three chip select lines, two register select lines, two interrupt request lines, read/write line, enable line and reset line. These signals, in conjunction with the HD6800 ‘YMA output, permit the MPU to have complete control over the PIA, VMA should be utilized in conjunction with an MPU addeess line into a chip select of the PLA. © BiDievetional Data (Do ~D} Pin No, 33 ~ 26 (DP-40) Pin No, 43 ~ 36 (FP-54) Input ‘The bidirectional data lines (Dy ~ Dy) allow the transfer of data between the MPU and the PLA. The data bus output drivers are three-state devices that remain in the high-impedance (off) ‘ate except when the MPU performs a PIA read operation. The R/W line isin the Read ("High") state when the PLA is selected for a Read operation. = Enable (E) Inpur/Output Pha No. 25 (DP-40) Pin No. 32 (FP-S4) The enable pulse, E, is the only timing signal that is supplied to the PIA. Timing of all other signals is referenced to the leading, and trailing edges of the E pulse. This signal will normally be & derivative of the HMCS6800 System #3 Clock ‘This signal must be continuous clock pulse. + Read/Write (RAW) Pin No. 21 (DP-40) Pin No. 28 (FP.S4) Input This signal it generated by the MPU to control the direction cof data tranafers on the Dats Bus. A “Low” state on the PIA. line enables the input buffers and data is transferred from the (MPU to the PIA on the E signal ifthe device has been selected. ‘A “High” on the R/W line sets up the PIA for a transfer of data to the bus, The PIA output buffers are enabled when the proper address and the enable pulse E are present. © Rew (RES) Input Pin No, 34 (DP-40) Pin No, 44 (FP.S4) ‘The active “Low” RES line is used to reset all register bi the PIA to a logical zero “Low”. This line can be used power-on reset and as a master reset during system operation. ‘* Chip Select (CS,, C8, and TS) HD6321/HD6821 Pin No. 22, 24,23 (DP-40) Pin No, 29, 31, 30 (FP-S4) Input ‘These three input signals are used to select the PIA. CS» and CS, must be “High” and CS, must be “Low” for selection of the device. Data transfers are then performed under the control of the E and R/W signals, The chip select Unes must be stable for the duration of the E pulse. The device is deselected when any of the chip selects are in the inactive tat. © Register Select (RS, and RS,) Input Pin No, 36, 35 (DP-40) Pin No, 50, 45 (FP-54) ‘The two register select lines are used to select the various registers inside the PIA. These two lines ae used in conjunction with internal Control Registers to select a particular register that 1s to be written or rea. ‘The register and chip select lines should be stable for the uration ofthe E pulse while in the read or write cycle. Interrupt Request (RGA and IRCB) Input Pin No. 38, 37 (DP40) Pin No. $2, 51 (FP.54) ‘The active “Low” Interrupt Request ines (TEA and TRGB) fact 10 interrupt the MPU either directly or through interrupt Priory circuitry. These lines are “open drtin” (no load device fn the chip). This permits all interrupt request lines to be ted together in wire-OR configuration. Each TRO line has two internal interrupt fag bits that can ‘cause the IRG line to go "Low ”. Each fg bit is amociated with & particular peripheral interrupt line. Also four interopt enable bits are provided in the PLA\which may be used to inhibit a particula interrupt from a peripheral deve. Servicing an interrupt by the MPU may be accomplished by 2 software routine that, on & prioritized basis, sequentially reads and tess the two contol registers in each PIA for interrupt fag bits that ae set, ‘The interrupt fags are cleared (zeroed) a result of an MPU Read Peripheral Data Operation of the comesponding data repster. After being cleared, the interrupt flag bit cannot be enabled to be set until the PIA is deselected during an E pulse The E pule is used to condition the interrupt controf lines (CAs, CAy, CBy, CBy). When these lines are used as interrupt inputs at least one E pulse must oocur from the inactive edge to the active edge of the interrupt input sigaal to condition the edge sense network. Ifthe interrupt flag has been enabled and the edge sense circuit has been properly conditioned, the interrupt flag will be set on the next active transition of the Anerrupt input pin, @HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 + (415) 589-6300 669 Be sure to vist ChipDocs web site for more information.HD6321/HD6821 "= PIA PERIPHERAL INTERFACE LINES. The PIA provides two 8.bit bi-directional data buses and four {nterrupt/control lines for interfacing to peripheral devices, ‘There is difference between HD6821 and HD6321 in Port structure. Fig. 15 shows the block diagram of Port A and Port B in HD6321. The output driversof Port A and Port B consist of threestate drives, allowing them to enter a Highimpedance state when the peripheral data line is used as an input. Port A and Port B have the same output buffer. But the circuit con- figuration is slightly different and this makes the difference on data flow when MPU reads Port A and Port B in the case each Port is specified as output. As shown in Fig. 15, the output of the peripheral data A is transferred to internal date bus when ‘wed as output. On the other hand, in the case of Port B the contents of output register (ORB) is directly transferred to internal data bus through the multiplexor. Secondly the equivalent circuit of the port in HD6821 is shown in Fig. 16. The output circuits of A port is different from that of B port. When the port is used as input, the input '& pullup to Vee side through load MOS in A port and B port becomes “OAT” (high impedance). on 1 hoa a fo pox Faure 15 lock Diogram of Port Aand Port 8 (HOBSZN! acl ous a rep Fo a B on Pom From ORB 4 to pon pon Figure 18 Circuit of Port A and Port B (HD6821) @HITACHI 670 \worwchipdoes.com Hitachi America, Ltd. « Hitachi Ptaza © 2000 Siarra Point Pkwy. « Brisbane, CA 94006-1819 » (415) 589-8300 Be sure to vist ChipDocs web site for more information.\worwchipdoes.com (© Port A Peripheral Data (PAy~PAr) HD6321/HD6821 Peripheral Control (CA;) Input/Output Pin No. 2~ 9 (DP-40) Pin No.2~ 5,9~ 12(FP-S4) Pin No, 39 (DP40) Pin No. 53 (FP-54) Input/Output ach of the peripheral data lines can be programmed to act as an input or output, This is accomplished by setting aL" in the corresponding Data Direction Register bit for those tines which are to be outputs. A “0” in abit of the Data Direction Register causes the corresponding peripheral data line to act a8 ‘an input, During an MPU Read Peripheral Data Operation, the data on peripheral lines programmed to act as inputs appears directly on the corresponding MPU Data Bus lines. ‘The data in Output Register A will appear on the peripheral ata lines that are programmed to be outputs. A logical “I” ‘wntten into the register will cause a “High” on the correspond: ‘ng peripheral data line while a “0” results in a “Low”. Data in Output Register A may be read by an MPU “Read Peripheral Dats A” operation when the corresponding lines ae programm ed as outputs But concerning HD6821, this data will be read properly if the voltage on the peripheral data lines is greater than 2.0 volts for a loge “I” output and less than 0.8 volt for 2 logic “0” output. Loading the output lines such that the voltage on these fines does not reach full voltage causes the data transfered into the MPU on 2 Read operation to differ from that contained in the respective bit of Output Register A. © Port ripheral Data (PB ~ PB>) ‘The peripheral control line CAz can be programmed to act 18 an interrupt input or asa peripheral control output. “The function of this signal is programmed by the Control Register A. When used as an input, ths signal is in High-m- pedance state ipheral Control (CB) Input/Output Pin No. 19 (DP-40) Pin No, 26 (FP-S4) ‘The peripheral Control line CB, may also be programmed to act as an interrupt input or peripheral coatrol output ‘This line is programmed by Control Regster B ‘When used a an input, this signal i in Highsmpedance, (NOTE) |. Pulse width of interupt inputs CAs Ca CB: and (CB, shall be greater than aE cycle time. Inthe case that “High” time of E signal is not contained in Interrupt pulse en interrupt flag may not beset. Input/Output Pin No. 10~ 17 (DP.40) Pin No. 13 ~ 18, 23 ~ 26 (FP.S4) Each of the Port B peripheral data bus can be programmed to.actas an input or output like PAy ~ PA PB, ~ PB; ate in High-mpedance condition because they are three-state outputs just like PA ~PBy when the peripheral buses are used a6 inputs, when programmed ss outputs, MPU sO Electrical Characteristics (1)0C characteraties tead of Port B make i posible to read the output RSE tan Syn [oma | Armas Yong feqardless of PBy ~ PB; loads and concerning HD6821, these tot frame [in [a Tine may be wed as a source of up to 2.5 mllampare (typ) on 21.5 volt to directly dive the base of transistor switch input [Poovey Car caz| | 22 | Yeo . ) sgn [08 vn 22 | vee | ¥ Inwerupt Input (CA, and CB ee cree xt [TSp, Sp, RSs. FES| ve} Input Pin No. 40, 18 (DP-40) aracteitic (Only tr H08382) Bn No.4 1 eet {@)AC Gnaracterates (Ont for HOS3E21) ‘tem ‘symbot } 06 Fase F.mes* una ‘The peripheral Input lines CA, , and CB, are input only lines Timing EAB) mo max min mak that set the interrupt flags of the control registers. The active GUE TINNGIREAD) | vo transition for these signals is also programmed by the two con- Setup Time (across, | tas | 60 “ trol registers BAW Enable) 1 Trg (ATED Seuptime adsoss, | tas | © “0 RI.Enasie) @HITACH! Hitachi America, Ltd. Hitachi Ptaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (416) 89-8300 671 Be sure to vist ChipDocs web site for more information.\worwchipdoes.com ———— HD6321/HD6821 “Oe mask arson ot tienter o6921 Hoss21FP JAPAN JAPAN = = nak en sour vaaaT Hoss21 HosaaieP sAPAN | JAPAN mun am # INTERNAL CONTROLS ‘There ate sx locations within the PLA accesible tothe MPU data bus: two Peripheral Regsters, two Data Direction Re- Bates, and two Control Registers, Selection of these locations it ‘controlled by the RSg and RS, inputs together with bit 2 in the Conteot Register, as shown in Table 1 Table 1 intemal Adsressing rs, {ons, [omar [CAST | Location Selested pet Pacoheral Regate AY Tconwet Rosine A op Perghera Rega Oyo Besa Devcon wpe pL coniot Reser 8 tw conning oepher ton reset line has the effect of zeroing all PIA registers, ‘This wil set PAg~PAs, PBy~PB;,CAs and CB; 48 inputs, and all interrupts disabled. The PIA must be configured during the restart program which follows the reset. Details of possible configurations of the Data Direction and Conteot Register are as follows. © Data Direction Repistan (DORA and DORB) The two Data Direction Registers allow the MPU to control the direction of data through each comesponding peripheral data line. A Data Direction Register bit set at""O” configures the corresponding peripheral data line as an input: an output. * result in © Control Registers (CRA and CRB) ‘The two Control Registers (CRA and CRB) allow the MPU to control the operation of the four peripheral control lines CA , CA,,CB, and CB. In addition they allow the MPU to enable the interupt lines and monitor the status ofthe interrupt Mags Bits 0 through 5 of the two registers may be written or read by the MPU when the proper chip select and resister select signals are applied. Bits 6 and 7 of the two registers are read only and are modified by external interrupts occurring on contol lines Ay, CAs, CBy oF CBy. The format of the control words is showin in Table 2. ‘Table 2. Control Word Format 7 es [+13 z 7 =| cna TRGAT [Rana] CA; Cones | BORA | CR Conor eee Ge, conral | Bo Date Direction Acces: Control Bit (CRAZ and CRE) Bit 2 in each Control register (CRA and CRB) allows selection of either a Peripheral Interface Register or the Data Direction Register when the proper tegster select signals are (a RSp and RS, pt Flags (CRAG, CRAT, CABS, ond CRB?) ‘The four interrupt Mag bits are set by active transitions of signals on the four Intecrupt and Peripheral Copiral lines when those lines are programmed to be inputs. These bits cannot be set directly from the MPU Data Bus and are reset indizectly by 4 Read Peripheral Data Operation on the appropriate section. Control of CA, and CB, Interrupt Lines (CRAAD, CABO, CRAI, snd cREN) ‘The two lowest order bits ofthe control registers ae use to control the interrupt input lines CA, and CBy. Bits CRAG and CRBO are used to enable the MPU interrupt signals IRQA and TROB, respectively. Bits CRAL and CKBI determine the active jun of the interrupt mput signals CA, and CB, (Table 3) CA; and CB, Peripheral Conttot Lines (CRA3, ‘CRAG, CRAS, CRBS, CAB4, and CRBS) Bits 3, 4 and 5 of the’ (wo control registers are used to control the CA; and CB; Peripheral Control lines. These bits determine if the control lines will be an iniettupt input or an 7 . cone [inGav | vRO87 rt CRAS (CRBS) is that may be used to control peripheral data transfers. When in CAs (CB,) becomes an output signal the output mode, CA, and CB, have slighily eifferent characteristics (Table 5 and 6). @HITACcH! 672 Hitachi America, Ltd, Hitachi Plaza # 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 Be sure to vist ChipDocs web site for more information.HD6321/HD6821 Control Register A (CRA) 71]* [sl4[3[2]ilo IROA; | IRQA2 | Control CAg | DDRA | Control CAy "Bit o 1 ‘CRAO ‘CAs, interrupt output mask bit | CA1 interrupt output mask bit |] (CAt Peripheral | CRA7 (IRG Ax) is set according | CRA7 (IROA1) is set according Control Lines) | to the interrupt signal CA, but |to the interrupt signal CA, and IRQA is masked and not output | IROA changes ‘ow’ | (in short, ROA = “high’). CRAY ‘CRAT (IROA1) is set when CAr | CRA7 (IRQAt) is set when CAr (CAr active is fallen is risen edge bit) ‘CRA2 Data direction register A Peripheral interface register A (00RA) YORA3_JOA2|CAe interrupt output mask bit_|CAg iterupt output mask bit CA CARE (/RQA2) is set according | CBR6 (IRQAz) is set according (Peripheral | tothe interrupt signal CAp, but | tothe interrupt signal CA2 ‘ Control TROA is masked and not output | And [ROA changes ‘ow’ \ Line) (in short, IROR = high) ‘ CRAG ‘GRAB is set when Cag s fallen | GRA6 is Set when CAz is risen. ] 1 CA (active edge bit) - ‘4 RAS CRAG =0 CRA4=0. it Handshake mode bit Handshake mode bit it The output CAz is ‘low’ when | After reading, CA ‘high’ re pulse is falen on MPU is | when next 'E” pulse is fallen on 1 ‘read the data from Peripheral | MPU is read the data from 1 Interface Register A and CA2 is | interface Register A and, after 1 ‘high’ when CBy is active reading, CA2 is ‘high’ when 1 (edge). next “E’ pulse is fallen, L. CRAS CRA3 is the handshake mode | The content of CRA3 is out to bit. CA2. RAS CARs input mode (CA2 is output mode CAz inpul output seect bit ‘CRAG (\ROAa) | No interupt request from GA | Interrupt request from Cagis ‘oF Chg output (Reset Mode) | oocured ‘ERAT (ROA) | No interrupt request from GAs Interrupt request from Ay is occurred @HITACHI Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) $89-8300 673 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 Control Register B (CRB) 7] 6 [sj4jajs2fiyo ‘ROB; | 1ROB2 | Control C82 [OORB | Control CBr ‘The output CB is ‘low’ when | After reading, CBr is ‘high’ “E’ pulse is fallen on MPU is | when next ‘E” puse is fallen on ‘ead the data from Peripheral | MPU is read the data from Interface Register B and CBp is | Interface Register B and, after Bit 0 i CREO ‘CBs, interrupt output mask bit CBr interrupt output mask bit (CB: Peripheral_| CRB7 (IG 81) is set according | CRB7 (ROB) is set according [Control Lines) | to the interrupt signal CBs, but to the interrupt signal CB, and TROB is masked and not output | [ROB changes ‘iow’. (in short, IROB = high’). _ ‘cre (CRB? (ROB) is set when CA: | CRB7 (IROBT) is Set when Cy (CB; active is fallen is tise. edge bi) . (cRB2 Data direction register B Peripheral interface register 8 (oor) _ (CRBS ‘[CB2| CBz interrupt output mask bit | CBz interrupt output mask bit CBz |_| CBRE (IROBa)is set according | CBRE (IRQBa) is set according (Peripheral | | to the interrupt signal CB, but j to the interrupt signal CB2. And t Control TROB is masked and not output | IROB changes ‘iow’ t Line) (in shor, iROB = ‘high’. 1 crea (CRBG is set when CB2is faien | CRBG is set when CBp is risen T 08. (active 1 edge bit) 7 I RBS CRB =0 CRBs = 0 1 Handshake mode bit Handshake mode bit p--- eee “high when CB is active | reading, CB is ‘high’ when (edge). ext ‘E* pulse is fallen, cree ‘CRBS is the handshake mode | The content of CRBS is out to coed bit, ca ‘CRBS (2 is input mode CB2 is output mode 82 input output select bit | (CRBE (ROB) | No interrupt request rom CB |terupt request rom CBzis | or CBz is output (Reset Mode)_| occured. (CRBT (IRQBS) —_|No interrupt request from CB. )Interupt request rom By is occurred. @HITACHI 674 Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 + (415) 589-8300 wwchipdocs.com Be sure fo visit ChipDocs website for more information.__ HD6321/HD6821 Tobie 3 Conil of Inrupt inputs and CB) T Qt cra crao | imeuptinnst | nerupt Fag PU va (rey) {CRBO} CA, (CB) ‘RAT (CRB) | TROA (ROB) 0 0 + Active. ‘Set "1" on} of CAy | Disabled — TRG remains | ‘eb ans ° 1 1 Active: y Set"t" on ¥ of CA, T ‘Goes “Low” when the inter- | (€8,) | Ripe ag bt CRAT {CRB} xe 1 0 T Active | Ser71 on T of CA, T Disabled — TRO romaine _ | { tees) | gm i i | Ser on ofA, oes "Law whan te te Gy Toot ago GRAD IERBT tone wwe 3 } 3 ‘ 28 anon rt er erage Bat Secale Enno UENO ein oo “abe 4 Cont ofCAy and CB Intro Input = CRAB (CRBS) "0" eras | crae | crag | imguust ont lovee Fag PU tnceruor Enos) | (Gree | (eres | "CA," icerh chao tenes! aaa, oO o 0 | Active Set "1 on 4 of CA Disebled — TRO remains: | ee Pa 7 po ys Theta Sion of GR | Gow "Low" wen tein (Ba) rupt flag bit CRAG (CRB6) | mes 0 1 0 T Active Set “1 on t of CAy Disabied — TAG remains - | i ee |i ° To T Ser" on tof GA | Goes “Low” when te intr | (CB,) rupt flag bit CRAG (CRB) | wupt tag (Wo 4. nnn etn anion hah rH ie ae} 3 Igbo oF mao te Arron Rpt and CBB 2 Siecle he ‘ et at i nd ae we RAS EAST weno Table 5 Control of CBs an Ovtot_— CAB c cnos_| cass | cass Gana Ea a 3 | “Lo on te pontive waraiion oF “Hag whe thenont Moab te fat € poe ater MPO aay win by mst wnation ‘We "0" Oat Regie operation Stine Coy signa (ue Figure 16) 7 3 7 Lom on the poste Vans tion of ont pone ee af he et € peter an MPU Write Sete Reger open Dole whh ozrred ie he i Bart wan vlc (Se Fire 1) i 7 5 ew {Th content of CRBS it outgut on CBr) 1 7 1 “ah (Te conten of CRED is oto on CBs) Hitachi America, Ltd, © Hitachi Pkaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1619 » (416) 589-8300 \worwchipdoes.com @HITACHI Be sure to vist ChipDocs web site for more information. 675\worwchipdoes.com eS eee HD6321/HD6821 Table 6 Convol of CAy 2¢ an Output — CRAG is "1" Cy CRAB craa_| crag Cleared Ser 7 0 0 “Low” on regativ High” when the interrupt Tag BF after an MPU Read "A Data Opera: CRA7 is set by an active transition tion of the CAy signal, (See Figure 16). 1 ° 1 “Low” on negative wansiton of E “High on the negative edge of the after an MPU Read "A" Date oper first"E” pulse which occurs during tion a deselect (See Figure 16) 1 7 0 “Low” (The content of CRAS is output on CAs) 1 1 7 ‘High (The content of CRA is outout on CAs) © PIA OPERATION © Initialization ‘When the extemal reset input RES goes “Low”, all internal registers are cleared to “0”. Periperal date port (PA,~PAT, PB,~PB») is defined to be input and control lines (CAy,CA,, (CB, and CB,) are defined to be the interrupt input lines. PLA is Also initialized by software sequence at follows, Gerth convo ieee I Teed input lown dreaion tania ACC ‘lor tha sontens of AGE fo I ‘ood contra at 10 be writen int ACE I Store the contents of ACC into tha contol rasea T Imouvoutput procetiog (¢ Reed/Write Operation Not Using Control Lines ‘ ‘Stee dete crsetion rine 10 “00" Program the data diection register acces bit of the control register to "0" to allow to access the dada ‘+ The data of the control lin function is set into the accumnu- lator, of which Data Direction Register Access Bit shall be programmed to "1" + Transfer the control data ftom the accumulator into the contro register. CUR CRA «Clear the DDRA access bit ofthe control register to “0” CLR OORA 5 Clear all bits of the dada dtectionrepster I LOA #804 Set DDRA access bit of the control register to "1" to allow Tein te corre STAR , CRA {0.ccess the peripheral interface register. ‘and conte ot oa pipirt i imaracerspmerina me sccumr | LAA pina @HITACHI 676 Hitachi America, Ltd, » Hitachi Plaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 « (415) 589-8300, Be sure to vist ChipDocs web site for more information.——— eee HD6321/HD6821 ‘ CLR CRA Set DDRB access bit ofthe control register to ‘serene cea dnevon wget FF SOAK 98°F) 6 Set all bit ofthe data direction rege to “FF Leite ene corel rope OAR #804 ‘Set DDRB access bit of the control register to “1” to allow to I stan, one }* Ses he peripheral interface register. ‘Store the deta in the accumwiator into ‘ sae toma OATA) «wate daa he pce intercept ] © Rlend/Weiee Operating Using Control Lines Read/wite request from peripherals shall be put into the ‘control lines at an interrupt signal, and then MPU reads or ‘write afer detecting interrupt request. ‘The following came Is that Port A is used and that the riing ‘edge of CA; indicates the request for read from peripherals. CLR OA 6 Set the DRA acces bit to "0", ‘et the dr direction igineeto00" | CLR. DRA s Set all bits of the data direction reglatar to “O”. Lowa #808 + Program the ising edge of CA to be active. ROA ts masked Tenia the control oe TAA cma RSDDRA socess biti wt to 1. LOOP LOAA CRA mE |" SOY + ne ste a pp = oS Seer] OM e+ Le a pl tis ant Se sta at ‘Toread the peripheral data the data i directly transfered to the data buset Do~Dz through PAg~PAy or PBy~PBy and they are not latched in the PLA. If necessary, the data should be held inthe externa latch unt MPU completes reading it ‘When kntializing the control register, interrupt flag bit (CRAT, CRAG, CRB7, CRB6) cannot be written from MPU. If ecesary the interrupt flag must be reset by dummy read of ‘Peripheral Register A and B. write> ‘Witte operation using the interrupt signal is as follow. In ‘case, B port is used and interrupt request is input to CB, ‘And the TRO flag ia st at the rising edge of CB, . @HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 # (415) 589-8300 677 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 cur ‘St te ta dreson reir to“ LOAA sTAa Loan STAA LOOP LOAA. ore ad Ere7-1? Lond tha contents of i ovtout u Taoier mtn sccometator aa ‘Store the cotana ofthe scomutetor Inte the our epater STAB ] Interrupt request flag bits (CRAT, CRAG, CRB7 and CRB6) ssannot be written and they cannot be alto reset by write ‘Operation tothe peripheral interface register. So dummy read of Detipheral interface register is needed to reset the fags. ‘To accept the next interrupt, it ls euentil to reset indirectly the interrupt flag by dummy read of peripheral interface eter. ‘Software poling method mentioned above requires MPU to: continuously monitor the control regster to detect the read/ ‘write request from peripherals. So other programs cannot run at the same time, To avoid this problem, hardware Interrupt may bbe used. The MPU is interrupted by IRQA or PROB when read/write request i occurred from peripherals and then MPU. analyzes cause of the interrupt request during interrupt pro coming. (© Handitaks Mode ‘The functions of CRA and CRB are similar but not identical in the handshake modes. Port A is used for read hand shake ‘operation and Port Bis used for write hand-thake mode Ay and CB, are used for interrupt input requests and CAy ‘and CB, are control outputs (answer) in hand-ahake mode. Fig. 17, Fig. 18 and Fig. 19 show the timing of hand-shake ‘< Reed Hand-shake Mode> ‘CRAS="I", CRAG="0" and CRA3="0" © A peripheral device puts the Sit data on the cme + SetDDRB ass i t0"0" 0 seca bits of DDRB to output“, #408) 6 Progam the sing ge of Bt be ate. TROB ie masked cre |” guiboRB ac beer oe cw}, tee | eh wheter wate gut come om pipes Pine Reset the CRBT ag by the denny read of he erotic rete pint «Store dua ofthe cantor Bt the pepe Interface register @ CRA? flag is set and CA, becomes “High” (CA, auto- mately becomes “High” by te interupt CA’), Tha indleates the pepberl to multan the Curent data and not to trae he next da @ MPU accepts the rad requent by IRQK hadareintrupt ‘or CRA read, Then MPU reads the peripheral register A. © CAj goes “Low” on the following edge of read Enable rl Ths sfrma that the paripharl aot hw nex att Bpom a. the Wea Handak> RBS 1 CRO CRE duty ‘A peripheral device raquets MPU to write o e CB, input. CB; output remains “High” unti) MPU write date co the peripheral interface rept. CRB? fag i set and MPU accepts the write requet. MPU reads the peipheral interface register to reset CRB (Gummy read), @ Then MPU write data to the peripheral interface regite. The data is output to por: B through the output reper © CB, automatically becomes “Low” to tell the peripheral that new data ison port B. © The peripheral read the dats on Port B peripheral data lines and set CBy to “Low” to tel MPU that the data on the Peripheral data lines has been taken and that next data can be weten othe peripheral interface restr. data lines after the control output CAs goes “Low SAS ni, CRAM" 0" md CRAB = "1" ® The peripheral requests MPU to read the data by using CA, CRBS = “1"; CRB4 = “0” and CRB3 = “1 input. ‘This mode i shown in Figure 17, Figure 20 and Figute 21 @HITACHI 678 Hitachi America, Ltd. » Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 \worwchipdoes.com Be sure to vist ChipDocs web site for more information.re HD6321/HD6821 [cans [onas [ona] tm © i i i sjols rol] cas [oman [oD Tae 3 z i vfo}s Figure 17. Timing of Hand shake Mode and Pulse Mode @ HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1619 » (415) 589-8300 679 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 _ on “i on ons “Low” whan dats on ‘ertdon at CA, SA aa Do ron OY URQAT Fig Boe) MPU‘ter fling spe -—_—_ Fence gn wore am oA SU UL abies |Handsnoking with peripheral on “A side Dew —] Co am, A, —. Seve Om whan — oa Khia tena Figure 18 Bits 5, 4, 3 of CRA = 100 (Mand shake Mode) onto epee re soos, SER ty mouse FLOSS Handshaking with peripheral on ’8 side ea Parone aR ma Rogen fo Figure 19 Bits5, 4, 3 of CRB = 100 {Hand shake Mode! @ HITACHI 680 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 wwchipdocs.com Be sure fo visit ChipDocs website for more information.HD6321/HD6821 (CA, Normety Gown "Low tar 8 “Raga aie “ (aa neucton (LOA) we Neti wanton ore) enabie sia Pulte mode Pulte output on A side CT Ty PIA Peripher cA, > cra ° CEEELTEE)) / pete “Rass” by MPU Figure 20 Bits, 4, of CRA ~ 101 (Pulse Mode) ‘Game High onthe rest pont © 2 cs CELTEEEL) Naw ata pred a un eget tee vga for prior Figure 21. Bits, 4,3 of CRB = 101 (Pulse Mode) @HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 681 wwchipdocs.com Be sure fo visit ChipDocs website for more information.\worwchipdoes.com HD6321/HD6821 = SUMMARY OF CONTROL REGISTERS CRA AND CRB Control registers CRA and CRB have total control of CA; Ay, CB,, and CB, lines. The status of eight bits of the control ‘eisters may be read into the MPU. However, the MPU ean only, wate into Bit 0 through Bit $ (6 bits), since Bit 6 and Bit 7 ace set only by CAs, CAs, CB, oF CB, © Addressing PAs Before addressing PIAS, the data direction (DDR) must frst be loaded with the bit pattern that defines how each lin is to function, i¢., a8 an input or an output, A lopie “I” inthe data, iretion register defines the corresponding line as an output While a logic 0” defines the corresponding line as an input. Since the DDR and the peripheral interface resister have the same address, the control register bit 2 determines which register is being addvessed. If Bit 2 in the conttol register isa logic “O", then the DDR is addressed, If Bit 2 in the control register is & logic “I”, the peripheral interface register is addressed. Thet fore, itis essential that the DDR be loaded first before sett Bit 2 of the control register. Given a PIA with an address of 4004, 4005, 4006, and 4007, 4004 is the address of the A side pecipheral interface register. 4005 is the address of the A side control register, 4006 is the address of the B side peripheral interface register, 4007 is the address of the B side control regste.On the A sie, Bits 0, 1,2, and 3 will be defined as inputs, while Bits 4, 5,6, and 7 will be used as outputs, On the B sie, all lines will be used as outputs PIAIAD= 4004 (DRA, PIRA) PIAIAC= 4008. (CRA) PIAIBD = 4006 (DDRB, PIRB) PIAIBC= 4007 (CRB) 1. LDA A #611110000 (4 outputs, 4 inputs) 2 STAA — PIAIAD (Loads A DDR) 3. LDAA SEIT (All outputs) 4. STAA —PIAIBD (Loads B DDR) 5, LDA A #%00000100 (Sets Bit 2) & STA PIAIAC (Bit 2 set in A control register) 7. STAA — PIAIBC (Bit 2 set in B control cegister) Statement 2 addresses the DDR, since the control register (Bit 2) has not been loaded. Statements 6 and 7 load the control registers with Bit 2 set, so addressing PIAIAD or PIAIBD, accesses the peripheral interface riser, ‘9 PIA Programming Vie The Index Register The program shown in the previous section can be accom: plished using the Index Register. 1. LOX #8F004 2 STX PIAIAD —_SFO-PIATAD:SO4PIAIAC 3 LDX #SFFO4 4. STX PIAIBD ——_SFF-+PIA1BD$04PIAIBC Using the index register in this example has saved six bytes of program memory 36 compared to the program shown tn the previous section, © Active Low Outputs When all the outputs of given PLA port are to be active “Low” (True $ 0.4 volts), the following procedure should be used a) Set Bit2in the control register. ) Store all 1s (SEF) in the peripheral interface register. ©) Clear Bit 2 in the control register 4d) Store all 1s (SFF) inthe data direction register 2), Store control word (Bit 2 1) in control register. The B side of PIA is set up to have all active low outputs By and CB; are set up to allow interrupts in the HAND: SHAKE MODE and CB, will respond to positive edges ("Low"to-"High” transitions). Assume reset conditions, Ad- ‘esses are set up and equated to the same labels as previous example 1 LDA ASS 2. STA APIAIBC Set Bit 2 in PIAIBC (control register) 3. LDA BASFF 4 STA BPIAIBD All 1s in peripheral interface cepister 5 CLRPIAIBC Clear Bit? 6 STA BPIAIBD All Isin data direction repster 7. LDA A #827 8. STA APIAIBC 00100111» contiol register ‘The above procedure is required in order to avold outputs going “Low”, to the active “Low” TRUE STATE, when all Is Ae stored to the data direction register as would be the case If the normal configuration procedure were followed, © Interchanging RS) And RS, Some system applications may require movement of 16 bits ‘of data to or from the “outside world” via two PIA ports (A side + B side). When this is the case it is an advantage to interconnect RS, and RSp 28 follows, RS, to Al (Address Line Al) RS; to AO (Address Line AQ) ‘This will place the peripheral interface registers and control registers side by side in the memory ap as follows, Table Example Address PIAIAD ‘$4004 (DDRA,PIRA) PIAIBD 4005 (DDRB, PIRI: PIATAC $4006 (CRA) PrAIBC 4007 (CRB) The index register or stackpointer may be used to move the 6bit data in two Bit bytes with one instruction AS an example: 'LDX PIALAD. PIALAD-+* Xi: PIAIBD ++ 1X} © PIA — After Reset When the RES (Reset Line) has been held “Low” for 2 ‘minimum of one microsecond, all registers in the PIA will be cleared, Because of the reset conditions, the PIA has beer defined as @HITACHI 682 Hitachi America, Ltd, » Hitachi Plaza © 2000 Sierra Point Pray. « Brisbane, CA 94006-1819 « (415) 589-8300, Be sure to vist ChipDocs web site for more information.\worwchipdoes.com follows. 1. All 1/0 lines to the inputs 2. CAs,CAz,CB1, and CB) have been defined as interrupt input lines that are negative edge sensitive re masked, Setting of tside worl * have been defined a5 HD6321/HD6821 = SUMMARY OF CA,-CB, PROGRAMMING Bits 5, 4, and 3 of the control registers are used to program the operation of CA; CB, 3. All the interrupts on the conto line bs bebo intern wil not eause TRA ot TROB to go “Low” verrupt fag bits wit toe cA,—cB, [9] 0) 0 (Maski CA;—CB, Input Mose Tipat ts [0 | Ol-) 1 (Allow) bd = Edge (O= ~,1= 4) iret 19 | nee) 0 (Mak) 03 = Mask (0 Mas, ‘= SUMMARY OF CA,-CB, PROGRAMMING otis) 1 (Allow) 1 =Allow) Bits I and O of the respective control registers ate used to program the interrupt input control lines CA, and CB Ca,-ca, | 1] 0 0— Handshake Mode Cue |1 | 0 1 Pale Mode Mode “| 1] 1 ©} b3 Fotiowing Mode ot 0 tt ’ 0 ° ‘bt = Edge (O= -.1 ~ 0 BO Mabe (0 Niask, 1 = Allow) a) +4 Note thet this isthe sume logic a Bits 4 and 3 for CAs-CB, when CA;-CBy ave programmed a inputs YO Aa Foi ‘entrol Line {ay Poon Ea, Ato intrupt x, “haw ee 18, — Neate Eee, Mak ner | Hawa Shake ose riatee Loa AweBC 10111100 Pg co, STAAMIAIAD 10 10D0RA [> LOA A a8FF watt . * STAAPIAIBO 1/010 DORB : Ua wager onan STAAPIAIAC To "A" Controt : Ua aeant — do100100 . STAAPIAIBC —To"8" Como! : |_*_ sr, Figure 22. PIA Configuration Problem Q@HITACHI Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300 683 Be sure to vist ChipDocs web site for more information.————_—_———— HD6321/HD6821 = NOTE FOR USE ‘There no iferencebxtween CHGS PIA nd NMOS PIA in pin arrangement @HITACHI 684 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 © (415) 589-8300 wwchipdocs.com Be sure fo visit ChipDocs website for more information.