Sensor Fault Detection for Line Regulating
Converters supplying Constant Power Loads in DC
Microgrids
1st Kasper Jessen 2nd Mohsen Soltani
Department of Energy Technology Department of Energy Technology
Aalborg University Aalborg University
Esbjerg, Denmark Esbjerg, Denmark
Kje@et.aau.dk Sms@et.aau.dk
Abstract—The objective of this paper is to increase the reli-
ability of DC-DC converters operation, used in DC Microgrids
(MG). This paper will determine the design requirements for a
Sensor Fault Diagnosis (SFD) strategy for a DC-DC converter
intended for DC MG, in order to allow continuous operation
during erroneous sensor measurements. The SFD scheme is based
on residuals generated by a generalized observer scheme. The
observer gains is based on adaptive high-gain observer theory.
The generated residuals are compared with thresholds, to detect
sensor faults. The SFD scheme for the Line Regulating Converter
(LRC) side is validated through simulations on a prototype DC
MG system where the sensors are subjected to three types of
sensor faults. In this paper, the prototype DC MG system will
consist of a battery which is connected to the DC bus through a
bidirectional buck/boost converter. A buck converter is used as
LRC connected to the DC bus.
I. I NTRODUCTION
The DC Microgrid (MG) has in recent years drawn more
attention in comparison to the AC MG [1]. The voltage and
current sensors are crucial parts of the DC MG as they are both
used as feedback for the control system and in many cases
also for the protection system. Therefore, erroneous sensor
measurements could lead to reduced system performance,
instability, damage of components and incorrect triggering of
the protection system [2]. The fault detection and isolation
for DC MGs is important as the employment of DC MGs
are often over a smaller distributed area. Therefore, the line
impedance is low and the fault current can increase to more
than a hundred times of the nominal current in a couple of
milliseconds [3]. The protection of DC MG is often done by
a protection scheme, which utilizes a sensor for feedback, for
controlling a protective device.
There exist several fault detection methods for DC MGs;
these include over-current, current derivative, directional over-
current, distance, and differential protection. A review and
comparison of these different protection methods can be seen
in [3], [4]. The fault detection methods presented in these
reviews for the DC MGs protection methods many rely on
978-1-7281-6990-3/20/$31.00 ©2020 European Union
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3rd Amin Hajizadeh
Department of Energy Technology
Aalborg University
Esbjerg, Denmark
Aha@et.aau.dk
real-time data from current and/or voltage sensors in the DC
MG. On the subject of Sensor Fault Diagnosis (SFD) for DC
MGs, not much research have been published. In [5], a sliding
mode observer-based fault diagnosis theory is used to diagnose
and mitigate different sensor errors for some of the sensors in
a DC MG. The different sensor errors considered are either
from sensor faults or cyber attacks.
However, no SFD scheme has been developed for a DC
MG where the DC protection system sensors have been taken
into consideration. Therefore, the contribution of this paper
is to develop a SFD scheme which can detect sensor faults
for all the sensors used in DC MGs where the protective
system has also been taken into account. Furthermore, the
design requirement regarding the speed of the SFD scheme
will be analysed, which to the authors knowledge have not
been given in existing literature. The use of the adaptive
high-gain observer theory for residual generation is also an
unexplored subject for the SFD for DC MG. Furthermore,
the case study of the buck Line Regulating Converter (LRC)
supplying a Constant Power Load (CPL) for SFD has not yet
been conducted.
This paper will first present an overview of the test DC
MG system in section II . In section III, the SFD design
requirements for the SFD scheme is presented. In section IV,
the mathematical model of the LRC and the CPL and the
adaptive high-gain observer are presented. In section V, the
SFD scheme is tested through simulations, and the results is
shown. At last in section VI, the conclusion and future work
is outlined.
II. OVERVIEW OF T EST DC-M ICROGRID
An overview of the DC MG layout used for the testing of the
SFD scheme can be seen in fig 1. The test DC MG considered
in this paper, is a part of a larger DC MG which is physically
located at the Renewable Energy Control Laboratory (RECL)
at Aalborg University, campus Esbjerg. It consists of an Energy
Storage System (ESS), which consists of a 6 kWh battery
storage that is connected to the DC bus through the ESS
converter, which is a bidirectional buck-boost converter. The
 DC bus will have a rated voltage of 300 V over the DC
bus capacitor. The LRC converter is a buck converter, which
supplies a CPL at 150 V. The CPL used in this test DC MG is a
programmable linear DC electronic load. For the protection of
the test DC MG a unit protection methodology will be, where
the Circuit Breaker (CB) and current sensor is placed near the
DC bus for each unit and the CB will consist a IGBT. The
ESS converter control system consists of two PI controllers
to control the charging or discharging of the battery as in [6].
The objective of the ESS control system is to keep the DC
bus voltage fixed at 300 V. The LRC control system consists
of a PI controller and an active stabilization feedback. The
objective of the PI controller is to keep the input voltage to
the CPL at its nominal value of 150 V.
The CPL exhibits negative incremental resistance that tends
to destabilize the power system, unless properly damped [7]–
[9]. The active damping method used in this paper, compen-
sates for the negative incremental resistance caused by the
CPL by increasing the effective resistance of the inductor. A
non dissipative way to increase the inductors resistance is to
provide a feedback loop from the inductor current sensor to
the voltage control signal, as this can produce the effect of a
virtual resistor [10]. Therefore, the impact of erroneous sensor
measurement for the LRC control system, is that the CPL can
cause reduced system damping, oscillations in the DC bus
voltage, and even voltage collapse [11].
III. S ENSOR FAULT D IAGNOSIS R EQUIREMENTS
The sensor faults considered in this paper are three common
types, which are: open-circuit fault, gain deviation, and noise
abnormality. The causes of these types of sensor faults can be
either the electrical system interpreting the data or failure of
the sensing mechanism. When designing the SFD scheme for
a DC MG, it is important to ensure that it is robust, reliable,
and fast. The sensor fault detection time of the SFD scheme
for the sensors used in the protection system needs to be faster
than the fault detection time of the protection system such that
sensor faults do not interfere with the protection system.
The speed requirement of the protection system often de-
pends on the DC MG layout, the grounding configuration,
the fault withstanding capability of the unit the protection
system is protecting, and the possible fault types the unit can
exposed to. In [12], a comparison of the different protection
schemes for low voltage DC applications can be seen, where
the claimed fault detection time is 0.1 ms - 0.2 ms for the
fastest method in [13]. Whereas, most of the other methods
ESS
Converter ESS CB LRC CB LRC
Battery
presented in [12] claims to be able to detect the fault within
2 ms. Therefore, the maximum sensor fault detection time for
the current sensor used for the protection system is set to 0.05
ms, in order to detect the sensor fault in an appropriate time
compared to the fastest fault detection methods whereas the
maximum sensor fault detection time for the other sensors that
are not used in the protection scheme are set to 0.5 ms.
IV. M ATHEMATICAL M ODEL OF THE L INE R EGULATING
C ONVERTER
The LRC circuit considered in this paper is shown in
Fig. 2. The governing nonlinear differential equations for the
dynamics of the LRC are
VL 1
I˙L = = σ(t)VDC − Rc IESS − RL IL − VCP L
L L

− (1 − σ(t))VD
 
Io 1 PCP L
V̇CP L = = IL − (1)
Co Co VCP L
IDC 1
V̇DC = = (IESS − ILRC )
CDC CDC
where L and RL are the inductance and resistance of the
inductor, Rc is the resistance of the conductor connecting
the LRC to the DC bus, Co is the capacitance of the output
capacitor of the buck converter , CDC is the capacitance of
the DC bus capacitor. Furthermore, IL is the inductor current,
VL is the voltage across the inductor, VD is the voltage drop
across the diode, IESS is the current from the ESS, VCP L is
the voltage at the input to the CPL, Io is the current flowing
into the output capacitor of the buck converter, ILRC is the
current drawn by the LRC, σ(t) is the switching variable, and
VDC and IDC are the voltage across and current flowing to
the bus capacitor, respectively. The switching variable can take
two binary values, when the switching variable σ(t) = 0 the
IGBT is OFF, and when σ(t) = 1 the IGBT is ON.
The current drawn by the LRC, ILRC is calculated by
ILRC = σ(t)IL (2)
The CPL is in this paper considered as a nonlinear current
sink whose power is constant. A increase in the CPL voltage
results in a decrease in the current drawn, and thereby the
power is kept constant. Before the differential equations for
the dynamics of the LRC in (1) can be converted to a state
space description, the current drawn by the CPL, ICP L , needs
to be linearised. The linearisation is conducted by a first order
Taylor series expansion around the equilibrium point V̄CP L ,
which in this case is nominal operating voltage of the CPL.
PCP L PCP L 1
ICP L = ≈2 + VCP L (3)
VCP L V̄CP L R̄CP L
where ICP L is the current drawn by the CPL. The linearised

+ CPL
V current drawn by the CPL can thereby at a given operating
- DC point be approximated by a constant current source in parallel
with a negative resistance R̄CP L = −P 2
CP L
V̄CP
.
L
The dynamics of the LRC converter considered in this paper,
Fig. 1. Overview of the test DC MG is a time-varying system as it contains a switch. The switching

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 ESS σ(t)
IESS ILRC + VL - IL ICP L
Rc RL
IDC + Io +
-
VDC PCP L
Vd VCP L
VCP L
- + -

Fig. 2. Overview of the DC bus and LRC circuit. The variables written in red, are the variables which are measured by a sensor

changes the systems topology, though at each of the switching The adaptive observer gain K(t) is given in (7) according to
configurations, the converter subsystem is linear. the adaptation law defined by E. Bullinger [15]
This type of system is generally known as a switched linear 2
K̇(t) = γ dλ (e(t)) , K(0) = K0 (7)
system, which is a collection of linear subsystems that have
a switching rule that determines the switching between the where
linear subsystems [14]. 

λ̂ − λ, for |e(t)| ≥ λ̂.
Therefore, the LRC dynamics is in this paper described by
continuous switched linear state space model given in (4) dλ (e(t)) = |e(t)| − λ, for λ ≥ |e(t)| ≥ λ̂. (8)


0, for |e(t)| ≤ λ̂.
ẋ(t) = Aσ(t) x(t) + Bσ(t) u(t)
(4) where γ is the constant gain vector, dλ is the adaptive gain
y(t) = Cσ(t) x(t)
vector, K0 the initial gain vector and λ and λ̂ are the inner
where x(t) is the state vector, ẋ(t) is the time derivative of and outer thresholds for the estimation error. By using the
the state vector, y(t) is the ouput vector and u(t) is the input adaptation law for the observer gain in (7) there is no difficulty
vector. The matrices A, B and C are the state, input and in choosing the constant high-gain K for the observer, as in
output matrices, respectively. other observers such as high-gain or Luenberger observers. It
The state space vectors and matrices for the LRC model are is only the thresholds λ and λ̂ for which the estimation is to
be kept within, which are needed to be set. The adaptation law
  will then increase the observer gain K(t) monotonically with
−RL −Rc σ(t) −1 σ(t)  
 L L L
 IL (t) a bounded derivative until the estimation error is within the
 1 1
0    inner threshold λ. The proof of convergence of the adaptation
Aσ(t) = Co R̄CP L Co , x(t) =VCP L (t)
  law and boundedness of the observer error for the adaptive
−σ(t)
0 0 VDC (t)
CDC observer can be found in [15].
 −1+σ(t)
 To estimate all the sensor values accurately from the bank of
0 " #
L
  IESS (t) observers, the observability of the observer banks have been
Bσ(t) = 0 0 , u(t) = (5)
VD analysed. Also, due to the switched nature of the system, the
1
0 state and output matrices changes according to the value of
 CDC   
1 0 0 IL (t) the switching signal. The observability analysis condition was
    satisfied for all observer banks pairs (Cr,i , Aσ(t) ), except at
 0 1 0 VCP L (t)
Cσ(t) = , 
y(t) =  for the observer bank monitoring the DC bus voltage at the
 0 0 1 
   VDC (t)  switching instant σ(t) = 0. Where Cr,i is the residual output
σ(t) 0 0 ILRC (t) matrix for the i’th observer bank.
The unobservable state at the switching instant σ(t) = 0 for
the DC bus voltage is caused by analysing the LRC side of the
A. Adaptive high-gain state observer design DC MG, as this causes the ESS current to be an input to the
The full state adaptive high-gain observer is developed as observer. Though, the observer bank for the residual generation
in (6) of the DC bus voltage is still controlled observable, as there
exists a frequent switching of σ(t) for which the system is
ˆ = Aσ(t) x̂(t) + Bσ(t) u(t) + K(t) (e(t))
ẋ(t) observable in one of the states [16].
(6)
ŷ(t) = Cσ(t) x̂(t) B. Sensor Fault Detection
where x̂ and ŷ is the estimated observer state vector and output For the evaluation of sensor faults on the i’th sensor, the
vector, respectively. The observer output error is defined as peak value measure is calculated from the scalar residual
e(t) = y(t) − ŷ(t). signal from the estimated state from the adaptive high-gain

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observer for the i’th sensor and the measured sensor value of A

I L Residual [A]
4
the i’th sensor as in (9) Residual
Threshold
2
Detection Time
rpeak,i (t) = ||Cr,i x(t) − Cr,i x̂(t)|| (9)
0
where rpeak,i is the absolute value of the sensor residual from 0.047 0.048 0.049 0.05 0.051
Time [s]
0.052 0.053 0.054 0.055

the i’th observer bank. B

I L Residual [A]
The peak value measure of the residual signal is compared 4

to a constant threshold setting as in (10) for detection of the 2

sensor fault
0
rpeak,i (t) > rth,i → Fault 0.047 0.048 0.049 0.05 0.051 0.052 0.053 0.054 0.055
(10) Time [s]
rpeak,i (t) ≤ rth,i → No Fault C

I L Residual [A]
where rth,i is the constant threshold for the residual from the 30

i’th observer bank, which is set at 3 % of the nominal value 20

10
of the i’th sensors measurement, which can be seen in table 0
I. 0.047 0.048 0.049 0.05 0.051 0.052 0.053 0.054 0.055
Time [s]
V. R ESULTS
Fig. 3. Absolute residual of the inductor current during three separate sensor
In this section the SFD scheme is validated through simu- fault scenarios, the sensor fault is introduced at 0.05 s. Sensor affected by: A)
lation. The SFD scheme is tested by applying three different An additive gain deviation fault of 10%. B) Additive white Gaussian noise
with a variance of 4. C) An open circuit fault
types of sensor faults individually, to each of the four sensors. A
V CPL Residual [V]

The simulation model of the experimental system has been 20

Residual
developed in MATLAB Simulink by using the Simscape Threshold
10
Power Systems Toolbox. The residual signal from the observer Detection Time

bank are sampled at 50 kHz. The parameters used in the 0

0.047 0.048 0.049 0.05 0.051 0.052 0.053 0.054 0.055
simulation is listed in table I. Time [s]
The inner and outer estimation thresholds for the inductor B
V CPL Residual [V]

10
current λIL and λ̂IL are set to 0.2 A and 1 A and the gain
γIL at 9 × 106 . The inner thresholds for the input voltage to 5

the CPL and the DC bus voltage λVCP L and λVBU S are set to
0
1 V. The outer estimation thresholds for input voltage to the 0.047 0.048 0.049 0.05 0.051 0.052 0.053 0.054 0.055
CPL and the DC bus voltage λ̂VCP L and λ̂VBU S are set to 5 Time [s]
C
V CPL Residual [V]

V and the gains γVCP L and γVBU S are set to 5 × 104 . 300

The SFD scheme is first tested on the current sensor measuring 200
the inductor current. The results can be seen in Fig. 3, it can 100
be seen that the SFD scheme is able to detect all the sensor 0
faults for the inductor current sensor, as the absolute residual 0.047 0.048 0.049 0.05 0.051
Time [s]
0.052 0.053 0.054 0.055

from the adaptive high-gain observer is for all three sensor

fault scenarios above the constant detection threshold within Fig. 4. Absolute residual of the CPL input voltage during three separate
the detection time for the SFD scheme. sensor fault scenarios, the sensor fault is introduced at 0.05 s. Sensor affected
by: A) An additive gain deviation fault of 10%. B) Additive white Gaussian
Next, the SFD scheme is tested on the voltage sensor measur- noise with a variance of 15. C) An open circuit fault
ing the input voltage to the CPL. The results can be seen in
Fig. 4, where it can be seen that the SFD scheme is able to detect all the sensor faults for the CPL input voltage sensor, as
the absolute residual from the adaptive high-gain observer is
for all three sensor fault scenarios, above the constant detection
TABLE I threshold within the detection time for the SFD scheme.
N OMINAL PARAMETERS FOR THE SIMULATION
Next, the SFD scheme is tested on the current sensor which is
Parameter Symbol Value measuring the current flowing into the LRC converter for the
DC bus voltage VBU S 300 V
Input voltage to CPL VCP L 150 V
protection system. The results can be seen in Fig. 5. where the
Nominel power of CPL PCP L 3 kW absolute residual of the the input current for the LRC is above
Inductance of LRC inductor L 2.43 mH the constant detection threshold within the short detection time
Resistivity of LRC inductor RL 0.4 Ω for the SFD scheme for the additive gain deviation fault ad
Resistivity of conductor Rc 0.1 Ω
Capacitance of DC bus capacitor CDC 2 mF the open circuit fault. But, for the additive white Gaussian
Capacitance of LRC output capacitor Co 0.44 mF noise sensor fault, the stochastic nature of the noise makes
Forward voltage drop of diode VD 0.82 V the actual detection time longer than the required detection
Nominal RMS current through inductor IL,rms 20.3 A time. Though, the additive white Gaussian noise sensor faults
Switching frequency FSW 10 kHz

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 A
VI. C ONCLUSION
I LRC Residual [A]

4
Residual
Threshold
The aim of this paper was to design an adaptive high-gain
2
Detection Time observer, based on a switched state-space model to detect
0 sensor faults for all the sensors used for a LRC connected
0.048 0.0485 0.049 0.0495 0.05 0.0505
Time [s]
0.051 0.0515 0.052 0.0525 0.053
to a CPL in a DC MG setup. The developed SFD scheme
B was tested in simulation for three types of sensor faults for
I LRC Residual [A]

1 all the sensors considered in the case study in this paper. The
0.5 SFD scheme was able to detect all the sensor faults within the
0 maximum sensor fault detection time, except for the additive
0.048 0.0485 0.049 0.0495 0.05 0.0505 0.051 0.0515 0.052 0.0525 0.053 noise fault on the sensor measuring the LRC input current.
Time [s] This was though to be expected due to the stochastic nature
C
of the added noise, and with low severity for the protection
I LRC Residual [A]

30 system as the fault signal was at a low level until detection and
20
10
therefore not large enough to trigger the protection system.
0 In the future work, more elements of the DC MG are to be
0.048 0.0485 0.049 0.0495 0.05 0.0505 0.051 0.0515 0.052 0.0525 0.053 considered for the SFD scheme. The SFD scheme should be
Time [s]
implemented in a fault-tolerant control strategy, such that the
Fig. 5. Absolute residual of the input current to the LRC during three separate fault-tolerant control strategy can be tested experimentally.
sensor fault scenarios, the sensor fault is introduced at 0.05 s. Sensor affected
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