ABSTRACT

Data security of present day plays a critical role in human digital life. Data is a
valuable asset to every company and so it is very important to ensure its protection from
external attack. Security of information is not only an important aspect but essential to secure
data from unauthorized access. Key factors in data protection include data encryption,
decryption and key management. The confidentiality of any communication system is
strengthening with the help of random number generators along with some analog circuitry.
This type of analog models demands more power and area. So analog circuit-based hardware
RNGs are least preferred over digital RNGs.

Getting the correct data protection to meet the challenging threats emerging from
unauthorized access is very critical. Implementation of cryptosystems and Random Number
Generators are critical for Cryptosystem applications including security applications, space
applications, military applications and smart cards etc. There has been growing interest to
design a system which is highly confidential, unpredictable, non-deterministic and truly
random. PRNGs are deterministic, can be predicted, not truly random in nature. On the other
hand, TRNGs are truly random, non-deterministic, and unpredictable though key is known.
This work focuses on the implementation of Truly Random Number Generator in digital
signature generation based on Application Specific Integrated Circuit (ASIC).

The n-bit of signature can be generated and verified with the help of proposed. Here
work with the 10bit of signature generated as well as verified. The work has been developed
in Xilinx ISE simulator.
 CHAPTER 1
INTRODUCTION
1.1 Overview

Security is the more important in digital life. Data transfer through electronic gadgets
is faster compared to conventional data transfer methods. In present days data security is
concerned along with data transfer rate.
Key generation is the crucial factor in data security. In earlier days key is transmitted
along with data over a transmission medium which is more vulnerable to data hackers. So key
generation is a primary concern in secure data transfer. We have many methods for
generation of key, like source obfuscation, binary delivery method and crypto system.
Source obfuscation is the oldest of data security method, in which a meaningful data, in IP
source or replaced with something that is harder to understand intentionally confusing. So it
is not really secure method.
Binary delivery is another method of data security, in which the system is technology
dependent. Its operation is different from user to user, system to system and technology to
technology. Cryptosystem is a new method of data transmission, which is also referred as a
hybrid cypher (combination symmetric and Asymmetric). Which generates a key with longer
sequences.

1.2 Problem Statement

Data is a valuable asset to any organization and hence its security from external
attacks is very important. Information security is not only an important aspect but essential, to
secure data from unapproved access. Data encryption, decryption and key management are
the key factors in data protection.
Random sequence generation is one such option of securing the data. By using the
pseudorandom property of LFSR, we can generate random numbers that have various
cryptographic applications.
Random numbers are obtained using random number Generators (RNGs), Pseudo
Random Number Generators (PRNGs). Although random numbers are required in most of
the applications, their generation is often overlooked. Key generation is very crucial in
Cryptosystem. Various key generation methods are deployed based on the application. Most
of the digital systems use PRNGs, because of their deterministic nature. All the input device
combinations are stored into a pool of numbers, from which the seed is picked. This seed is
used to generate the keys in the PRNG scheme. Though key is generated, because of the
deterministic nature of the PRNGs, there are chances for attackers to predict the data.

In order to assure absolutely random numbers, RNGs must not be endangered to

prediction, one such method is generation of key by True random number generator (TRNG)
which is non-deterministic and truly random in nature. In this work we implemented TRNG
for the key generation which produce non deterministic key with longer data length.

1.3 Objective

Data security is an incredibly complicated and vast topic of interest. The major
management issues and information security issues are faced by IT professionals every day.
Organizations may have privileged data such as credit card numbers, online banking
credentials, stock holder data and addresses, customer lists, aadhar information, e-banking
credentials and other intellectual property. Securities fraud or commonly called stock fraud
involves corporate fraud, Dummy Corporation, internet fraud, insider trading, microchip
fraud, accountant fraud, boiler rooms or brokerage houses et.al. There are various reasons for
cyber frauds, such as:
To gain unauthorized access to private information
To get financial details of a business
To get customers sensitive information
To get clients lists
To use/extend others license illegally
To steal intellectual property (trade information)
To modify/remove secret information in network
To access the communication between two nodes
To insert incorrect/inappropriate information into a network
To create apparent failure in the system/network.
 Fig.1.1 Topology of a simple network

Yesterday’s goal of blocking access to these information resources is no longer

valid in the new digital economy and the rush to open up their network as sown in Fig.1.1, is
causing business to reevaluate their security needs. The attacks on the network or security
system are best categorized into
Interruption: The destruction or make unavailable or unusable of an asset of the organization,
referred to as attack on availability.
Interception: Gaining unauthorized access to an asset of the organization, referred to as
attack on confidentiality.
Modification: Tampering the data or modify an asset of the organization, referred to as attack
on integrity.
Fabrication: An unauthorized party inserts spurious messages into the network or security
system referred to as attack on authenticity.
Where interception is considered as passive threat to the system, while interruption,
modification and fabrication are comes under active threats.
The discipline of security is anxious with protecting intellectual assets. Network
security is a division of information security, which is a subdivision of security. These
definitions are important because they demonstrate the hierarchical relationship of network
security in relation to the other branches of security.

Fig.1.2 hierarchy of level of security.

The practice of data security has changed dramatically over the decade. In the
field of computer security, academic and government institutes established practices that are
still around today.

The hierarchy of level of security is given in Fig.1.2, where security is the primary
goal of any system. As moving from bottom to top, we have four layers of security levels.
Where database security, data security, device security, computer security and application
security covers the base level of security system. In second level of security, network security
plays a dominant role. And the information security is the branch of security.

Obfuscation, which in the context of network security is defined as the process of

hiding secret messages by breaking them up or burning them in an unexpected place can be
effective if nobody knows where to look. This obfuscation method is one of the earliest
methods of protecting confidentiality of the data on networks, computer systems and data
buses, and continues to be one of the most common practices for protecting data today.
Techniques for searching finger prints and identifying secrets have advanced to the point
where contemporary forms of obfuscation provide only an insignificant challenge if it is
known that a secret exists. Obfuscation is commonly seen in encryption techniques, used to
store secret keys. These techniques have certain strengths against casual offenders, but they
can be ineffective against determined attackers. Considering these techniques by analogy can
provide insight into their short comings.

Chapter 1 Deals with the Introduction to security and randomness.

Chapter 2 Gives details about the literature survey.
Chapter 3 discussed the principles of Random Number Generation.
Chapter 4 Explains about the Design and implementation of Random Number Generation.
Chapter 5 shows the respective results and analysis of both the existing and proposed
methods.
Chapter 6 Briefly described the overall summery of this report and the scope of it in future.
 CHAPTER 2
LITERATURE SURVEY

Daniel Morrison, Et.al, (2019), were proposed linear feedback shift register is used
to generate pseudo sequence. It is very fast and easy to implement in hardware and low
power. LFSR Counters are replaced by binary counter for their performance enhancement
LFSR counters are mainly used in single photon detection where speed place a vital role.
LFSR generated pseudo random sequence is converted into binary sequence by decoding
logic scaled logarithmically with stages than exponentially which no of bits depends. Because
of decoding logic the design requires extra circuitry which consumes more power compared
to its conventional one and occupies larger area on chip.
Aysha S. Shanta, Et.al, (2019), the light weight reconfigurable PRNG using 3T
chaotic map in the existing work. Discreet time chaotic signals can be generated by using of
chaotic map. To generation of this signals requires the chaotic oscillator. This design is
reconfigurable because, it has two branch parameters which is used to generate multiple
random sequence. The two chaotic oscillators, analog mux, 10 bit ADC, 2 bit shift register,
and XOR gates can be used in the proposed work. This work can be implemented by using
65nm CMOS technology with the 1.2V power supply. It was applied in IOT device which
requires low area and high performance.
Adriaan Peetermans, Et.al, (2019), exploits the significant of TRNGs in modern
cryptosystem applications. TRNGs have a very complex process of implementation which
often involves manual placement and routing. To ensure the produced numbers are highly
entropic. In this work, designer implemented a dynamic TRNG (COSO-TRNG) based
Coherent Sampling Ring Oscillator which facilitates the simple integration of the entropy
source into complex frameworks. The TRNG arrangement methodology consequently
chooses a setup that ensures the security prerequisites.
Bikram Paul, Et.al, (2019), discussed the importance of PRNGs as essential part of
the cryptographic systems such as key generators, digital signatures, and IoT securities. In
this work, the authors proposed two PRNG methods based on Blum-Blum-Shub (BBS), XOR
shift and Permuted Congenital PRNGs. The first one is chosen for general purpose
applications after that the later one is chosen for low-power IoT applications. The total
dynamic powers at different frequencies are calculated for the both the PRNG methods and
system throughput is observed.
 Bohan Lin, Et.al, (2019), new for the True Random Number Generator (TRNG)
generation based on analog RRAM. A high-speed and high-reliability TRNG based on analog
RRAM can be built for the IoT protection application. This high-speed and high-reliability
TRNG design is great for the current memory square and helpful for circuit use, making it
appropriate for potential IoT applications.
M. Garcia-Bosque, Et.al, in this paper a CSPRNG dependent on a STM and a LFSR
has been proposed and actualized in a TSMC 0.18 μm CMOS innovation. The proposed
framework has accomplished a 1Gbps throughput utilizing a low territory and low force
utilization. The security of the proposed calculation has been examined concentrating on
various angles, for example, the randomness of the produced groupings, the key size, the
affectability on the key and the forward/in reverse mystery. With this investigation, the
author have presumed that the proposed CSPRNG is secure. Accordingly, the proposed
CSPRNG is appropriate for being utilized in applications with counting cryptography-
related ones that need to create pseudo-irregular numbers at a rapid up to 1 Gbps.
Ghazi Muhammad Abdullah, Et.al, The verification proposes, the selection of
Lamport Signature plan to be actualized in the IoT system and gadgets so as to include an
additional layer of quantum verification security as far as validation of updates. Use of
Lamport sign will empower a quantum safe plan to be executed on the low-end gadgets
which will make sure about gadgets from being abused by the assailants. With the
accessibility of all the more hashing capacities that require less space and are more quicker,
this plan will pick up fascination by an ever increasing number of designers and producers to
receive its usage in IoT.
Radu Hobincu, Et.al, (2018), throughout this work, the designer clarified how
chaos-based PRNGs can be implemented throughout FPGA to facilitate secret
communication, and also addressed the digital implementation of a chaos-based
cryptographic pseudo-random number generator (CPRNG) using a Zynq SoC, which offloads
the computation to the FPGAThe proposal is based on the extensive Henon map, which is
performed using the arithmetic of fixed point 3.61. The designer showed that the ARM
Cortex A9 processor has a performance improvement compared to the execution, and that the
irregular bytes produced are steady with the use of the device.
Faqiang Mei, Et.al, (2018), Proposed True Random Number Generator Highly
Flexible Lightweight and High Speed on FPGA. Real Random Number Generator (TRNG),
which plays a critical role in IS. Random number generators using traditional TRNGs use
standard stochastic physical processes like thermal noise, circuit dependent on chaos, etc.
Such basic frameworks of TRNG often require a lot of hardware resources and are not easy to
incorporate into digital systems. In this study, using mixed oscillation produced from XOR
gates nested multiple ring oscillators (ROs) was proposed a low-cost and high-speed TRNG.
To get high-speed output, multi-group mixed oscillation XOR operation is used..
Yifan Zhang, Et.al, (2018), Proposed True Rand Number Generator, Self-Timed Ring
Based and implemented on FPGA. The designer introduced the importance of TRNGs, and
data protection components as appropriate. This work introduces a mixture of self-timed ring
(STR) and ultra-fast carry-logic primitives developing a new TRNG on FPGA. Usage of this
framework will increase the TRNG 's entropy extraction efficiency.
Chitstoper fritz, Et.al, (2017), were utilised in this work A new binary counter based
on a novel symmetric bit stacking approach, it was increases the speed of operation. The 6:3
counter and 7:3 counter can be used for counting method, which can be used in binary
multiplier circuit to add the partial products. In this work defined, it has less no of XOR gates
and more number of critical paths are used in implementation of 6:3 counter, because of the
proposed work designer achieves rapid speed than other higher order counters , as well as it
reduces the power consumption.
Alan J. Michaels, Et.al, (2017), explores the generation of Pseudo random numbers
sequence combination techniques via Galois extension fields. There are variety of ways in
generating pseudo random number generators, with the most secure techniques for generous
handling to produce. This paper sorted out a blending strategy Any number of PRNG streams
using Galois Extension Field strategies that achieve maximum entropy when formed on any
individual data, making it extremely difficult to reverse engineer the joined outcome. In
addition to this simple mixing process, upgraded adjustments are implemented which further
improve the yield while using basic statistical operators at the bit level.
Lihua Dong, Et.al, (2017), True Random Number Generator Analysis and
Improvement, Based on Autonomous Boolean Network. This work presents a chaotic
oscillator in a true random number generator based on boolean network for typical analysis of
the required condition of oscillation A true random number generator (TRNG) based on an
autonomous Boolean network with a small number of nodes is implemented By adding a time
delay self-feedback circuit to increase circuit delay, the autonomous Boolean network with a
small number of nodes will serve as a chaotic TRNG oscillator. Few elements of logic are
needed in this circuit.
Oleg Garasym, Et.al, (2016), exploits the requirement of keys for the designing of
robust chaotic PRNGs. In this work, the authors stated that as the e-transactions numbers
increases rapidly, its security is a challenging task. For every transaction produces a unique in
the encryption process, there is a demand for generation of huge random numbers following
different random generation techniques. In this work a new robust, aperiodic and simple in
implementation chaotic generator is proposed. The ring-coupling is used in the construction
of randomness generator. The author assured the design of robust implementation to
cryptosystems.
Dongsheng Liu, Et.al, (2016), the designer explains about the design of A Low-Cost
Low-Power Ring Oscillator-Based TRNG for Encryption, which is used in preparation of
smart cards. The ring oscillator based TRNG can improves generated bit sequence, which is
have been obtainable and verified by simulation. A post digital processor is added to further
enhance the randomness of the output bits. The proposed TRNG has been made into an IP
and successfully applied in an SD card for encryption application.
Xiufeng Xu, Et.al, (2016), implemented a High Speed True Random Number
Generator Based on FPGA. TRNGs plays a vital role in communication security systems.
The combination of TRNGS with FPGAs usually has high speed and quality. In this work
designer explains the several methods to generate the true random numbers in the FPGA with
the help of ring oscillators. The proposed TRNG can be designed with the help of 16 ring
oscillators, which is used consist of odd no of not gates. In the proposed TRNG gives the
high quality and performance with analyzes the sampling frequency with fewer resources
compared with the several methods mentioned in the references. This work was implemented
in Altera-II FPGA.
Avinash Ajane, Et.al, (2011), in this work the designer can used decoder. Which is
used for transfer the data from one format to another format. Decoder is capable on behalf of
2n bits of coded information. In the prosed work decoder used for set of input elements
transforms into a respective binary elements of output data. Here compared the area, power
and performance of the prosed with the help of the binary decoder. A binary decoder used to
transform a coded input into a coded output, where the input and output codes are different,
and decoders are available to decode a binary or BCD input pattern to a normally decimal
output. The designer compared to a known binary count against an effective algorithm for
decoding LFSR count. In this work delay is greater and it consumes more power and requires
additional circuit.
Nilanjan Mukarjee, Et.al, (2009), Explained about a discrete ring generator dependent
event counter. With the aid of the ring generator this paper explored very fast synchronous
event counter. A single stage of XOR logic, reduced internal fan-out, simpler circuit layout
and routing are the benefits of the proposed methodology. Minimum Length of Series.
Kin-Joe sham, Et.al, (2008), were worked the generation of Pseudorandom bit
sequence at 12 GB/s with modified active inductor load for better high speed large signal
behaviour. The main characteristics of PRNGs are Efficient, Deterministic and periodic.
Drawback of this work is limited test setup and consumes larger area because of the
introduction of inductive load.
Marina A. Kiryakina, Et.al, (2020), the authors considered logical encryption as one
of the most important hardware protection scheme, and gives an additional key to secure the
functionality from the external unauthorized access. The authors proposed a new method of
cryptography with the introduction of PRNG logical encryption, which is useful in
controlling integrated circuit production, Trojans prevention and many more in the field of
hardware security. The additional key inputs not only secure the hardware but it is important
in improving the speed of circuit under test.
 CHAPTER 3
RANDOM NUMBER GENERATION PRINCIPLES

3.1 Introduction of Random Number Generators

True random sequence generation is hard to generate and its sources have limited
utility in more applications. On the other hand, the generation of the sequence that exhibits
statistical randomness is of paramount importance. Furthermore, cryptographic applications
make use of algorithms to generate random numbers and these algorithms are deterministic in
nature. However, by make use of good algorithm, the sequence that is generated would be
pass many tests of randomness. The numbers in such sequences are referred as pseudorandom
numbers. The key blocks of any cryptosystem are the words encryption and decryption. The
block diagram for the widespread system of cryptography. Cryptography is the data
encryption or decryption method to protect the sensitive information, also known as
cryptanalysis or cryptosystem. The cryptosystem process works when key and plain text are
combined. Here the key is either phrase, number or mix of both. This key is used to encrypt
the plain text or bits of messages based on system strength and key isolation.

Random numbers plays a crucial role in the applications of cryptosystems. One such
major requirement is in network security applications. With the abundant availability of the
data and exponential increment in the data speed over the years, the data transfer rate is
increasing rapidly. In such data transfer techniques with high data rate, the data security over
the network becomes an issue. Hence, randomness gives relief from such scenarios. This
chapter discussed about some approaches to randomness generation and sources of random
number generation.
Random Number Generators can be designed by using counters and shift registers. Counters
have more unused states compared to shift registers. If there are more unused states,
obviously area can be increased at the same time number of states is proportional to the
security of the system. If the number of states are less randomness is less, proposnately
security also less. To reduce the number of unused states in counters need to use the decoding
logic, when there is an unused of decoding logic cost is more at the same time area also
increases, leads to less security. So in this work shift registers are preferred to generate the
RNGs. The RNGs can be generates the random numbers without unused states. In this work
several types of RNGs are discussed and compared to each other to find which is more
suitable to generate the most secured key for data transferring with key based.

Randomness:

Traditionally the sequence that is generated by any digital machine shall be some
well-defined in statistical sense. To validate this statement, it has uniform distribution and
independent distribution concepts. Firstly in the uniform distribution, the sequence of
numbers that are generated are uniform and well defined that is the frequency of the
occurrence is almost same. While in the independent distribution no one number in the
sequence can be interpret from the others. Several algorithms are defined to test the
distribution of the sequence that is generated. A number of such tests are performed on the
sequence to prove there is no sequence exhibits independent distribution. However, the
strategy behind this is to apply such tests until the independent sequence generation is
sufficiently strong.

Unpredictability:

In a random sequence generation, if the successive numbers of the sequence are

independent of each other or there is no fixed arrangement between the numbers of the
sequence is called unpredictability. In such sequence, each number generated is statistically
independent on previously generated number, hence unpredictable. This property is very
useful in designing a cryptosystem or for network security applications. Unfortunately, very
few algorithms understand this truly randomness. In fact the unpredictable sequence
generation is very rare and have limited utility in cryptosystem applications. There are many
algorithms proposed to generate the sequence that appear to be random.

3.2 Types of Random Number Generator

A random number generator is a device that generates random number sequences.

RNG produces no specific pattern though it generates a sequence of random numbers. It has
many applications like security, lottery, gamming and sampling etc. For different
applications, have several methods to generate a random data. The RNGs which are
implemented in software for enhancement of the security of the hardware and fastness. LFSR
has been introduced based on its specific property of randomness as well the property of
LFSR is randomness. Randomness generation is based upon initial value. That initial value is
called seed. The generator of random numbers shown in Fig.3.1 is a simple block which
yields a bunch of numbers. The stream of bits can be deterministic or totally unpredictable
depending on the circuit of random number generators used.

Fig. 3.1 Random Number Generation.

Seed Generation

Initial seed is a number, which is used to initiate random number generation. Seed can
be generated based on probability distribution algorithm. Always seed is the starting value of
the sequence, if seed is present in every process of generating the Random number it will
generate same sequence. So sequence of RNG is depends on the initial seed.
Fallowing sample formula can be treated as RNG initial seed
Xn+1 = (aXn+C) mod m [1]
In this case X0, X1, ………….and Xn are the sequence of RNG. Here X 0 is the initial
seed, this process is also called as Kick off process of RNG. The fig. 3.2 represents the seed
generation of the sequence. Here Q0 – Q3 is the initial seed, S0 – S9 is the test pattern.

Fig. 3.2 Kick off process of RNG.

 Fig.3.3 Data Generation from the seed.

The generated seed is given to the appropriate random number generator circuit to
generate a bunch of keys that are utilized in the cryptographic applications. The seed is trying
to initiate the operation of random number generator and it generate bit stream, which is
given to the finite state machine where the state of the bit stream is decided. When the
generation of correct sequence of stream, it will be reflected as output else the state is
updated and fed back to the generator. The entire process of bit stream generation is shown in
Fig.3.3.

3.3 Pseudo Random Number Generator

Lehmer proposes the first algorithm for the generation of pseudo random numbers,
and it is the technique most commonly used. The algorithm is called the Linear Form of
Congruence. The algorithm uses the following four parameters.
m the modulus generally m>0;
 a the multiplier 0 ≤ a < m;
C the increment 0 ≤ C < m;
X0 the seed or starting value 0 ≤ X0 < m;
Based on the following iterative equation, the sequence {Xn} will be generated.
Xn+1 = (aXn + C) mod m; [2]
From the equation, one can conclude that it gives a well-defined random sequence in which
the number generated is well related to the previously generated number. Based on the values
of a, C and m, good random sequence will be generated.
For a=7, C=0, m=32 and X0=1, the sequence will be Xn= {7,17,23,1,7,17,23,1,7…….}
The above generated sequence has period 4, that means the sequence will be repeated itself
after 4 cycles.
For a=5, C=0, m=32 and X0=1, then the sequence will be Xn= {1,5,25,29,17,21,9,13,1……}.
The sequence generated above has a period of 8. Like this, based on the values of a, C and m,
it can generate longer sequences. To produce a longer sequence of distinct numbers, ‘m’
should be large. Typical value of ‘m’ is 231 will be chosen, to generate longest sequence.
By choosing appropriate values of a, C and m, the RNG passed all the three above mentioned
tests.
If ‘m’ is prime and C=0, for certain value of ‘a’, the period of the sequence will be ‘m-1’.
For 32-bit, the convenient prime value of m is 231-1 and the corresponding sequence is:
Xn+1 = (aXn) mod (231-1) [3]
For example, an IBM 360 family of computers have a=75, C=0 and m = 231-1.
The pitfall of this linear congruential algorithm is, if the user knows that this algorithm is
being used and if parameters are known, then all the numbers in the sequence can be
discovered. Knowledge of the some numbers in the sequence is sufficient to predict the other
numbers in the sequence.
Let’s elaborate the above equation for individual values i.e.
X1 = (aX0 + C) mod m; [4]
X2 = (aX1 + C) mod m; [5]
X3 = (aX2 + C) mod m; [6]

By solving the above equations, the user come to know the values for a, C and m.
Thus, the user can predict the remaining numbers in the sequence. This predictability of the
sequence can be overcome by introducing the internal system clock. This internal clock
modifies the stream of random number generation. By using internal system clock, the
sequence would be restarted for every ‘N’ numbers, whereas initial value of the clock is acts
as seed.
Fig. 3.4 Shows Pseudo Random Number Generator (PRNG) block diagram, which is
of a periodic nature. The sequence generated by PRNG is predictable and random. The output
sequence is deterministic in each series, and repeated sequence. So it's really simple and cost
effective. Although it is predictable, the PRNG sequence is used in safe key generation for
larger bits. PRNG depends entirely on the initial value, that initial value is known as seed.
PRNGs are very common in high-performance safety systems design.

The PRNG's basic unit is Linear Feedback Shift Register (LFSR) which is a
combination of shift register and ripple carry logic. The LFSRs are cascaded into several
stages to form the generator of the random numbers. The sequence length depends on the
position of the tapped bits inside the internal LFSR circuit. PRNG is primarily used in the
security applications of cryptosystems. Those applications are popular as PRNG (CSPRNG)
is cryptographically secure. In this case CSPRNG should pass all the statistical test to the
polynomial time at the size of regulated seed. Whereas PRNG, on the other hand, is less
stable than TRNG.

Fig. 3.4 Block Diagram of PRNG

The main property behind PRNG is, to create the unpredictable random numbers. As
well as the LFSR generate the random numbers. The basic structure of LFSR is constructed
by using shift registers and XOR. The next state of the LFSR can be depends on the previous
state of the LFSR. The inputs to the XORs are bits from the shift register that are called tap
bits or tap position. Therefore, the duration of the sequence will depend on the location of the
bits that have been tapped. The overall length of the Pseudo random can be absolutely
dependent on the location of the bits being tapped. LFSR can be implemented in two ways:
Fibonacci and LFSR in Galois form. Fibonacci and Galois can be discussed in section 3.4 and
3.5 respectively.
Cryptographically Random Number Generator:

In this method of random number generation, here only consider the advantage of
encryption logic to produce the RNGs. The setup is shown in Fig. 3.5, In this Pseudorandom
Number Generation, a counter with period ‘N’ is acts as input to the encryption logic. The
principle involved is generation of session keys from the master key that is given to the
encryption logic block. After the generation of each key, the counter value is incremented by
‘1’. Thus the stream generated through this scheme is cycle through full period. Hence the
length of the sequence is maximum. However, the outputs generated are X0 ≠ X1 ≠ X2 ≠
X3….....≠Xn. Each of the counter values are distinct and not depends on the previous value. As
the master key is protected, hence it is difficult to side any of the secret keys generated
through encryption logic. To strengthen this scheme, the counter input is replaced with fully
period PRNG.
 Fig. 3.5 Block diagram of PRNG counter
ANSI Pseudorandom Number Generator:

Many techniques are defined to generate PRNG sequence. ANSI PRNG is one such
method to generate strongest PRNG sequence. This technique employs many applications,
mainly financial security applications. As shown in Fig. 3.6 It has two inputs. One is input
‘DT’ which indicates present date and time, while the other input ‘S i’ represents initial seed.
Both the inputs are updates along with the sequence generation. Where EDE represents the
sequence of Encrypt-Decrypt-Encrypt (EDE), which uses two keys K1 and K2 as shown.
The outputs are
Ri = EDEK1, K2 [Si⊕ EDEK1, K2 [DTi]]; [7]
Si+1 = EDEK1, K2 [Ri⊕ EDEK1, K2 [DTi]]; [8]

Fig. 3.6 Block Diagram of ANSI Pseudorandom Number Generator

 Fig. 3.7 Block diagram of Generate function

Fig. 3.8 Block diagram of Initialize and Update function

Example for PRNG:

 Fig: 3.9 Example for PRNG

Now, here discussed about the 5-bit PRNG with the initial seed 00101. Fig. 3.9
shows the logic diagram of the PRNG. As per shown in the figure a particular taps can gives
the maximum length of the sequence. For the 5-bit, 2 polynomials can be XOR and gives a
new MSB bit. Here it have a five internal bits that can’t be all zeros. The length of the 5-bit
is
2 n – 1 = 25 - 1 = 31.
[9]
As followed by working principal of fig. 3.10, the 00101 state follows the 00101
state, the new tap bits set by XOR of 0 and 0 resulting with 0. Same process can be followed
by remaining all states. The other tap combination of tab bits set by the 0 and 1, 1 and 0
resulting with the 1, similarly 1 and 1 resulting 0. As per the state transition LSB is the output
of the PRNG.

LFSR’s have many practical applications. It can be used as a high speed counter and
pseudorandom sequence generator. It has wide applications in communications theory. There
are many ways to describe the LFSRs, in both practical and theoretical approaches based on
the field of use. Practical approach of LFSR is described by bit wise approach, whereas
theoretical approach includes representation using polynomials and matrices.

The 5-bit PRNG gives the 31 random bit sequence.

 Fig: 3.10 Random bit sequence using PRNG

A shift register is a combination of flip-flops which are also referred to as bit cells.
It has an input signal and it stores a single bit of data, either ‘0’ or ‘1’. The bits in the LFSR
can propagate from right to left or from left to right depends on the shift register chosen.

Y B4 B3 B2 B1 B0 X X B4 B3 B2 B1 B0 Y

Bit cells are numbered from 0 to N-1; where N represents number of bit cells or
number of flip flops used in that particular shift register. In discrete time system these can be
represented as
Bi[k]: represents the content of bit ‘i’ at time step k, and X[k], Y[k] represents input and
output in discrete instances at time step k respectively.
B0[k] = X[k-1]: first bit cell gets its input from input bit stream;
Bi[k] = Bi-1[k-1]; for i>0 each bit cello gets input from previous cell;
Y[k] = BN-1[k];
Bi[k] = X [k-i-1] and Y[k] = X [k-N] because input is delayed by ‘i+1’ and ‘N’ respectively.
Let input signal X[0,1,2,3,4] = (0,1,0,0,1) and initial bit stream would be B[0] = 1 1 0 1 0,
then to get output
B [0] = 1 1 0 1 0, X [0] =0;
B [1] = 1 0 1 0 0, X [0] =1;
B [2] = 0 1 0 0 1, X [0] =0;
B [3] = 1 0 0 1 0, X [0] =0;
B [4] = 0 0 1 0 0, X [0] =1;
B [5] = 0 1 0 0 1,
Then Y [0…..5] = [1 1 0 1 0 0];
X bit is shift in from the right and Y bit is shift out from the left.

3.4 Fibonacci form LFSR

The selected position of bits are known as tapped bits. In Fibonacci form of LFSR
depends on the tapped positions. These tapping bits are combined with the XOR sequentially
with the output bits. The length of the sequence is 2m – 1. The Fibonacci form of LFSR shows
the fig. 3.11. The right most bit of the LFSR is known as output bit stream. The taping bits of
the 16th, 14th, 13th and 11th. These tapped polynomial positions are called feedback path. The
polynomial feedback equation is
X16 + X14 + X13 + X11

Fig. 3.11 Polynomial representation using Fibonacci form.

Fig.3.12. Example of Fibonacci form of LFSR

 A couple of places are tapped. In that one set only gives sequence of the full length.
Let's assume tapped bits in an n-bit LFSR are [n, X, Y, Z, 0], where 0 corresponds to the first
term of the sequence, then [n, n − Z, n − Y, n − X, 0] corresponds to the "mirror" series. So,
the tap sequence [32, 22, 2, 1, 0] has [32, 31, 30, 10, 0] as its counterpart. Both sequences
give the same maximum length.

Fig.3.12. represents an example of Fibonacci form of LFSR with the 00101 is the
initial seed of the form. In the Fibonacci form working process, the tapping bits should be 0,
1, 2 and 5. Those tapped bits XOR and gives the MSB bit. The 00101 state fallows by 10010
state, the new tapped bit values are 1, 0 and 0 resulting with 1. Similarly the even number of
one gives the 0, odd number of ones gives the 1 and all zero tapped bit values resulting with
0. The fig. 3.13 shows the all possible states of the random bit sequence of the Fibonacci
form of LFSR. The length of the sequence is very lesser than the PRNG form. In this case
unused states are more.

Fig.3.13. Random bit sequence of Fibonacci form of LFSR

3.5 Galois form LFSR

Fig. 3.14 Block Diagram of Galois Form.

 Fig.3.15. Example for Galois form of LFSR

In The Galois method, the tapping bits are same like as Fibonacci form of LFSR
method, but the major difference from Fibonacci form LFSR method is reverse engineering
operation of the shifting. This register generates the 2 n - 1states of the non-zero states. To
generates the same output sequence need to use same polynomials as tapping bits. In Galois
form of LFSR method do not focused on every taping bit is crops a new input bit.

Fig.3.16. Random bit sequence of Galois form of LFSR

3.6 True Random number Generator

For the generation of key random numbers are makes very important role in the
modified digital signature generation and validation work. In order to avoid the difficulties
fallowed from various types those are Galois form of LFSR, Fibonacci form of LFSR and
PRNG. TRNG has been selected for key generation.
3.6.1 Functional Block Diagram

Fig. 3.17 Functional diagram of TRNG.

Implementing 32-bit TRNGs, it can be operated using LFSR which can be clocked by
Ring Oscillator, three LFSR which are 13-bit, 19-bit, and 32-bit LFSRs are used. These
XORs play a big role here to improve TRNG's completely random and unpredictable number
generation. The output sequence is non-deterministic and non-repeatable in each cycle, even
if the generation of the bit stream is known. So, it's extremely stable. Through using the
TRNG one can produce the unpredictable and non-periodic random series. The TRNG
functional diagram is shown in Fig 3.17. Concatenation of both 13-bit LFSR and 19-bit LFSR
is performed and XORing the concatenated 32-bit and 32-bit LFSR produces the security
KEY afterwards. Every block of the diagram can be explained in the next section. The
preload block can be used to reshuffle in each cycle of the concatenation block.

3.6.1.1 Ring Oscillator

The odd number of inverters connected back to back to form a simplest Ring
Oscillator as shown in fig. 3.18. The last inverter output feedback to the first inverter input,
which is known as feedback loop, it gives the oscillations. The first inverter can be creates a
stable state.

Fig. 3.18 Functional Diagram of Ring Oscillator.

Fig. 3.19 Jitter Pulses.

The ideal oscillator period is constant, time period of rising and falling edge would
be the same. If the time period of oscillator is not constant because of time period of rising
and falling edges are not constant that shown in in fig.3.19. The RO has an unpredictable
clock, this type of clock is known as clock Jitter. The RO can changes the rising and falling
edges randomly. One of the source to generate random number is TRNG. The RO have a
clock jitter that gives the long time to generate the random numbers.

3.6.1.2 13-Bit / 19-Bit LFSR

The 13-bit LFSR consists of the mux, 13-bit LFSR shift register, and 12, 3, 2 and 0
preload blocks of tapping locations. 13-bit register allows to database the 13-bit LFSR
database output bits. The several MUXs can be used for the transfers the inputs from either
preload block or output from the LFSR block. The architecture of 19-Bit LFSR is same as 13-
bit LFSR with XOR positions are 18, 5, 1 and 0. The size of the shift register is same as bit
size of the LFSR. The structure of LFSR block as shown in figure 3.20.

Fig. 3.20 Functional Diagram of 13 and 19 Bit LFSR.

3.6.1.3 Concatenation

The combination of different bit size of LFSR is generating the required size of LFSR
is the use of concatenation block. In this work 13-bit and 19-bit are used for concatenation.
Each LFSR is clocked with RO and preload. The output of each LFSR is Preload, it helps to
reshuffle the output.
 Fig. 3.21 Functional Diagram of Concatenation Block.

The difference of the concatenated 32-bit LFSR and normal 32-bit LFSR is, for
concatenated LFSR is selectively combined with both 13-bit and 19-bit LFSR. So it has no
sequence expected and another 32-bit LFSR gives regular outputs like pseudo random
sequence generator. The output bits can be stored in 32-bit shift register like as shown in fig.
3.21.

3.6.1.4 32-Bit LFSR

LFSR tapping locations for 32 bit are at 31, 21, 1 and 0 bits. The LFSR have the non-
zero positions that have the 2n-1 states to the maximum length of the sequence. The fig. 3.22
represents the functional diagram of the 32-bit LFSR block. It contains the inputs like enable,
reset and ring oscillator block. The ring oscillator block helps to control, when to shift the
next state with the help of the enable input signal, as well as reset can helps to resets the
LFSR to all zero states.
The output block is final stage to generate the truly random numbers with the help
of 32- bit LFSR and concatenation blocks. By using of more number of PRNGs security can
be increases. The security and PRNG blocks are proportional to each other. The numbers can
be generated in the form of binary numbers, which is used as key in the lots of cryptography
applications.
 Fig. 3.22 Functional Diagram of 32-bit LFSR block.

3.7 Digital Signature Generator

The most important and most valuable technology in security applications is digital
signature generation. When generating the digital signature the RNG property must be used.

 Digital signatures

The digital signatures can also be similar to electronic fingerprints. The sequence of
characters considered by a digital signature represented numerical value. It is very difficult to
generate the digital signature process, and can be done by computer. Throughout the process
of coding the note, the digital signature carefully linked the signer with a record for the
transaction verification. The digital signature uses a common format, which is referred to as a
public key infrastructure. It is used to ensure the highest possible level of protection and
unique acceptance. This type of generation of digital signatures used during the signing
process.

 Digital signature Vs electronic signature

The electronic signature is very different from the physical signature. Digital signature
property is utilized in the process of electronic signature. Today, the signer's signed document
and verification use both the physical signature and the electronic signatures. At the same
time, these are used in purpose, technical implementation, geographical use and legal and
cultural.

Specifically, the use of digital signature technologies for e-signatures fundamentally

varies between nations that adopt transparent, neutral e-signature rules, including the U.S.,
UK, Canada and Australia. What's more, many adopting complex e-signature models
learning to privately defined guidelines that focus on creative computerized signature,
recalling various nations for the European Union, South America, and Asia. Furthermore, a
few companies also support explicit principles which rely on advanced innovation in the
mark.

 Working of digital signature

Fig. 3.23 TRNGs in Digital Signature Generation

Hand written signature unique to each person. Likewise, digital signature also has a
unique identity. This identity created by two things. One is signer document, which is
generated by signer, this is called signer’s private key; it keeps with the signer securely. And
TRNG generates another key, involvement of numerical calculation in hash makes the
coordination between the information and marked archive. The encoding of the information
also takes place like cipher. The digital signature is the remaining scrambled information.
Similarly, the signature is set apart from the time the report was signed. The modifications
that occur after the signing, the digital signature becoming invalid.

For example, Mr John uses a hidden key to sign an agreement to sell his house. The
buyer who obtains the report by receiving the deed additionally receives John’s public key.
The public key's unscrambles cannot occur (the key cannot be decoded using the cipher
technique from which the keys were made), it means the preserved mark is not John's, or
before the altered one is accepted. The sign is otherwise considered as null.

In order to ensure the integrity of the signature, PKI requires the keys to be made,
handled and the certificate authority (CA) requires security administration. Suppliers of
digital signatures, since DocuSign secures information by meeting PKI needs.

 Creation of digital signature

The section 3.7.1.3 explains how digital signatures are produced and digital signatures
validated. For example, the e-Signature providers, DocuSign, which provide agreements
based on advanced innovation in digital signatures, make it easy to sign reports carefully. It
have an interface for sending and labeling reports on the site, and work with the correct
certificate authorities to offer trust in advanced statements. These are called digital
certificates.

The explicit data for the changes in the certificate authority is the basic supply
requirement. The request and changes in the record for marking can be done by using the
DocuSign’s interface. This interface includes the information related to procedures and
guarantee, the report is received by email for marking according to the preconditions of the
certificate authority and then the record is "signed" by signing online.

 Usage of digital signature

For business studies, several industries and topographical regions have established
e-Signature guidelines that depend on innovation in digital signatures, just as CAs have
specifically confirmed. Holding these community standards based on PKI innovation and
collaborating with a trustworthy authentication authority will ensure that an e-signature
agreement is enforceable and accepted in every digital market. Through using the PKI
approach, digital signatures use a basic, undeniably proven, standards-based innovation that
also helps avoid imitation or record changes after signing.

Whenever you need confirmation that the report originated from you and nobody
has messed with it since you sent it. Digital Signature with your SSL certificate fills the bill.
Then again, sometimes you have to demonstrate that a report originated from another person
and has not been changed en route. In legitimate issues, for instance, you may need to
demonstrate that an agreement has not been changed since somebody sent it as an email.
Since the PC persistently combines the Digital Signature to one protected form of the record,
it is almost difficult to revoke a carefully digital signed report. Or then again, in the event that
you are an engineer disseminating programming on the web, you may need to promise your
clients that your executables truly are from you. Put a code signing certificate in your
toolbox.

3.7.1 Working of digital signature generation flow chart

The fig. 3.24 represents the how to process the digital signature generator. This can
chronicled by consolidating digital signature with encryption plot. Let us quickly talk about
how to accomplish this requirements. There are two chances those are

 signer stage
 verifier stage

The cryptography is similar to digital signature, used for decoding the information
and secret key by means of signer. In a signer stage designer have a several steps to generate
the digital signature. Initially, a unique signature collected from the signer. This signature
stores in data block, which is stored in the form of text. This text can be converted into binary
code by using hash function. This binary code known as hash code.
 Fig. 3.24 Flow chart for Digital Signature Generation
In the next step by using of TRNG block generates a key, which is used as a signature
private key. Both the combination of hash code and signature private can be generates a
digital signature with the help of signature process. This digital signature called as digitally
signed document.

In verifier stage, it contains hash function, verification process, hash code and decision
block. In this stage data comes from the signer stage. The verifier after getting the scrambled
information and sign on it, first confirms the signature utilizing sender's public key.
Subsequent to guaranteeing the legitimacy of the signature, he at that point recovers the
information through unscrambling utilizing his private key.

3.7.1.1 Hash function Algorithm:

The mapping of fixed values to variable size data is achieved by the use of hash
function. The properties such as hash codes, digits and hash functions are used to create a
fixed-size hash table. Hash capacity to use the fixed list in the table is defined as hashing hash
capacities and their associated hash tables are used in information storage and recovery
applications to get information in a limited amount of time per recovery, and storage space is
only slightly more prevalent than the actual space available for the information or recording
itself. Hashing is a computationally and storage space efficient type of information that
preserves a strategic distance from the non-straight access time of requested and unordered
records and structured trees and the periodically exponential storage conditions for the direct
access of large or variable keys to state spaces.

Fig. 3.25 Processes of Hash function

At the core of a hashing is a mathematical capacity that works on two fixed-size blocks
of information to make a hash code. This hash work frames the portion of the hashing
algorithm. The fig. 3.25 shows the block diagram of the hash code generation with the hash
function, based on the algorithm size of the each block can be changed. The maximum size of
the block is between the 128 to 512 bits.

3.7.1.2 Key management

The generation of the key is very important in all key based application. It is given that,
the security of any cryptosystem relies on how safely its keys are overseen. Without secure
strategies for the treatment of cryptographic keys, the advantages of the utilization of solid
cryptographic plans are conceivably lost. The fig. 3.26 shows the stage from the key
generation to key distribution. Most of the important requirements of assertion of a public
key can be reached a goal through PKI, the key management process supports the public key
generation.

Fig. 3.26 Process of key management

In key management, several stages are available, it’s starting with key generation stage
and ends with the key distribution. In between the key need to pass the four stages, those are
namely key establishment stage, key storage stage, key usage stage and key arrival stage then
it is finally reaches a key distribution stage.
3.7.1.3 Generator and Validator

Fig. 3.27 Block diagram of Digital Signature Generator and Validator

The generator and validator block plays a very important role in the digital signature.
In various advanced correspondences, making the text scrambled is more preferable to plain
text to accomplish classification. The strategy of using public key of sender in open domain
accessibility for encryption is known as public key encryption and subsequently anybody can
parody his personality and encodes the message to the receiver. This results for the advanced
PKC technique for the encryption of the information along with digital signature. The
validation of the message and non-renouncement takes place.
 This makes it fundamental for clients utilizing PKC for encryption to look for
advanced digital signature alongside encoded information to be guaranteed of message
validation and non-renouncement.

The receiver subsequent to getting the scrambled information and signature on it, first
confirms the signature utilizing sender's public key. After confirming the validity of
guaranteeing the legitimacy of the signature, at that point recovers the information through
decoding utilizing signers private key. The fig. 3.27 represents the block diagram of digital
signature generator and validator.
 CHAPTER 4
Design and Implementation of Random Number Generator

Introduction

The technique true random number generation is one among the highly secured
techniques while transmitting the data. In the field of digital systems, while transferring and
processing the data, it may subject to some disturbances which can change the data bits from
encrypted to decrypted and vice versa.
The main property of RNG is to generate random numbers which are unrepeated and
unexpected sequence. These RNGs takes major roll when there is a need of huge number of
randomness, those are namely

 Gaming applications
 Banking applications
 Lottery
 Security applications
 Cryptography

Fig. 4.1 RNGs in Gaming Application

In gaming applications, RNGs can be widely used in online games like Rummy,
Tic – Tac Toe, dice game and other games. RNGs can be generates random events for critical
hit or picking up the random chances at bullet hit target games. These are maintained by
website which is used to shuffle the data, in rummy game, shuffle the cards and distribute the
cards and to continue the game. Similarly, in dice game RNG can be used for flipping a coin
or rolling a dice after the results can be generates by unpredictable chances and gives the
random number as shown in fig. 4.1.

In all banking services are completely depends on the OTP generation. These OTP
should be needs more random nature for the purpose of customer security. Suppose, money
transfer through mobile banking or net banking, OTP is need to complete the transaction.
Similarly all the services like pin generation for ATM card, MPIN and all i-mobile services
OTP can be used. Here TRNGs are more secure than remaining all RNGs. For example, how
to use the RNG in a login page for any banking login home page, in this page first need to
give personal data of the user then based on that it generates the OTP and validate as shown
in the fig. 4.2.

Fig. 4.2 RNGs in Banking Applications

In lottery, toss the coin or shuffle the tickets to pick up the one chance randomly. At
the time of lottery RNGs are more preferable, because of it must be requires the more
randomness. The RNG framework utilizes two sections to haphazardly draw winning
numbers: a seed esteem and a calculation. In the first place, the seed esteem goes about as a
beginning stage for the procedure. It's a number created from different, unusual sources to
guarantee each draw starts from a random point that can't be anticipated early. For the second
place, the seed esteem is then goes into the true random number generator, which utilizes a
calculation to draw the winning numbers.

The role of Cryptography in information security

Excellent RNGs are a major innovation required to construct a chain of trust in

frameworks the lots of cryptographic applications for encryption/Authentication and security
conventions rely upon RNG for generation of keys, challenges and initial values. The RNG
contains the source entropy and whitening block, which is used to generates an unexpected
random sequence. RNGs are secured from attackers to hide the data and important business
and personal information. Overall the security of the system and strength of the application
depends on the entropy source.

Cryptography can be used to meet a few data protection, information security goals,
including confidentiality, honesty and authentication.

 Confidentiality: Firstly, cryptography protects data protection (or mystery). In any

case, when the transmission or capability medium has been compromised, the
encoded data is useless to unapproved people for all intents and purposes without the
best possible keys to unscrambling.
 Integrity: Cryptography may also be used to ensure the data are respectable (or
accurate) using hashing calculations and digesting messages.
 Authentication: Finally, cryptography can be used by computerized marks, advanced
statements or a public key infrastructure (PKI) for confirmation (and non-
renouncement) benefits.

 Cryptography is described by following:

Type of activities used to change plaintext to cipher text. All encryption measurements are
subject to 2 standards:

 Replacement: where the components in the plaintext are mapped into another
components.
 Transposition: where the components in the plaintext are improved.
 The two types of keys utilized in the cryptography applications, those are namely
symmetric and asymmetric. On the off chance that encryption and unscrambling calculations
utilize a similar key, this framework is symmetric. Where the two separate keys are used in
the same scheme, asymmetric or public key encryption is known.

 The manner by which the plaintext is prepared

Block Cipher: The input of the each block produced by one block of output for each input
bit of data.

Stream Cipher: The infois each component in turn and delivers one yield for everyone
information.

Cryptosystem having two types of texts. One is the plain text is what you want to
protect the data from others, and another one is cypher text which produces from the plaintext
with the help of secret key. The block diagram of cryptosystem is shown fig. 4.3.

Fig. 4.3 RNGs in Cryptography Applications

4.1 PRNG as a Key generator

Pseudo-random number generator is one of the simplest methods for key generation.
For the current digital world, key-generation is very important. Where the random numbers
used in PRNGs requirement.

4.1.1 Working Principle of PRNG

The process of generating the random numbers are shown in fig. 4.4. There are three
stages namely generate, state and collect. In collect stage unpredictable inputs can be
received from the “initial seed pool”, after collecting the initial seed from seed pool transfer
to the next state that is stable state. From that stable state goes to the generate level, in this
level delivers the Pseudo Random outputs. This process is known as cyclic process.

Fig. 4.4 Logic Diagram of PRNG.

Input bit stream is given at the collect block and it is passed to the FSM block, where
the state of the data is decided and it is then given to generate block. This generator block
generates the output bit stream which is referred as pseudorandom bit stream. The advantage
of the PRNGs are they produce the same sequence of the next cycle, so easily find out the
starting point of the each cycle, easy to generate the random numbers and faster in operation.
The disadvantage of the PRNG is some of the seeds have minimum length of the
sequence, this kind of seed is known as “weak seed”. The main disadvantage of the PRNG is
security, it is very less because of easily expected the sequence of the random numbers.

4.2 Implementation of LFSR Counter as a Key generator

The feedback of linear shift register is used for the generation of pseudo random
series. It got to implement very quickly in hardware and low power. For their performance
enhancement LFSR counters are replaced by binary counters. The LFSR counters are mainly
used in single photon detection where speed plays a vital role. The LFSR generated pseudo
random sequence is converted into binary sequence by decoding logic. By using multi stage
LFSR counter, the decoding logic scaled logarithmically with stages than exponentially
which on depends number of bits.

The LFSR counter consists of no linear feedback shift registers with carrying ripple logic.
The LFSRs are cascaded into countless levels. By 3 methods, the LFSR counter is decoded to
binary count. These are the method of iteration, the direct method of LUT and the tradeoff
algorithm of time memory. When the method of iteration is used it needs on average 2 n-1
comparisons and requires a large memory. Direct LUT approach uses n*n LUT to decode the
LFSR state directly, instead of m*n LUT.
4.2.1 Working of LFSR Counter

In fig. 4.5 shows the working principle of the existing key generation method. Here,
the key can be generated by components used one LFSR block, one PRNG block, feedback
network and one 8*1 mux. The LFSR block can be used to generate the random sequence of
the data which can be stored in the feedback network as shown in the fig.4.5. The LFSR
block stated by the initial vector, it should not be all zero states. The feedback network place
sequence can be stored which is generated by the LFSR block.
The x is output sequence which is generated by LFSR block. The 8*1 MUX is used
for select one number from the above sequence. The 3 bit PRNG block can be used like
selection lines of the MUX. By using of PRNG block, the number can be selected from the
sequence. The selected number is considered as a key. Here multiple number of keys can be
generated and it is completely based on the selection line of the MUX block and sequence.
 Fig. 4.5 Logic Diagram of LFSR Counter
Generally, LFSRs used as PRNGs for encryption and decryption of the data securing.
But here cryptographically secured PRNGs are used instead of PRNGs, two level procedure
of design and placing of key makes the previous data secures. The utilization of
cryptographically secure LFSRs randomizes the procedure even more and consequently
magnifies the general security of the system. In this LFSR counter composed with the
multiple stages of LFSRs.

Trade off algorithm is used in established work time memory which combines both
methods. I.e. it stores 2n/2 LFSR count values and compares the number of iterations
subtracted from the stored value to obtain decoded value until the count value matches a
value in the table. The decoding logic used in conversion should be integral and fast the
ripple carry logic is used to trigger the value of the LFSR state i.e. 0b1111…….0b0000. It is
called locked upstate. The LFSR counter does not count the ripple carry logic is used to
detect the 0b1111…… state in LFSR and trigger to 0b000…. state.
The ripple carry logic signal generated by first LFSR is taken as input to second
LFSR stage. The ripple carry logic signal is generated for every clock cycle. The LFSR state
has disadvantage i.e. it stops the count when they encounter the 0b1111…… state or
0b0000…… the traditional LFSR consist of D flip flop cascaded and XOR gate used for
feedback. The state 0b1111…… problem can be eliminated by using a NOR gate in feedback
along with XOR. If ob1111…. State problem cannot be eliminated. It can cause missing
counter states from counter state space. The 0b0000 state is called locked up state as it stop
the count.

The decoding logic acts as post-processing steps on the LFSR counter multi-stage as
ripple carry logic causes one clock cycle per stage to delay the transition edge. The delayed
transition causes a triangle of errors to form. There are two types of errors in decoding the
LUTs. They are the original error, and the error of excess. LUT corrects most of the binary
commands that are entered to display the unit.

The initial errors on the upper edge of the transition error triangle occur in the state.
On the clock cycle, when counter is stopped before transitions to the m th stage. Overflow
errors arise when there is an error in the previous stage and equals 0X ....... FF. These errors
suggest that a prior stage would have caused an earlier clock cycle to bring a ripple event.

4.3 Implementation of TRNG as a Key generator

Today, all the numbers generated by digital computers are not truly random, these are
deterministic with a certain period. The output defined the next outcome. As per the
definition of randomness, one output doesn’t define the next outcome. True Random Number
Generator (TRNG) is one such a method of generating genuinely or absolute random
numbers. The True Random Generators are the basic blocks used in security cryptographic
systems. Lot of things in the universe are random. These random numbers generated by
TRNG technique are commonly used as secret keys in communication systems, network
security, and statistics, gaming and gambling in cryptographic field.

Fig. 4.6 Stochastic model of testing TRNG.

 Fig. 4.8 Block diagram of TRNG

Getting truly or absolutely random number is very important. This true random
number generation is generally observed in our daily physical life. The physical processes
like flipping a coin which is purely unpredictable. The main property of the TRNG is, its
output cannot be reproduced.

Fig. 4.7 Basic building block of TRNG

TRNGs will pass all statistical testing performed on their bit streams. There are
numerous predefined statistical measures to verify the true randomness. The testing process
for true randomness is given in fig.4.6, where the bit stream generated from the RNGs is
given for testing. If the stream passed all the tests performed on it, then the sequence is true
else it is deterministic.
 The input to the TRNG is physical noise, as discussed in chapter I, TRNGs are
classified into software TRNGs and Hardware TRNGs. Today, software based techniques are
very vulnerable to external attacks, so software TRNGs are least popular. Whereas hardware
TRNGs takes physical noise present in the hardware as input. The noise from the physical
source is given to digitizer to process it and to get the digital signal. This signal is given to
Data Acquisition System (DAS), for further data processing. Post data processing it is
directly given as input to the random number generator.

Generally, digital world having hardware-based TRNGs where the randomness is

generated from the noise present in the system and software-based TRNGs where the
randomness is generated from the predefined algorithms. As software based techniques are
vulnerable to security attacks, here hardware based TRNGs are mostly preferable. Its entropy
source is an important fundamental property of the TRNG.

4.4 Implementation of digital signature through TRNG as a key

4.4.1 Design Flow of work

 Fig. 4.9 Work design Flow in Xilinx ISE

Now a days, ASIC configuration stream is an extremely developed procedure in

silicon turnkey structure. The ASIC configuration stream and its different strides in VLSI
building that we portray underneath depend on best practices and demonstrated philosophies
in ASIC chip plans. This blog endeavors to clarify various strides in the ASIC configuration
stream, beginning from ASIC plan idea and moving from details to benefits.

To warrant effective ASIC configuration, engineers must follow a demonstrated

ASIC configuration stream which depends on requirements, work specifications with an
attention on meeting the goal of the desired work. Each phase of ASIC configuration cycle
has EDA apparatuses that can assist with actualizing ASIC structure effortlessly. In work
design flow, involves various steps such as work specifications, logical implementation for
key, development of digital signature generator and finally verification and validation of the
work.

4.4.2 XILINX ISE TOOL DESIGN FLOW

Starting the ISE Software

Start -> All Programs -> Xilinx ISE 14.5 -> Project Navigator
Creating a New Project
For the creation of new project
1. Select New Project option in File menu, it opens a New Project Wizard.
2. Enter the Project Name field as tutorial.
3. Enter or browse to a location (path of a directory) for the new project. A subdirectory
with name tutorial is automatically created.
4. Verify that HDL is selected from the top-level source type list.
5. Click on Next, it moves to the device properties page.
6. Fill the properties in the table by leaving the default values for remaining fields.
Steps to Create a Project
1. Select File > New Project to launch the New Project Wizard.
 4.10 New Project to launch the New Project Wizard
2. In the Create New Project page, set the name, location, and project type, and click
Next.

4.11 Setup location in the New Project Wizard

3. In the Project Summary page, review the information, and click Finish to create the
project.
 4.10 Project summery page
Creating Source code of Verilog
1. Select New Source and then select Verilog Module as source type the specified file
name and click Next.

4.11 Creation of new module in source Wizard page

2. Declare the required ports and then click Next.
 4.12 Pins declaration in source Wizard page
3. Click on Finish. A new file will be created and opened

4.13 Project summary in source Wizard page

4. Write the program in the editor
4.14 Program editor page
 CHAPTER-5
RESULTS AND ANALYSIS

Key Generation: The key can be generated in several methods which is discussed in
Chapter3. The existing work is based on the LFSR counter as a key generator and pseudo
random number generator. In proposed work, key can be generated by using true random
number generator.

Existing work:
Pseudo Random Number Generator

Fig. 5.1 Pin diagram for PRNG

Fig. 5.2 RTL schematic for PRNG

 Fig. 5.3 RTL schematic for PRNG
The fig 5.1, fig 5.2 and fig 5.3 represents the pin diagram, RTL schematic and technology of
the PRNG, which contains the two input ports and one output port named as en, clk and out it
has 10 bits of data. The fig 5.4 represents the simulation results of the PRNG.

Fig. 5.4 Simulation Result for PRNG

Table 1. Performance table for PRNG

Table 2. Resource summery table for PRNG

LFSR Counter:
 Fig. 5.5 Pin diagram for LFSR Counter

Fig. 5.6 RTL schematic for LFSR counter

The fig 5.5, fig 5.6 and 5.7 are represents the pin diagram, RTL schematic and
technology diagram of the LFSR counter. It has two inputs namely en and clock. Two inout
ports named as a and s, a contains 10 bits of data and s contains 3bits of data. One output
ports which is named as y, it contains 10bit. The LFSR counter contains one top module and
three sub-modules. Top module have two inputs and one output. Sub-modules namely 10 bit
LFSR module, 3 bit LFSR module and one mux module. The en and clk are input and 10 bit
a is output of the 10bit LFSR module. The same inputs are taken for the 3 bit LFSR module,
it gives the 3bit output which is named as s. The module mux has a 10 bit input a and s
considered as selection line of the mux module. The output of the mux y considered as key.
Fig. 5.7 Technology diagram for LFSR counter
 Fig. 5.8 Simulation Results for LFSR counter

Table 3. Performance table for LFSR counter

Table 4. Resource summery table for LFSR counter

The fig 5.8 is simulation results of the LFSR counter. The output of the LFSR counter
gives always gives binary values, which are either 1 or 0. So the security of the system is
reduces because of the two stages are repeated frequently. The table3 and table 4 represents
the performance summary and resource summery respectively. To avoid the problems in
existed LFSR counter introduced the proposed TRNG. It improves the security of the system.

Proposed work:
TRNG Block:

Fig. 5.9 Pin diagram for TRNG

 Fig. 5.10 RTL schematic for TRNG

Fig. 5.11 Technology diagram for TRNG

The fig. 5.9, fig 5.10 and fig 5.11 is represents the pin diagram, schematic diagram
and technology diagram of the TRNG Block. It shows all possible internal blocks as well as
their interconnections with both output and input pins. Here en and rst are taken as inputs.
[9:0]a and [9:0]b are the inout ports of the concatenation block and LFSR block respectively.
[9:0]out is the sequence of the TRNG block, which is considered as the security key. The fig.
5.12 represents the simulation results of the proposed key generation method of the random
number generation.

Fig. 5.12 Simulation Result for TRNG

Ring Oscillator:

Fig. 5.13 RTL schematic for Ring Oscillator

 The ring oscillator is one of the block in the TRNG method. The fig. 5.13 shows the
schematic diagram of the ring oscillator. The odd number of inverters can be connected by
cascading way is known as ring oscillator. Here en is the input of the ring oscillator. It helps
to enable the circuit. When the en 1 starts the circuit operating. The output of the ring
oscillator can be connected to the one of the input of the TRNG block. The fig. 5.14 gives the
simulation results of the ring oscillator.

Fig. 5.14 Simulation Result for Ring Oscillator

Concatenation:

Fig. 5.15 RTL schematic for Concatenation

The fig. 5.15 and 5.16 exhibits the RTL schematic and simulation results for the
Concatenation block, which is one of the important block in the TRNG design. Because of
this block increases the randomness of the system. This process also known as whitening
method. The combination of two different sizes of LFSR circuits. In this work 6-bit LFSR
and 4-bit LFSR.

Fig. 5.16 Simulation Result for Concatenation

LFSR Block:

The fig. 5.17 and 5.18 represents the Schematic and simulation results of the LFSR
block which is one of the block in TRNG. The LFSR has two inputs those are en, clock, and
one output which is named as out. In this work input is feeding 10bit as well as 10bit output
sequence is generated like as shown in fig 5.18.
 Fig. 5.17 RTL schematic for LFSR

Fig. 5.18 Simulation Result for LFSR

Table 5. Performance table for TRNG

Table 6. Resource summery for TRNG

Comparison:

PRNG LFSRcounter TRNG

Leakage power 48.531 nw 82.125 nw 113.060 nw

 Dynamic power 27222.682 nw 47607.764 nw 71003.993 nw

Total power 27271.214 nw 47689.889 nw 71117.052 nw

Area 1315 2689 2947

Delay 348 ps 416 ps 367 ps

cells 22 85 59

Fan out 38 38 40

PRNG LFSRcounter TRNG

Min. Clock Period 5 ns 5 ns 15.500 ns

Max. Clock 200 MHz 200 MHz 64.516 MHz

Frequency

Clock to setup 5 ns 5 ns 15.500 ns

Clock pad to 4.700 ns 8.400 ns 90.100ns

Output pad delay

Microcells used 10/32(32%) 23/32 (72%) 35/36 (98%)

Pterms used 10/112 (9%) 21/112 (19%) 66/108 (37%)

Registers used 10/32(32%) 13/32 (41%) 20/36 (56%)

Pins used 12/33 (37%) 25/33 (76%) 32/34 (95%)

Functional blocks 9/80 (12%) 12/80 (15%) 41/108 (38%)

inputs used

Application for the proposed work:

The digital signature generation and validator is one of the best application for the
random number generation, this is implemented in various types of the RNGs. In this work
the digital signature can be generated with the help of true random number generator, it helps
to improve the security of the system. The fig 5.19 represents the pin diagram of the digital
signature generator and validation. In this work the data is secure with help of Cryptosystem.

Digital Signature Generation and Validation:

Fig. 5.19 Pin diagram for digital signature and Generator and validation
 Fig. 5.20 RTL schematic for digital signal generation and validation
Digital signature generation can be implemented with the help of proposed
TRNG key. The fig 5.20 shows the RTL schematic of the digital signature generator and
validation, the signature is converted as signature prevented key. User prevented key can be
generated by using proposed secure method. Digitally secured doc can be generated with the
help of user prevented key and signature prevented key. Verification is the done by verifier.
Digitally signed doc can be decoded with the help of user prevent key. Decoded data should
be equal to the signature. In fig5.21, [9:0]out is the key which is proposed method, given
signature is “tulsi” and [9:0]doc is the digitally signed document. The fig 5.22 represent the
technology diagram of the digital signature and validation. In the simulation results [9:0]x is
the document which is generated from validation stage. If [9:0]h is equal to the [9:0]x the
signature is validated successfully.

Fig. 5.21 Simulation results for digital signature generation and validation
Fig. 5.22 Technology diagram for digital signature generation and validation
 CHAPTER-6
CONCLUSION& FUTURE SCOPE

Conclusion
This report has dealt with the comparison of the conventional random number generators and
the proposed generators. These generation methods were designed, implemented and the
measurement results were compared with simulations. This work is an overhead to the PRNG
and TRNG generation. Both the methods were designed for high speed and lower power
consumption. As seen from the simulation results in chapter 5, the TRNG method of
randomness generation has higher security because of its unpredictability. The simulations
were carried out for 8, 16, 32, 64 and 128 bit generators.
As seen in chapter 4 the area consumed by the TRNG is slightly more than the conventional
PRNG. This is because PRNG has minimum routing complexity. Whereas the area consumed
by the RNGs, PRNGs and TRNGs, a brief report is given in chapter 4. This can be attributed
to less required logic for the PRNG compared to the TRNG. But, reduced power consumption
and higher security are the two distinct advantages of the TRNG over its counterpart.

Future Scope
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