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Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation ■ Top or bottom boot block configurations
— 5.0 Volt-only operation for read, erase, and available
program operations ■ Embedded Algorithms
— Minimizes system level requirements — Embedded Erase algorithm automatically
■ Manufactured on 0.35 µm process technology preprograms and erases the entire chip or any
combination of designated sectors
— Compatible with 0.5 µm Am29F800 device
— Embedded Program algorithm automatically
■ High performance writes and verifies data at specified addresses
— Access times as fast as 55 ns
■ Minimum 1,000,000 program/erase cycles per
■ Low power consumption (typical values at 5 sector guaranteed
MHz) ■ Package option
— 1 µA standby mode current — 48-pin TSOP
— 20 mA read current (byte mode) — 44-pin SO
— 28 mA read current (word mode)
■ Compatibility with JEDEC standards
— 30 mA program/erase current
— Pinout and software compatible with single-
■ Flexible sector architecture power-supply Flash
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and — Superior inadvertent write protection
fifteen 64 Kbyte sectors (byte mode)
■ Data# Polling and toggle bits
— One 8 Kword, two 4 Kword, one 16 Kword, and
— Provides a software method of detecting
fifteen 32 Kword sectors (word mode)
program or erase operation completion
— Supports full chip erase
■ Ready/Busy# pin (RY/BY#)
— Sector Protection features:
— Provides a hardware method of detecting
A hardware method of locking a sector to
program or erase cycle completion
prevent any program or erase operations within
that sector ■ Erase Suspend/Erase Resume
Sectors can be locked via programming — Suspends an erase operation to read data from,
equipment or program data to, a sector that is not being
Temporary Sector Unprotect feature allows code erased, then resumes the erase operation
changes in previously locked sectors ■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash preprograms the array (if it is not already programmed)
memory organized as 1,048,576 bytes or 524,288 before executing the erase operation. During erase, the
words. The device is offered in 44-pin SO and 48-pin device automatically times the erase pulse widths and
TSOP packages. The word-wide data (x16) appears on verifies proper cell margin.
DQ15–DQ0; the byte-wide (x8) data appears on DQ7–
The host system can detect whether a program or
DQ0. This device is designed to be programmed in-
erase operation is complete by observing the RY/BY#
system with the standard system 5.0 volt VCC supply.
pin, or by reading the DQ7 (Data# Polling) and DQ6
A 12.0 V VPP is not required for write or erase opera-
(toggle) status bits. After a program or erase cycle has
tions. The device can also be programmed in standard
been completed, the device is ready to read array data
EPROM programmers.
or accept another command.
This device is manufactured using AMD’s 0.35 µm
The sector erase architecture allows memory sectors
process technology, and offers all the features and ben-
to be erased and reprogrammed without affecting the
efits of the Am29F800, which was manufactured using
data contents of other sectors. The device is fully
0.5 µm process technology.
erased when shipped from the factory.
The standard device offers access times of 55, 70, 90,
Hardware data protection measures include a low
120, and 150 ns, allowing high speed microprocessors
VCC detector that automatically inhibits write opera-
to operate without wait states. To eliminate bus conten-
tions during power transitions. The hardware sector
tion the device has separate chip enable (CE#), write
protection feature disables both program and erase
enable (WE#) and output enable (OE#) controls.
operations in any combination of the sectors of mem-
The device requires only a single 5.0 volt power sup- ory. This can be achieved via programming equipment.
ply for both read and write functions. Internally gener-
The Erase Suspend feature enables the user to put
ated and regulated voltages are provided for the
program and erase operations. erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
The device is entirely command set compatible with the erasure. True background erase can thus be achieved.
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan- The hardware RESET# pin terminates any operation
dard microprocessor write timings. Register contents in progress and resets the internal state machine to
serve as input to an internal state-machine that con- reading array data. The RESET# pin may be tied to the
trols the erase and programming circuitry. Write cycles system reset circuitry. A system reset would thus also
also internally latch addresses and data needed for the reset the device, enabling the system microprocessor
programming and erase operations. Reading data out to read the boot-up firmware from the Flash memory.
of the device is similar to reading from other Flash or The system can place the device into the standby
EPROM devices. mode. Power consumption is greatly reduced in
Device programming occurs by executing the program this mode.
command sequence. This initiates the Embedded AMD’s Flash technology combines years of Flash
Program algorithm—an internal algorithm that auto- memory manufacturing experience to produce the
matically times the program pulse widths and verifies h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t
proper cell margin. effectiveness. The device electrically erases all
Device erasure occurs by executing the erase com- bits within a sector simultaneously via
mand sequence. This initiates the Embedded Erase F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s
algorithm—an internal algorithm that automatically programmed using hot electron injection.
2 Am29F800B
P R E L I M I N A R Y
BLOCK DIAGRAM
RY/BY# DQ0–DQ15 (A-1)
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
WE# State
Control
BYTE#
Command
Register PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
OE# Logic
Y-Decoder Y-Gating
STB
Address Latch
A0–A18
21504C-1
Am29F800B 3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15 1 48 A16
A14 2 47 BYTE#
A13 3 46 VSS
A12 4 45 DQ15/A-1
A11 5 44 DQ7
A10 6 43 DQ14
A9 7 42 DQ6
A8 8 41 DQ13
NC 9 40 DQ5
NC 10 39 DQ12
WE# 11 38 DQ4
RESET# 12 37 VCC
NC 13 36 DQ11
NC 14 35 DQ3
RY/BY# 15 34 DQ10
A18 16 33 DQ2
A17 17 32 DQ9
A7 18 31 DQ1
A6 19 30 DQ8
A5 20 29 DQ0
A4 21 28 OE#
A3 22 27 VSS
A2 23 26 CE#
A1 24 25 A0
A16 1 48 A15
BYTE# 2 47 A14
VSS 3 46 A13
DQ15/A-1 4 45 A12
DQ7 5 44 A11
DQ14 6 43 A10
DQ6 7 42 A9
DQ13 8 41 A8
DQ5 9 40 NC
DQ12 10 39 NC
DQ4 11 38 WE#
VCC 12 37 RESET#
DQ11 13 36 NC
DQ3 14 35 NC
DQ10 15 34 RY/BY#
DQ2 16 33 A18
DQ9 17 32 A17
DQ1 18 31 A7
DQ8 19 30 A6
DQ0 20 29 A5
OE# 21 28 A4
VSS 22 27 A3
CE# 23 26 A2
A0 24 25 A1
21504C-2
4 Am29F800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
RY/BY# 1 44 RESET#
A18 2 43 WE#
A17 3 42 A8
A7 4 41 A9
A6 5 40 A10
A5 6 39 A11
A4 7 38 A12
A3 8 37 A13
A2 9 36 A14
A1 10 35 A15
A0 11 34 A16
CE# 12 33 BYTE#
VSS 13 32 VSS
OE# 14 31 DQ15/A-1
DQ0 15 30 DQ7
DQ8 16 29 DQ14
DQ1 17 28 DQ6
DQ9 18 27 DQ13
DQ2 19 26 DQ5
DQ10 20 25 DQ12
DQ3 21 24 DQ4
DQ11 22 23 VCC
21504C-3
Am29F800B 5
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am29F800B T -70 E C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be sup-
Valid Combinations ported in volume for this device. Consult the local AMD sales
Am29F800BT-55, office to confirm availability of specific valid combinations and
EC, EI, FC, FI, SC, SI to check on newly released combinations.
Am29F800BB-55
Am29F800BT-70,
Am29F800BB-70
Am29F800BT-90,
Am29F800BB-90 EC, EI, EE,
FC, FI, FE,
Am29F800BT-120, SC, SI, SE
Am29F800BB-120
Am29F800BT-150,
Am29F800BB-150
6 Am29F800B
P R E L I M I N A R Y
BYTE# BYTE#
Operation CE# OE# WE# RESET# A0–A18 DQ0–DQ7 = VIH = VIL
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.
Am29F800B 7
P R E L I M I N A R Y
After the system writes the autoselect command se- In the DC Characteristics tables, ICC3 represents the
quence, the device enters the autoselect mode. The standby current specification.
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array) RESET#: Hardware Reset Pin
on DQ7–DQ0. Standard read cycle timings apply in this The RESET# pin provides a hardware method of reset-
mode. Refer to the “Autoselect Mode” and “Autoselect ting the device to reading array data. When the system
Command Sequence” sections for more information. drives the RESET# pin low for at least a period of tRP,
ICC2 in the DC Characteristics table represents the ac- the device immediately terminates any operation in
tive current specification for the write mode. The “AC progress, tristates all data output pins, and ignores all
Characteristics” section contains timing specification read/write attempts for the duration of the RESET#
tables and timing diagrams for write operations. pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
Program and Erase Operation Status terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
During an erase or program operation, the system may
integrity.
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC Current is reduced for the duration of the RESET#
read specifications apply. Refer to “Write Operation pulse. When RESET# is held at VIL, the device enters
Status” for more information, and to each AC Charac- the TTL standby mode; if RESET# is held at VSS ±
teristics section for timing diagrams. 0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
Standby Mode
cuitry. A system reset would thus also reset the Flash
When the system is not reading or writing to the device, memory, enabling the system to read the boot-up firm-
it can place the device in the standby mode. In this ware from the Flash memory.
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde- If RESET# is asserted during a program or erase oper-
pendent of the OE# input. ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
The device enters the CMOS standby mode when CE# time of tREADY (during Embedded Algorithms). The
and RESET# pins are both held at VCC ± 0.5 V. (Note system can thus monitor RY/BY# to determine whether
that this is a more restricted voltage range than VIH.) the reset operation is complete. If RESET# is asserted
The device enters the TTL standby mode when CE# when a program or erase operation is not executing
and RESET# pins are both held at VIH. The device re- (RY/BY# pin is “1”), the reset operation is completed
quires standard access time (tCE) for read access when within a time of tREADY (not during Embedded Algo-
the device is in either of these standby modes, before it rithms). The system can read data tRH after the RE-
is ready to read data. SET# pin returns to VIH.
The device also enters the standby mode when the RE- Refer to the AC Characteristics tables for RESET# pa-
SET# pin is driven low. Refer to the next section, “RE- rameters and timing diagram.
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program- Output Disable Mode
ming, the device draws active current until the When the OE# input is at VIH, output from the device is
operation is completed. disabled. The output pins are placed in the high imped-
ance state.
8 Am29F800B
P R E L I M I N A R Y
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.
Am29F800B 9
P R E L I M I N A R Y
Note:
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See “Word/Byte Configuration” section for more information.
Autoselect Mode
The autoselect mode provides manufacturer and de- dress must appear on the appropriate highest order
vice identification, and sector protection verification, address bits. Refer to the corresponding Sector Ad-
through identifier codes output on DQ7–DQ0. This dress Tables. The Command Definitions table shows
mode is primarily intended for programming equipment the remaining address bits that are don’t care. When all
to automatically match a device to be programmed with necessary bits have been set as required, the program-
its corresponding programming algorithm. However, ming equipment may then read the corresponding
the autoselect codes can also be accessed in-system identifier code on DQ7–DQ0.
through the command register.
To access the autoselect codes in-system, the host
When using programming equipment, the autoselect system can issue the autoselect command via the
mode requires VID (11.5 V to 12.5 V) on address pin command register, as shown in the Command Defini-
A9. Address pins A6, A1, and A0 must be as shown in tions table. This method does not require VID. See
Autoselect Codes (High Voltage Method) table. In addi- “Command Definitions” for details on using the autose-
tion, when verifying sector protection, the sector ad- lect mode.
10 Am29F800B
P R E L I M I N A R Y
01h
X
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
X
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both START
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro- RESET# = VID
tected sectors. (Note 1)
Sector protection/unprotection must be implemented
using programming equipment. The procedure re- Perform Erase or
quires a high voltage (VID) on address pin A9 and the Program Operations
control pins. Details on this method are provided in a
supplement, publication number 20374. Contact an
AMD representative to obtain a copy of the appropriate RESET# = VIH
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting Temporary Sector
Unprotect
sectors at its factory prior to shipping the device Completed (Note 2)
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected 21504C-5
or unprotected. See “Autoselect Mode” for details. Notes:
1. All protected sectors unprotected.
Temporary Sector Unprotect 2. All previously protected sectors are protected once
This feature allows temporary unprotection of previ- again.
ously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the Figure 1. Temporary Sector Unprotect Operation
RESET# pin to VID. During this mode, formerly pro-
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Am29F800B 11
P R E L I M I N A R Y
Hardware Data Protection proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection Write Pulse “Glitch” Protection
against inadvertent writes (refer to the Command Defi- Noise pulses of less than 5 ns (typical) on OE#, CE# or
nitions table). In addition, the following hardware data WE# do not initiate a write cycle.
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri- Logical Inhibit
ous system level signals during VCC power-up and Write cycles are inhibited by holding any one of OE# =
power-down transitions, or from system noise. VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
Low VCC Write Inhibit CE# and WE# must be a logical zero while OE# is a
logical one.
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC Power-Up Write Inhibit
power-up and power-down. The command register and If WE# = CE# = VIL and OE# = VIH during power up, the
all internal program/erase circuits are disabled, and the device does not accept commands on the rising edge
device resets. Subsequent writes are ignored until VCC of WE#. The internal state machine is automatically
is greater than V LKO. The system must provide the reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se- ters, and Read Operation Timings diagram shows the
quences into the command register initiates device op- timing diagram.
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect Reset Command
address and data values or writing them in the im- Writing the reset command to the device resets the de-
proper sequence resets the device to reading array vice to reading array data. Address bits are don’t care
data. for this command.
All addresses are latched on the falling edge of WE# or The reset command may be written between the se-
CE#, whichever happens later. All data is latched on quence cycles in an erase command sequence before
the rising edge of WE# or CE#, whichever happens erasing begins. This resets the device to reading array
first. Refer to the appropriate timing diagrams in the data. Once erasure begins, however, the device ig-
“AC Characteristics” section. nores reset commands until the operation is complete.
Reading Array Data The reset command may be written between the se-
quence cycles in a program command sequence be-
The device is automatically set to reading array data
fore programming begins. This resets the device to
after device power-up. No commands are required to
reading array data (also applies to programming in
retrieve data. The device is also ready to read array
Erase Suspend mode). Once programming begins,
data after completing an Embedded Program or Em-
however, the device ignores reset commands until the
bedded Erase algorithm.
operation is complete.
After the device accepts an Erase Suspend command,
The reset command may be written between the se-
the device enters the Erase Suspend mode. The sys-
quence cycles in an autoselect command sequence.
tem can read array data using the standard read tim-
Once in the autoselect mode, the reset command must
ings, except that if it reads at an address within erase-
be written to return to reading array data (also applies
suspended sectors, the device outputs status data.
to autoselect during Erase Suspend).
After completing a programming operation in the Erase
Suspend mode, the system may once again read array If DQ5 goes high during a program or erase operation,
data with the same exception. See “Erase Sus- writing the reset command returns the device to read-
pend/Erase Resume Commands” for more information ing array data (also applies during Erase Suspend).
on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
12 Am29F800B
P R E L I M I N A R Y
Autoselect Command Sequence the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
The autoselect command sequence allows the host
cessful. However, a succeeding read will show that the
system to access the manufacturer and devices codes,
data is still “0”. Only erase operations can convert a “0”
and determine whether or not a sector is protected.
to a “1”.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program- START
mers and requires VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect Write Program
Command Sequence
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
Data Poll
A read cycle at address XX00h or retrieves the manu- from System
facturer code. A read cycle at address XX01h in word Embedded
mode (or 02h in byte mode) returns the device code. Program
algorithm
A read cycle containing a sector address (SA) and the
in progress
address 02h in word mode (or 04h in byte mode) re-
turns 01h if that sector is protected, or 00h if it is un- Verify Data?
No
protected. Refer to the Sector Address tables for valid
sector addresses.
Yes
The system must write the reset command to exit the
autoselect mode and return to reading array data.
No
Increment Address Last Address?
Word/Byte Program Command Sequence
The system may program the device by byte or word,
Yes
on depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com- Programming
mand sequence is initiated by writing two unlock write Completed
cycles, followed by the program set-up command. The
program address and data are written next, which in 21504C-6
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim- Note: See the appropriate Command Definitions table for
program command sequence.
ings. The device automatically provides internally gen-
erated program pulses and verify the programmed cell Figure 2. Program Operation
margin. The Command Definitions take shows the ad-
dress and data requirements for the byte program com-
mand sequence.
Chip Erase Command Sequence
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad- Chip erase is a six-bus-cycle operation. The chip erase
dresses are no longer latched. The system can deter- command sequence is initiated by writing two unlock
mine the status of the program operation by using DQ7, cycles, followed by a set-up command. Two additional
DQ6, or RY/BY#. See “Write Operation Status” for in- unlock write cycles are then followed by the chip erase
formation on these status bits. command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
Any commands written to the device during the Em- preprogram prior to erase. The Embedded Erase algo-
bedded Program Algorithm are ignored. Note that a rithm automatically preprograms and verifies the entire
hardware reset immediately terminates the program- memory for an all zero data pattern prior to electrical
ming operation. The program command sequence erase. The system is not required to provide any con-
should be reinitiated once the device has reset to read- trols or timings during these operations. The Command
ing array data, to ensure data integrity. Definitions table shows the address and data require-
Programming is allowed in any sequence and across ments for the chip erase command sequence.
sector boundaries. A bit cannot be programmed Any commands written to the chip during the Embed-
from a “0” back to a “1”. Attempting to do so may halt ded Erase algorithm are ignored. Note that a hardware
Am29F800B 13
P R E L I M I N A R Y
reset during the chip erase operation immediately ter- are ignored. Note that a hardware reset during the
minates the operation. The Chip Erase command se- sector erase operation immediately terminates the op-
quence should be reinitiated once the device has eration. The Sector Erase command sequence should
returned to reading array data, to ensure data integrity. be reinitiated once the device has returned to reading
array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See When the Embedded Erase algorithm is complete, the
“Write Operation Status” for information on these device returns to reading array data and addresses are
status bits. When the Embedded Erase algorithm is no longer latched. The system can determine the sta-
complete, the device returns to reading array data tus of the erase operation by using DQ7, DQ6, DQ2, or
and addresses are no longer latched. RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC Figure 3 illustrates the algorithm for the erase opera-
Characteristics” for parameters, and to the Chip/Sector tion. Refer to the Erase/Program Operations tables in
Erase Operation Timings for timing waveforms. the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
Sector Erase Command Sequence waveforms.
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un- Erase Suspend/Erase Resume Commands
lock cycles, followed by a set-up command. Two addi- The Erase Suspend command allows the system to in-
tional unlock write cycles are then followed by the terrupt a sector erase operation and then read data
address of the sector to be erased, and the sector from, or program data to, any sector not selected for
erase command. The Command Definitions table erasure. This command is valid only during the sector
shows the address and data requirements for the sec- erase operation, including the 50 µs time-out period
tor erase command sequence. during the sector erase command sequence. The
Erase Suspend command is ignored if written during
The device does not require the system to preprogram
the chip erase operation or Embedded Program algo-
the memory prior to erase. The Embedded Erase algo-
rithm. Writing the Erase Suspend command during the
rithm automatically programs and verifies the sector for
Sector Erase time-out immediately terminates the
an all zero data pattern prior to electrical erase. The
time-out period and suspends the erase operation. Ad-
system is not required to provide any controls or tim-
dresses are “don’t-cares” when writing the Erase Sus-
ings during these operations.
pend command.
After the command sequence is written, a sector erase
When the Erase Suspend command is written during a
time-out of 50 µs begins. During the time-out period,
sector erase operation, the device requires a maximum
additional sector addresses and sector erase com-
of 20 µs to suspend the erase operation. However,
mands may be written. Loading the sector erase buffer
when the Erase Suspend command is written during
may be done in any sequence, and the number of sec-
the sector erase time-out, the device immediately ter-
tors may be from one sector to all sectors. The time be-
minates the time-out period and suspends the erase
tween these additional cycles must be less than 50 µs,
operation.
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended After the erase operation has been suspended, the
that processor interrupts be disabled during this time to system can read array data from or program data to
ensure all commands are accepted. The interrupts can any sector not selected for erasure. (The device “erase
be re-enabled after the last Sector Erase command is suspends” all sectors selected for erasure.) Normal
written. If the time between additional sector erase read and write timings and command definitions apply.
commands can be assumed to be less than 50 µs, the Reading at any address within erase-suspended sec-
system need not monitor DQ3. Any command other tors produces status data on DQ7–DQ0. The system
than Sector Erase or Erase Suspend during the can use DQ7, or DQ6 and DQ2 together, to determine
time-out period resets the device to reading array if a sector is actively erasing or is erase-suspended.
data. The system must rewrite the command sequence See “Write Operation Status” for information on these
and any additional sector addresses and commands. status bits.
The system can monitor DQ3 to determine if the sector After an erase-suspended program operation is com-
erase timer has timed out. (See the “DQ3: Sector Erase plete, the system can once again read array data within
Timer” section.) The time-out begins from the rising non-suspended sectors. The system can determine
edge of the final WE# pulse in the command sequence. the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
Once the sector erase operation has begun, only the
ation. See “Write Operation Status” for more informa-
Erase Suspend command is valid. All other commands
tion.
14 Am29F800B
P R E L I M I N A R Y
Yes
Erasure Completed
21504C-7
Am29F800B 15
P R E L I M I N A R Y
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Word 555 2AA 555
Manufacturer ID 4 AA 55 90 X00 01
Byte AAA 555 AAA
Autoselect (Note 8)
Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 8. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read cycle.
3. Except when reading array or autoselect data, all bus cycles 9. The data is 00h for an unprotected sector and 01h for a
are write operations. protected sector. See “Autoselect Command Sequence” for
more information.
4. Data bits DQ15–DQ8 are don’t cares for unlock and
command cycles. 10. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
5. Address bits A17–A11 are don’t cares for unlock and mode. The Erase Suspend command is valid only during a
command cycles, unless SA or PA required. sector erase operation.
6. No unlock or command cycles required when reading array 11. The Erase Resume command is valid only during the Erase
data. Suspend mode.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
16 Am29F800B
P R E L I M I N A R Y
Am29F800B 17
P R E L I M I N A R Y
RY/BY#: Ready/Busy# The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
The RY/BY# is a dedicated, open-drain output pin that
algorithm, and to the Toggle Bit Timings figure in the
indicates whether an Embedded Algorithm is in
“AC Characteristics” section for the timing diagram.
progress or complete. The RY/BY# status is valid after
The DQ2 vs. DQ6 figure shows the differences be-
the rising edge of the final WE# pulse in the command
tween DQ2 and DQ6 in graphical form. See also the
sequence. Since RY/BY# is an open-drain output, sev-
subsection on “DQ2: Toggle Bit II”.
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
DQ2: Toggle Bit II
If the output is low (Busy), the device is actively erasing The “Toggle Bit II” on DQ2, when used with DQ6, indi-
or programming. (This includes programming in the cates whether a particular sector is actively erasing
Erase Suspend mode.) If the output is high (Ready), (that is, the Embedded Erase algorithm is in progress),
the device is ready to read array data (including during or whether that sector is erase-suspended. Toggle Bit
the Erase Suspend mode), or is in the standby mode. II is valid after the rising edge of the final WE# pulse in
Table 6 shows the outputs for RY/BY#. The timing dia- the command sequence.
grams for read, reset, program, and erase shows the DQ2 toggles when the system reads at addresses
relationship of RY/BY# to other signals. within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
DQ6: Toggle Bit I trol the read cycles.) But DQ2 cannot distinguish
Toggle Bit I on DQ6 indicates whether an Embedded whether the sector is actively erasing or is erase-sus-
Program or Erase algorithm is in progress or complete, pended. DQ6, by comparison, indicates whether the
or whether the device has entered the Erase Suspend device is actively erasing, or is in Erase Suspend, but
mode. Toggle Bit I may be read at any address, and is cannot distinguish which sectors are selected for era-
valid after the rising edge of the final WE# pulse in the sure. Thus, both status bits are required for sector and
command sequence (prior to the program or erase op- mode information. Refer to Table 6 to compare outputs
eration), and during the sector erase time-out. for DQ2 and DQ6.
During an Embedded Program or Erase algorithm op- Figure 5 shows the toggle bit algorithm in flowchart
eration, successive read cycles to any address cause form, and the section “DQ2: Toggle Bit II” explains the
DQ6 to toggle. (The system may use either OE# or algorithm. See also the “DQ6: Toggle Bit I” subsection.
CE# to control the read cycles.) When the operation is Refer to the Toggle Bit Timings figure for the toggle bit
complete, DQ6 stops toggling. timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
Reading Toggle Bits DQ6/DQ2
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, Refer to Figure 5 for the following discussion. When-
the Embedded Erase algorithm erases the unpro- ever the system initially begins reading toggle bit sta-
tected sectors, and ignores the selected sectors that tus, it must read DQ7–DQ0 at least twice in a row to
are protected. determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
The system can use DQ6 and DQ2 together to deter- after the first read. After the second read, the system
mine whether a sector is actively erasing or is erase- would compare the new value of the toggle bit with the
suspended. When the device is actively erasing (that is, first. If the toggle bit is not toggling, the device has
the Embedded Erase algorithm is in progress), DQ6 completed the program or erase operation. The sys-
toggles. When the device enters the Erase Suspend tem can read array data on DQ7–DQ0 on the following
mode, DQ6 stops toggling. However, the system must read cycle.
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use However, if after the initial two read cycles, the system
DQ7 (see the subsection on “DQ7: Data# Polling”). determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
If a program address falls within a protected sector, high (see the section on DQ5). If it is, the system
DQ6 toggles for approximately 2 µs after the program should then determine again whether the toggle bit is
command sequence is written, then returns to reading toggling, since the toggle bit may have stopped tog-
array data. gling just as DQ5 went high. If the toggle bit is no longer
DQ6 also toggles during the erase-suspend-program toggling, the device has successfully completed the
mode, and stops toggling once the Embedded Pro- program or erase operation. If it is still toggling, the
gram algorithm is complete. device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
18 Am29F800B
P R E L I M I N A R Y
Am29F800B 19
P R E L I M I N A R Y
20 Am29F800B
P R E L I M I N A R Y
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Am29F800B 21
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA
VCC
VIH Input High Voltage 2.0 V
+ 0.5
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.
22 Am29F800B
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V
Notes:
1. ICC active while Embedded Erase or Embedded Program is in progress.
2. Not 100% tested.
Am29F800B 23
P R E L I M I N A R Y
TEST CONDITIONS
Table 7. Test Specifications
5.0 V
All
Test Condition -55 others Unit
2.7 kΩ
Device Output Load 1 TTL gate
Under
Test Output Load Capacitance, CL
30 100 pF
(including jig capacitance)
CL 6.2 kΩ
Input Rise and Fall Times 5 20 ns
Steady
Changing from H to L
Changing from L to H
KS000010-PAL
24 Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Operations
Parameter Speed Option
JEDEC Std Description Test Setup -55 -70 -90 -120 -150 Unit
CE# = VIL
tAVQV tACC Address to Output Delay Max 55 70 90 120 150 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 ns
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
tRC
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
21504C-13
Figure 9. Read Operations Timings
Am29F800B 25
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
Note:
Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
21504C-14
Figure 10. RESET# Timings
26 Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
CE#
OE#
BYTE#
tELFL
BYTE# DQ0–DQ14 Data Output Data Output
Switching (DQ0–DQ14) (DQ0–DQ7)
from word
to byte
mode DQ15/A-1 DQ15 Address
Output Input
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte DQ0–DQ14 Data Output Data Output
to word (DQ0–DQ7) (DQ0–DQ14)
mode
DQ15/A-1 Address DQ15
Input Output
tFHQV
21504C-15
Figure 11. BYTE# Timings for Read Operations
CE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
21504C-16
Figure 12. BYTE# Timings for Write Operations
Am29F800B 27
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Byte Typ 7
tWHWH1 tWHWH1 Programming Operation (Note 2) µs
Word Typ 12
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
28 Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
tGHWL
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
tBUSY tRB
RY/BY#
tVCS
VCC
21504C-17
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Am29F800B 29
P R E L I M I N A R Y
AC CHARACTERISTICS
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
tGHWL
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
tBUSY tRB
RY/BY#
tVCS
VCC
21504C-13
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
30 Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21504C-18
Figure 15. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21504C-19
Figure 16. Toggle Bit Timings (During Embedded Algorithms)
Am29F800B 31
P R E L I M I N A R Y
AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
DQ6
DQ2
Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the
erase-suspended sector.
21504C-20
Figure 17. DQ2 vs. DQ6
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
12 V
RESET#
0 or 5 V 0 or 5 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
21504C-21
Figure 18. Temporary Sector Unprotect Timing Diagram
32 Am29F800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Am29F800B 33
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.
21504C-22
Figure 19. Alternate CE# Controlled Write Operation Timings
34 Am29F800B
P R E L I M I N A R Y
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -55), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
Am29F800B 35
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
SO 044—44-Pin Small Outline Package (measured in millimeters)
44 23
13.10 15.70
13.50 16.30
1 22
1.27 NOM.
TOP VIEW
28.00
28.40
2.17 0.10
2.80 0.21
2.45 MAX.
0°
SEATING 8° 0.60
0.35 0.10 PLANE 1.00
0.50 0.35
END VIEW
SIDE VIEW 16-038-SO44-2
SO 044
DF83
8-8-96 lv
36 Am29F800B
P R E L I M I N A R Y
Pin 1 I.D.
1 48
11.90
12.10
0.50 BSC
24 25
18.30 0.05
18.50 0.15
19.80
20.20
16-038-TS48-2
0.08 TS 048
1.20 0.20 DT95
MAX 8-8-96 lv
0.10
0.21
0°
0.25MM (0.0098") BSC 5°
0.50
0.70
Pin 1 I.D.
1 48
11.90
12.10
0.50 BSC
24 25
18.30 0.05
18.50 0.15
16-038-TS48
TSR048
0.08 DT95
1.20 0.20 8-8-96 lv
MAX 0.10
0.21
0°
0.25MM (0.0098") BSC 5°
0.50
0.70
Am29F800B 37
P R E L I M I N A R Y
Corrected text to indicate that these functions can only Revision C+1
be implemented using programming equipment. Distinctive Characteristics
Table 1, Device Bus Operations Changed typical program/erase current to 30 mA to
Revised to indicate inputs for both CE# and RESET# match the CMOS DC Characteristics table.
are required for standby mode. Changed minimum endurance to 1 million write cycles
Program Command Sequence per sector guaranteed.
Changed to indicate Data# Polling is active for 2 µs AC Characteristics
after a program command sequence if the sector spec- Erase/Program Operations: Corrected the notes refer-
ified is protected. ence for tWHWH1 and tWHWH2. These parameters are
Sector Erase Command Sequence and DQ3: Sector 100% tested. Changed tDS and tCP specifications for 55
Erase Timer ns device. Changed tWHWH1 word mode specification
to 12 µs.
Corrected sector erase timeout to 50 µs.
Alternate CE# Controlled Erase/Program Operations:
Erase Suspend Command
Corrected the notes reference for tWHWH1 and tWHWH2.
Changed to indicate that the device suspends the These parameters are 100% tested. Changed tDS and
erase operation a maximum of 20 µs after the rising tCP specifications for 55 ns device. Changed tWHWH1
edge of WE#. word mode specification to 12 µs.
DC Characteristics Temporary Sector Unprotect Table
Changed to indicate VID min and max values are 11.5 Added note reference for tVIDR. This parameter is not
to 12.5 V, with a VCC test condition of 5.0 V. Added 100% tested.
typical values to TTL table. Revised CMOS typical
standby current (ICC3). Erase and Programming Performance
In Notes 1 and 6, changed the endurance specification
Figure 14: Chip/Sector Erase Operation Timings;
to 1 million cycles.
Figure 19: Alternate CE# Controlled Write
Operation TImings
Corrected hexadecimal values in address and data
waveforms. In Figure 19, corrected data values for chip
and sector erase.
38 Am29F800B
P R E L I M I N A R Y
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29F800B 39
This datasheet has been downloaded from:
www.DatasheetCatalog.com