ClkMinTrans Merged

RULE: ClkMinTrans
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Input pins (of clock cells) that have slope smaller than the spec
FIX ADVICE:
RULE: ClkMinTrans
CATEGORY: Clocks
SEVERITY: must
FIX ADVICE:
RULE: ClkMinTransPBA
CATEGORY: Clocks
SEVERITY: must
FIX ADVICE:
RULE: ClkMinTransPBA
CATEGORY: Clocks
SEVERITY: must
FIX ADVICE:
RULE: ClkNetworkRCDelay
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: RC delays (in clock network) exceed the specified limit
FIX ADVICE:
RULE: ClkNetworkRCDelay
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: RC delays (in clock network) exceed the specified limit
FIX ADVICE:
RULE: ClkRCStageDelay
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Nets in the clock network with RC delay greater than

$caliber_rc_stage_max_delay_limit (ps)
FIX ADVICE:
RULE: ClkRCStageDelay
CATEGORY: Clocks
SEVERITY: must

FIX ADVICE:
RULE: ClkShortedMacroEnb
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Clockgate with enable pin is connected to vcc or vss.
PROBLEM: The clock gate is not used for any power saving and there is wastage of power and
area. Clock gates tied off may stop clock propagation.
FIX ADVICE: Fix should be done in RTL. Still there might be cases in which those cells are
required for metal option fix
RULE: ClkShortedMacroEnb
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Clockgate with enable pin is connected to vcc or vss.
PROBLEM: The clock gate is not used for any power saving and there is wastage of power and
area. Clock gates tied off may stop clock propagation.
FIX ADVICE: Fix should be done in RTL. Still there might be cases in which those cells are
required for metal option fix
RULE: ClockBufInvDualOnDataPath
CATEGORY: Quality
SEVERITY: must
DESCRIPTION: These are clock cells reported on data paths that swapping to data cells can
provide power savings
FIX ADVICE: convert to non clock cells

RULE: ClockBufInvDualOnDataPath
CATEGORY: Quality
SEVERITY: must
DESCRIPTION: These are clock cells reported on data paths that swapping to data cells can
provide power savings

RULE: ClockCellOnDataPath
CATEGORY: Quality
SEVERITY: must
DESCRIPTION: Clock cells found on data path cause inaccurate timing modeling and possible
missing arcs. In addition clock cells consume more area and power relatively to the same sized
data cells.

RULE: ClockCellOnDataPath
CATEGORY: Quality
SEVERITY: must
DESCRIPTION: Clock cells found on data path cause inaccurate timing modeling and possible
missing arcs. In addition clock cells consume more area and power relatively to the same sized
data cells.

RULE: ClockLatency
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Clock latency must be no larger or smaller than the specified constraints
FIX ADVICE:
RULE: ClockLatency
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Clock latency must be no larger or smaller than the specified constraints
FIX ADVICE:
RULE: ClockLSCheck
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Report clock levelshifter instances in the design .
FIX ADVICE:
RULE: ClockLSCheck
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Report clock levelshifter instances in the design .
FIX ADVICE:
RULE: ClockMinPulseWidth
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Flags minimum pulse width violations at sequential elements.
Rule will report violation if either the high PW or low PW is smaller than limits. Limits are the
maximum of ($caliber_lowest_pulse_width_limit, $caliber_min_pulse_width_mult*clock phase)
$caliber_lowest_pulse_width_limit is the guard banding for case when limit is not defined
For violation which sense=nonunate/half_nonunate and duty cycle is 0.25
For violation which sense=positive_unate/negative_unate, if both actual pulse width and

threshold are '99999' (either hi or lo), this mean that only one of hi/lo pulse is violated.
In order to debug run the following command inside pt_shell and look for extremely unbalanced
cells on the clock trace:
report_min_pulse_width -path_type full_clock_expanded -input_pins -transition_time \$pin
Note that primetime limit (in pt_shell) might be different than the project limit. You must meet the
project limit as defined in caliber.
FIX ADVICE: Consider clock route changes if the pulsewidth has degraded much from the
masterclock's (mclk).
RULE: ClockMinPulseWidth
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Flags minimum pulse width violations at sequential elements.
Rule will report violation if either the high PW or low PW is smaller than limits. Limits are the
maximum of ($caliber_lowest_pulse_width_limit, $caliber_min_pulse_width_mult*clock phase)
$caliber_lowest_pulse_width_limit is the guard banding for case when limit is not defined
For violation which sense=nonunate/half_nonunate and duty cycle is 0.25
For violation which sense=positive_unate/negative_unate, if both actual pulse width and

threshold are '99999' (either hi or lo), this mean that only one of hi/lo pulse is violated.
In order to debug run the following command inside pt_shell and look for extremely unbalanced
cells on the clock trace:
report_min_pulse_width -path_type full_clock_expanded -input_pins -transition_time \$pin
Note that primetime limit (in pt_shell) might be different than the project limit. You must meet the
project limit as defined in caliber.
FIX ADVICE: Consider clock route changes if the pulsewidth has degraded much from the
masterclock's (mclk).
RULE: ClockMultiplication
CATEGORY: Power
SEVERITY: recommended
DESCRIPTION: In a clock tree, if we have A driving B and B driving C (A, B, C are clock buf/inv),
and if, the cap on A=>B and B=>C is < 7fF, then we suggest can remove B and save power.
PROBLEM: Power wastage
EXCLUDES: None
RULE: ClockMultiplication
CATEGORY: Power
DESCRIPTION: In a clock tree, if we have A driving B and B driving C (A, B, C are clock buf/inv),
and if, the cap on A=>B and B=>C is < 7fF, then we suggest can remove B and save power.
PROBLEM: Power wastage
EXCLUDES: None
RULE: ClockNetworkRCDelay
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: This rule calculates the RC delay along the path to the D data pin of a
sequential and flags a violation if the RC exceeds 25% of the clock insertion delay.
RULE: ClockNetworkRCDelay
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: This rule calculates the RC delay along the path to the D data pin of a
sequential and flags a violation if the RC exceeds 25% of the clock insertion delay.
RULE: ClockNetworkVTType
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: This rule checks the VTâ€”Type for each clock network against the reference
VT-Type pre-specified for the clock.
PRIOBLEM: Avoid the use of mix-VT in the clock path.
FIX ADVICE: Swap the cells with proper VTâ€“Type or redo clock synthesis with the given VT-
Type.
WAIVERS:
RULE: ClockNetworkVTType
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: This rule checks the VTâ€”Type for each clock network against the reference
VT-Type pre-specified for the clock.
PRIOBLEM: Avoid the use of mix-VT in the clock path.
FIX ADVICE: Swap the cells with proper VTâ€“Type or redo clock synthesis with the given VT-
Type.
WAIVERS:
RULE: ClockPropCheck
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Report cells in clockpath which donot propagate clock .
FIX ADVICE:Check for stop clock commands

RULE: ClockPropCheck
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Report cells in clockpath which donot propagate clock .
FIX ADVICE:Check for stop clock commands

RULE: ClockRCStageDelay
CATEGORY: Clocks
SEVERITY: must

FIX ADVICE:
RULE: ClockRCStageDelay
CATEGORY: Clocks
SEVERITY: must

FIX ADVICE:
RULE: ClockShielding
CATEGORY: Clocks
SEVERITY: info
DESCRIPTION: This rule checks for a silicon induced delay delta above some threshold. The
threshold value is in picoseconds, and the net length is in nanometers.
PROBLEM:
FIX ADVICE: .
RULE: ClockShielding
CATEGORY: Clocks
SEVERITY: info
DESCRIPTION: This rule checks for a silicon induced delay delta above some threshold. The
threshold value is in picoseconds, and the net length is in nanometers.
PROBLEM:
FIX ADVICE: .
RULE: ClockSlowSlope
CATEGORY: Clocks
SEVERITY: must
PROBLEM: Flags clock pins for which slopes are worse than the threshold value. The rule
checks the sum of both actual pin transition and project_factor * annotated transition which
comes from PTSI analysis (actual_rise_transition_max +
$caliber_si_slope_adjustment*annotated_rise_transition_delta_max). Slopes for HIP/STD-CELL
clk-outputs with zero-slopes are estimated using elmore-method and these have a different limit.
The slope_calc_method column indicates the method employed to calculate slope. Typically
these cells would be untimed DC-only cells or Cells carrying constaints because they are driven
by a Logic0/Logic1 cell.
FIX ADVICE: For internal pins - Upsize the driver and downsize the receiver For interface nodes
report to FCT owner.
CATEGORY: Clocks
SEVERITY: must
CATEGORY: Clocks
SEVERITY: must
CATEGORY: Clocks
SEVERITY: must
RULE: ClockSlowSlopeProfileICC
CATEGORY: Clocks
DESCRIPTION: Rule reports diff between Caliber and ICC2 slope values and limits for Clock pins.
Rule uses ICC2 MaxCap viol report that will located in following order:
1. G_MAX_TRANS_PROFILING_VIOL_RPT gvar if it is defined

2. WARD/apr2/reports/\$block.vio.max_transition.rpt is exit
3. WARD/apr2/reports/\$block.vio.rpt is exit
4. Latest updated file matching WARD/apr2/reports/\$block.*.vio.rpt
5. If no file is found - rule will generate warning.
Rule uses G_CALIBER_PROFILING_CORNER for coner definition if exist Otherwise G_SCENARIO replacing \"all\" by \"func\":
all_max_lowvcc will be convted to func_max_lowvcc
If G_CALIBER_PROFILING_COMPARE_ALL = 1 rule will generate info for all violations in the ICC2 report Otherwise rule will
apply internal; algorithm to report only violations that more than thresholds
Rule uses follwoing Caliber global limits:
caliber_slowslope_profiling_value_default_threshold_percent=$caliber_slowslope_profiling_value_default_threshold_percent
caliber_slowslope_profiling_value_small_threshold=$caliber_slowslope_profiling_value_small_threshold
caliber_slowslope_clock_limit_threshold_ICC2=$caliber_slowslope_clock_limit_threshold_ICC2
How rule works:

Rule will report value_diff violation if diff between ICC2 and Caliber values are >
$caliber_slowslope_profiling_value_default_threshold_percent %
For small values uses diff treshold (format (small value) (small value treshold)) : $caliber_slowslope_clock_limit_threshold_ICC2
So potentially rule uses diff limits for small and big values.
Rule will report limit_diff if ICC2 limit for clock is more than
PROBLEM: Big miscorrelation causes delay in rule conversion

RULE: ClockSlowSlopeProfileICC
CATEGORY: Clocks
DESCRIPTION: Rule reports diff between Caliber and ICC2 slope values and limits for Clock pins.
Rule uses ICC2 MaxCap viol report that will located in following order:
1. G_MAX_TRANS_PROFILING_VIOL_RPT gvar if it is defined

2. WARD/apr2/reports/\$block.vio.max_transition.rpt is exit
3. WARD/apr2/reports/\$block.vio.rpt is exit
4. Latest updated file matching WARD/apr2/reports/\$block.*.vio.rpt
5. If no file is found - rule will generate warning.
Rule uses G_CALIBER_PROFILING_CORNER for coner definition if exist Otherwise G_SCENARIO replacing \"all\" by \"func\":
all_max_lowvcc will be convted to func_max_lowvcc
If G_CALIBER_PROFILING_COMPARE_ALL = 1 rule will generate info for all violations in the ICC2 report Otherwise rule will
apply internal; algorithm to report only violations that more than thresholds
Rule uses follwoing Caliber global limits:
caliber_slowslope_profiling_value_default_threshold_percent=$caliber_slowslope_profiling_value_default_threshold_percent
caliber_slowslope_profiling_value_small_threshold=$caliber_slowslope_profiling_value_small_threshold
How rule works:

Rule will report value_diff violation if diff between ICC2 and Caliber values are >
$caliber_slowslope_profiling_value_default_threshold_percent %
For small values uses diff treshold (format (small value) (small value treshold)) : $caliber_slowslope_clock_limit_threshold_ICC2
So potentially rule uses diff limits for small and big values.
Rule will report limit_diff if ICC2 limit for clock is more than
PROBLEM: Big miscorrelation causes delay in rule conversion

RULE: ClockStampingAtHIPOutput
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION:Checks for non-generated clocks stamped at the HIP output pin instead of
internal check pins of the HIPs. This can possible lead to some incorrect timing analysis if the
clock is not stamped at the actual generating pin of the hip.
FIX ADVICE:Move the clock stamping from the output pin to the internal pin. Can be stamped on
output pin if that is actually the generating point of the clock and there is not an internal pin as the
generation point.
RULE: ClockStampingAtHIPOutput
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION:Checks for non-generated clocks stamped at the HIP output pin instead of
internal check pins of the HIPs. This can possible lead to some incorrect timing analysis if the
clock is not stamped at the actual generating pin of the hip.
FIX ADVICE:Move the clock stamping from the output pin to the internal pin. Can be stamped on
output pin if that is actually the generating point of the clock and there is not an internal pin as the
generation point.
RULE: CmosInputsTiedTogether
CATEGORY: Modeling
SEVERITY: must
DESCRIPTION: Flags input pins that are tied to a single net and have a min margin less than
15ps
PROBLEM: Cell characterization is not done for input pins tied together due to which timing
modeling will be inaccurate for min analysis
FIX ADVICE: The min margin needs to be fixed

RULE: CmosInputsTiedTogether
CATEGORY: Modeling
SEVERITY: must
DESCRIPTION: Flags input pins that are tied to a single net and have a min margin less than
15ps
PROBLEM: Cell characterization is not done for input pins tied together due to which timing
modeling will be inaccurate for min analysis
FIX ADVICE: The min margin needs to be fixed

RULE: ConstantClockRegisters
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Constant signal is recognized at the sequential clk input pin which results in
timing checks not being done.
PROBLEM: Clock is not recognized at the sequential clock input. If clock is not recognized, then
setup/hold checks don't get done and this may cause a silicon escape (We've had real mindelay
silicon escapes resulting from someone waiving this rule).
Note for cases where a flop is disabled by tying the clock input to supply or a constant: This
guarantees that the logical output of the flop is "X". If you have done this and are planning to
waive it, you will need to prove that all endpoints of the downstream logic cone are nocon (not
connected to anything).
FIX ADVICE:Typically caused by a missing clock attribute at the block interface or missing clock
stamping on the output of a divider or other atypical cell. This also happens if the clock is tied
constant. Fix by backtracking through the clock network and find where the clock property gets
dropped. Then either add the property or clock stamp. For sequentials with clocks "tied off" -- this
is not a good idea unless the sequential has a reset input pin that is actively used and
guarantees a known logical output. If you have circuits that you believe are no longer used, its
best to remove or comment out the RTL rather than tying clocks constant.
Debug BKM:
- Open the DC GUI
- Type the following in the design vision commandline
set pin {/full/path/pin/reported/in/duet}
set input_pin_collection \[all_fanin -to \$pin -flat\]
change_selection \$input_pin_collection
- Click on the "Create schematic of selected objects" button in design vision
RECENT_CHANGES: The reporting for this rule has changed in BXT. The reason column will
now contain semi-colon separated list of driver-types. The driver-column will contain the Logic0/1
cell causing the constant-propagation on clk-pin, instead of saying "NA". Please check to make
sure your waivers, which were applied on the 'reason' or 'driver' column are not dropped.
KNOWN_ISSUES:For unit-level waivers: do not use unit interface names (names without
any hierarchy) from the â€œdriverâ€ column because they prevent waivers from being re-
used at partition level.
RULE: ConstantClockRegisters
CATEGORY: Clocks
SEVERITY: must
DESCRIPTION: Constant signal is recognized at the sequential clk input pin which results in
timing checks not being done.
PROBLEM: Clock is not recognized at the sequential clock input. If clock is not recognized, then
setup/hold checks don't get done and this may cause a silicon escape (We've had real mindelay
silicon escapes resulting from someone waiving this rule).
Note for cases where a flop is disabled by tying the clock input to supply or a constant: This
guarantees that the logical output of the flop is "X". If you have done this and are planning to
waive it, you will need to prove that all endpoints of the downstream logic cone are nocon (not
connected to anything).
FIX ADVICE:Typically caused by a missing clock attribute at the block interface or missing clock
stamping on the output of a divider or other atypical cell. This also happens if the clock is tied
constant. Fix by backtracking through the clock network and find where the clock property gets
dropped. Then either add the property or clock stamp. For sequentials with clocks "tied off" -- this
is not a good idea unless the sequential has a reset input pin that is actively used and
guarantees a known logical output. If you have circuits that you believe are no longer used, its
best to remove or comment out the RTL rather than tying clocks constant.
Debug BKM:
- Open the DC GUI
- Type the following in the design vision commandline
set pin {/full/path/pin/reported/in/duet}
set input_pin_collection \[all_fanin -to \$pin -flat\]
change_selection \$input_pin_collection
- Click on the "Create schematic of selected objects" button in design vision
RECENT_CHANGES: The reporting for this rule has changed in BXT. The reason column will
now contain semi-colon separated list of driver-types. The driver-column will contain the Logic0/1
cell causing the constant-propagation on clk-pin, instead of saying "NA". Please check to make
sure your waivers, which were applied on the 'reason' or 'driver' column are not dropped.
KNOWN_ISSUES:For unit-level waivers: do not use unit interface names (names without
any hierarchy) from the â€œdriverâ€ column because they prevent waivers from being re-
used at partition level.
RULE: CustomChopperFound
CATEGORY: General
SEVERITY: must
DESCRIPTION: On any non-gated-clock CMOS gates - if more than one input is clock then
custom chopper is created - we do not want this in cbd world - known exceptions would be scan
subsytem
FIX ADVICE: Custom chopper needs to be removed

CATEGORY: General
SEVERITY: must
subsytem

CATEGORY: General
SEVERITY: must
subsytem

CATEGORY: General
SEVERITY: must
subsytem

CATEGORY: General
SEVERITY: must
subsytem

RULE: DanglingInNet
CATEGORY: Quality
SEVERITY: must
DESCRIPTION: This rule flags any input pin that is not driven. Note that in silicon we only care
about input pins tied to transistor gate inputs. If you have a symbolic hierarchy pin that is not
connected to any real circuit, this is a false violation.
PROBLEM: Undriven transistor inputs can go metastable in real silicon and do physical damage
to any devices or wires in close proximity. Therefore even circuits that are not used cannot be left
with undriven inputs.
FIX ADVICE: Add a driver to the flagged input pin or tie to ground.
RULE: DanglingInNet
CATEGORY: Quality
SEVERITY: must
RULE: DanglingInNet
CATEGORY: Quality
SEVERITY: must
RULE: DanglingInNet
CATEGORY: Quality
SEVERITY: must
RULE: DanglingInNet
CATEGORY: Quality
SEVERITY: must
RULE: DanglingInNet
CATEGORY: Quality
SEVERITY: must
RULE: DesignMismatch
CATEGORY: Quality
SEVERITY: must
DESCRIPTION: Reports design mismatches between the netlist and lib files during linking as
reported by the PT command report_design_mismatch
FIX ADVICE: Fix the library link issues that are reported by using the correct lib files
CATEGORY: Quality
SEVERITY: must
CATEGORY: Quality
SEVERITY: must
CATEGORY: Quality
SEVERITY: must
CATEGORY: Quality
SEVERITY: must
CATEGORY: Quality
SEVERITY: must
RULE: DirectEnable
CATEGORY: Power
SEVERITY: must
DESCRIPTION: The rule reports usage of sequential library cells that have direct enable pins on
them.
PROBLEM: This is a power wasting configuration.
FIX ADVICE: Move the enable up to the clock tree.
EXCLUDES: None.
RULE: DirectEnable
CATEGORY: Power
SEVERITY: must
them.
EXCLUDES: None.
RULE: DirectEnable
CATEGORY: Power
SEVERITY: must
them.
EXCLUDES: None.
RULE: DisallowedConstPins
CATEGORY: General
SEVERITY: must
DESCRIPTION: Flags pins in the design which are physically tied high or low on library cells for
which the pins have been marked (by project) as not allowed to be physically tied.
PROBLEM: A physically tied pin is not controllable, and there are certain types of cells for which
this could cause serious problems in the design. Example: Sleep control signal should never tied
off or constant.
FIX ADVICE: Fix the design in DC or ICC2 or ECO the fix or verify with RTL owner if it's
allowed.
CATEGORY: General
SEVERITY: must
off or constant.
allowed.
CATEGORY: General
SEVERITY: must
off or constant.
allowed.
RULE: DotProcessMismatch
CATEGORY: Timing
SEVERITY: info
DESCRIPTION: Reports dot process mismatches between the top level and lib file used
FIX ADVICE: Use the lib file with the correct dot process in the hip_list file
CATEGORY: Timing
SEVERITY: info
CATEGORY: Timing
SEVERITY: info

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RULE: ClkMinTrans

DESCRIPTION: RC delays (in clock network) exceed the specified limit

DESCRIPTION: RC delays (in clock network) exceed the specified limit

DESCRIPTION: Nets in the clock network with RC delay greater than

DESCRIPTION: Nets in the clock network with RC delay greater than

DESCRIPTION: Clockgate with enable pin is connected to vcc or vss.

DESCRIPTION: Clockgate with enable pin is connected to vcc or vss.

FIX ADVICE: convert to non clock cells

FIX ADVICE: convert to non clock cells

FIX ADVICE: convert to non clock cells

FIX ADVICE: convert to non clock cells

DESCRIPTION: Report clock levelshifter instances in the design .

DESCRIPTION: Report clock levelshifter instances in the design .

DESCRIPTION: Flags minimum pulse width violations at sequential elements.

For violation which sense=nonunate/half_nonunate and duty cycle is 0.25

For violation which sense=positive_unate/negative_unate, if both actual pulse width and

report_min_pulse_width -path_type full_clock_expanded -input_pins -transition_time \$pin

DESCRIPTION: Flags minimum pulse width violations at sequential elements.

For violation which sense=nonunate/half_nonunate and duty cycle is 0.25

For violation which sense=positive_unate/negative_unate, if both actual pulse width and

report_min_pulse_width -path_type full_clock_expanded -input_pins -transition_time \$pin

PROBLEM: Power wastage

PROBLEM: Power wastage

PRIOBLEM: Avoid the use of mix-VT in the clock path.

PRIOBLEM: Avoid the use of mix-VT in the clock path.

DESCRIPTION: Report cells in clockpath which donot propagate clock .

FIX ADVICE:Check for stop clock commands

DESCRIPTION: Report cells in clockpath which donot propagate clock .

FIX ADVICE:Check for stop clock commands

DESCRIPTION: Nets in the clock network with RC delay greater than

DESCRIPTION: Nets in the clock network with RC delay greater than

1. G_MAX_TRANS_PROFILING_VIOL_RPT gvar if it is defined

Rule uses follwoing Caliber global limits:

How rule works:

PROBLEM: Big miscorrelation causes delay in rule conversion

1. G_MAX_TRANS_PROFILING_VIOL_RPT gvar if it is defined

Rule uses follwoing Caliber global limits:

How rule works:

PROBLEM: Big miscorrelation causes delay in rule conversion

FIX ADVICE: The min margin needs to be fixed

FIX ADVICE: The min margin needs to be fixed

- Open the DC GUI

- Type the following in the design vision commandline

set pin {/full/path/pin/reported/in/duet}

set input_pin_collection \[all_fanin -to \$pin -flat\]

- Click on the "Create schematic of selected objects" button in design vision

- Open the DC GUI

- Type the following in the design vision commandline

set pin {/full/path/pin/reported/in/duet}

set input_pin_collection \[all_fanin -to \$pin -flat\]

- Click on the "Create schematic of selected objects" button in design vision

FIX ADVICE: Custom chopper needs to be removed

FIX ADVICE: Custom chopper needs to be removed

FIX ADVICE: Custom chopper needs to be removed

FIX ADVICE: Custom chopper needs to be removed

FIX ADVICE: Custom chopper needs to be removed

PROBLEM: This is a power wasting configuration.

FIX ADVICE: Move the enable up to the clock tree.

PROBLEM: This is a power wasting configuration.

FIX ADVICE: Move the enable up to the clock tree.

PROBLEM: This is a power wasting configuration.

FIX ADVICE: Move the enable up to the clock tree.