IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO.
1, JANUARY 2017
Front-End Isolated Quasi-Z-Source DC–DC
Converter Modules in Series for High-Power
Photovoltaic Systems—Part I: Configuration,
Operation, and Evaluation
Yushan Liu, Member, IEEE, Haitham Abu-Rub, Senior Member, IEEE, and Baoming Ge, Member, IEEE
Abstract—A quasi-Z-source modular cascaded converter
(qZS-MCC) is proposed for dc integration of high-power
photovoltaic (PV) systems. The qZS-MCC comprises
series-connected front-end isolated qZS half-bridge (HB)
dc–dc converter submodules (SMs). With the front-end
isolation, the qZS-MCC achieves high-voltage dc capability,
while maintaining modularity and PV panel grounded. The
post-stage qZS-HB handles the PV voltage and power
flows, dc-link voltage balance, and output-series power
integration. Whereas, the front-end isolation converters of
all SMs perform a constant duty cycle, lowing the control
complexity. There is no double-line-frequency power
flowing through the dc-side PV panels, qZS inductors, and
qZS capacitors in the qZS-MCC, so small qZS impedance is
possible compared to the existing qZS cascaded multilevel
inverter. The configuration, operating principle, power loss
evaluation, and passive components design of the pro-
posed system are investigated in this part of the paper. The
system control, modeling, and corresponding verifications
are stated in Part II of this paper.
Index Terms—DC–DC power conversion, galvanic isola-
tion, photovoltaic power system, quasi-Z-source converter.
I. INTRODUCTION
OWADAYS, the ever-increasing installed capacity of
N large-scale photovoltaic (PV) power plants, ranging from
few hundreds of kilowatts (kWs) up to several hundreds of
megawatts (MWs), has driven the research and development
of utility PV converter topologies moving toward multilevel
structure. Such structure is capable of delivering better har-
monic spectra, lower weight of filtering components, and higher
power capacity with low-voltage low-power devices [1]–[3].
The quasi-Z-source cascaded multilevel inverter (qZS-CMI) has
Manuscript received August 19, 2015; revised December 18, 2015;
accepted February 2, 2016. Date of publication August 10, 2016; date
of current version December 9, 2016. This work was made possible
by NPRP-EP Grant no. X-033-2-007 from the Qatar National Research
Fund (a member of Qatar Foundation). The statements made herein are
solely the responsibility of the authors.
Y. Liu and H. Abu-Rub are with the Department of Electrical and
Computer Engineering, Texas A&M University at Qatar, Qatar Founda-
tion, Doha 23874, Qatar (e-mail: yushan.liu@qatar.tamu.edu; haitham.
abu-rub@qatar.tamu.edu).
B. Ge is with the Department of Electrical and Computer Engineer-
ing, Texas A&M University, College Station, TX 77843 USA (e-mail:
baomge@gmail.com).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2016.2598673
0278-0046 © 2016 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution
requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
347
spurred growing attention in PV applications recently [4]–[9].
Xue et al. [4] presented the feasibility and evaluation of qZS-
CMI for MW-scale PV power systems; Zhou et al. [5] developed
the design criterion of the qZS-CMI for module-integrated PV
converter when using the wide bandgap power device; Liu et al.
[6]–[8] explored control methods of qZS-CMI-based PV power
system, fulfilling the distributed maximum power point track-
ing (MPPT), independent dc-link voltage balance, and grid-tie
power injection; and the battery energy storage was modularly
combined to compensate the PV power in [9]. In common, the
qZS-CMI accomplished features of:
1) the single-stage qZS H-bridge inverter modules indepen-
dently achieving dc-link voltage balance and dc–ac power
conversion;
2) the high reliability of power devices benefiting from the
short-through feasibility;
3) the direct connection of medium-voltage (MV) grid with-
out the bulky, costly, and lossy line-frequency (LF) trans-
former that the central inverter used;
4) the distributed MPPT and low harmonic spectra;
5) one-third reduction of the module number and efficiency
enhancement with respect to the traditional CMI; and
6) the simple circuit and control compared to the two-stage
CMI, where a dc–dc converter was embedded into each
H-bridge module [10]–[12].
However, the double-line-frequency (DLF) power oscillates
at the dc link of each qZS-CMI module and causes DLF ripple
on qZS inductor currents and capacitor voltages [5], [6]. Con-
tributions have been dedicated to mitigate the undesired DLF
ripple in the following categories:
1) a passive way utilized qZS inductance and capacitance
to buffer the DLF voltage and current ripple within en-
gineering tolerant ranges [5], [6], [13], but large qZS
impedance values were resulted despite of using wide
bandgap devices at an ultra-high switching frequency [5],
which faced challenges with size, cost, power derating,
and reliability for high-power applications of qZS-CMI
PV systems [13];
2) a hybrid pulse width modulation (PWM) made the dc-
link voltage envelope cope with the ac voltage, thus to
not limit the dc-link DLF voltage ripple while reducing
the qZS impedance [14], whereas, a large capacitor has
to be mounted at PV terminal to prevent the ripple power
from propagating to PV panels;
348 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 1, JANUARY 2017

3) ripple reduction methods have been explored to minimize

the qZS impedance values [15], [16], leading to compli-
cated control design;
4) an active power filter (APF) integrated single-phase qZSI
stored the dc-side DLF power to APF’s LC branch [17],
but which will inevitably increase complexity and com-
ponent counts in building the qZS-CMI.
In view of PV’s natural dc and distributed characteristics,
the modular multilevel converter (MMC) was developed for dc
collection of high-power PV systems, expecting to minimize the
power conversion stages, reduce the power loss on transmission
lines, and improve the efficiency [18]–[20]. Whereas, due to the
PV-panel insulation demand that is within one kilovolt (kV),
the PV panels in series forming the dc link of dc–ac part of the
MMC has restricted dc-bus voltage that is far from the utility grid
voltage level [21]. A dc–dc MMC overcomes such limitation by
coupling the high-frequency (HF) isolated converter into the
front end of each half-bridge (HB) PV SM in [22]. However,
both isolation and output-stage converters require independent
control methods and gating signals, which will significantly
increase the burdens of control, hardware resources, and costs
with the rise of dc-bus voltage level.
This paper proposes a qZS modular cascaded converter (qZS-
MCC) for high-power PV systems to overcome the above de-
fects. The qZS-MCC is a series connection of front-end isolated Fig. 1. Configuration of the qZS-MCC PV power system integrated into
qZS-HB dc–dc converter SMs. The front-end isolation ensures dc collection grid. (a) SM topology of the front-end isolated qZS-HB dc–
dc converter, (b) system configuration with a dc–ac MMC interfacing with
the PV panel isolating from the grid and safely grounded. In utility grid.
comparison with the qZS-CMI, there is no DLF ripple power
flowing through the dc-side PV panels, qZS inductors, and qZS
capacitors in the qZS-MCC, so low impedance values are pos- The front-end isolation converter of each SM insulates the
sible. The qZS-HB distributes shoot-through events into the PV array from the series output, so that an HV is achieved.
HB dc–dc converter, while no longer demanding for the shoot- Here, the HB isolation converter is performed due to the less
through combination as the qZS inverter or back-end isolated power devices and high-power applicability [27]–[29]; the H-
qZS dc–dc converter [6], [23]–[26]. In addition, a unified duty bridge isolation converter could also be an option [11], [12]. As
cycle is executable for all front-end isolation converters, so low Fig. 1 (a) shows, the front-end isolation comprises an HB con-
complexity of control is achieved with respect to the existing verter, an HF transformer TH , and a voltage doubler. The primary
dc–dc MMC while maintaining the high voltage (HV). of TH connects between center tapes of the HB switches Sf k 1
The qZS-MCC demonstrates free of DLF ripple, dc distri- and Sf k 2 , and capacitors CH 1 and CH 2 ; the secondary of TH
bution/transmission of PV power, and HV output with unified links with the voltage doubler, comprising two diodes DH 1 and
front-end galvanic isolation, which has not yet been disclosed. DH 2 , and two capacitors CH 3 and CH 4 . The two inductors L1
This paper (Part I) is organized as follows. Section II addresses and L2 , two capacitors C1 and C2 , and one diode D1 constituted
the system configuration and operation; Sections III and IV impedance network is coupled between the voltage doubler and
present the major passive components design and the power the output-side HB, with switches Sbk 1 and Sbk 2 , forming the
loss evaluation, respectively; Section V discusses definition of post-stage qZS-HB converter. The suffix f and b denote the front-
SM specifications; Section VI illustrates simulation and exper- end and post-stage HB, respectively; k ∈ {1, . . . , n} stands for
imental results; and finally, Section VII draws conclusion. the kth SM, with n for the number of total SMs.

II. QZS-MCC-BASED DC-INTEGRATED PV POWER SYSTEM B. Operating Principle of qZS-MCC

A. System Configuration
Fig. 1 shows the proposed qZS-MCC for dc collection of
high-power PV system. Fig. 1 (a) shows the front-end isolated
qZS-HB dc–dc converter SM. Fig. 1(b) shows the system con-
figuration, where series connection of those qZS-HB SMs con-
stitutes the qZS-MCC PV system. Several qZS-MCC-based PV
systems can be simply integrated at the HV dc terminal and
further interface with the utility grid through a dc–ac MMC.
Due to the voltage handling capability of qZS concept that
is sufficient for the 1–2 times PV voltage variation [4], a 1:1
turn ratio is applied to the transformer TH , so as to small size.
A unified duty cycle of D0 = 0.5 for upper switches Sf k 1 and
1 − D0 for lower ones Sf k 2 , k ∈ {1, . . . , n}, is performed to
the front-end HB of all SMs. Then, the qZS-HB input voltage
and current are [27]
vink = vPV k /D0 = 2vPV k , iink = D0 iPV k = iPV k /2 (1)
LIU et al.: FRONT-END ISOLATED QUASI-Z-SOURCE DC–DC CONVERTER MODULES IN SERIES FOR HIGH-POWER PHOTOVOLTAIC
Fig. 2. Operating illustration by using two SMs formed qZS-MCC.
(a) Simplified topology, (b) typical waveforms.
where vPV k and iPV k denote the PV voltage and current of the
kth SM.
The front-end isolation converter works at the constant 0.5
duty cycle independent of the post-stage qZS-HB. With the volt-
age doubler, the HB isolation converter boosts the PV voltage
and operates as a dc voltage source supplying the post-stage
qZS-HB, as (1) shows. The HB isolated dc–dc converter has
been widely studied in literatures, such as [27]–[29]. Therefore,
the principle, analysis, and design of the front-end HB isolation
converter are not addressed in this paper. A two-SMs qZS-MCC
is simplified into Fig. 2(a) by equivalizing PV voltages and cur-
rents to the secondary of TH , to illustrate the operation and
power loss estimation of the post-stage qZS-HB.
Fig. 2(b) shows typical waveforms of the two qZS-HB SMs in
cascade. A 2π/n phase shift between carriers aims at interleaving
of adjacent SMs. The sawtooth carrier is performed to avoid
additional switching introduced by shoot-through events [5]. It
also introduces soft switching to the lower switches Sbk 2 , which
is analyzed in Section IV.
In one control period Ts , each qZS-HB SM possesses the
active state, traditional zero state, and shoot-through state.
They are termed as ACT, ZERO, and ST, and shown in
349
Fig. 3. qZS-HB SM1 in the (a) ACT, (b) ZERO, and (c) ST states.
Fig. 3(a)–(c), respectively, by using SM1 . The carrier vC ar r 1
of SM1 lower than its modulation index M1 determines the
ACT, during which the upper switch Sb11 is ON while the lower
one Sb12 is OFF; the output voltage vo1 is high with the value of
dc-link peak voltage, as Figs. 2(b) and 3(a) show. There are
vDC1 = vo1 = v̂DC1 = vC 1 + vC 2 , iDC1 = io ,
iD 1 = iin1 + iL 2 − io ,
iC 1 = iin1 − io , iC 2 = iL 2 − io , vL 1 = vin1 − vC 1 ,
vL 2 = −vC 2 (2)
where vDC1 and iDC1 denote the dc-link voltage and current of
SM1 ; iD 1 denotes the qZS diode current of SM1 ; iin1 denotes
the qZS-network input current, i.e., qZS inductor-L1 current
of SM1 ; iL 2 denotes the qZS inductor-L2 current; vL 1 and vL 2
denote the voltages of qZS inductors L1 and L2 of SM1 ; vC 1 and
iC 1 denote the qZS capacitor-C1 voltage and current of SM1 ;
vC 2 and iC 2 denote the qZS capacitor-C2 voltage and current
of SM1 .
In the ZERO state, when vC ar r 1 is higher than M1 , the an-
tiparallel diode of Sb12 freewheels, as Fig. 3(b) shows. The
voltages and currents are as follows:
vDC1 = v̂DC1 = vC 1 + vC 2 , vo1 = 0, iDC1 = 0,
iD 1 = iin1 + iL 2 ,
iC 1 = iin1 , iC 2 = iL 2 , vL 1 = vin1 −vC 1 , vL 2 = −vC 2 . (3)
In addition, once vC ar r 1 is higher than 1–D1 , where D1
denotes the ST duty cycle of SM1 , the ST occurs; both Sb11 and
Sb12 turn ON; the dc-link voltage is zero, as Figs. 2(b) and 3(c)
350 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 1, JANUARY 2017

show. The voltages and currents are as follows: dc-link peak voltage of all SMs will be
vDC1 = vo1 = 0, iDC1 = iin1 +iL 2 , iD 1 = 0, iC 1 = −iL 2 ,
Vdc  n  vinkn

iC 2 = −iin1 , vL 1 = vin1 + vC 2 , vL 2 = vC 1 . (4) VDC =

Mt
, Mt = Mk =
Vok
. (10)
k =1 k =1
The qZS-HB does not contribute the output voltage in
the ZERO and ST. Hence, the qZS-MCC’s output voltage is In the qZS inverter SMs of the qZS-CMI [6] and the back-end
summarized as isolated qZS dc–dc converter, where an H-bridge isolation con-
n n verter following the qZS network [23]–[26], modulation signal
vo = vok = Sk v̂DCk (5) comparing with the carrier obtains the gating signals for ACT;
k =1 k =1 while the carrier comparing with 1 − Dk and Dk − 1 imple-
with its average dc value of ments the ST. Then, one extra register of the microcontroller or
comparator chip is demanded for each converter bridge to com-

n 
n
Vdc = Vok = Mk v̂DCk (6) bine the gating signals from the ACT and ST [24]. Whereas,
k =1 k =1 for the qZS-HB of qZS-MCC, from Fig. 2 (b), the 1 − Dk and
Mk configured to one register is able to produce the combined
where Sk denotes the switching function of the kth SM, Vok
gating signal with ACT and ST, avoiding the ST combination.
denotes the average dc output voltage of the kth SM, and Mk
In addition, with the constant and unified duty cycle of all
denotes the ACT duty cycle and is named as the modulation
front-end isolation converters, one PWM register comparing
index of the kth SM, k ∈ {1, . . . , n}.
with D0 = 0.5 is sufficient to all switches Sf k 1 and Sf k 2 ,
The dc-link peak voltage, and the average voltages of capac-
k ∈ {1, . . . , n}. In this way, n + 1 registers are able to op-
itors C1 and C2 of the kth SM are, respectively [6],
erate the proposed qZS-MCC with n SMs in cascade. Com-
1 paring with the dc–dc MMC formed by the two-stage dc–dc
v̂DCk = vink ,
1 − 2Dk converter SMs without a qZS network [22], 3 × n registers
1 − Dk are required because of independent control of the front-end
VC 1k = vink , isolation converter and the output-stage HB converter for each
1 − 2Dk
SM. It is obvious that the qZS-MCC decreases the control com-
Dk putation and reduces almost two-third gating signals of exist-
VC 2k = vink (7)
1 − 2Dk ing dc–dc MMC, demonstrating the low complexity of control
where Dk denotes the ST duty cycle of the kth SM. and realization.
From (5) and Fig. 2 (b), the qZS-MCC’s output voltage vo in- In summary, the most important features of the proposed
cludes pulses in the amplitude of one SM’s dc-link peak voltage, qZS-MCC PV system compared to the qZS-CMI [4]–[9] and
producing charging-discharging events to the output current io the dc–dc MMC [22] based PV counterparts are as follows.
through the filter inductor LF . The qZS inductors charge in the 1) The qZS-MCC PV system inherits the two counterparts
ST and discharge in the non-ST of each qZS-HB, as the inductor in terms of modularity, distributed MPPT, flexibility, as
voltages vL 1 and vL 2 in (2)–(4) as well as typical waveforms of well as HV capability without bulky LF transformer.
iin1 and iin2 in Fig. 2 (b) show. 2) Different from the qZS-CMI, there is no DLF pulsating
According to the power balance, the kth qZS-HB has power flowing through dc-side qZS network in the qZS-
MCC. Hence, the qZS-MCC can achieve low values and
vink Iink = Vok Io = Mk v̂DCk Io (8) small size of qZS inductance and capacitance especially
where Iink denotes the average current of iink ; Io denotes the with silicon carbide (SiC) power devices.
average value of qZS-MCC’s output current io . From (6) to (8), 3) Unlike the existing dc–dc MMC, no closed-loop control
the qZS-HB input current of the kth SM has the relationship is demanded for the front-end isolation converters of the
with the output current of qZS-MCC. The shoot-through duty cycles and modula-
tion indexes of post-stage qZS-HB are able to control
Mk the PV power and voltage, balance dc-link voltages, and
Iink = Io . (9)
1 − 2Dk achieve HV-side dc integration, with low complexity in
control and realization.
C. Analysis of Control Complexity and Features
Even though Part II of the paper details the system closed-
loop control, it is worth noticing that the modulation index Mk III. PARAMETERS DESIGN OF MAJOR PASSIVE COMPONENTS
and the ST duty cycle Dk of the kth SM’s post-stage qZS-HB The qZS inductance, qZS capacitance, and output filter induc-
are two control variables to adjust the SM’s PV-array voltage tance should be designed in the qZS-MCC. From (2)–(4) and
and power flows as well as the total power of the qZS-MCC PV Fig. 3, the two qZS inductors charge in the ST at the capacitor-
system. In the open-loop analysis, the PV-array current is kept C1 voltage vC 1 and discharge in the ACT and ZERO at the
at its maximum power point (MPP) value at the rated power, capacitor-C2 voltage vC 2 .
which is a common approach because the PV features behave The equal inductances L1 and L2 and the equal capacitances
likewise to a current source [25]. Hence, from (6), the balanced C1 and C2 are selected due to the reasons that:
LIU et al.: FRONT-END ISOLATED QUASI-Z-SOURCE DC–DC CONVERTER MODULES IN SERIES FOR HIGH-POWER PHOTOVOLTAIC 351

1) the L1 = L2 and C1 = C2 will lead to the same steady-

state capacitor currents iC 1 and iC 2 , and the same steady-
state inductor currents iin1 and iL 2 ;
2) the L1 = L2 and the same behavior of iin1 and iL 2 benefit
to reducing the size and weight of inductors in a high-
power SM by building one coupled inductor;
3) it will enable easier design in terms of reducing the sys-
tem order of control design and simplifying the control
parameters design; and
4) the C1 = C2 will have the maximum total capacitance
during the ST since C1 and C2 are in series to support
the dc-link voltage in the ST. Resultantly, at the steady
state, there are iin1 = iL 2 and iC 1 = iC 2 at L1 = L2 and
C1 = C2 .
The charging-discharging behavior of the inductors alternates
one time in each control cycle. Thus, from (7), the qZS induc-
tance and capacitance to limit the switching-frequency ripple of
inductor current and dc-link voltage are, respectively
vC 1 ΔT vC 1 Ts Dm ax
L1 = L2 = =
ΔiL (Pm /vin,m in )riL
Dm ax (1 − Dm ax )vin,m
2
in
Fig. 4. Typical voltage and current waveforms of qZS-HB power
= (11) devices.
fs Pm riL (1 − 2Dm ax )
2Iink ΔT 2(Pm /vin,m in )Ts Dm ax the collector-emitter voltages of the upper and lower switches,
C1 = C2 = =
Δv̂DC rv dc VDC,m ax respectively; iT1 and iT2 represent the IGBT currents of the
2Pm Dm ax (1 − 2Dm ax ) upper and lower switches; iSD2 represents the free-wheeling
= 2 (12) current of antiparallel diode in the lower switch; and iD1 repre-
fs vin,m in rv dc
sents the current flowing through the qZS diode D1 . There is no
where riL denotes the peak-to-peak ripple ratio of inductor current through the antiparallel diode of the upper switch. Note
current, and rv dc denotes that of dc-link voltage; vin,m in = that suffix of the kth SM is excluded in the following to make
2vPV ,m in denotes the minimum input voltage of qZS network. power loss equations legible, and there is iin = iL 2 in (2)–(4),
As Fig. 2(b) shows, the ST duty cycle is distributed in the as addressed in Section III.
ZERO of each qZS-HB, hence, the Dk is limited to 1 − Mk . In the ACT, as Figs. 3(a) and 4, and (2) show, the Sb11 is ON
Besides (7) and (10), the minimum modulation index Mm in , the and Sb12 is OFF; the current iT1 equals to the qZS-MCC’s output
maximum dc-link peak voltage VDC,m ax , and the maximum ST current io ; the qZS diode is ON with the current iD1 of 2 iin − io .
duty cycle Dm ax are given as, respectively, In the ZERO, the antiparallel diode of Sb12 is freewheeling for
the qZS-MCC’s output current io , and the qZS-diode current
vin,m in Vdc
Mm in = , VDC,m ax = , Dm ax = 1 − Mm in . iD1 equals to 2iin , as Fig. 3(b) and (3) as well as iSD1 and iD1 in
Vok nMm in Fig. 4 show. In the ST, as Fig. 3(c) and (4) show, the qZS diode
(13)
is blocked due to negative voltage; Sb11 and Sb12 are ON, with
The output filter inductor has voltage drop of nVDC − Vo .
currents 2iin and 2iin − io , respectively.
Thus, the required inductance to filter the switching-frequency
From Fig. 4, the switching event of the qZS-HB power devices
ripple of output current io should meet
is summarized as follows:
(nVDC − Vo ) 1) Sb11 turns ON and OFF one time in each control cycle,
LF ≥ (14)
2nfs rio Io where the switching current are io and 2iin , respectively,
and the switching voltage is the dc-link peak voltage VDC ;
where rio denotes the peak-to-peak current ripple ratio.
2) the ON and OFF events of Sb12 are at the same voltage
of VDC , but with zero-current switching (ZCS) at the
IV. POWER LOSS EVALUATION turn-ON event and the current of 2iin − io at the turn-OFF
The qZS-HB introduces shoot-through behavior to the post- event;
stage HB. The power loss includes the HB switching loss, HB 3) the antiparallel diode of Sb12 holds zero-voltage switch-
conduction loss, qZS diode loss, and qZS inductors and ca- ing (ZVS) at the reverse recovery event;
pacitors loss. Here, the popular insulated-gate bipolar transistor 4) the reverse recovery loss of qZS diode D1 occurs at
(IGBT) is used as example to illustrate the power loss analysis. the current of 2iin and voltage of VDC . It is noticeable
Fig. 4 shows typical voltage and current waveforms of power that there is no extra switching when performing ST;
devices for one qZS-HB. The Sb11 and Sb12 denote the ON–OFF moreover, the ZCS for transistor and ZVS for its antipar-
state of the upper and lower IGBTs; uCE1 and uCE2 represent allel diode in the lower switch are obtained.
352 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 1, JANUARY 2017

A. HB Switching Loss where ED REC denotes the reverse recovery energy of D1 ; Vref z ,
and Iref z denote the reference of switching voltage and current.
From the above summary, the qZS-HB switching loss is com-
puted by From the conducted current of qZS diode D1

 Ts 2iin − io , d(t) = M
1 fs VDC iD 1 (t) = (19)
PSW = [io EOFF + 2iin EON + (2iin − io ) 2iin , d(t) = 1 − M − D
Ts 0 Vref Iref
we can obtain the conduction loss of qZS diode D1 as follows:
EOFF ] dt
2Iin fs VDC PCON,D 1 = [2Iin (1 − D) − M Io ] VF O
= (EON + EOFF ) (15)  
Vref Iref + (2Iin − Io )2 + 4Iin2
rF (20)
where fs denotes the switching frequency; EON and EOFF
denote the turn-ON and turn-OFF energy, respectively; Vref and where VF O denotes the forward voltage drop of the qZS diode
Iref denote the reference of switching voltage and current. and rF denotes the conduction resistance.

B. HB Conduction Loss D. Power Loss of qZS Inductors and Capacitors

The conduction loss of a switch is generally expressed by The power loss of qZS inductors includes core loss and copper
loss. The core loss depends on the magnetic core. The magnetic
2
PCON = IAVE VON + IRM S RON , components can be selected according to that of a traditional
 Ts dc–dc converter [30], once the qZS inductance value is deter-
1
IAVE = iCON (t)d(t)dt, mined by (11). The copper loss of the two qZS inductors can be
Ts 0
calculated by
 Ts
2 1 2
IRM S = i2CON (t)d(t)dt (16) PLcopp er = 2Iin rL (21)
Ts 0
where rL denotes the parasitic resistance of each qZS inductor.
where VON denotes the threshold voltage of an IGBT or antipar-
The qZS-HB capacitor current will be iin − io in the ACT,
allel diode; RON denotes the conduction resistance of an IGBT
–iin in the ST, and iin in the ZERO, as Fig. 3 shows. Thus, the
or diode; IAVE and IRM S denote the average and RMS current
RMS current of each qZS capacitor is computed by (22), shown
through the IGBT or diode; iCON (t) denotes the conduction
at the bottom of the page.
current of the IGBT or antiparallel diode; d(t) denotes the duty
Then, the power loss of the two qZS capacitors is
cycle function.
From the aforementioned analysis, the conducted current 2
PCZ = 2ICZ resr (23)
iCON (t) and duty cycle for the IGBT and its anti-parallel diode
of the upper and lower switches are written as where resr denotes the equivalent series resistance of each qZS
 capacitor.
i d(t) = M  
iT 1 (t) = o , iT 2 (t) = 2iin − io d(t) = D ,
2iin d(t) = D V. SM SPECIFICATIONS DEFINITION
 
iS D 2 (t) = io d(t) = 1 − M − D . (17) The power devices’ switching frequency is of critical impor-
tance for passive component values, as (11)–(14) show. The
Therefore, the HB conduction loss can be calculated through
1.2-kV/193-A all SiC HB power module CAS120M12BM2,
(16) and (17).
which is appropriate for high switching frequency and high
temperature, is therefore adopted as a design example. Accord-
C. qZS Diode Power Loss ingly, the 600-V/60-kW qZS-HB SM is defined in consideration
According to the analysis, the reverse recovery power loss of of the voltage and current stresses.
qZS diode D1 is Fig. 5 shows the HB conduction loss, HB switching loss, qZS
 Ts diode loss, and total loss of power devices versus input volt-
1 fs VDC age vin and switching frequency fs , computed by power loss
PREC,D 1 = [2iin ED REC ] dt
Ts 0 Vref z Iref z analysis of (15)–(20). From datasheets of CAS120M12BM2,
2Iin ED REC fs VDC the electrical parameters for evaluating the power loss are:
= (18) EON = 1.7 mJ and EOFF = 0.4 mJ at Vref = 600 V and
Vref z Iref z

 Ts  
1
ICZ = (iin − io )2 · M + (−iin )2 · D + (iin )2 · (1 − M − D) dt
Ts 0

= (Iin )2 − 2Iin Io M + (Io )2 M (22)

LIU et al.: FRONT-END ISOLATED QUASI-Z-SOURCE DC–DC CONVERTER MODULES IN SERIES FOR HIGH-POWER PHOTOVOLTAIC 353

Fig. 6. HB conduction loss, HB switching loss, and qZS diode loss

versus the input voltage of the qZS-HB at the defined specifications.
is obtained as 300 V from (1). It is known that the PV-array
voltage has a 1∼2 variation range. Whereas, the lowest MPP
voltage, denoted as Vlow , is normally not exact half of the Vh .
Usually Vlow = (0.525 ∼ 0.64) × Vh from commercial high-
power PV inverters. Hence, Vlow = 0.58 × 300 V = 175 V is
performed, so as to a 175∼300 V MPP voltage range, which
requires 350∼600 V qZS-HB input voltage when the H-bridge
isolation converter is used. According to Vh and 60-kW rated
power, the PV array is configured based on the MPP voltage
Fig. 5. Power losses of qZS-HB devices versus input voltage v in and
switching frequency fs . (a) HB conduction loss, (b) HB switching loss, and current of the PV panel model in our study. In summary, the
(c) qZS diode loss, and (d) total loss of power devices. PV panel model, the PV array configuration, the highest MPP
voltage, the type of isolation converter, and the power devices
TABLE I should be taken into account to determine the rated voltage of
SPECIFICATIONS OF DEFINED 60-KW SM
front-end and post-stage converters in practical design.
With vin,m in = 350 V and Vok = 600 V, then Dm ax = 0.33
Parameters Values
from (13). At inductor current and dc-link voltage ripple limits
Solar panel MSX-60 of riL = 20% and rvdc = 1%, with fs = 80 kHz, the resultant
Maximum power point power 60 W qZS capacitance and inductance are 137 μF and 83 μH, respec-
Maximum power point voltage 17.1 V
Maximum power point current 3.5 A tively. Coupling the two qZS inductors will achieve the compact
PV array per qZS SM 18 × 57
size with 42 μH inductance. The low qZS capacitance value also
Maximum power, P m 60 kW
demonstrates the justification of performing film capacitors,
Solar panels in series per string 18 panels resulting in higher reliability and longer life time than elec-
PV strings in parallel per array 57 strings trolytic capacitor banks. Whereas, large qZS impedance values
MPPT voltage range of the PV array, v P V k 175∼300 V
are obliged to mitigate the dc-side DLF ripple of single-phase
HB isolation converter qZS inverter modules in the qZS-CMI, if without special control
Filter inductance, L H 20 μH or extra compensation circuits [6], [13]. For instance, the 4.7-
Turn ratio of transformer T H 1:1
Capacitance C H 1 , C H 2 , C H 3 , and C H 4 25 μF
mF qZS capacitance and 3.3-mH qZS inductance are needed for
Switching frequency of front-end HB 80 kHz a 21-kW single-phase qZS inverter to restrict the dc-link DLF
qZS network ripple within 5% [13], inevitably leading to low power density.
qZS-HB input voltage range, v i n k 350∼600 V Fig. 6 shows the estimated power loss of the defined
Average dc output voltage of one SM, V o k 600 V 60-kW qZS-HB SM, which presents a 98.5% efficiency at the
Switching frequency of post-stage HB 80 kHz full power. Through soft switching to alleviate the power loss of
qZS inductance, L 1 and L 2 42 μH coupling
qZS capacitance, C 1 and C 2 150 μF front-end HB isolation converter, a highly efficient qZS-MCC
Filter inductance, L F 300 μH system is achievable.

VI. SIMULATION AND EXPERIMENTAL INVESTIGATIONS

Iref = 120 A. Associated SiC qZS diode has ERECZ = 0.5 mJ
A qZS-MCC PV system in series of four 60-kW front-end iso-
at Vref z = 1200 V and Iref z = 120 A. From Fig. 5, it can be
lated qZS SMs is simulated in PSIM software, which presents a
seen that the switching frequency fs is lower, the HB switch-
2.4-kV/240-kW system. A resistive load RL , as Fig. 2(a) shows,
ing loss and qZS diode loss are smaller; on the contrary, the 2
is adjusted by RL = Vdc /Po to keep a constant series-output
lower fs is, the value, size, and cost of passive components will
dc-bus voltage Vdc = 2.4 kV when the system total power Po
be higher. Taking tradeoffs of power devices’ loss and passive
changes.
components’ values, an 80-kHz switching frequency is selected.
Table I lists system specifications according to the design.
Note that at the 600-V average dc output voltage of the qZS-HB
A. Simulation Results
SM, the maximum qZS-HB input voltage from the front-end First, all four qZS-HB SMs work at the same condi-
converter is also defined as 600 V to maximize the voltage tion of PV-array voltage vPV k = 175 V and PV-array current
utilization. Then, the highest PV MPP voltage, denoted as Vh , iPV k = 200 A, with D0 = 0.5 for the front-end HB. Then,
354 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 1, JANUARY 2017
Fig. 7. Simulation results of qZS-MCC-based PV power system at the
175-V PV-array voltages: SM1 ’s PV-array current iP V 1 and qZS-HB input
current iin 1 ; SM1 ’s PV-array voltage v P V 1 , qZS-HB input voltage v in 1 ,
and dc-link voltage v D C 1 ; SM1 ’s qZS capacitor voltages v C 1 and v C 2 ;
qZS-MCC’s output voltage v o and dc-bus voltage V d c ; and load current
io .
the kth qZS-HB modulation index Mk = 0.583, input voltage
vink = 350 V, input current Iink = 100 A, dc-link peak voltage
VDC = 1029 V, ST duty cycle Dk = 0.33, and the qZS-MCC’s
output current Io = 58.3 A, calculated from (7) to (10).
Fig. 7 shows simulation results of the SM1 ’s PV-array current
iPV1 and qZS-HB input current iin1 ; SM1 ’s PV-array voltage
vPV1 , qZS-HB input voltage vin1 , and dc-link voltage vDC1 ;
SM1 ’s qZS capacitor voltages vC 1 and vC 2 ; qZS-MCC’s output
voltage vo and dc-bus voltage Vdc ;as well as load current io .
Fig. 8 shows the SM1 and SM2 ’s qZS-HB input currents iin1
and iin2 , SM1 ’s dc-link voltage vDC1 and output voltage vo1 ,
SM2 ’s dc-link voltage vDC2 and output voltage vo2 , qZS-MCC’s
output voltage vo and dc-bus voltage Vdc , as well as qZS-MCC’s
output current io in two control cycles.
From Fig. 7, it can be seen that a 2.4-kV series-output voltage
is achieved, even though all SMs work at the 175-V low PV-array
voltage. This demonstrates that the proposed system can have a
constant HV output (over the one kV limit) while handling wide
PV voltage variations. In addition, the SM’s PV-array voltage,
qZS inductor current, and qZS capacitor voltage are constant
without low-frequency ripple that is presented in the qZS-CMI;
while low qZS inductance and capacitance are applied to only
filter the switching frequency ripple.
From Fig. 8, it can be seen that each qZS-HB operates at its
own states independently. The qZS inductors are charging in
the ST and discharging in the non-ST, with the peak-to-peak
current ripple within 20%. In addition, the qZS-MCC’s output
voltage vo has pulses in the amplitude of single-module dc-link
peak voltage VDC and with frequency of four-times switching
Fig. 8. Results in two control cycles when all SMs are at the same
175-V PV-array voltages: SM1 and SM2 ’s qZS-HB input currents iin 1
and iin 2 ; SM1 ’s dc-link voltage v D C 1 and output voltage v o 1 ; SM2 ’s dc-
link voltage v D C 2 and output voltage v o 2 ; qZS-MCC’s output voltage v o
and dc-bus voltage V d c ; and load current io .
frequency fs , as a result of the 4fs -times charging-discharging
event to the output current io . The average values of qZS-HB
input currents, qZS-MCC’s output current, and dc-bus voltage
in simulation results are in accordance with the calculation.
Further test is carried out by setting the SM1 with PV-
array voltage of vPV1 = 230 V, while all the other SMs are at
vPV k = 240 V. Then, from (7) to (10), the SM1 ’s qZS-HB input
voltage vin1 = 460 V and modulation index M1 = 0.767; and
the others are vink = 480 V and Mk = 0.8, k∈ {2, 3, 4}. In this
case, the balanced dc-link peak voltage becomes VDC = 758 V
from (10); thereby, the shoot-through duty cycle of SM1 is
D1 = 0.1965 and Dk = 0.1833 for the other three SMs; the
qZS-MCC’s output current Io = 79 A.
Fig. 9 shows SM1 ’s vPV1 and vin1 , SM2 ’s vPV2 and vin2 ,
qZS-MCC’s output voltage vo and dc-bus voltage Vdc , as well
as load current io . It can be seen that the qZS-HB input voltage
doubles the PV voltage, respectively, at the constant 0.5 duty
cycle of front-end HB.
Fig. 10 shows simulation results in two control cycles for iin1
and iin2 , vDC1 and vo1 , vDC2 and vo2 , vo and Vdc , as well as
io , respectively. From Figs. 9 and 10, it can be seen that even
though the input voltage vin1 of SM1 ’s post-stage qZS-HB is
lower than the others, the smaller duty cycle of the ACT and
larger duty cycle of the ST in the SM1 than those in the SM2
produce a same dc-link peak voltage between the SMs. Thus, the
pulse amplitude of qZS-MCC’s output voltage vo are balanced
and a low peak-to-peak current ripple of io is obtained, as vo
and io show in the two figures.
In summary, Figs. 7–10 demonstrate that the qZS-MCC is
not like the qZS-CMI and there is no DLF power ripple flowing
LIU et al.: FRONT-END ISOLATED QUASI-Z-SOURCE DC–DC CONVERTER MODULES IN SERIES FOR HIGH-POWER PHOTOVOLTAIC 355

Fig. 9. SM1 ’s PV-array voltage v P V 1 and qZS-HB input voltage v in 1 ;

and SM2 ’s v P V 2 and v in 2 ; qZS-MCC’s output voltage v o and dc-bus
voltage V d c ; and load current io when SM1 has different condition from
the others.
TABLE II
PROTOTYPE SPECIFICATIONS
Fig. 10. Results in two control cycles when SM1 has different condition
from the others: SM1 and SM2 ’s currents iin 1 and iin 2 ; SM1 ’s dc-link
Parameters Values voltage v D C 1 and output voltage v o 1 ; SM2 ’s dc-link voltage v D C 2 and
output voltage v o 2 ; qZS-MCC’s output voltage v o and dc-bus voltage
Rated power of one SM, P m 1 kW V d c ; and load current io .
qZS-HB input voltage range, v i n k 55∼100 V
Average dc output voltage of one SM, V o k 100 V
Total dc output voltage, V d c 200 V
Switching frequency of front-end HB 80 kHz
Switching frequency of post-stage HB 10 kHz
qZS inductance, L 1 and L 2 550 μH coupling
qZS capacitance, C 1 and C 2 680 μF
Filter inductance of qZS-MCC, L F 4.5 m H
Semiconductors Specifications
Diodes of D H 1 , D H 2 , and D 1 SiC diode, SCS230AE2, 650 V/30 A
Switches of S f k 1 and S f k 2 SiC MOSFET, CMF20120D, 1200 V/42 A
Switches of S b k 1 and S b k 2 Si-IGBT/SiC-diode co-pack,
GB100XCP12-227, 1200 V/100 A

through the dc-side qZS network and PV array of the qZS-MCC-

based high-power PV system, so that the low qZS impedance
is enough to handle the switching frequency ripple. In addition,
a high and scalable dc output voltage is fulfilled for the PV
system, with a constant duty cycle for all front-end isolation
converters.
B. Experimental Results
A 2-kW downscaled qZS-MCC prototype, consisted of
two front-end isolated qZS-HB SMs, is built as the proof-of-
concept, as shown in Fig. 11. Table II lists the specifications
of the prototype. The qZS inductance and capacitance values
are attained from (11) to (14). Each SM’s qZS network
contains the coupled inductor built on the AMCC-250 core.
The transformer of the front-end isolation converter is also a
coupled inductor, benefiting from the 1:1 turn ratio. The SiC
Fig. 11. Downscaled prototype.
power devices in Table II are employed to build the prototype.
Limited by the laboratory condition, Si-IGBT/SiC-diode
co-pack is employed in the post-stage qZS-HB, which causes
a low switching frequency of 10 kHz rather than 80 kHz. The
TMS320F28335-based DSP control board performs gating
signals. The front-end HB of SM1 and SM2 share one PWM
register of the DSP, with 0.5 duty cycle. Each post-stage
qZS-HB utilizes one register, as illustrated in Fig. 2(b).
The qZS-MCC is tested in two cases, two SMs have the
same operating condition, and two SMs operate in the different
356
Fig. 12. Steady-state experimental results of the two SMs at the same
condition. (a) The iP V 1 , iin 1 , v P V 1 , and v in 1 ; and (b) V d c , io , v o ,
and v o 1 .
conditions. The two separate dc voltage sources feed two SMs.
From (10), each SM’s power becomes proportional to its mod-
ulation index during the open-loop test, with the maximum cur-
rent. An adjustable resistive load is used to maintain the 200-V
dc output voltage when the total power varies. Figs. 12 and 13
show experimental results.
First, the two SMs of qZS-MCC work at vPV k = 30 V,
k ∈ {1, 2}. Then from (1) and (7)–(10), theoretically, the qZS-
HB input voltage vink = 60 V, input current Iink = 10 A, mod-
ulation index Mk = 0.6, dc-link peak voltage VDC = 167 V,
shoot-through duty cycle Dk = 0.32, output power Pok =
600 W, and the qZS-MCC’s output current Io = 6 A. The 33-Ω
load resistance and the 200-V dc-bus voltage are performed.
Fig. 12(a) shows steady-state results of SM1 ’s front-end input
current iPV1 , qZS-HB input current iin1 , front-end input voltage
vPV1 , and qZS-HB input voltage vin1 , which are identical to
SM2 in this case. Fig. 12(b) shows the qZS-MCC’s dc-bus
voltage Vdc , output current io , output voltage vo , and SM1 ’s
output voltage vo1 .
From Fig. 12(a), it can be seen that the iin1 is half of the iPV1 ,
while the vin1 doubles the vPV1 , matching (1) at the constant 0.5
duty cycle of the front-end isolation converter. From Fig. 12(b),
the qZS-MCC’s output voltage vo holds pulsed waveform with
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 64, NO. 1, JANUARY 2017
Fig. 13. Steady-state experimental results of the two SMs at differ-
ent conditions. (a) The iP V 1 , iin 1 , v in 1 , and v in 2 ; and (b) V d c , io , v o ,
and v o 1 .
the amplitude of one SM’s dc-link peak voltage and with the
frequency of two-times switching frequency of qZS-HB. That
pulse voltage introduces a charging-discharging behavior of the
filter inductor, and the output current io is smoothed. The iin1
and vin1 , as well as qZS-MCC’s output current io and dc-bus
voltage Vdc match the theoretical values.
Further test is carried out by using different voltages of the
two SMs, i.e., vPV1 = 37.5 V and vPV2 = 30 V. From (1), (7),
and (10), the SM1 and SM2 ’s qZS-HB input voltages are vin1 =
75 V and vin2 = 60 V, modulation indexes are M1 = 0.75 and
M2 = 0.6, shoot-through duty cycles are D1 = 0.247 and D2 =
0.298, respectively. Thereby, both of the two SMs’ dc-link peak
voltage become VDC = 148 V. Besides, the operating power of
the two SMs are Po1 = 750 W and Po2 = 600 W. Thus, the
qZS-MCC’s average current is Io = 6.75 A at the 200-V dc-
bus voltage, with the load resistance of 30 Ω. Fig. 13(a) shows
SM1 ’s front-end input current iPV1 , qZS-HB input current iin1 ,
qZS-HB input voltage vin1 , and SM2 ’s qZS-HB input voltage
vin2 . Fig. 13(b) shows the Vdc , io , vo , and vo1 in this case. From
Fig. 13(a), it can be seen that the qZS-HB input voltages vin1
and vin2 double the dc source voltages of their own SMs.
From the two SMs’ ACT intervals, ACT1 and ACT2 in
Fig. 13(b), it can be seen that the SM1 performs larger ACT
LIU et al.: FRONT-END ISOLATED QUASI-Z-SOURCE DC–DC CONVERTER MODULES IN SERIES FOR HIGH-POWER PHOTOVOLTAIC
Fig. 14. Calculated and tested efficiencies of the qZS-HB SMs in
prototype.
duty cycle than the SM2 , indicating the higher power seen from
(10). From vo1 and vo , the balanced dc-link peak voltages be-
tween the two SMs and the balanced pulse amplitude of vo are
achieved, even though the two SMs operate at different voltages
and powers, and the front-end converters keep a constant and
identical duty cycle.
In summary, Figs. 12 and 13 demonstrate the feasibility that
the modulation index and ST duty cycle of the post-stage qZS-
HB handle the voltages and power flows among SMs; the front-
end HB isolation converters use a constant duty cycle, thus to a
low control requirement for the qZS-MCC.
Based on the parameters in Table II, the efficiency of the pro-
totype is calculated, with the tested results shown in Fig. 14.
To assess the power loss method in Section IV, the front-end
stage is disabled in the tests and each dc voltage source sup-
plies post-stage qZS-HB directly. The two SMs of qZS-MCC
operate at the same input voltages, modulation indexes, and ST
duty cycles. Moreover, a constant 200-V dc-bus voltage is main-
tained when the input voltage varies. The SMs’ qZS-network
input voltages and currents, and the qZS-MCC’s output current
and dc-bus voltage are recorded to compute the efficiency by
η = (Vdc Io )/(vin1 Iin1 + vin2 Iin2 ). From Fig. 14, the ± 1 %
error from the tested to the calculated efficiency validates the
presented power loss evaluation
VII. CONCLUSION
This paper proposed a qZS-MCC, series connection of front-
end isolated qZS-HB SMs, for dc integration of high-power
PV systems. In this part of the paper, the system configuration,
operating principle, and power loss evaluation of the proposed
qZS-MCC were detailed. The specification was designed based
on 60-kW SM. Simulation results were presented for a 240-kW
system by four SMs in series. Experimental results carried out
on downscaled prototype validated the theoretical analysis.
Low control complexity of this modular cascaded system
was fulfilled through the post-stage qZS-HB dealing with volt-
age and power difference among SMs, while all front-end HB
isolation converters working at a unified and constant duty cycle
without control.
357
In addition to the properties of HV dc integration, gal-
vanic isolation, free of DLF ripple, and modular structure, the
qZS-MCC provided a competitive candidate for dc distribu-
tion/transmission of large-scale PV power systems.
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Yushan Liu (S’12–M’15) received the B.Sc. de-
gree in automation from Beijing Institute of Tech-
nology, Beijing, China, in 2008, and the Ph.D.
degree in electrical engineering from the School
of Electrical Engineering, Beijing Jiaotong Uni-
versity, Beijing, China, in 2014.
She is currently an Assistant Research Scien-
tist in the Department of Electrical and Computer
Engineering, Texas A&M University at Qatar,
Doha, Qatar, where she was a Research As-
sistant from 2011 to 2014 and a Postdoctoral
Research Associate from 2014 to 2016. She has published more than
50 journal and conference papers, one book, and one book chapter in
the area of expertise. Her research interests include impedance source
inverters, cascade multilevel converters, photovoltaic power integration,
renewable energy systems, and pulse width modulation techniques.
Dr. Liu received the “Research Fellow Excellence Award” from Texas
A&M University at Qatar, one of “Excellent Ten Doctoral Dissertations”
from Beijing Jiaotong University, and many other prestigious research
awards.
Haitham Abu-Rub (M’99–SM’07) received two
Ph.D. degrees, one in electrical engineering
from the Technical University of Gdansk, Poland,
in 1995, and one in the humanities from Gdansk
University, Poland, in 2004.
Since 2006, he has been associated with
Texas A&M University at Qatar, Doha, Qatar,
where he was promoted to a Professor, and is
currently the Chair of the Electrical and Com-
puter Engineering Program and the Managing
Director of the Smart Grid Center–Extension in
Qatar. He has published more than 250 journal and conference pa-
pers, and has earned and supervised many research projects. He is
currently leading many potential projects on photovoltaic and hybrid re-
newable power generation systems with different types of converters
and on electric drives. He is the coauthor of four books, three of which
were published by Wiley. He is also an author/coauthor of five book
chapters. His main research interests are energy conversion systems,
including electric drives, power electronic converters, renewable energy,
and smart grid.
Baoming Ge (M’11) received the Ph.D. degree
in electrical engineering from Zhejiang Univer-
sity, Hangzhou, China, in 2000.
He was with the Department of Electrical En-
gineering, Tsinghua University, Beijing, China,
from 2000 to 2002. In 2002, he joined the School
of Electrical Engineering, Beijing Jiaotong Uni-
versity, Beijing, China, where, in 2006, he was
promoted as a Professor. He worked with the
University of Coimbra, Coimbra, Portugal, from
2004 to 2005, and with Michigan State Univer-
sity, East Lansing, MI, USA, from 2007 to 2008 and 2010 to 2014. He
is currently with the Renewable Energy and Advanced Power Electron-
ics Research Laboratory in the Department of Electrical and Computer
Engineering, Texas A&M University, College Station, TX, USA. He has
authored more than 200 journal and conference papers, two books, two
book chapters, and holds seven patents. His main research interests in-
clude renewable energy generation, electrical machine drives, and power
electronics.