SJQ MAS All in One For MAS Rev1 1

Manufacturing With Intel® FCBGA Components for
Solder Joint Quality
Videos & Information Dynamic Warpage Fundamentals
MAS 1.1
Q3 2012
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For Use Under NDA Only - 1
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Course Agenda
Learning Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Next Slide
Introduction to Solder Joint Quality (SJQ) . . . . . . . . . . . . . . Module 1
Defects Modes & Mechanisms . . . . . . . . . . . . . . . . . . . . . . . Module 2
Printed Circuit Board (PCB) and Package Warpage . . . . . . . . . Module 3
SMT Solder Paste Impacting SJQ . . . . . . . . . . . . . . . . . . . . . Module 4
SMT Process Parameters Impacting SJQ . . . . . . . . . . . . . . . . Module 5
SJQ Inspection & Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . Module 6
Knowledge Checks at the end of each module summarize the key points
Intel Confidential
Learning Objectives
Mission:
To provide an understanding of how to achieve solder joint quality and acceptable
SMT yields on Intel® FCBGA components, while considering impacts of SMT
process, SMT materials, dynamic warpage & potential defects. This training
provides the fundamental solder joint knowledge that Intel has compiled to help
customers make effective manufacturing & SJQ inspection/analysis decisions.
At the conclusion of this course the student can:

• Understand FCBGA component thinning trend.
• Define the SMT defect modes & mechanism for thinner packages.
• Understand dynamic warpage signatures (PCB and FCBGA).
• Identify room-temperature and high-temperature warpage specifications.
• Have the knowledge to implement solder paste screening tests.
• Recognize the critical SMT process parameters that modulate SMT yield.
• Understand solder joint inspection and failure analysis tools & options.
Deep technical training to help prepare Customers for the

Haswell Ultrabook™ FCBGA component manufacturing launch!
Intel Confidential
Module 1: Introduction to Solder Joint Quality
(SJQ)
Solder Joint Quality MAS (Manufacturing Advantage Service)

MAS Rev 1.0, July 2012
Intel Confidential
Overview - Table of Contents
This course is divided into the following modules:
Module 1: Module 2: Module 3: Module 4: Module 5: Module 6:

Introduction to Defects Modes & PCB and Package SMT Solder Paste SMT Process SJQ Inspection &
Solder Joint Mechanisms Warpage Impacting SJQ Parameters Analysis
Quality Impacting SJQ
1.1 Definition of 2.1 Dynamic 3.1 Introduction 4.1 SMT Solder 5.1 Introduction 6.1 Introduction
SJQ and SJR Warpage Defect to Warpage and Paste 5.2 Solder Paste 6.2 SJQ
1.2 Introduction & Signature Coplanarity Volume
4.2 Solder Flux Monitoring &
Challenges 2.2 Head on Pillow 3.2 Mobile Functions and Optimization Analysis
1.3 Dual Core Defect Mechanism Package Trends Components 5.3 Reflow Recommendations
Mobile Z-Height 2.3 Solutions for 3.3 Mobile Pallet 4.3 Solder Flux Parameters 6.3 Optical
Package Trend HoP Defect Use for SMT & Components: Optimization Microscope
Resolution Board Warpage Importance of 5.4 Intel SMT
1.4 Dynamic 6.4 NCTF Solder
Warpage 2.4 Non Wet Open 3.4 Package and Activators Process Joint Test
Challenges Defect Mechanism Board Interaction 4.4 Solder Paste Characterization 6.5 2D X-Ray
1.5 Factors 2.5 Solutions for During SMT Screening Tests Approach
Introduction 6.6 3D
Potentially NWO Defect 3.5 Industry 5.5 Knowledge Laminography
Influencing SMT Resolution Standards 4.5 Instrument- Check Tool
Yield (Fishbone 2.6 Solder 3.6 Intel Based Screening
Diagram) 6.7 Dye and Pull
Bridging Defect Publication 4.6 Component-
1.6 Knowledge Mechanism Approach Based Screening 6.8 Cross
Check Sectioning
2.7 Solutions for 3.7 Knowledge 4.7 Solder Paste
Bridging Defect Check Screening Tests 6.9 3D X-Ray Tool
Resolution Summary Table 6.10 Knowledge
2.8 Summary 4.8 Knowledge Check
Table Check
2.9 Knowledge
Check
Intel Confidential
Module 11
Module
Acronyms Found in this Module
CTE Coefficient of Thermal Expansion

FCBGA Flip-Chip Ball Grid Array
HDI High Density Interconnect
HoP Head on Pillow
INEMI* International Electronics Manufacturing Initiative
Institute for Interconnecting and Packaging Electronic Circuits (now IPC*,
IPC*
Association Connecting Electronics Industries
Joint Electron Devices Engineering Council (now the JEDEC* Solid State
JEDEC*
Technology Association)
JEITA* Japan Electronics and Information Technology Industries Association
LDI Low-Density Interconnect
MAS Manufacturing Advantage Service
NWO Non Wet Open
PCB Printed Circuit Board
RoHS Restriction of Hazardous Substances Directive
SJ Solder Joint
SJQ Solder Joint Quality
SJR Solder Joint Reliability
SMT Surface Mount Technology
TAL Time Above Liquidus
Intel Confidential
Module 1
Module
1.1 Definition of SJQ and SJR

Example of typical well formed FCBGA solder joints
Package
PCB Pad
Solder Joint Image (Cross Section)
Solder Joint Quality (SJQ) refers to the quality and robustness of the solder joint that
is formed during the SMT process (Time Zero).
Solder Joint Reliability (SJR) refers to the ability of a product (surface mount solder
joints) to function under specified condition for a specified period of time without
exceeding acceptable failure rates.
This document will focus on SJQ on FCBGAs –> Producing well

formed and robust solder joints during the SMT process.
Intel Confidential
Module 1
Module
1.2 Introduction & Challenges (1 of 3)
Over the last few years the trend in the mobile industry has been moving toward:
• Thinner and larger component form factors, with thinner PCBs, board & system designs.
• Environmentally friendly manufacturing (Lead Free, RoHS Compliant, etc…).
Thin Large
This industry trend to thin is driving an increased importance of SMT process capability to
mitigate solder joint formation defects from warpage and ensure high SJQ & SMT yields.
Industry standards (i.e. JEDEC*, IPC*, INEMI*, JEITA*) continue to be outpaced by these
technologies. More Info in Module 3
Ultrabook™
The dynamic warpage projection for the 2013
Platform FCBGAs on the Shark Bay Mobile
Platform, including the Haswell Ultrabook™
package (ULT Dual Core), show an increase from
the prior platform.
This document will provide a fundamental level of SJQ and dynamic

warpage information & solutions to obtain a high yield SMT process.
Intel Confidential
Module 1
Module
Robust solder joint formation / high SMT yields

are a function of many SMT parameters:
• Solder paste formulation
• Solder paste volume (stencil design)
• Reflow profile / environment
• PCB dynamic warpage (reflow pallet use)
• Package dynamic warpage
Optimized SMT process & materials can overcome the increase in component / PCB dynamic
warpage and result in acceptable SMT yields, as demonstrated in the Platform MAS document.
For Intel® FCBGA packages, these are the two most effective ways to mitigate solder joint
formation defects at SMT:
Solder Paste Formulation Solder Paste Volume (Stencil Design)
Optimization Optimization
More Info in Modules

4&5
Intel Confidential
Module 1
Module
In order to optimize the SMT process, an improved understanding of SMT process & material
performance is essential.
Fishbone Diagram
• Identify the main factors that impact SJQ and contribute to SMT yield.
• Process and material characterization responses through SMT reflow.
Intel is performing a higher level of SJQ characterization on next

generation FCBGAs, and will provide this information in the Platform MAS
to customers as a Manufacturing Advantage Service, for example:
Example FCBGA Package Dynamic Example FCBGA Solder Paste Volume

Warpage Data Process Window (For Corner Pads)
Example Only
Example Only
More Info in Module 3 More Info in Module 5

The Platform MAS contains all of the latest SMT process & material parameter
recommendations, to achieve acceptable SJQ and SMT yields.
Intel Confidential
Module 1
Module
1.3 Dual Core Mobile Z-Height Package Trend (1 of 2)
Mobile Dual Core FCBGA Processors

MAX Package Z-Height (Post SMT)
2.5
Package 1.5
Z-Height
(mm) 1
0.5
0
2010 - Arrandale 2C 2011 - Sandy Bridge 2C 2012 - Ivy Bridge 2C 2013 - Haswell ULT 2C
Calpella Platform Huron River Platform Chief River Platform Shark Bay Platform
Legend:
Dual core mobile FCBGAs are continuing on a Z-height reduction trend.

Intel Confidential
Module 1
Module
1.3 Dual Core Mobile Z-Height Package Trend (2 of 2)
Haswell Package Evolution

2012 Chief River
Ivy Bridge 31 mm Haswell ULT (Dual Core) Package Evolution ->
(Dual Core) More features / increased functionality in one package!
FCBGA / Single Die 2013 Shark Bay

24 mm
1.62 mm MAX 40 mm Mobile
(Z-Height Post-SMT) Haswell ULT
(Dual Core)
HT1 Pkg Coplanarity
Range: 24 FCBGA / Multi Chip
-0.16 to +0.23 mm mm Package (MCP)
25 mm 1.51 mm MAX
2012 Chief River (Z-Height Post-SMT)
Panther Point
Mobile PCH Expected HT1 Pkg
Sign Convention Coplanarity Range:
FCBGA / Single Die -0.25 to +0.23 mm
2.18 mm MAX 25 mm
(Z-Height Post-SMT)
HT1 Pkg Coplanarity
Range: These changes were required to include the many Intel® microarchitecture
-0.13 to +0.20 mm features into the Haswell ULT (Dual Core) package and to reduce the Z-
height for the Ultrabook™ market segment of very thin systems (<18 mm).
The industry trend to thin is driving higher dynamic

warpage - Following Intel’s MAS guidelines is critical.
1Between lowest active temperature of the board paste to peak reflow temperature.
Intel Confidential
Module 1
Module
1.4 Dynamic Warpage Challenges (1 of 3)

• Dynamic warpage of the PCB / FCBGA stack occurs during the SMT reflow process.
• Expansion of materials with increased temperature is characterized by their Coefficient of
Thermal Expansion (CTE).
• During heating and cooling (SMT reflow soldering process), for FCBGA packages the silicon
die expands much less than the package substrate laminate, creating a generalized `bi-
metallic strip` effect, creating `dynamic` warpage.
Generalized Images:
At Room Temperature / Before When Heated To Reflow Temperature
Reflow Soldering
FCBGA Package1 FCBGA Package1 FCBGA Package1
Convex (+) Warpage Concave (-) Warpage Concave (-) Warpage
CTE ~ 4
ppm/°C
(OR)
CTE ~15
ppm/°C PCB
PCB PCB PCB
Relatively Flat Convex (+) Warpage Concave (-) Warpage
1Not all FCBGAs will have this warpage signature. See the Platform MAS for specific
package warpage details. More Info in Module 3
Even though the PCB / FCBGA stack will warp when heated, this effect
can be mitigated by optimizing the SMT process & materials.
Intel Confidential
Module 1
Module
Example Schematic depiction of possible solder joint defects that can occur as a result
of increased PCB and/or FCBGA stack warpage, under an un-optimized SMT process
FCBGA Package
Concave (-) Warpage
PCB
Convex (+) Warpage
Head on
Pillow (HoP) Non Wet
Open Bridging Open (NWO)
Head on
Pillow (HoP)
More Info in Module 2
HoP and NWO solder joints defects, for FCBGAs in Concave (-) Warpage shape (during reflow),
are typically seen in package corners, while bridging is typically seen in package center.
Various solder joint defects can occur during SMT reflow soldering but they
can be mitigated by optimizing the SMT process & materials.
Intel Confidential
Module 1
Module

Un-optimized SMT Reflow Scenario
HEAT
FCBGA Package FCBGA Package
Convex (+) Warpage, pre reflow Concave (-) warpage, at high
temperature
SMT
Reflow
PCB Pads
Customer Mother Board
NWO HoP Bridging
SMT Conditions:
• Un-optimized solder paste formulation,
volume, reflow profile / environment,
uncontrolled PCB warpage
Need to optimize the SMT reflow process to minimize SMT defects.
Intel Confidential
Module 1
Module
1.5 Factors Potentially Influencing SMT

Yield (Fishbone Diagram)
PCB Package
PCB Design Solder Mask Dam Package Design
Fishbone Surface Finish Thickness Full Grid vs. Peripheral

Solder Ball Alloy
diagram used Array
to identify Vendor LDI vs. HDI
Solder Ball Size Package X-Y-Z
all possible Material (Low Halogen Pad Size / Type
SMT Yield vs. FR4) Package Dynamic
factors. PCB Dynamic Warpage / Warpage
Reflow Pallet Usage
Dynamic
warpage Many Factors Potentially Contributing to SMT Yield
related
Placement Force Operator Variation
defects found
to be Solder Paste Formulation
Solder Powder Size
primarily
influenced by Reflow Environment Reflow Peak, TAL & Soak
those factors (Air vs. N2) Time
highlighted Solder Paste Volume /
SMT Equipment Variation
on this page. Stencil Design
Ambient Temperature
SMT Process and Materials
The upcoming modules will go into more detail on these primary factors.
Intel Confidential
Module 1
Module 1 - Knowledge Check: Multiple Choice

Question 1 of 5
The industry transition to thinning system designs is driving Z-height

reductions in components & PCBs (True or False)?
A) True. For example, the

B) False.
Ultrabook™ Ultrabook™
market segment
of very thin
systems.
Correct!
Intel Confidential
Module 1

Question 2 of 5
What are the solder joint defects that can occur, as a result of increased
PCB and/or FCBGA stack warpage, under an un-optimized SMT process
(choose all that apply)?
A) Solder Bridging.
B) Solder Contamination. For FCBGAs packages, NWO and HoP
solder joints defects are typically
C) Head on Pillow (HoP). seen in the package corner regions,
while solder bridging is typically seen
D) Solder Shifting.
in the package center.
E) Non Wet Open (NWO).
Correct!
Intel Confidential
Module 1

Question 3 of 5
What package shape nomenclature does Intel use when referring to this
shape (choose one)?
A) Convex (+) Warpage “Sad Face”

B) Concave (-) Warpage “Smiling Face”
Correct!
Intel Confidential
Module 1

Question 4 of 5
Which of these methods are the most effective ways to mitigate solder
joint formation defects at SMT (Surface Mount Technology) (choose
two)?
A) Solder paste formulation optimization.

These are the two
B) Reflow in N2 environment. methods that
C) Minimizing board warpage (use SMT pallet). Intel has found to
be most effective.
D) Solder paste volume optimization.
Correct!
Intel Confidential
Module 1

Question 5 of 5
Where do customers find Intel’s specific platform SJQ (Solder Joint

Quality) Characterization and SMT process & material recommendations
(choose one)?
A) Thermal Mechanical Design Guide (TMDG).

B) External Design Specification (EDS).
C) Platform Manufacturing Advantage Service (MAS). Contact your
Intel Customer
D) Manufacturing Technology Excellence (MTE). Quality
Engineer (CQE)
for more
information.
Correct!
Intel Confidential
Module 2: Defects Modes & Mechanisms

Intel Confidential

Introduction 6.6 3D
Check Sectioning
Table Check
2.9 Knowledge
Check
Intel Confidential
Module 12
Module

HoP Head on Pillow
IMC Intermetallic Compounds
NWO Non Wet Open
PoP Package on Package
Intel Confidential
Module 2
2.1 Dynamic Warpage of Thin FCBGA Defect

Signature
HoP
NWO
Package is Package is lifted up During reflow, Defect
placed on the due to CTE mismatch paste is fully formation after
printed paste during heating melted cool down
Two situations can happen when a package is lifted from

the paste which result in a different defect mode.
Intel Confidential
Module 2
Module
2.2 Head on Pillow Defect Mechanism (1 of 5)
FCBGA Head on Pillow (HoP) open solder joint is defined as:
A joint that is comprised of two metallurgical distinct

masses formed from the FCBGA ball and reflowed solder
paste with incomplete or no coalescence.
This defect is an
This defect is also known by several extension of HoP with
other names: a gap (HoP open)
•Head and pillow
•Head in pillow
•Ball in cup
•Ball in socket
•Hidden pillow
But, IPC50-T* has
standardized
it to Head on
Corner View Pillow (HoP) Cross Section View Cross Section View
HoP: A) May not result in an electrical open, with a little pressure it may pass in-circuit test
and escape to the customer.
B) Is difficult to detect through non-destructive techniques such as X-ray, particularly
in the inner rows of solder joints.
Intel Confidential
Module 2
At reflow there is a gap
FCBGA is placed With increase between some balls and During cool
on solder paste, in temperature, paste. Dry flux and oxide down, the solder
reflow process flux becomes covers solder balls and the solidifies and the
is starting. active. FCBGA solder on the board. Gap FCBGA ball is
Temp could be a result of a number resting on the
start to warp
of factors, such as package
upward. dynamic warpage ,
solidified paste.
uneven PCB,
FCBGA or uneven ball
FCBGA
Convex (+) Warpage Concave (-) Warpage
collapse.
FCBGA
Concave (-) Warpage
PCB
160-190°C 220-250°C
25°C
25°C
Gap
HoP starts to occur later in the reflow process ( 220-250°C). Time
Intel Confidential
Module 2
Ball
Ball
The essential root cause for
the generation of the HoP
defect from this mechanism is
the existence of the gap Paste
Paste
Paste/Ball
Paste/Ball Contact
Contact before
before reflow
reflow
between the molten solder

ball and the molten solder
paste deposit on the PCB.
If this gap does not form Gap

Gap Formation
Formation at
at 220
220 cc
during the reflow soldering
process, then the HoP defect
will not form unless there is
either contamination present
on the solder ball or excessive
oxidation.
Paste/Ball
Paste/Ball Contact
Contact after
after cool
cool down
down
Intel Confidential
Module 2
Video: Head on Pillow - Defect Formation Reflow Temperature

Solder ball after reflow:
(C)
Package side
Time (minutes)
 This video is showing

three edge balls of FCBGA
substrate with die during
reflow. Mother board is
on a flat surface.
 Separation between the
Watch Video on Brightcove*
solder and the ball occurs
during reflow.
 Left ball has HoP after
solidification.
Intel Confidential
Module 2
Video: No Head on Pillow - Ideal Case Reflow Temperature (C)
Solder ball after reflow:
Time (minutes)
 This video is showing a

FCBGA substrate without
die during reflow.
 This is the ideal case since
there is no warpage or
gap during reflow.
 Mother board is on a flat
surface. Watch Video on Brightcove*
 Paste melted at  217C
and ball collapsed at
222C to form join.
Intel Confidential
Module 2
2.3 Solutions for Head on Pillow Defect Resolution
1. Increase paste amount printed on PCB lands.

2. Use Solder Pastes with better formulation.
3. Equilibrate the temperature across all solder balls
of the FCBGA during reflow soldering.
4. Reflow in N2 environment
5. Minimize board warpage by the use of SMT
reflow pallets etc.
These areas will be covered in greater
depth later in this document.
Intel Confidential
Module 2
Module
2.4 Non Wet Open Defect Mechanism (1 of 8)
FCBGA Non Wet Open (NWO) solder joint is defined as:
A joint that is comprised of one metallurgical mass formed

from the FCBGA ball and reflowed solder paste or flux
with incomplete or no coalescence to the PCB pad. There
is no evidence of solder on the PCB lands.
This defect is also known by

several other names:
•Non wet
•Hanging ball
•Ball on pad
•Ball on land
Cross Section View

Side views
Intel Confidential
Module 2
Module
FCBGA Non Wet Open (NWO) solder joint

could be a result of different modes:
1. Clogged stencil aperture can leave little or

no paste on the PCB land.
2. Dynamic warpage or interference between

top and bottom packages during reflow of
PoP package where the top package is
dipped into flux or paste.
3. Contamination on PCB land.
4. Dynamic warpage and paste adhesion.
In this presentation we will address NWO defect that is common to thin

FCBGAs packages due to dynamic warpage and paste adhesion.
Intel Confidential
FCBGA Module 2
Concave (-) Warpage
2.4 Non Wet Open Defect 230-250°C
Mechanism (3 of 8) FCBGA
Concave (-) Warpage
210-220°C
Temp During soak FCBGA
~160-190°C, Concave (-) Warpage
package warps 160-190°C

upward. Paste
starts to lift up
from PCB pad.
During reflow, paste
is fully melted and
Package wicked upward, and
continues to the Ball and paste
warp upward coalesce.
and the paste 25°C
wets to the ball.
FCBGA
Convex (+) Warpage
25°C
Package After cool

enters the down, the ball
reflow.
NWO starts to occur early in the rests on pad.
reflow process (160-190°C).
Time
Intel Confidential
Module 2

Ball Paste
The mechanism for the

generation of the NWO defect is Paste/Ball Contact before melting
the solder paste adhering to the

ball instead of the PCB pad
during heating & reflow. Gap Formation at ~160-190 °C
Because of warpage, a gap is

formed between the package
ball and the solder paste. Gap continues as package heats up
The paste just wets to the ball

and oxide builds up on the PCB
Solder is melting
land causing an open joint.
Ball Contact after cool down
Intel Confidential
Module 2
Video 1: Non Wet Open - Defect Formation

Reflow Temperature
 Three edge
solder balls on (C)
FCBGA unit with

die.
 Solder paste is
lifting from the
PCB pad
adhering to the
solder sphere
during reflow
pre heat.
 Right ball has Watch Video on Brightcove*
NWO after
solidification.
 Mother board is
on a flat surface.
Intel Confidential
Module 2
Video 2: Non Wet Open - Defect Formation
 Seven edge
solder balls on
FCBGA unit with
die.
 Solder paste is
lifting from the
PCB pad
adhering to the
solder sphere
during reflow
pre heat.
 Mother board is
on a flat surface.
Intel Confidential
Module 2
There could be partial IMC

if some paste is left on the
pad.
Flux residue indicates that

paste was on the pad but
coalesced with the ball.
Intel Confidential
Module 2
NWO Defect Sample Images
Package
Side
Board Side
Board Side
Images were taken after
(Mirror
pulling the package from
Image of
the mother board.
Package)
Intel Confidential
Module 2
2.5 Solutions for Non Wet Open Defect Resolution

1. Chose the right paste formulation .
2. Increase solder paste quantity deposited on the
land by increasing stencil aperture.
3. Minimize board warpage (use of pallet etc.)
These areas will be covered in greater

depth later in this document.
Intel Confidential
Module 2
Module
2.6 Solder Bridging Defect Mechanism (1 of 6)
Solder Bridging is defined as:
Adjacent solder joints coalesced into one large mass.
X-Ray View Cross Section View
Intel Confidential
Module 2
Module

Causes for Solder Bridging:
PCB Related
 Improper Land Design …. Large lands with very little spacing
 No solder mask between lands
 Solder Mask misalignment around the lands
 Solder mask thickness
Component Related
 Moisture sensitivity of component, leading to excessive component Bulging of FCBGA substrate
substrate warpage changing the package
 Moisture in the package that is releasing during reflow. co-planarity.
 `Heavy `Component with weight pushing down on the molten solder ball
Solder Paste Printing Related

 Excessive solder aperture size…..leading to excessive solder paste
 Contaminated stencil underside leaving smudged paste print
 Excess paste due to stencil thickness and solder mask thickness issues
 Excess Solder paste slumping
 Improper board support during print process resulting in excess print
 Improper gasket formation when using electroform stencils FCBGA bridging
 Print misalignment
due to moisture.
 Paste smear due to mishandling
Pick and Place Process Related

 Excess placement pressure
 Improper board support during placement
 Placement misalignment smudging paste onto the mask
Solder bridging has many root causes, not just component or board warpage.
Intel Confidential
Module 2
Module
In this section we will address solder bridging defect as a

result of dynamic warpage.
Cross Section View
X-Ray View
FCBGA with Concave
(-) Warpage at reflow
Intel Confidential
Module 2
Module
Solder melts and adjacent joints FCBGA

Concave (-) Warpage Exacerbates
coalesce because they get
compressed due to the warpage;
This leads to solder bridging.
FCBGA
Concave (-) Warpage
As package cools, warpage

becomes less and solder
solidifies, and a solder bridge
forms where two adjacent balls
FCBGA
Convex (+) Warpage had coalesced when molten.
FCBGA Surface tension of solder keeps
the bridge formed even as the
Board
negative Warpage reduces.
Intel Confidential
Module 2

Package/Board Warpage Effect
During solder joint collapse, the solder collapse force pulls the package toward the
board. Solder bridging can occur when the squeezed solder joints are bulged too
much becoming asymmetric shape to get in contact with a neighbor bulged joint.
Before Collapse After collapse

PCB Convex (+) Warpage
Before Collapse After collapse

PCB Concave (-) Warpage
Symmetric Asymmetric
Intel Confidential
Module 2
Module
Video: Bridging - Defect Formation
 Temperature is raising
to 220 °C, solder balls
collapse.
 Molten solder moves
easily around the
pads.
 Molten solder balls
are contacting each
other causing solder
bridge defect.
Intel Confidential
Module 2
2.7 Solutions for Bridging Defect Resolution

1. Decrease the amount of paste printed on the
center PCB lands.
FCBGA with out cavity FCBGA with cavity
Check the specific platform Manufacturing Advantage

Service (MAS) for stencil design guidance.
Intel Confidential
Module 2
Module
2.8 Summary Table
Board assembly materials and processes

that can reduce component/board warpage
induced solder joint defects.
Solder Paste
Stencil N2 Reflow
Formulation Reflow Pallet Reflow
Defect Name Aperture Environment
(Flux Vehicle Design Profile
Design (02<3000 PPM)
Composition)
Head on
Pillow     
Non Wet
Open   
Solder
Bridging  
Tick mark () indicates the material/process item that can reduce the solder joint defects
Component / board warpage induced defects can be

minimized / eliminate with modification / optimization of
board assembly materials and processes.
Intel Confidential
Module 2

Question 1 of 6
What is the main mechanism for Head on Pillow (HoP) defect (choose
one)?
A) Excessive solder paste slumping.

B) Separation of the package ball from the solder paste.
C) Lifting of the solder paste from the PCB land.
D) Excessive placement pressure.
Correct!
Intel Confidential
Module 2

Question 2 of 6
What is the main mechanism for Non Wet Open (NWO) defect (choose
one)?
A) Separation of the package ball from the solder paste.

B) Excessive placement pressure.
C) Excessive solder paste slumping.
D) Lifting of the solder paste from the PCB land.
Correct!
Intel Confidential
Module 2

Question 3 of 6
At what stage in the SMT reflow profile do Head on Pillow (HoP) defects
form (choose one)?
A) At Soak (~160 to 190°C).

B) At Reflow (~220°C to solidification temperature).
At reflow there is a gap between

some balls and paste.
During cool down, the solder

solidifies and the FCBGA ball is
resting on the solidified paste.
Correct!
Intel Confidential
Module 2

Question 4 of 6
At what stage in the SMT reflow profile do Non Wet Open (NWO) defects
form (choose one)?
A) At Soak (~160 to 190°C).

B) At Reflow (~220°C to solidification temperature).
During soak ~160-
190°C, package
warps upward.
Paste starts to lift
up from PCB pad.
Package continues
to warp upward
and the paste wets
Correct! to the ball.
Intel Confidential
Module 2

Question 5 of 6
What leads to solder bridging due to dynamic warpage (choose one)?
A) Solder joint expansion.

B) Solder joint gets compressed.
C) Solder joint solidification.
Correct!
Intel Confidential
Module 2

Question 6 of 6
What is the primary modulator of Non Wet Open (NWO) defects (choose
one)?
A) Reflow Profile.
B) Solder Paste Formulation. Some solder pastes have a greater
tendency to adhere onto the
C) Solder Stencil Design.
surface of the solder ball instead on
D) Solder Paste Printing. the surface of the land, causing the
paste to fully melt on the solder
ball (away from the land).
Correct!
Intel Confidential
Module 3: PCB and Package Warpage

Intel Confidential

Introduction 6.6 3D
Check Sectioning
Table Check
2.9 Knowledge
Check
Intel Confidential
Module 3
Module

FCBGA Flip Chip Ball Grid Array
HDI High Density Interconnect
HoP Head on Pillow
HT High Temperature
Institute for Interconnecting and Packaging Electronic Circuits (now IPC*,
IPC*
Association Connecting Electronics Industries
Joint Electron Device Engineering Council (now the JEDEC Solid State
JEDEC*
Technology Association)
NWO Non Wet Open
PMD Package Mechanical Drawing
POR Process of Record
RT Room Temperature
Intel Confidential
Module 3
3.1 Introduction to Warpage and Coplanarity

 Warpage is the deviation from uniform planar flatness (or coplanarity).
 Warpage of FCBGA & PCB1 is driven largely by CTE mismatch between
the various material constituents during a temperature change.
CTE2
– Figure to right depicts FCBGA warpage (vs. a seating plane)
CTE1 CTE2
– In figure, CTE2 (substrate) is typically 5-10x of CTE1 (die)
 As the reflow process involves changes from RT to HT, understanding

the warpage of the FCBGA and PCB is important to insure good SJQ.
 JEDEC* has defined methods to quantify flatness and adopted consistent
sign convention as shown below (per JEDEC* SPP-024, see Module 3.5).
FCBGA & PCB warpage is inherent to the reflow process.

1PCB warpage due to a combination of unsupported sag (gravity) and CTE mismatch
Intel Confidential
Module 3
3.2 Mobile Package Trends

 Demand for thinner systems driving FCBGA package height, e.g. Ultrabook™ and
package z-height reduction.
 Demand for more features/increased functionality driving larger packages with
both processor and chipset in one FCBGA, e.g. Haswell ULT package (see Module
1 for details of Haswell ULT package evolution).
 Thinner + “longer” mobile package driving increased warpage.
Normalized Z-Height & Longest Package Normalized Package Warpage by

Dimension by Intel® Mobile Platform Generation Intel® Mobile Platform Generation
Due to adding more features/increase functionality packages are

becoming thinner & longer, resulting in increased package warpage.
Intel Confidential
Module 3
3.3 Mobile Pallet Use for SMT & Board Warpage (1 of 2)
 Demand for thinner systems is also driving thinner PCB use.

 Routing design is driving use of different PCB materials/design (e.g. HDI1).
 Thinner mobile PCB’s drive the need to control warpage / PCB sag.
 To control FCBGA land area PCB warpage (i.e. keep “flat”) to improve SMT yield
and/or protect key components, metal or ceramic reflow pallets are often used.
Normalized Mobile PCB Thickness by Spring

Intel® Mobile Platform Generation Clamps
(a) (b)
Example Depiction of
Example of Spring Clamp: “2-Up” (one pallet for 2
Example Depictions of (a) Without Board and PCB’s) SMT Pallet with
SMT Pallet Designs with & (b) Clamping a Board Spring Clamp Design
Without Spring Clamp
Pallets are used to control increases in PCB warpage (& sag).

1See the Intel® mobile platform design guides for more information.
Intel Confidential
Module 3
3.3 Mobile Pallet Use for SMT & Board Warpage (2 of 2)
• Intel evaluated several mobile customer product boards & pallets.

• All customer product boards evaluated used a pallet as Plan of Record (POR).
• All but two customer pallets used a spring clamp design.
• All boards evaluated with pallets using spring clamps had high-temperature1
warpage of <50 µm in land area2 (without clamps ~20-30% higher).
• For specific requirements, consult the Platform MAS (e.g. Shark Bay MAS).
Example Mobile Product Board High-

Temperature1 Warpage at 11 Different
FCBGA Land Areas with POR SMT Pallet
(With Spring Clamp vs. Without Spring
Clamp Designs).
1Between lowest active temperature of the board paste

to peak reflow temperature.
2 Land area under FCBGA (full board span was not

measured).
Pallet use can minimize board warpage in the FCBGA land area.
Intel Confidential
Module 3
3.4 Package and Board Interaction During SMT(1 of 2)

 Combinations of package and board warpage shapes can occur in SMT
1
Board
Board
Example Only Example Only
1Other FCBGA may exhibit different behavior

(sign / shape).
 Schematic depiction of possible

solder joint defects that can occur
as a result of increased PCB
and/or FCBGA warpage, under un-
optimized SMT process.
SMT process optimization is required for warpage shape interactions.
Intel Confidential
Module 3
3.4 Package and Board Interaction During SMT(2 of 2)

Video: Package and PCB Interaction
 Video shows an
example
interaction of
Haswell (4
Core) FCBGA
package and
PCB, through a
typical SMT
reflow process.
 Warpage is
Die
measured
relative to the
Substrate
mathematical
least square Local PCB Land Area
fitted plane.
Intel Confidential
Module 3
3.5 Industry Standards (1 of 4)
 While several standards are in place (see below), they lag new “thinning” trend
of FCBGA as a standard revision or adding a new standard typically takes 2-4
years to be approved.
Consortia Standard Topic Parameters
JEDEC* Publication RT Coplanarity Specification for Ball Diameter, Ball Pitch, Package
95 FCBGA Shape
JEDEC* SPP-024 HT Flatness (alternate to RT Ball Diameter, Ball Pitch, Package
Coplanarity) Requirement for FCBGA Size (longest x-y dimension)
JEDEC* JESD22- RT Coplanarity Test Method for n/a
B108A FCBGA
JEDEC* JESD22B1 HT Flatness Test Method for FCBGA n/a
12
 Several standards activities are underway to meet “thinning” FCBGA trend:

– Revision of JEDEC* HT with optimized SMT process for thinner, less flat packages at HT.
– Addition of SMT optimization approaches for SMT defects in IPC* 7095 Revision C
– Establishment of an IPC* PCB warpage test method (none currently exists).
– Establishment of an IPC* PCB warpage guideline (none currently exists).
Consortia Standard Current Activities Ballot Expected
JEDEC* SPP-024 Revise to allow more warpage for thinner packages (e.g. HSW) Q4'12
IPC* 7095 (Revision C) Revise to address optimizing SMT Process for "thinning" trend Q1'13
IPC* 650 X.XX.X HT Warpage Test Method for PCB (FCBGA land area) Q1'13
IPC* 9641 HT Coplanarity Guideline for PCB (FCBGA land area) Q1'13
Updates to standards are underway to meet the “thinning” needs.

Intel Confidential
Module 3

JEDEC* Publication 95 Design Guide 4.5: Square Package, ball pitch < 1.0mm
e = ball pitch
b= ball diameter
ddd = coplanarity
Table by ball pitch

(e) of specification
for ball diameter (b)
minimum, nominal,
and maximum
values.
Table by nominal ball

diameter to extract RT
coplanarity value (ddd).
Example: if ball diameter
of 0.4, RT coplanarity
limited to 0.10, etc.
*Other names and brands may be claimed as the property of others. All dimensions are in mm
RT JEDEC* Publication 95 does not consider package size & Z-height thinning
Intel Confidential
Module 3

JEDEC* Publication 95 Design Guide 4.14: Ball pitch > 1.0mm (for
Square & Rectangular packages)
A low melt solderball has a metallurgical composition that
will go into the liquidus state when subjected to standard
e = ball pitch industry surface mount reflow temperatures of 230 °C
ddd = coplanarity
Table by ball pitch

(greater than 1.0mm)
to extract RT
coplanarity value
(ddd). Example: If
ball pitch of 1.5, RT
coplanarity limited to
0.15 or 0.2 depending
on method.
A high melt solderball has a metallurgical composition that

will not reach the liquidus state when subjected to standard
*Other names and brands may be claimed as the property of others. industry surface mount reflow temperatures of 230 °C
RT JEDEC* Publication 95 does not consider package size & Z-height thinning
Intel Confidential
3.5 Industry Standards
Module 3
(4 of 4)
Standard Practices and Procedures - Reflow Flatness Requirements
for Ball Grid Array Packages. JEDEC* SPP-024A Mar 2009
Define: “The greatest deviation from flatness (greatest magnitude of
e = ball pitch warpage) in the range from the lowest active temperature of the board paste
to peak reflow temperature shall be used to show compliance to the flatness
b= ball diameter
requirement”.
Table 1: For packages 15mm
or less in longest dimension,
table by ball pitch (e) & ball
diameter (b) to determine HT
Flatness requirement range.
Example for ball diameter 0.45
& ball pitch 0.65, HT flatness
requirement to be between
+0.12 to -0.12.
Table 2: For packages

greater than 15mm in longest *Other
dimension, table by ball pitch names and
brands may
(e) & ball diameter (b) to be claimed
determine HT Flatness as the
requirement range. Example property of
for ball diameter 0.45 & ball others.
pitch 0.65, HT flatness
All
requirement to be between
dimensions
+0.23 to -0.14. are in mm
HT JEDEC* SPP-024A does not currently consider thinner & longer packages.
Intel Confidential
Module 3
3.6 Intel Publication Approach (1 of 3)
 Starting with Shark Bay platform, Intel publishes RT & HT

information for mobile FCBGA products:
– For Room Temperature:
– Maximum coplanarity value indicated on PMD
– Incoming parts from Intel can be measured to this value
– For High Temperature:
– Expected high-temperature1 coplanarity range in note on PMD
– Example package dynamic warpage data in MAS
 See next two slides for examples of publication in PMD & MAS.
 For specific product information, consult the Platform MAS (e.g.
Shark Bay MAS).
1Between lowest active temperature of the
board paste to peak reflow temperature.
Intel publishes room temperature & high

temperature information on the PMD & in the MAS.
Intel Confidential
Module 3
3.6 Intel Publication Approach: PMD Example (2 of 3)
Package expected to be within high-temperature coplanarity range of-xx to +xx mm.
Location of High
Temperature
(HT)
information in
Note #1.
Maximum Room
Temperature
(RT) Coplanarity
Value. x
PMD includes HT coplanarity range and maximum RT coplanarity.
Intel Confidential
Module 3
3.6 Intel Publication Approach (3 of 3)

Example Package Dynamic Warpage Data
 Measured: Warpage of the package FCBGA area through a temperature
profile of 25°C, 165°C, 260°C as well as 25°C Return
 Sample Size: 6 units
 Summary of Results:
• Max high-temperature1 warpage: -140mm (5.51mils) concave shape
• All samples have incoming convex shape
• Units transition from convex to concave between 25°C and 165°C.
• All samples indicated a warpage increase on the return to room
temperature of 5mm to 35mm
Sign Convention
Convex
Sad Face
(+) warpage
Concave
Smiling Face
(-) warpage
Example Only
Example Only 1Between lowest active temperature of the
board paste to peak reflow temperature.
Platform MAS includes product-specific “Example Package Dynamic Warpage Data”.
Intel Confidential
Module 3

Question 1 of 6
What causes warpage in FCBGA packages during heating? (choose

one)?
A) Electro-Static Discharge (ESD).

B) SMT reflow oven rail mis-alignment.
C) Coefficient of thermal expansion (CTE) mismatch
between Silicon and organic substrate material.
CTE2
CTE1
Correct!
Intel Confidential
Module 3

Question 2 of 6
Intel® mobile FCBGA package warpage is increasing because packages

are becoming thicker and smaller (True or False)?
A) True.
B) False. Thinner + “longer” mobile packages (with
more features & increased functionality),
is driving increased warpage.
Correct!
Intel Confidential
Module 3

Question 3 of 6
What is one means to keep the FCBGA land area on the PCB “flat”
during SMT (choose one)?
A) Apply adhesive beads to hold PCB down in reflow oven.

B) Use of an SMT reflow pallet.
C) Place PCB directly on conveyor.
D) 90 degree rotation of PCB on conveyor.
Correct!
Intel Confidential
Module 3

Question 4 of 6
Is Printed Circuit Board (PCB) warpage always Convex (Yes or No)?
A) Yes.
B) No. PCB warpage can
be Convex or
Concave.
Correct!
Intel Confidential
Module 3

Question 5 of 6
Which industry standards are planned to meet “thin” need (choose all
that apply)?
A) JEDEC* SPP-024 revision, high temperature for thinner packages.
B) IPC* 7095 (Revision C), addition of SMT optimization approaches for SMT defects.
C) IPC* 650 X.XX.X, PCB HT warpage test method (FCBGA land area).
D) IPC* 9641, PCB HT coplanarity guideline (FCBGA land area).
All of the above.
Correct!
Intel Confidential
Module 3

Question 6 of 6
What two FCBGA package coplanarity values are documented on the

Package Mechanical Drawing (PMD) (choose two)?
A) Room-Temperature coplanarity maximum value of xx mm.

B) Room-Temperature coplanarity range of –xx to +xx mm.
C) High-Temperature coplanarity maximum value of xx mm.

D) High-Temperature coplanarity range of –xx to +xx mm.
JEDEC* HT Definition: Applies between the lowest active

temperature of the board paste to peak reflow temperature.
Correct!
Intel Confidential
Module 4: SMT Solder Paste Impacting SJQ

Intel Confidential

Introduction 6.6 3D
Check Sectioning
Table Check
2.9 Knowledge
Check
Intel Confidential
Module 4
Module
Acronyms Found in This Module

HoP Head on Pillow
ImAg Immersion Silver
LF HASL Lead-Free Hot Air Solder Leveling
NWO Non Wet Open
OSP Organic Solderability Preservative
SAC SnAgCu (tin-silver-copper alloy)
Intel Confidential
Module 4
4.1 SMT Solder Paste Typical Solder Paste SMT Process

Solder Paste consists of metal powder suspended in a Squeegee
viscous medium called flux. Solder paste

Stencil
Typical Solder paste =
88-90 weight% solder alloy powder / 10-12 weight% flux PCB
50% by volume solder alloy powder / 50% by volume flux
Print solder paste
onto PCB
Metal Powder Alloy
 SAC XYZ = X.Y% Ag + 0.Z% Cu + remaining % of Sn
 Today, most used alloy is SAC305. Place package onto
PCB with paste deposits
Types of solder powder based on particle size:
Solder Paste Type 80% of Metal Powder Sized Between (µm) Package
1 75-150
2 45-75
3 25-45
4 20-38 Run package/PCB sandwich
5 15-25 through reflow oven
6 5-15
7 2-11
Solder Flux Types1
Halogenated (H) - No limit to the content of Chlorine or Bromine (>900 ppm Bromine or Chlorine; >1500 ppm total halogen), either as ions or in
elemental form, in the flux of the solder paste.
Low Halogen (LH) - Chlorine or Bromine content is <900 ppm and total combined amount of Chlorine or Bromine <1500 ppm total halogen in the
flux of the solder paste.
Zero Halogen (ZH) - Chlorine or Bromine not intentionally added to the flux of the solder paste and both would register as non-detectable by
current testing methods.
1Disclaimer: These are common definitions from solder paste suppliers and not Intel’s definition.
Intel Confidential
Module 4
4.2 Solder Flux Functions and Components

Two main functions of Flux components: Example Only
 Removal of oxide layer and organic contaminates from solder
powder, FCBGA solder ball and Cu pad on the board. Temp.
Profile
 Rheology control of paste (ability to be dispensed/deposited
and maintain its shape after printing).
Uniquely designed proprietary flux components:
Paste
 Solvents – improve paste transfer for printing. Weight Loss
 Rosins/Resins – serve as encapsulants/protectors of activators.

 Thickeners – modulate thrixo index.
 Plasticizers – promote pin testability and transfer for printing.
 Inhibitors – prevent Cu corrosion.
 Activators – clean oxides - key components of flux
responsible for solderability of component to PCB. Example Only
 During reflow heating solder pastes undergo
weight loss due to evaporation of solvents,
boiling, decomposition and chemical
transformation of other organic components.
Flux chemistry has major effect on formation of

defect-free solder joints and overall SMT yield.
Intel Confidential
Module 4
4.3 Solder Flux Components: Importance of

Activators (1 of 6)
Activators in the Solder Paste
 Oxide cleaning activity of solder pastes is
temperature dependent: activity goes up as
temperature increases.
 Most solder pastes’ fluxes have a blend of

activators rather than just one activator. Each
one becomes highly active at a different
temperature during the reflow.
 When activator is used up by reacting with the

oxides, then it gets `spent` and stops the
reduction of any more oxide.
 Some activators may boil off or decompose at

certain high temperatures. Above these
temperatures the activators lose their ability to
reduce oxides.
Every solder paste supplier has a different

activator packages in their pastes.
Intel Confidential
Module 4

Activators (2 of 6)
Activator Example of an
Activator is Spent Activator during
Activates
`
Reflow Soldering
Activity for Oxide Reduction

Temperature
Activator Melting
Temp
X
Example Only
Time
Intel Confidential
Module 4

Activators (3 of 6) Activator A Activator B Activator C
Example of a
Three Activator
System

Temperature
Example Only
Time Activators are selected such that they activate

sequentially at different temperatures.
Intel Confidential
Module 4

Activators (4 of 6) Activator A Activator B Activator C Activator D
Example of a
Highly Active
Solder Paste

Temperature
Example
Only
Time Another activator is added which activates at a higher

temperature than the other activators in the solder paste.
Intel Confidential
Module 4

Activators (5 of 6) Activator A Activator B Activator C
HoP Defect
Formation for a
Standard Solder
Paste

Temperature
Example Only
Time When molten ball and molten solder paste deposit

on a board make contact, all activators are spent.
Intel Confidential
Module 4

Activators (6 of 6) Activator A Activator B Activator C Activator D
High Activity
Solder Paste
During Reflow
(Addition of

“Activator D” –
no HoP)
Temperature
Example
Only
Time When molten ball and molten solder paste deposit on a

board make contact, one activator (“D”) is still `active’.
Intel Confidential
Module 4
4.4 Solder Paste Screening Tests - Introduction

 Screening tests are designed to down select solder paste(s) capable to
improve solder joint quality and SMT yield by comparison of materials to
each other.
 Combination of screening test might required to identify desired solder

paste.
 Some testing parameters might need further adjustment to provide better

fit to customers’ process conditions.
 SMT validation build recommended to confirm final selection of solder paste.
Instrument-based Component-based
SMT Yield Solution
Keep in mind that paste printing parameters, reflow

conditions and PCB surface finish can alter SMT yield!
Intel Confidential
Module 4
4.5 Instrument-Based Screening: Tackiness

Malcom TK-1* Tackiness Tester:
 IPC* Solder Paste Tack Test Example Only
2.4.44 method – IPC-TM-650*
Example Only
 Test Benefit: Measure Paste Tackiness vs.

Temperature.
 Pastes with low rate of tack force change (per Deg
C) were found to have improved SMT Yield % (can
help with both HoP and NWO defects).
 HoP and NWO defects can be reduced/ eliminated
by thermally stable solder pastes (i.e., low rate of
tack force change per °C).
Intel Confidential
Module 4
4.5 Instrument-Based Screening: Cu Wire

Wetability >80% SMT Yield
Modified Rhesca SAT-5100*:
 510 µm Cu wire
 3.2-mm diameter, 0.20-mm thick Example Only
circular paste print on Cu coupon
 235 °C test temperature
 0.2 mm/sec immersion speed
 100 µm immersion depth
 10 sec test time
Intel
Developed
Setup
 Higher wetting force and shorter wetting time are

preferred for better solderability.
 For NWO defect, wetting time has predominant
impact on rate of defect formation.
 Results shown here use parameters shown above.
Intel Confidential
Module 4
4.5 Instrument-Based Screening: PCB Surface

Finish Wetability
Menisco ST78*: Example Only
 Bath of SAC305 set at 240 C
 Fluxes heated to liquefy to ~140 C
 1cm x 3.8cm double-sided PCB strips with
different surface finishes (ImAg, OSP and LF
Hasl) dipped into liquid fluxes
 Measurements conducted by immersing PCB
strips with speed of 1mm/s to depth of 3 mm
into bath of molten SAC305 for 20 s.
Intel
Developed
Setup
PCB Strips
 When selecting paste to minimize NWOs chose

ImAg
paste that wets the best to PCB finish of interest

OSP
whereas for HoPs find paste that wets equally

good to LF HASL (FCBGA ball) and PCB surface
finish.
 Paste A1 produces 100% SMT yield while paste

B1 results in NWO fallout rate of 80% when PCB
land finish is OSP.
Intel Confidential
Module 4
4.5 Instrument-Based Screening: Solidification

Temperature
Perkin Elmer DSC7*:
 10 to 12 mg of paste
 Heating Cycle:
1) Hold temp. for 1 min at 25 ˚C
2) Heat from 25 ˚C to 245 ˚C at
heating rate of 60 or 120 ˚C/min
3) Cool to 25 ˚C at cooling rate of
120 ˚C/min
Intel Melting
Developed transition
Setup
Solidification
Example Only
transition
 There is significant difference between different solder pastes

in solidification temperatures (melting temp. is the same).
 Paste B1 resulted in NWO fallout rate of 80% on OSP surface
finish.
 In order to mitigate HoP and NWO defects, one needs paste
with low solidification temperature.
Intel Confidential
Module 4
4.6 Component-Based Screening: Paste-to-Ball

Wetting Test (1 of 2)
Paste-to-Ball wetting test: Good wetability indicates that the solder
 A FCBGA package was inverted and paste should coalesce with the solder ball
solder paste was printed on the after reflow.
solder balls.
 The package was then reflowed in an
air atmosphere and inspected under Solder Balling (FAIL) Solder “Dome” (PASS) Perfect Coalesce (PASS)
microscope. Stencil
Stencil Setup
Intel Developed Setup Information:
Thickness =
~101.6 µm
(4 mil)
Aperture Solder Balling: Bad Solder Dome: Good Good solder wetting
Opening = wetting at solder wetting at solder ball condition (PASS)
Circular ball surface (FAIL) surface (PASS)
~ 50.8 µm
(2 mil)
smaller than Good solder Good joint
FCBGA ball Solder Solder Solder “dome”
diameter dome wetting
balling
FCBGA
Solder balling
FCBGA
FCBGA
Before reflow After reflow
Intel Confidential
Module 4
4.6 Component-Based Screening: Paste-to-Ball

Wetting Test (2 of 2)
Solder Balling vs HoP rate
Solder Balling, %
HoP Fallout, %
Solder “dome” (PASS)
Example Only Example Only

 Solder ball formation on FCBGA balls can be correlated to the HoP
fallout rate by SMT reflow.
 Higher solder balling % shows higher HoP fallout rate.
 Good wetability of the solder paste to the solder balls is a key property
to ensure no HoP.
Intel Confidential
Module 4
4.6 Component-Based Screening: Paste Oxidation

Resistance Test (1 of 3)
Graping / strawberry effect indicates poor thermal stability of rosin
and poor oxidation resistance of flux in paste to protect solder powder
at outer surface. Graping shows non-coalescence of solder powder on
outer layer of solder joint.
Experimental Conditions:
 Printed solder pastes on PCB test
coupons with different pad sizes and
surface finishes (ImAg, OSP and LF
HASL). Stencil thickness used: 102 um
(4 mil).
 Run coupons through standard reflow.
 Visually evaluated degree of graping /
strawberry using 40X microscope.
Good coalesce of solder
particles
PCB Test Coupon PCB Test Coupon

Non coalescence of solder
PCB Test Coupon particles
PCB Test Coupon Risk for HoP

PCB Test Coupon
defects
Intel Confidential
Module 4

Resistance Test (2 of 3)
Graping / Strawberry Effect vs HoP rate

Example Only
Example Only
HoP Fallout, %
203 254 305 µm
[8] [10] [12] mil
SMT Paste
 Non-coalesce of solder particles with decreasing

stencil aperture can be correlated to HoP fallout rate.
Intel Confidential
Module 4

Resistance Test (3 of 3) Example Only
R R G R
R
R G G G
G
Y
R R
G
Y B B B B B B B B B B B B B
G G B B B B B
Y B
B
B
152 203 254 305 356 406 457 µm 152 203 254 305 356 406 457 µm 152 203 254 305 356 406 457 µm
(6) (8) (10) (12) (14) (16) (18) mil (6) (8) (10) (12) (14) (16) (18) mil (6) (8) (10) (12) (14) (16) (18) mil
Graping / Strawberry Observations:

 Defect is paste volume-dependent: Less graping is observed
B with larger pad sizes which have higher paste volumes.
G  Can be used to identify paste suitable for finer pitches/ smaller
Y pad sizes and for mitigating HoP defects.
R  Degree of Graping varies with different PCB surface finishes,
thus performance of solder pastes can potentially be tuned by
selection of different finish.
Intel Confidential
Module 4
4.6 Component-Based Screening:

Paste Bake Test (1 of 2)
Conditions:
 FCBGAs were placed on PCBs with
freshly printed paste.
 PCB/FCBGA sandwiches were heated
in stand-alone oven for 6 min at 180 C.
 After cooling, FCBGAs were removed
from PCBs and PCB lands were
examined for failures – paste lift off.
Intel Developed Setup
Top Board View
Example Only
Side View Side View
Note: 100% correlation (SMT vs. Paste Bake yield)
is not expected. Reason: Paste bake test only looks
at initial phase of the NWO mechanism (25–180°C).
 Paste Bake test indicates solder pastes with bake yield of

70% or above are good candidates to minimize or
eliminate NWO defects.
Intel Confidential
Module 4
4.6 Component-Based Screening:

Paste Bake Test (2 of 2)
Video: Paste Bake Test
 Video shows
example of the
solder paste
bake test being
performed at
Intel.
 FCBGA with
printed paste is
baked in oven
for 6 minutes
at 180 deg C.
After cool
down, remove
FCBGA from
the PCB and
perform visual
inspection. Watch Video on Brightcove*
Intel Confidential
Module 4
4.7 Solder Paste Screening Tests – Summary Table

Component-
Instrument-
Based
Based Screening Test Benefit(s) Desired Result(s)
Screening
Tests
Tests
Tackiness  Tests paste tackiness Low rate of tack force change

(HoP & NWO test) (thermal stability). per Degree C.
Cu Wire  Tests paste’s solderability /

Higher wetting force & shorter
(NWO test for PCB wettability to Cu/OSP
Wettability surface.
wetting time.
lands with OSP SF)
NWO Prevent: Wets best to
PCB Surface
Finish  Tests paste’s wetability to desired PCB finish.
(HoP & NWO test) PCB surface finishes. HoP Prevent: Wets equally to
Wetability LF HASL & PCB Surface.
Solidification  Identifies paste’s
Low solidification temperature.
Temperature (HoP & NWO test) solidification temperature.
Paste-to-Ball  Tests paste’s wetability to Solder “dome” or perfect

Wetting Test (HoP Test) a package solder ball. coalesce.
Paste
Tests stability & oxidation
Oxidation  Good coalesces of solder
resistance of solder paste
Resistance (HoP Test) powder particles.
flux.
Test
Tests paste’s adhesion to
Paste Bake  Paste does not lift off from the
package balls and PCB
Test (NWO Test) lands.
PCB.
Summary table for the solder paste screening tests covered in this module.
Intel Confidential
Module 4

Question 1 of 6
What is the composition of SAC 405 alloy (Ag/Silver% + Cu/Copper% +

Sn/Tin%) (choose one)?
A) SAC 405 = 0.4% Ag + 0.5% Cu + 99.1% Sn.

B) SAC 405 = 4.0% Ag + 0.5% Cu + 95.5% Sn.
C) SAC 405 = 0.4% Ag + 5.0% Cu + 94.6% Sn.
D) SAC 405 = 4.0% Ag + 5.0% Cu + 91.0% Sn.
SAC XYZ = X.Y% Ag + 0.Z% Cu + remaining % of Sn
Correct!
Intel Confidential
Module 4

Question 2 of 6
What key components of flux (in the solder paste) that clean oxides and
are responsible for the solderability of component to PCB (choose one)?
A) Activators. • Every solder paste supplier has a different

activator packages in their pastes.
B) Stabilizers.
C) Synthesizers. • Most solder pastes’ fluxes have a blend of
activators rather than just one activator.
D) Energizers.
• Each one becomes highly active at a
different temperature during the reflow.
Correct!
Intel Confidential
Module 4

Question 3 of 6
What are three key solder paste properties impacting solder joints
defects formation? (choose all that apply)?
A) Thermal Stability.
B) Fast wetting time and higher wetting force to the surface of interest.
C) Low solidification temperature.
All of the above.
Correct!
Intel Confidential
Module 4

Question 4 of 6
What are the two FCBGA component-based solder paste screening

tests Intel performs for Head on Pillow (HoP) risk prediction (choose
two)?
A) Paste Bake Test.

B) Paste-to-Ball Wetting Test.
C) Paste Oxidation Resistance Test.

D) PCB Surface Finish Wetability.
Correct!
Intel Confidential
Module 4

Question 5 of 6
What is the one FCBGA component-based solder paste screening test

Intel performs for NWO risk prediction (choose one)?
A) Paste Bake Test.

B) Paste-to-Ball Wetting Test.
C) Paste Oxidation Resistance Test.

D) PCB Surface Finish Wetability.
Correct!
Intel Confidential
Module 4

Question 6 of 6
A ≥ ____% yield, from the Paste Bake Test, would indicate a good
solder paste candidate to minimize or eliminate Non Wet Open (NWO)
defects (choose one)?
A) ≥ 50%. Top Board View
B) ≥ 60%.
C) ≥ 70%.
Side View Side View
D) ≥ 80%.
Correct!
Intel Confidential
Module 5: SMT Process Parameters Impacting
SJQ

Intel Confidential

Introduction 6.6 3D
Check Sectioning
Table Check
2.9 Knowledge
Check
Intel Confidential
Module 5
Module
DOE Design of Experiments

HoP Head on Pillow
NWO Non Wet Open
PRT Peak Reflow Temperature
TAL Time Above ≥ 220 oC
Intel Confidential
Module 5
5.1 Introduction
 Robust solder joint formation / high SMT yields are a function of
many SMT parameters.
– Solder paste formulation, Solder paste volume, Reflow
profile/environment, Package and Mother board warpage, etc…
 Optimizing the SMT process & materials can overcome the
increase in package / mother board dynamic warpage, resulting
in acceptable SMT yields.
 For Intel® FCBGA packages, Solder paste formulation and solder
paste volume optimization (Over-print at package corners) are
the two most effective ways to mitigate solder joint formation
defects.
 Starting with Shark Bay Mobile platform, Intel® will be
performing a higher level of SJQ characterization on Intel®
FCBGAs and will provide this information in the Platform MAS
document.
Intel Confidential
Module 5
5.2 Solder Paste Volume Optimization (1 of 7)
Stencil Design Guidelines

• Solder paste volume optimization D
𝜋𝑫𝟐
is a critical factor to reduce/ 𝑷𝒂𝒅 𝑨𝒓𝒆𝒂 =
𝟒
eliminate defects (i.e., HoP or T 𝑾𝒂𝒍𝒍 𝑨𝒓𝒆𝒂 = 𝜋𝑫𝑻
NWO or Solder Bridge defects) in
SMT assembly.
𝑷𝒂𝒅 𝑨𝒓𝒆𝒂 = 𝑾 × 𝑳
• Solder paste volume can be
controlled by stencil design. T 𝑾𝒂𝒍𝒍 𝑨𝒓𝒆𝒂 = 𝟐 × 𝑾 + 𝑳 × 𝑻
W
• Optimal stencil design is critical to L
ensure consistent release of solder 𝑷𝒂𝒅 𝑨𝒓𝒆𝒂
paste (transfer rate) from stencil 𝑨𝒓𝒆𝒂 𝑹𝒂𝒕𝒊𝒐 =
𝑾𝒂𝒍𝒍 𝑨𝒓𝒆𝒂
openings.
– Area Ratio ≥ 0.66 𝑨𝒑𝒆𝒓𝒕𝒖𝒓𝒆 𝑾𝒊𝒅𝒕𝒉
– Aspect Ratio ≥ 1.5 𝑨𝒔𝒑𝒆𝒄𝒕 𝑹𝒂𝒕𝒊𝒐 =
𝑻𝒉𝒊𝒄𝒌𝒏𝒆𝒔𝒔
Optimal stencil aperture design is necessary to

achieve the best solder transfer rate.
Intel Confidential
Module 5
Benefits of Over-printing
• Higher solder crest height (H’1 and H’2) helps to maintain contact between the
molten solder paste and package solder balls during reflow.
• Extra flux from solder paste protects against oxidization of solder balls which
can prevent HoP defects.
After Solder Paste Printing

d1 d2 d3
Solder mask
d1, d2, d3 Diameter of solder paste
Land
PCB H’1 Crest height difference
between d1 and d2
After Reflow Process H’2 Crest height difference
H’2
H’1 between d2 and d3
Solder mask
Land
PCB
Additional solder paste volume (i.e. over-printing)

provides margin to overcome HoP and NWO defects.
Intel Confidential
Module 5
Module
Benefits of Over-printing Example Only
Crest Height
on 1:1 Paste
Crest Height (um)

1:1 Paste
volume volume
Post Reflow Crest Height
Increase in paste volume (i.e. stencil opening) increases the crest height &
help close the gap between PCB and package solder balls in reflow.
Intel Confidential
Module 5
Consideration for Over-printing
• Paste print volume and pad size variations impact post reflow solder crest heights.
• Square stencil aperture design deposits (~25%) higher volume compared to
round aperture design.
• Diamond shape stencil aperture design can provide additional stencil air gap to
address solder bridging risk.
• Rectangular stencil aperture design can also be used in outer row pads to provide
additional paste volume with increased stencil air gap.
Example Only
Square Aperture Diamond Aperture
Circular Aperture
Design with Design with rounded
Design
rounded corner corner
Stencil aperture design can be used to increase paste volume at risk areas.
Intel Confidential
Module 5

FCBGA land without over-print
Consideration for Over-printing
• Follow minimum stencil air gap recommended to

prevent solder bridge defects.
Pitch Minimum Air Gap Recommendation
≥ 0.5mm ≥ 203µm (8mils)

< 0.5mm ≥ 152µm (6mils)
Stencil Air Gap

FCBGA land with over-print
• Stencil aperture position can also be offset to meet

the stencil air gap requirement.
• Solder paste volume monitoring using automated

inspection system is recommended for HVM.
Follow stencil air gap recommendation to prevent solder bridge defects.
Intel Confidential
Module 5
SMT Process Window Characterization (Cliff Study) for Solder Paste Volume
Example Only
Paste
Volume
Variation
(± 20%)
Generic FCBGA example
Target Paste Volume
Check the specific platform Manufacturing Advantage

Service (MAS) for stencil design guidance.
Intel Confidential
Module 5
Impact of Paste Volume

Example evaluation was conducted, on FCBGA product (31 x 24mm, 0.65mm
pitch) to understand the impact of increased solder paste volume on SJQ.
The results confirmed that, while holding all other factors constant, over-printing
with additional solder paste reduced the NWO defect rate from 96% to 8%.
Example Only
DOE Solder Normalized Paste PCB Reflow Reflow SMT Qty SMT Defect Rate Comments
Leg Paste1 Volume @ NCTF Warpage Profile Ambient (Pry Test)
pads
NWO defects observed in
1 Paste H 1.0X +50um MAS Air 25 96% (24/25) package corner (A61
corner)
NWO defects observed in
2 Paste H 1.6X +50um MAS Air 25 8% (2/25) package corner (A61
corner)
Hammer Test Conditions

(Stress Test to Force Failures)
for Package Warpage
Solder paste volume modulates solder joint quality.

Note 1: Solder paste formulation influences the failure/defect signature, for example NWO versus HoP, etc.
Intel Confidential
Module 5
5.3 Reflow Parameters Optimization (1 of 9)
Reflow profile optimization is a critical factor to reduce / eliminate HoP

defects in SMT assembly.
• Solder Joint Peak Reflow Temperature (PRT)
• Time Above Liquidus (TAL)
• Soak Time
• Reflow Environment
Impact of Peak Reflow Temperature

• If the solder joint peak reflow temperature is not above the minimum peak reflow
temperature requirement (Liquidus temperature + 15 oC) of the solder alloy, solder
paste and FCBGA balls will not collapse, leading to a incomplete reflow or cold solder
joint defect.
Solder joint peak reflow temperature must be above minimum peak

reflow temperature requirement to avoid cold solder joint defect.
Intel Confidential
Module 5
Impact of Peak Reflow Temperature (Phase Diagram)

Lead Free SAC alloys are not eutectic alloy. Solder joint peak reflow temperature
must be above minimum peak reflow temperature to avoid cold solder joint defects.
Sn / 3.8Ag / 0.8Cu
Solidus=Liquidus=217°C
Alloys with lower silver content
Sn / 3.0Ag / 1.5Cu raises the melting temperature.
SAC 315
Sn / 4.0Ag / 0.5Cu
The liquidus temperature is
SAC 405
Sn / 3.0Ag / 0.9Cu
ranging between 217°C to 258°C.
SAC 309
Sn / 3.0Ag / 0.5Cu
SAC 305
Minimum Peak Temperature
Sn / 2.0Ag / 0.5Cu for Lead Free Solder
SAC 205
Sn / 1.0Ag / 0.5Cu Solder SAC SAC SAC SAC
SAC 105 Alloy1 105 305 405 0307
Sn / 0.3Ag / 0.7Cu
SAC 0307 Liquidus 241°C 235°C 235°C 242°C
Sn / 0.7Cu / Ni +15°C
SN100C 1Applies to Solder Ball and Solder paste
Reference: Werner Engelmaier

“Inadequate peak reflow Minimum peak reflow temperature must be above the
temperatures” Global SMT & liquidus temperature of the solder alloy used.
Packaging 8.6 -June 2008
Intel Confidential
Module 5
Reflow Profile Parameter ΔT
Temperature difference between the Coolest to the Hottest Point is

defined as Delta T (ΔT).
Reflow profile parameter ∆T have strong impact to HoP defect.
∆T on the board is driven by board design, material, and type of

components. Reducing ∆T is always a challenge during profile
development.
Minimize Delta T (ΔT) to reduce HoP defects.
Intel Confidential
Module 5
Impact of ∆T in FCBGA
When there is a temperature delta between the outer and inner FCBGA balls,
solder paste will melt first at the outer solder balls before the interior solder
balls. Two attributes of ∆T significantly impact the solder joint formation.
• Liquidus Time Delay (LTD)
• True TAL
The time difference between the FCBGA inner & outer ball at liquidus
temperature is critical, and is defined as Liquidus Time Delay (LTD).
The time difference between last melting joint and first solidification joint is
define as True TAL.
Example Only True TAL
Representative FCBGA TC Location
Outer row solder ∆T

joint Thermal couple
Inner row solder

joint Thermal couple
Time [sec]
Intel Confidential
Module 5
Impact of LTD and True TAL
The liquidus time delay (LTD) that delayed the package ball from collapsing is
plotted against the true TAL which is the TAL of the FCBGA balls after the
package collapses.
Use this as a guideline

when developing the
reflow profile or to
troubleshoot HoP defect
issue.
HoP Zone
HoP
Defect
No
Published in SMTAI
Yes Example Only
October 2009
As LTD increases the HoP defect zone is increased (caused by a delay in

package ball collapse). Increased TAL is necessary in order to prevent HoP.
Intel Confidential
Module 5
Impact of Peak Temperture

and TAL
Increase in Peak Reflow

Temperature and Time Example Only
Above Liquidus can mitigate
HoP defects.
Example Reflow Process Parameters HoP Defect Rate

Nitrogen1 (N2)
Only Peak Temp °C TAL [sec] Air Reflow
[02<1500 PPM]
Low Range 226 - 234 29 - 56 90% 0%
Mid Range 233 - 241 53 - 75 25% 0%
Recommended 236 - 243 73 - 93 10% 0%
Increase in peak temperature, TAL and reflow

environment decreased HoP defect rates.
1Nitrogen is not required but its use has been shown to modulate SMT Yield
Intel Confidential
Module 5

Video: Simulated SMT Process
Impact of TAL and Peak Temperature on HoP
Reflow Temperature (C)
 Video shows HoP defects

corrected by long TAL and
Peak Temperature Time (minutes)
Optimization.
 Left ball: Wetted
immediately at 225 °C.
 Center ball: HoP at
beginning, wetted after
90s TAL at 246°C.
 Hammer (worst case) Test

Conditions:
 Bench-top oven heating, 
120s Soak Time and  90s
TAL, Peak Temp: 250C; air
ambient.
 Stencil Design: 381 um Watch Video on Brightcove*
round aperture, 75 um
thickness.
Intel Confidential
Module 5
Impact of Soak Time:

Example Only
Example of a particular lead-free paste and
impact of Soak Time to HoP defects.
In this example, a shorter Soak Time helped

reduce the HoP defect rate, but the optimal
Soak Time is based on the solder paste used
(For Soak Time, please follow
manufacturer’s recommendations).

Example Reflow Process Parameters

HoP Defect
Only Time Between Time Between TAL (≥ 217
150 to 175 oC 175 to 217 oC oC)
Peak Reflow
Temperature oC
Rate
Short Soak 13 sec 56 sec 65 sec 242 7%
Medium Soak 33 sec 56 sec 67 sec 241 22%
Long Soak 162 sec 63 sec 60 sec 241 100%
Soak time impact on HoP depends on the type of solder

paste used and its behavior in high temperature.
Intel Confidential
Module 5
Example of Reflow Profile Characterization Example Only

Time Above
Leg Peak Temp Soak Time
217°C
Example Only Spec Window
240 +/- 5°C 50 +/- 15°C 190 +/- 30 sec
(235-245°C) (35-65 sec) (160-220 sec)
Leg 1 Low Low Low
Leg 2 Low Low High
Leg 3 High High Low
Leg 6 Leg 5 Leg 4 High High High

Leg 5 (high
Mid Mid Mid
ramp)
Leg 6 Mid Mid Mid
Leg 3
Leg 5 Leg 4
Leg 6
HoP Risk Area
Reflow validation should be performed

on the extreme points of the profile Example Only
within the reflow process window.
Intel Confidential
Module 5
5.4 Intel SMT Process Characterization Approach

(1 of 3)
Example from Shark Bay Platform
Characterization DOE Plan
Impact of Paste Volume to SMT Yield

• Intel characterization DOEs evaluate
FCBGA package performance as a
function of paste volume, paste type,
Example: See
package warpage and Reflow profile.
Shark Bay MAS
for Details
• Future evaluations will look into:
• Impact of 4mil thick stencil.
• Impact of reduced pad sizes when
compared to Intel pad size
recommendation.
Stencil Thickness = 127um (5mils), Air gap = 203um (8mils)
Intel Confidential
Module 5

(2 of 3)
Impact of Paste Type to SMT Yield
A hammer test (stress test to force failures) was
Example: See Shark Bay performed across many different solder paste
MAS for Details formulations thus far to evaluate SMT yield performance
on Shark Bay Mobile FCBGA packages.
– Solder Pastes included three types: Halogenated (H),
Low Halogen (LH), Zero Halogen (ZH).
– SMT Yield % is based on T=0 solder joint defects from
e-test & Failure Analysis (i.e. NWO, HoP, Bridging).
 Packages:
– Shark Bay Mobile FCBGA test packages with a warpage
distribution of -200 to -300 µm (-250 µm average)
 SMT Parameters:
– Forced low solder paste volume at NCTF corners (1:1 /
no over-print, ~0.0165 cu. mm (~1,005 cu. mils)).
– Air reflow environment, Time Above ≥220°C 60-70
seconds, Peak Reflow Temperature 240 °C +/- 5 °C,
OSP PCB surface finish.
• Solder paste is the primary modulator of NWO defect

• Solder paste formulations that yield > 80% from hammer test are recommended for use
with the Shark Bay Mobile FCBGA packages, to achieve acceptable SMT Yields.
• 80% SMT yield line was drawn based on internal testing data. It was found that if a
particular solder paste provides > 80% SMT yield at the hammer test conditions,
when over-printing solder paste a 100% SMT yield was achieved.
Intel Confidential
Module 5

(3 of 3)
Reflow Characterization Example: See Shark Bay MAS for Details
Example: See Shark Bay MAS for Details
Leg 3
Leg 2
 Reflow parameters showed no significant

impact to SMT yield performance for solder
paste A1, B3 and C1.
 For Solder paste B1, Increase in Soak Time

decreased SMT defect rate.
Leg 4 – Indicates Soak Time is paste supplier dependent.
Shark Bay Mobile FCBGA

SMT Reflow Window
Recommended reflow settings for Shark Bay Mobile FCBGA packages

– Peak Reflow Temperature = 240 ± 5 oC
– TAL (≥ 220 oC) = 60 to 90 sec (Air) / 40 to 90 sec (N2)
– Soak Time, please follow paste manufacturer recommendation
Intel Confidential
Module 5

Question 1 of 6
What are the two critical factors needed to ensure consistent release of
solder paste (transfer rate) from stencil openings (choose two)?
• Solder paste volume can be controlled

A) Area Ratio. by an optimal stencil design.
B) Aspect Ratio. • An optimal stencil design (with Area

Ratio ≥ 0.66 and Aspect Ratio ≥ 1.5) is
C) Stencil Ratio. critical to ensure consistent release of
solder paste (transfer rate) from
D) Flux to Paste Ratio.
stencil openings.
𝑷𝒂𝒅 𝑨𝒓𝒆𝒂
𝑨𝒓𝒆𝒂 𝑹𝒂𝒕𝒊𝒐 =
𝑾𝒂𝒍𝒍 𝑨𝒓𝒆𝒂
𝑨𝒑𝒆𝒓𝒕𝒖𝒓𝒆 𝑾𝒊𝒅𝒕𝒉
Correct! 𝑨𝒔𝒑𝒆𝒄𝒕 𝑹𝒂𝒕𝒊𝒐 =
𝑻𝒉𝒊𝒄𝒌𝒏𝒆𝒔𝒔
Intel Confidential
Module 5

Question 2 of 6
What is the minimum air gap that Intel recommends in stencil design,
for ≥ 0.5 mm pitch FCBGA packages, to avoid solder bridge defects
(choose one)?
A) 152 µm (6 mils).
B) 203 µm (8 mils).
C) 254 µm (10 mils).
D) 305 µm (12 mils).
Correct!
Intel Confidential
Module 5

Question 3 of 6
What two type of defects can be overcome by over-printing in FCBGA

package corner areas and several rows inward (choose two)?
A) Solder Wicking Defect.

B) Non Wet Open Defect.
Always consult the Platform MAS
C) Head on Pillow Defect. for specific FCBGA component
D) Solder Bridging Defect. over-printing recommendations.
Correct!
Intel Confidential
Module 5

Question 4 of 6
These are the four main reflow parameters that Intel has found to have
an impact on solder joint formation (True or False)?
1) Solder Joint Peak Reflow Temperature (PRT)

2) Time Above Liquidus (TAL)
3) Soak Time
4) Reflow Environment
A) True.
B) False.
Correct!
Intel Confidential
Module 5

Question 5 of 6
Solder joint minimum peak reflow temperature must be ____°C above

the liquidus temperature of the solder alloy used (choose one)?
A) 5 °C.
B) 10 °C.
C) 15 °C. To Avoid Cold Solder Joints.
D) 20 °C.
Correct!
Intel Confidential
Module 5

Question 6 of 6
______ in Time Above Liquidus (TAL) and Peak Reflow Temperature

(PRT) were shown to decrease Head on Pillow (HoP) defect rates on
FCBGAs (choose one).
A) Increase. TAL: Increasing TAL provides additional

time for the solder be molten and make a
B) Decrease.
solder joint even during the cool down of
the reflow cycle.
PRT: Increasing PRT minimizes the

temperature difference (LTD / Liquidus
Time Delay) between outer and inner row
allowing for uniform solder joint collapse..
Correct!
Intel Confidential
Module 6: SJQ Inspection & Analysis

Intel Confidential

Introduction 6.6 3D
Check Sectioning
Table Check
2.9 Knowledge
Check
Intel Confidential
Module 6
Module
2D/3D 2-Dimensional/3-Dimensional
BGA Ball Grid Array
HoP Head on Pillow defect
KOZ Keep-out Zone
MB Mother Board
NCTF Non-Critical to Function
NWO Non Wet Open defect
OM Optical Microscope
QTM Quick Turn Monitor
ROI Return on Investment
SB Solder Ball
SJ Solder Joint
SOH Stand off heights
VCC Common Collector Voltage
VSS Supplier Source Voltage
XS Cross-sectioning
Intel Confidential
Module 6
Module
6.1 Introduction (1 of 2)
• Customers should check SJQ on their products.

• This module will explain recommended solutions:
1. Quick turn measurements with minimal impact to production.
2. Detailed destructive inspection and analysis.
3. Detailed non-destructive inspection and analysis for high risk
locations and root cause analysis.
• Intel’s recommended flowchart for SJQ monitoring & analysis:
1. Use quick turn methods as much as possible (Caveat: Some
issues and fundamental knowledge may be missed).
2. Include at least a minimal sample set for detailed inspection and
analysis.
Intel Confidential
Module 6
6.1 Introduction (2 of 2)
SJQ monitoring & analysis methods for understanding what options are available
and the trade offs for each option.
The table below shows an overview of SJQ analysis & methods:
Quick turn Destructive MB Design Expense HoP & NWO Detection?
monitor to MB? Change (USD)
(QTM)? Required?
Optical Microscope (OM) <25K HoP/NWO detection for edges
Optical Microscope (OM) NO only
<50K
– Fiber optic enabled
In-Circuit NCTF SJ PCB YES NO Detects NWO on NCTFs. Low
YES Various
E-Test detection rate of HoP.
2D X-ray >250K Limited HoP/NWO detection
3D Laminography >250K Detects opens only
Dye & Pull As per
local lab Detects HoP and NWO
Pull Only NO
YES setup and
Cross Sectioning NO operating HoP/NWO detection for cut
costs rows/columns only
3D X-ray Size
>500K Detects HoP and NWO
dependent
There is no perfect SJQ inspection & analysis metrology.

A combination of several metrologies may be the best option.
Note: Engineering skills required for optimal metrology ROI
Intel Confidential
Module 6
6.2 SJQ Monitoring & Analysis Recommendations

1. During SMT build for high risk location risk mitigation and GRC checks:
• Use either optical microscope and/or in-situ NCTF e-testing for higher risk locations.
• Use either 2D X-Ray or 3D Laminography for GRC health check across full package.
2. After SMT build for complete risk assessment
• Use Dye & Pull (or Pull only) to check for NWO/HoP on randomly drawn samples.
3. Failure root causing and process improvements:
• Use cross-sectioning (XS) to check SJ heights and shapes.
• Use 3D X-Ray to investigate failure type and locations, especially for units identified during GRC health checks.
3  Root cause
1 High Risk Locations understanding
 Slow and/or
OM E-test destructive tests
Issues Yes 3D
SMT build XS
observed? X-ray
Across Full Package Yes
D&P Pull only
2D 3D
X-ray Lamin.
No
Issues
2
SMT process
Improved
observed?
D&P Pull only
 QTMs on higher risk
areas
 Minimal production  Destructive testing No
impact  Issue identification
 Non-destructive on full package
Process Freeze1
Repeat as necessary
1 Process freeze implies no changes are made to the process at this point and line stability is maintained
Intel Confidential
Module 6
6.3 Optical Microscope Quick Destructive? Design HoP? NWO?

turn? Change?
Since HoP and NWO defects are most times
at the edges or corner of the package, YES NO NO Edge Edge
only only
optical microscope solutions can capture
these defects
1. Direct imaging by tilting samples Pros:
• Low Cost Solutions (<$50K USD)
NWO • Can be used as a quick edge defect detector
Cons:
• Can detect only package corner or edge
defects (HoP, NWO, solder bridging)
HoP • Direct imaging subject to interference by
population of other surface components
• KOZ required (approx. 5mm) around the
component for a clear view to the FCBGA
(hard with dense assembly) for fiber optic
solutions.
2. Fiber optic microscope
Intel Confidential
Module 6
6.4 NCTF Solder Joint Test

Quick Destructive? Design HoP? NWO?
turn? Change?
YES NO YES LOW NCTF only
Intel suggestion: Include mother board test features to test the

connectivity of corner NCTF (Non-Critical to Function) Solder Joints (SJ)
on mobile FCBGA processor and chipset packages
Background:
As we shift to thinner system designs, SMT is becoming more challenging with
the corners being more susceptible to solder joint defects.
Testing the corner NCTF solder joints is a good way to screen potential solder
joint defects and check health of process.
Intel’s mobile processor and chipset FCBGA packages feature corner NCTF SJ
testing capability.
– Mobile FCBGA processor corner NCTF SJ’s have daisy chain connections in all 4
corners.
– Mobile FCBGA chipset corner NCTF SJ’s are connected to either the package POWER
or GROUND planes.
Note: Refer to the Platform MAS for more details regarding Corner NCTF solder joint testing.
Intel Confidential
Module 6
6.4 NCTF Solder Joint Test (Mobile

Processor FCBGA’s)
Examples: Top View
Example: Side View
Corner #1 Corner Daisy Chains Corner #2
NCTF Balls NCTF Balls
Package
Motherboard
Min test pads, corner
Test Test Test Test daisy chain coverage
Pad Pad Pad Pad
• Corner NCTF balls have daisy chain connections routed inside MB Connections
the processor package. Package Connections
– Daisy chain coverage is not 100% of corner NCTF solder joints.

• Customer should add the corresponding Mother Board (MB)
pad-to-pad traces and test pads as necessary.
– Minimum of 2 Test Pads per corner are required to test the corner
daisy chain.
– Further isolation is possible down to solder ball pair if more than 2
test points are added.
• Customer uses the test pads to check corner NCTF SJ
connectivity.
Max test pads, solder
Note: Refer to the Platform MAS for more details regarding Corner NCTF ball pair isolation
solder joint testing.
Intel Confidential
Module 6
6.4 NCTF Solder Joint Test (Mobile Chipset

FCBGA’s)
Example: Ground Plane (Side View) Example: Top View
• VSS NCTF balls are connected to Ground in the
Package
VSS NCTF Ball

Package Ground
Planes
3 TPs per Corner 4 TPs per Corner 7 TPs per Corner

Motherboard MB Connections
Test Pad Test Pad • Two examples are shown (left) for Ground or Power
plane connections, depending if NCTF balls are VSS or
Example: Power Plane (Side View) VCC.
• VCC NCTF balls are connected to Power in the – Ground Example: Corner NCTF solder joints are
Package isolated by testing through the connected package
ground plane through the many package Ground
VCC NCTF Ball balls.
Package Power
Planes – Power Example: Corner NCTF solder joints are
isolated by testing through the connected package
power plane through the many package Power balls.
• Customer to add corresponding test pads on the MB
to each corner NCTF solder ball for testing.
Motherboard
• Customer can decide which specific balls to test and
Test Pad Test Pad fault isolation is available down to one specific ball
(See Top View Example above for several options).
• Customer can develop either a short-to-ground or a
Note: Refer to the Platform MAS for more details short-to-power test to check corner NCTF SJ
regarding Corner NCTF solder joint testing. connectivity.
Intel Confidential
Module 6
6.5 2D X-Ray
Tilt detector 2D X-Ray can be used as a QTM turn? Change?
for a full package limited HoP, NWO and YES NO NO Limited Limited
solder bridging or void defect detection.
OM image for edge HoP
X-ray source
PCB
HoP
Pros:
• Can detect solder joints with HoP, NWO
and solder bridging defects
detector • Less expensive and faster than 3D X-
Ray Tool
Tilt detector for HoP and NWO Cons:

detection: • Expensive Equipment (>$250K USD)
1. HoP shows up as disjointed SJs • Need capability to tilting x-ray detector
• Resolution not as high as 3D X-Ray Tool
2. NWO shows up as a circular SJ • Limited HoP and NWO detection by tool
3. Regular SJs appear as an NWO resolution and operator skill
ellipsoidal surface
Intel Confidential
Module 6
6.6 3D Laminography Tool

This tool take pictures of equidistant turn? Change?
slices in the Z-direction, through the YES NO NO Opens only
areas of interest (i.e. solder ball) and

can be used for gross defect detection.
Missing joints
Void
Pros:
• Less expensive and faster than 3D X-Ray Tool
• Detects SJ bridging and voids
Cons:
• Cannot detect HoP or NWO defects, unless they
are gross defects
• Expensive Equipment (>$250K USD)
Intel Confidential
Module 6
6.7 Dye and Pull (1 of 2) Quick Destructive? Design HoP? NWO?

turn? Change?
Pros: NO YES NO YES YES

• Low Cost Solution (as per local lab
operating costs)
• All package HoP, NWO and SJ bridging HoP NWO
defects can detected
Cons:
• Destructive to MB
• Labor intensive
• Requires a controlled lab environment Package
setup side
HoP dimple on solder ball
Board
side
Dye and Pull (or Pull only) is the best method to capture all HoP,
NWO and solder bridging defects across the entire package.
Intel Confidential
Module 6
6.7 Dye and Pull (2 of 2)
Step 6 - Apply tape

around the component (if
Step 3 - Submerge Step 4 - Use Vacuum to Step 5 - Dry required)
Component in Dye assist in dye penetration Sample in Oven
For an easier way to identify

HoP or NWO failures, do not add
the dye on the unit (skip steps
Step 7 – Place weld nut
1-5). and apply epoxy and let
dry
Step 2 - Clean component
using a flux cleaning agent,
to prepare for Dye step
Step 1 - Mill component from Step 9 – Use a Step 8 - Apply tensile force
the motherboard with 1” microscope to inspect using motorized pull tool to
clearance around the part the component defects Pulling machine remove component from board
Intel Confidential
Module 6
6.8 Cross-Sectioning (1 of 2) Quick Destructive? Design HoP? NWO?

turn? Change?
NO YES NO Edge only Edge only
Fixture and prep:
Pros:
• Low cost solution (as per local lab operating costs)
• Shows stand off heights (SOH), grain structure, IMC and other joint details
• Shows HoP/NWO on the cross-sectioned row/column
Cons:
• Destructive to MB
• Labor intensive
• Requires controlled lab environment setup
• Cannot identify defects on non- cross sectioned rows/columns
After epoxy potting:
FCBGAs:
Cutting line
After cut and polish:

BGA sockets:
Top view
Intel Confidential
6.8 Cross-Sectioning (2 of 2) Module 6
Example FCBGA solder joint height variations (as seen by Cross-Sectioning)

Lower warpage example Higher warpage example
Corner Middle Corner Corner Middle Corner
BG61 BG1 BG61
BG1 BG30 BG30
FCBGA Package
Concave (-) Warpage
Solder Joint Height
Row
BG
Lower Warpage Example Higher Warpage Example
= XS SJ height data location Pin / Ball Location on Example FCBGA Package
Due to dynamic warpage behavior at reflow,

package corners solder joints are taller than middle solder joints.
Intel Confidential
Module 6
6.9 3D X-Ray Tool (1 of 2) Quick Destructive? Design HoP? NWO?

turn? Change?
NO Size dependent NO YES YES
 Next slide: 3D X-Ray video’s
*Other names and brands may be

claimed as the property of others.
NWO NWO
Pros: NWO
• High resolution non
destructive 3D imaging of a
sample
• Good detection of solder joint
with HoP, NWO and solder NWO HoP
bridging defects
• Variable objective lens for
magnification flexibility
Cons:
• Expensive Equipment HoP HoP
(>$500K USD)
• Cannot test large boards non-
destructively
• Slow test times even for small
sample sizes
Intel Confidential
Module 6
6.9 3D X-Ray Tool (2 of 2)
3 Videos: Output from 3D X-Ray Tool
Watch Video on Watch Video on Watch Video on

Brightcove* Brightcove* Brightcove*
Intel Confidential
Module 6

Question 1 of 5
What is the best inspection method to capture Head on Pillow (HoP)

and Non Wet Open (NWO) defects across the entire FCBGA package,
with the faster processing time (choose one)?
A) Cross Section.
B) 3D X-Ray.
C) Optical Microscope.
D) Dye & Pull (or Pull only). All of the potential SJQ defects
(HoP, NWO, solder bridging) can
be detected using Dye & Pull (or
Pull only if prefer not to use Dye).
Correct!
Intel Confidential
Module 6

Question 2 of 5
Can the Optical Microscope (OM) inspection provide FCBGA package

edge or package interior inspection coverage (choose one)?
A) Package Edge. The Optical Microscope inspection

requires an un-obstructed view along
B) Package Interior.
the side edge of the FCBGA package.
Correct!
Intel Confidential
Module 6

Question 3 of 5
Which quick turn monitor (QTM) requires a mother board (PCB) design
change to implement (choose one)?
A) Optical Microscope (OM).

B) Corner Non-Critical To Function (NCTF) Solder Joint Electrical Test.
C) 2D X-ray.
D) 3D Laminography.
Mother board (PCB) test points
are required to be added into
the board design to test the
corner NCTF solder joints.
Correct!
Intel Confidential
Module 6

Question 4 of 5
Can a 2D X-Ray scan overlook the detection of Head on Pillow and Non
Wet Open defects for FCBGA packages (choose one)?
A) Yes. 2D X-Ray is limited by tool resolution

and operator skills. The correct tilt
B) No.
angle and rotation of the PCB has to
be identified along with a correct
analysis of the resultant image.
Correct!
Intel Confidential
Module 6

Question 5 of 5
Can a 3D X-Ray scan overlook the detection of Head on Pillow and Non
Wet Open defects for FCBGA packages (choose one)?
A) Yes. 3D X-Ray imaging provides a high

resolution solution to the detection of
B) No.
HoP and NWO defects, but at the
expense of processing time.
Correct!
Intel Confidential

SJQ MAS All in One For MAS Rev1 1

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Manufacturing With Intel® FCBGA Components for

Solder Joint Quality

Videos & Information Dynamic Warpage Fundamentals

Introduction to Solder Joint Quality (SJQ) . . . . . . . . . . . . . . Module 1

Defects Modes & Mechanisms . . . . . . . . . . . . . . . . . . . . . . . Module 2

Printed Circuit Board (PCB) and Package Warpage . . . . . . . . . Module 3

SMT Solder Paste Impacting SJQ . . . . . . . . . . . . . . . . . . . . . Module 4

SMT Process Parameters Impacting SJQ . . . . . . . . . . . . . . . . Module 5

SJQ Inspection & Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . Module 6

At the conclusion of this course the student can:

Deep technical training to help prepare Customers for the

Solder Joint Quality MAS (Manufacturing Advantage Service)

Module 1: Module 2: Module 3: Module 4: Module 5: Module 6:

Acronyms Found in this Module

CTE Coefficient of Thermal Expansion

*Other names and brands may be claimed as the property of others.

1.1 Definition of SJQ and SJR

Solder Joint Image (Cross Section)

This document will focus on SJQ on FCBGAs –> Producing well

1.2 Introduction & Challenges (1 of 3)

This document will provide a fundamental level of SJQ and dynamic

1.2 Introduction & Challenges (2 of 3)

Robust solder joint formation / high SMT yields

More Info in Modules

1.2 Introduction & Challenges (3 of 3)

Intel is performing a higher level of SJQ characterization on next

Example FCBGA Package Dynamic Example FCBGA Solder Paste Volume

More Info in Module 3 More Info in Module 5

1.3 Dual Core Mobile Z-Height Package Trend (1 of 2)

Mobile Dual Core FCBGA Processors

Dual core mobile FCBGAs are continuing on a Z-height reduction trend.

1.3 Dual Core Mobile Z-Height Package Trend (2 of 2)

Haswell Package Evolution

FCBGA / Single Die 2013 Shark Bay

The industry trend to thin is driving higher dynamic

1.4 Dynamic Warpage Challenges (1 of 3)

1.4 Dynamic Warpage Challenges (2 of 3)

1.4 Dynamic Warpage Challenges (3 of 3)

Need to optimize the SMT reflow process to minimize SMT defects.

1.5 Factors Potentially Influencing SMT

PCB Design Solder Mask Dam Package Design

Fishbone Surface Finish Thickness Full Grid vs. Peripheral

SMT Process and Materials

Module 1 - Knowledge Check: Multiple Choice

The industry transition to thinning system designs is driving Z-height

A) True. For example, the

Module 1 - Knowledge Check: Multiple Choice

Module 1 - Knowledge Check: Multiple Choice

A) Convex (+) Warpage “Sad Face”

Module 1 - Knowledge Check: Multiple Choice

A) Solder paste formulation optimization.

Module 1 - Knowledge Check: Multiple Choice

Where do customers find Intel’s specific platform SJQ (Solder Joint

A) Thermal Mechanical Design Guide (TMDG).

Solder Joint Quality MAS (Manufacturing Advantage Service)

Module 1: Module 2: Module 3: Module 4: Module 5: Module 6:

Acronyms Found in this Module

CTE Coefficient of Thermal Expansion

2.1 Dynamic Warpage of Thin FCBGA Defect

Two situations can happen when a package is lifted from

2.2 Head on Pillow Defect Mechanism (1 of 5)

FCBGA Head on Pillow (HoP) open solder joint is defined as:

A joint that is comprised of two metallurgical distinct