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Historical Perspective on Scan Compression

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 The Current State of Test Compression
Historical Perspective on
Scan Compression
Rohit Kapur Thomas W. Williams
Synopsys Synopsys
Subhasish Mitra
Stanford University
Editor’s note:
At the beginning of this decade, compression suddenly became a hot topic in
test. In reality, compression has had a long history. This historical survey ties
together the classical techniques of reducing test pattern size with the newer
methods, and shows the continuity of work in this area.
—Scott Davidson, Sun Microsystems
&THE BEGINNINGS OF the modern-day IC test trace
back to the introduction of such fundamental
concepts as scan, stuck-at faults, and the D-algorithm.
Since then, several subsequent technologies have
made significant improvements to the state of the art.
Today, IC test has evolved into a multifaceted industry
that supports innovation. Researchers present new
ideas in approximately 40 workshops every year.
Innovative advances in test research and practice over
four decades have culminated into a set of technol-
ogies that address the problem of the rising cost of test.
Scan compression technology has proven to be a
powerful antidote to this problem, as it has catalyzed
reductions in test data volume and test application
time of up to 100 times. As a result, the cost of test
might well be contained for many years to come.
This article sketches a brief history of test technol-
ogy research, tracking the evolution of compression
technology that has led to the success of scan
compression. It is not our intent to identify specific
inventors on a fine-grained timeline. Instead, we
present the important concepts at a high level, on a
coarse timeline. Starting in 1998 and continuing to the
present, numerous scan-compression-related inven-
tions have had a major impact on the test landscape.
However, this article also is not a survey of the various
scan compression methods. Rather, we focus on the
114 0740-7475/08/$25.00 G 2008 IEEE Copublished by the IEEE CS and the IEEE CASS
evolution of the types of constructs
used to create breakthrough solutions.
Historical overview
During the past decade, IC test
solutions mainly focused on cost con-
tainment (and low quality contributes
to cost). The variance is where cost is
encountered. In the beginning, cost
was a result of the delay impact and the area overhead
of adding the multiplexer to implement scan. Later, the
cost equation shifted to test time, as measured by the
time spent on expensive testers. Today, the cost
equation is moving toward flows in which test forms
a value link in achieving other tasks, such as yield
improvement. As a result of this change, we can clearly
demarcate four eras in the evolution of the technology
trying to contain the cost of IC test:
& expensive multiplexer,
& gate-to-gate connection,
& low-cost ATE, and
& manufacturing yield.
Figure 1 depicts these eras on a rough timeline.
From the 1960s through the 1980s, gate delay and
the area associated with gates played a significant role
in test solutions. This era represents the longest span of
change in test. It began with the invention of scan and
ended when scan tests became the primary test
solution used to manufacture digital ICs. To incorpo-
rate scan chains, the multiplexer was added in the
data path of a flip-flop. Although most optimizations in
this era, such as partial scan, did not add efficiency to
the testing process, there were many other significant
innovations that dealt with reducing the pattern count
IEEE Design & Test of Computers
Figure 1. Timeline divided into eras showing test technologies for test cost reduction.
for the designs. The technologies developed primarily
during this timeframe fall into the expensive multi-
plexer era.
Some of these technologies were improvements in
modeling and algorithms, and others can be classified
as DFT solutions. Most of the DFT solutions in this era
were classified as high-overhead solutions because the
need for compact tests was a secondary issue in the
testing process.
As semiconductor technology moved toward small-
er geometries in the 1990s, the shift in delay from the
gate to the net had a significant impact on test. With the
ability to manufacture a large number of transistors,
and the diminishing impact of gate delay on the design,
DFT solutions that were deemed impractical when first
invented suddenly became useful for reducing the
number of test patterns and the data associated with it.
These technologies, which fall in the gate-to-gate
connection era, are now recognized as a precursor to
today’s scan compression technology.
As test technologists continued to push the
envelope on issues related to high quality, or low
defects per million (DPM), the cost of test per transistor
stayed relatively constant. The cost of manufacturing a
transistor, meanwhile, kept decreasing. With the cost
of test projected to equal the cost of manufacturing a
transistor, the test industry moved into the low-cost
ATE era. Demands on reducing the cost of ATE, the
biggest ticket item, led to the creation of structural
testers.
While the commotion of the low-cost ATE contin-
ued to be sorted out, the EDA industry responded with
new DFT solutions that addressed the test data volume
March/April 2008
and test application time problem. Experience and
techniques gained from the expensive multiplexer era
(especially prior work on scan and logic BIST),
together with significant new innovations, resulted in
technology that was relatively quickly adopted and
implemented to address the needs created by the new
focus on scan compression.
Software solutions for test cost reduction
Scan made it practical to automatically generate
test patterns. With the single stuck-at fault model as a
target, the algorithms could structurally verify the
correctness of transistor-transistor logic (TTL) with
high confidence. Since then, the quest for efficient
automation has continued. One noted area of
efficiency was test pattern reduction—the effort to trim
test data volume and test application time. Today, this
is the primary goal of scan compression, and test
automation software has used several methods to
achieve it:
& fault dominance,
& reverse simulation of test patterns,
& static compaction, and
& dynamic compaction.
Single stuck-at faults ensure that the test set covers
every net of the design. However, it is unnecessary to
apply a unique test for each single stuck-at fault in the
netlist. Generating tests for single stuck-at faults for
inputs and the fan-out branches of the combinational
netlist guarantees that the resulting test set will detect
all the single stuck-at faults. Targeting the right faults
115
 The Current State of Test Compression
Figure 2. Venn diagram depicting all tests to
detect faults F1, F2, and F3.
first has a significant impact on the number of test
patterns created to fully cover the faults. At the heart of
this is the concept of fault dominance. A fault is said to
dominate another fault if the set of tests that render the
fault detectable is a proper subset of the set of tests that
detect the fault that gets dominated.
Figure 2 shows a conceptual view of all possible
tests for three different faults. Overlapping portions of
the Venn diagram regions depict tests that detect
multiple faults. Fault F2 dominates F1 because every
test for F2 is also a test for F1. By first targeting F2, we
ensure that both F1 and F2 get detected. The reverse
situation might not apply.
Using this principle, if we were to target faults with
the more restricted test set, the selected test guarantees
the detection of the faults with the larger test set. This is
not true if the fault with the larger test set is targeted
first. Fault dominance helps reduce the number of test
patterns. This concept, along with other fault-ordering
methods, plays a significant role in containing test
pattern count.
In the early days of ATPG algorithms, tests were
generated by first applying some random patterns to
the netlist and fault-grading the patterns against the
target faults. Although the process of generating tests
was efficient, the number of test patterns created in the
random-generation phase led to significant test data
volume. Solutions that reverse simulated patterns or
randomized and then simulated the patterns were able
to reduce the number of test patterns for the same
detection credit of targeted faults.
Although ATPG is performed one fault at a time,
fault simulation, depending on the platform’s word
length (32- and 64-bit machines), is performed with
many patterns. The process of collecting ATPG results
to accumulate the set of patterns that are simulated in
116
parallel is called static compaction. After ATPG
generates a test cube, the test pattern is stored in a
temporary set of bins with a process that attempts to
merge the test cubes that are created. Before starting a
new bin, the test cube is checked for compatibility
with bins that already have test cubes in them. If the
new test is seen as compatible with the existing test
cubes—that is, it has the same stimulus requirements
for common stimulus points—then the test cube is
merged with the test cube in the bin. With some exit
criteria, the test cubes are completed with random
values before fault simulation is performed.
After ATPG generates a test for a target fault
(primary fault), the algorithm tries to target many
more faults (secondary faults) before calling it quits
and sending the test cube on to the next step. This
process is called dynamic compaction.
In this section, we left out technologies that
contribute to the reduction in test data volume and
test application time improvements but are implement-
ed for other reasons. Examples of these technologies
include scan with parallel scan chains limited by the
device interface, random fill in ATPG, fault dropping in
fault simulation, and many heuristics that identify
redundant faults and guide the ATPG to better solutions.
The primary goal of most of these technologies was to
make ATPG fault simulation runtime more efficient.
Area-insensitive DFT to contain test cost
During the expensive multiplexer era, some re-
searchers ventured down the DFT path and spent
precious silicon real estate on the then-secondary
needs of test. Such technologies are represented by
test points and logic BIST. Both of these technologies
got a boost when shrinking technology changed the
delay equation. When interconnect delay became a
dominant factor in VLSI design, coupled with the
ability to put a large number of gates on silicon, these
area-insensitive technologies got a second wind and
became the natural precursor to scan compression.
In just a few years, researchers developed several
technologies to add logic between the scan inputs and
outputs and the internal scan chains. These efforts
leveraged the fact that a large portion of ATPG-
generated tests had few stimulus and observation
requirements for fault detection.1 These technologies
relied on decoupling the scan inputs and outputs from
the internal chains such that a larger number of
internal chains could be driven from a smaller
interface.
IEEE Design & Test of Computers
 Figure 3 shows the impact of decou-
pling the scan terminals from the
internal scan chains. This figure also
shows that a reduction in chain length
linearly reduces the test data volume
and test application time. A ratio of 4
times more internal chains than the scan
interface translates to 4-times-shorter
chains and the corresponding reduction
in the quality of results (data and time).
This is the fundamental mechanism
behind the numerous research papers
and the commercially available scan
compression technologies of today. A
one-to-one relationship between the Figure 3. Decoupling of the scan interface from the internal scan chains
number of stimulus, observed values helps reduce the test data volume and test application time.
on the boundary to the number of shifts
leads to equal gains in test data volume and test the number of unspecified values in the test patterns,
application time. A further decoupling of the number and thus improves the compaction algorithms sup-
of times a stimulus or observation is performed on the ported in the ATPG tools.
interface to the number of shifts in the internal scan
chains leads to solutions that have different gains for Reseeding logic BIST
data and time. Logic BIST technology was invented at a time when
Logic added to interface the scan input with the area overhead for test was a sensitive issue and played
internal scan chains is referred to as the decompressor an important role in a niche system test market.3 This
because it takes only a few values to supply a much heavy-handed solution for test was used in production
larger set of receiving flip-flops. Logic added to interface environments as a way to reuse existing system test
the internal scan chains to the scan outputs is referred infrastructures. This technology represented high test
to as the compressor because it takes many values from data compaction but not much, if any, test application
the flip-flops and funnels the data to a far smaller set of time improvements. However, it was never recognized
terminals. Logic X (unknown) values in the test as a scan compression solution. In the 1990s, reseeding
response have a negative impact on the observability technology was used to reduce the test application
of good responses that come together in the compres- time—at the expense of reduced test data volume
sor. To handle logic X values in the response, gating gains. This made logic BIST the first real scan
logic is added between the scan chains and the compression solution.4
compressor. This is called the masking logic. Figure 4 shows the popular Stumps structure for
logic BIST. Seeds applied directly to the linear-
Test points feedback shift register (LFSR), or through another scan
Scan itself is a test point added to the flip-flops in chain, allow for deterministic values to be supplied to
the design. This control-and-observe point on the flip- the self-test engine. If the seeds represent encoded
flops was critical to the ability to generate tests using values that the ATPG needs to detect the fault, the self-
ATPG algorithms. However, control-and-observe test engine becomes a deterministic test machine.
points can be added anywhere in the combinational
part of the circuit. Although the technology was Input scan compression
invented to increase the fault coverage when targets A large variety of solutions have been developed
were not achieved, adding test points has the effect of for the interfacing logic on the input side of Figure 3.1
reducing test patterns when fault coverage is kept the Touba discusses the details of the input decompres-
same.2 Thus, test points became the simplest DFT sors as code-based, linear-decompressor-based, and
construct to reduce test data volume and test broadcast-scan-based schemes.1 We can categorize
application time. This construct effectively increases these solutions as either combinational or sequential.

March/April 2008
117
 The Current State of Test Compression
Figure 4. Logic BIST structure showing reseeding to apply
deterministic tests through the linear-feedback shift register
(LFSR). (MISR: multiple-input signature register.)
Combinational solutions have been as simple as direct
(but shared) connections of scan inputs to the internal
scan chains,5,6 and they have been as complex as
decoding logic to unravel scan data to sequences of 1s
and 0s. The more common solutions use XOR gates on
the input,7,8 or multiplexers to distribute values from
the scan inputs to the receiving chains.9
The sequential solutions branch off into two
categories, of which some are efficient mutations of
the logic BIST structure tailored for scan compression.
With seeds streaming in at intervals, or on every shift,
the stimulus requirements for fault detection and
observation (masking) are encoded in the state of the
LFSR to provide significant gains in test data volume
and test application time.10
The other branch of sequential solutions uses
optional shift registers to temporarily store multiple
values that get applied with various spreading logic.8
Figure 5 shows examples of these techniques with
EDA solutions.
Output scan compression
On the output side, XOR gates represent the most
common interfacing logic.7,8,10 With high observability
provided by an XOR gate, other options have not been
able to compete. Various flavors of compressors with
XOR gates have developed around the basic concept
of dealing with unknown values in the test response,
also known as X-tolerant response compaction. X-
compact represents XOR structures that guarantee
118
error detection in the presence of a logic X.11 Shift
registers have been added to such XOR structures to
provide temporal trade-offs in the observation of
values such that fewer output pins can be used for
compaction.12
Before the emergence of such X-tolerant solutions,
traditional logic BIST solutions tried to completely
eliminate X values from a design, thus practically
achieving extremely high degrees of response com-
paction.6 Unfortunately, for most designs today, it is
impractical to eliminate all X sources, owing to timing
constraints, area overhead, inefficiencies of the
simulation engines (such as zero-delay simulation),
and inaccuracies in modeling the behaviors of certain
circuit blocks (for example, memory, custom-logic,
and analog-circuit blocks). Hence, X-tolerant solutions
are seeing wide adoption, as Figure 5 shows. In
addition to detecting defective chips, such X-compac-
tors are effective for diagnosis and yield-learning
purposes as well.13,14
Scan compression automation
Along with scan compression research, the EDA
industry has played a leading role in making scan
compression the focus of IC test solutions. Mentor
Graphics introduced the first commercially available
product for scan compression, but virtually every EDA
company has been quick to deliver similar solutions in
a short timeframe.
Figure 5 represents conceptual pictures of scan
compression technologies delivered by Mentor Graph-
ics,10 SynTest,8 Cadence,6 and Synopsys.9,15 These
technologies provide different trade-offs between the
quality of results as seen in data compression and test
application time, with differences in the amount of
area overhead spent to deliver the results. Although
Figure 5 does not necessarily show the current state of
the art for each tool, we expect the basic constructs to
remain the same.
Because EDA tools need to guarantee fault cover-
age, the solutions we outlined here provide masking
logic and also implement the traditional scan chains.
THE INNOVATIONS THAT LED to the current state of scan
compression culminate from optimizations developed
in their respective eras. The changing environment of
IC manufacturing has made the impractical solutions
of yesterday practical today. Scan compression, in its
current state, represents a significant change to the
way test was once done. This change appears to be
IEEE Design & Test of Computers
Figure 5. Four of the scan compression technologies represented at the conceptual level that are adopted by EDA
companies Mentor Graphics (a), SynTest (b), Cadence (c), and Synopsys (d).
permanent. The test industry is quickly gaining
confidence in using this technology. Today, traditional
scan chains are implemented along with scan
compression to create a bypass configuration, which
provides a safety net for test methodologies that use
scan compression when the compression logic causes
loss of fault coverage. The bypass configuration is also
used for debugging situations and nonmainstream use
of scan chains. The scan compression evolution will
complete its current arc once it is implemented on
designs without traditional scan.
Although scan compression has become part of the
mainstream IC test industry, this technology has not
had time to mature. In time, capabilities will be built
on top of it that will improve the quality of the results
(including high compression) and provide better
analysis tools for architecting scan compression. As
March/April 2008
new research introduces improvements, IC test
solutions will rely on scan compression to deliver the
increased number of patterns created by small delay
testing. Because data volume gains can be easily
achieved compared to test application time gains,
future research on this technology will likely focus on
test application time reduction.
As we move forward, manufacturing yield appears
to be the most-pressing industry problem. Experts
anticipate that test, and hence scan compression, will
need to undergo yet another revolution for break-
through solutions in this area. &
& References
1. N.A. Touba, ‘‘Survey of Test Vector Compression
Techniques,’’ IEEE Design & Test, vol. 23, no. 4, July-
Aug. 2006, pp. 294-303.
119
 The Current State of Test Compression
2. M.J. Guezebroek et al., ‘‘Test Point Insertion for Compact
Test Sets,’’ Proc. Int’l Test Conf. (ITC 00), IEEE CS
Press, 2000, pp. 292-301.
3. P.H. Bardell and W.H. McAnney, ‘‘Self-Testing of
Multichip Logic Modules,’’ Proc. Int’l Test Conf. (ITC 82),
IEEE CS Press, 1982, pp. 200-204.
4. B. Koenemann, ‘‘LFSR-Coded Test Patterns for Scan
Designs,’’ Proc. European Test Conf., IEEE CS Press,
1991, pp. 581-590.
5. I. Hamzaoglu and J. Patel, ‘‘Reducing Test Application
Time for Full Scan Embedded Cores,’’ Proc. 29th Ann.
Symp. Fault Tolerant Computing (FTCS 99), IEEE CS
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6. C. Barnhart et al., ‘‘OPMISR: The Foundation for
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11. S. Mitra and K.S. Kim, ‘‘X-Compact: An Efficient
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13. Z. Stanojevic et al., ‘‘Enabling Yield Analysis with X-
Compact,’’ Proc. Int’l Test Conf. (ITC 05), IEEE CS
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120
View publication stats
15. P. Wohl et al., ‘‘Minimizing the Impact of Scan
Compression,’’ Proc. VLSI Test Symp. (VTS 07), IEEE
CS Press, 2007, pp. 67-74.
Rohit Kapur is a scientist working in
the area of IC test at Synopsys. His
research interests include IC test
methods and their use in design flows.
He has a BS in electronics engineering
from Birla Institute of Technology, Mesra, India, and
an MS and a PhD in computer engineering from the
University of Texas at Austin. He is a fellow of the
IEEE.
Subhasish Mitra is an assistant
professor in the Departments of Elec-
trical Engineering and Computer Sci-
ence at Stanford University. His re-
search interests include robust system
design, VLSI design and test, and design for
emerging nanotechnologies. He has a PhD in
electrical engineering from Stanford University.
Thomas W. Williams is a fellow at
Synopsys. His research interests in-
clude IC test methods and their use in
design flows. He has a BS in electrical
engineering from Clarkson University,
an MA in pure mathematics from the State University
of New York at Binghamton, and a PhD in electrical
engineering from Colorado State University. He is
a fellow of the IEEE.
& Direct questions and comments about this article to
Rohit Kapur, Synopsys, 700 East Middlefield Rd.,
Mountain View, CA 94043; rkapur@synopsys.com.
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