semua NAND Gate Set-Clear Flip-Flop 121 NOR Gate Set-Clear Flip-Flop 127 €lock Signals 129 Clocked Flip-Flops 130 The Clocked S-C Flip-Flop 132 The Clocked J-K Flip-Flop 135 The Clocked D Flip-Flop 137 The D Latch 141 Asynchronous Inputs 142 Flip-Flop Timing Considerations 145 Master/Slave Flip-Flops 148 Flip-Flop Applications 152 Flip-Flop Synchronization 152 Detecting an Input Sequence 154 Data Storage and Transfer 154 ‘Shift Registers 157 Frequency Division and Counting 160 The One-Shot 163 Analyzing Sequential Circuits 165 Flip-Flop Summary 168thus far have been combinatorial circuits whose outp,, tant of are dependent upon the levels present at the inputs at that afr ‘conditions have no effect on the present outputs because its have no memory. Most digital systems are made up of I circuits and memory elements. shows a block diagram of a general digital system that combines logic with memory devices. The combinatorial portion accepts n Sian inputs and from the outputs of the memory elements. The orial circuit ‘on these inputs to produce various outputs, some of ‘used to determine the binary values to be stored in the memory elements. ‘of some of the memory elements, in turn, go to the inputs of logic gates al circuits. This process indicates that the external outputs of a are a function of both its external inputs and the information stored in ‘elements. most widely used memory clement is the flip-flop, which we shall study hly in this chapter. The flip-flop (abbreviated FF) is a logic circuit with two which are the inverse of each other. Figure 5.2 indicates these outputs as 0 O (actually any letter could be used, but Q is the most common). The Q outpu called the normal FF output and Q is the inverted FF output. When a FF is said to _ be in the HIGH (1) state or the LOW (0) state, this is the condition at the Q output Of course, the O output is always the inverse of Q. ~~ There are two possible operating states for the FF: (1) = 0, O = 1; and (2) @ =0. The FF has one or more inputs, which are used to cause the FF to h back and forth between these two states. As we shall see, when an input is ‘send the FF to a given state, the FF will remain in that state even after the to normal. This is its memory characteristic. flop, incidentally, is known by several other names, including bistable , latch, and binary, but we will generally use flip-flop because it is the designation in the digital field, Other memory elements, which we will Memory outputs Combinatorial logic gates elements ee} FIGURE 5.1 General digital External inputs system diagram. Chap. 5 Flip-FlopsNormal output Inputs O}———+ Inverted output FIGURE 5.2 General flip-flop __J symbol. study i chapter, are a ' he 4 later chapter, are also used in digital systems, but flip-flops are the most prs i because of their high speed of operation, the ease with which information can > Stored into and read out of them, and the ease with which they can be interconnected with logic gates. { NAND GATE SET-CLEAR FLIP-FLOP. A basic FF circuit can be constructed from two cross-coupled NAND gates as shown in Figure 5.3(a). Notice that the output of NAND-1 is connected to one of the inputs of NAND-2 and vice versa. The gate outputs, Q and Q, are the FF outputs, which, under normal conditions, will always be the inverse of each other. The two FF inputs are labeled SET and CLEAR for reasons that will be explained. ‘Phe SET and CLEAR inputs are normally resting in the HIGH state and one ot them will be pulsed LOW whenever we want to change the FF output state. We begin our analysis by showing that there are two equally likely output states when SET = CLEAR = 1. One possibility is shown in Figure 5.3(a), where we have Q = 0/0 = 1. With Q = 0, the inputs to NAND-2 are 0 and 1, which produce @ = 1. The 1 from Q causes NAND-! to have a | at both inputs to produce a 0 output at Q. In effect, what we have is the LOW at the NAND-1 output produces HIGH at the NAND-2 output, which, in turn, keeps the NAND-1 output LOW. _The second possibility is shown in Figure 5.3(b), where Q = 1/0 = 0. The HIGH frorn NAND-1 produces a LOW at the NAND-2 output, which, in turn, keeps the NAND-1 output HIGH. Thus, there are two possible output states when FIGURE 5.3 NAND FF has two possible resting states when SET = CLEAR = 1.2 SET = CLEAR = 1; as we shall soon see, the one that actually exists will depend 2 what has occurred previously at the inputs. Now let’s investigate what happens when the SET input is momentarily pul LOW while CLEAR is kept HIGH. Figure 5.4(a) shows what happens when @ = 0 priorto the occurrence of the pulse. As SET is pulsed LOW at time , Q will go HIGH, and this HIGH will force @ to go LOW so that NAND-1 now has two LOW inputs. Thus, when SET returns to the 1 state at “1, the NAND-1 output remains HIGH, which, in turn, keeps the NAND-2 output LOW Figure 5.4(b) shows what happens when Q = 1/0 = 0 prior to the application of the SET pulse. Since Q = 0 is already keeping the NAND-1 output HIGH, the LOW pulse at SET will not change anything. Thus, when SET returns HIGH, the FF outputs are still in the Q = 1/0 = 0 state We can summarize Figure 5.4 by stating that a LOW pulse on the SET input will cause the FF to end up in the Q = | state. This operation is called setting the FF. In fact, the Q = 1 state is also called the set state. Now let’s consider what occurs when the CLEAR input is pulsed LOW while SET is kept HIGH. Figure 5.5(a) shows what happens when @ = 0 and Q = 1 prior to the application of the pulse. Since Q = 0 is already keeping the NAND-2 output CLEAR FIGURE 5.4 Pulsing the SET input to the 0 stat Il always produce the Q = 1/Q = 0 out. (b) put state. CLEAR Chan. 5 Fliv-FlonsSET 1 ! () : SET 1 me 1 a i ' & FIGURE 5.5 Pulsing the CLEAR input to the LOW state will always produce (b) Q=0/Q=1. GH, the LOW pulse at CLEAR will not have any effect. When CLEAR returns JH, the FF outputs are still Q = 0/0 = 1. ‘Figure 5.5(b) shows the situation where Q = 1 prior to the occurrence of the EAR . As CLEAR is pulsed LOW at to, Q will go HIGH, and this HIGH esQ ‘go LOW so that NAND-2 now has two LOW inputs. Thus, when CLEAR HIGH at“, the NAND-2 output remains HIGH, which, in tur, keeps the D-1 output LOW. turn HIGH, the resulting FF output state will depend on "first. Simultaneous transitions back (o the | state will produce Tesults. ~ For these reasons the SET = CLEAR = 0 condition is never purposely used for the NAND FF. c Sec. 5.1 NAND Gate Set-Clear Flip-Flop 123Ambiguous 21 CLEAR FIGURE 5.6 (a) NAND FF; (a) (v) (b) truth table. Summary of NAND FF The operation described above can be conveniently placed in a truth table (Figure 5.6) and is summarized as follows: 1, SET = CLEAR = 1: This condition is the normal resting state and it has no effect on the FF output state. The Q and Q outputs will remain in whatever state they were prior to this input condition. 2. SET = 0, CLEAR = 1: This will always cause the output to go to the Q = 1 state, where it will remain even afier SEY returns HIGH. This is called setting the FF. 3. SET = 1, CLEAR = 0: This will always produce the @ = 0 state, where the output will remain even after CLEAR returns HIGH. This is called clearing the FF. 4. SET = CLEAR = 0: This condition tries to set and clear the FF simultaneously and can produce ambiguous results. It should not be used. Alternate Representations From the description of the NAND FF operation, it should be clear that the SET and CLEAR inputs are active LOW. The SET input will set O = 1 when SET goes LOW; the CLEAR input will clear @ = 0 when CLEAR goes LOW. For this reason, the NAND FF circuit is often drawn using the alternate Tepresentation for each NAND gate, as shown in Figure 5.7(a). The bubbles on the SET and CLEAR inputs emphasize the fact that these inputs are active LOW. SET ee ee a s oy FF 7 a c a CLEAR eee) (a) (b) FIGURE 5.7 (a) NAND FF equivalent representation; (b) sim- plified block symbol. 124 9 Chap. 5 Flip-FlopsFigure 5.7(b) shows a si , : on . The S and C a simplified block representation that we will sometimes label: j 's Tepresent the SET and CLEAR inputs, and the bubbles indicate the active LOW natu: re of i represents a NAND-pate pi inputs. Whenever we use this block symbol, it EXAMPLE 5.1 The waveforms of Figure 5.8 are 8 are applied to the inputs of a NAND-gate SET- CLEAR FF. Assume that initially @ = 0, and determine the Q waveform 1 Tals. Ts Ts Te FIGURE 5.8 Example 5.1 Solution: Initially, SET = CLEAR = | so that Q will remain in the 0 state. The LOW pulse that occurs on the CLEAR input at time 7; will have no effect, since Q is already in the cleared (0) state The only way that Q can go to the | state is input. This occurs at time 7 when SET first goe HIGH at 7, Q will remain in its new HIGH state, Attime 7; when SET goes LOW again, there will be no e Q is already set to the | state. : ‘The only way to bring Q back to the 0 state is by a LOW pulse on the | CLEAR input. This occurs at time 73. When CLEAR returns to 1 at time %, Q remains in its now LOW state. This example shows that the FF output “remembers” the last input that was ‘activated and will not change states until the opposite input is activated. by a LOW pulse on the SET LOW. When SET returns ject on Q because en Soo ee a It is virtually impossible to obtain a single voltage transition from a mechanical switch because of the phenomenon of contact bounce. This is illustrated in Figure 5.9(a), where closing the switch produces several output-voltage transi- | tions between 0 and 5 V as the switch contacts vibrate open and closed before finally staying closed. The duration of this switch bounce is generally only a couple of milliseconds or less, depending on the type of switch. The multiple transitions on the output signal may not be acceptable in many applications, so some means has to be used to “debounce” the switch, A NAND-gate FF can be used to perform this function as shown in Figure 5.9(b) Describe the operation of this “debounce” circuit, Gan KI NAND Gate Set-Clear Flip-Flop 125126 Contact bouncing Contact stays closed I Switch to Switch back to position 2 position 1 (b) FIGURE 5.9 (a) Mechanical contact bounce will produce multi- ple transitions; (b) NAND FF used to debounce a mechanical switch. Solution: Assume the switch is initially in position 1 so that the CLEAR input is LOW and Q = 0. When the switch is moved to position 2, it will put a LOW on the SET input when it first makes contact. This will set Q = 1 ina matter of a few nanoseconds, and it will stay there even if the contact bounces open (since that will produce SET = CLEAR = 1, which has no effect). Likewise, when the switch is moved back to position 1, it will place a LOW on the CLEAR input upon first contact. This clears Q = 0, where it will stay even if the contact bounces open. Thus, the Q output will consist of a single transition each time the switch is moved from one position to the other. Resetting a FF The action of clearing a FF (Q = 0) is also called resetting a FP, and both terms are used interchangeably in the digital field. In fact, CLEAR FFs are often called RESET-SET FFs (abbreviated as RS FF), where the RESET input is used in place of the CLEAR input. We will use both terms throughout the text. Chap. 5 Flip-Flops1. Whatis the normal REVIEW QUESTIONS input? al resting state of the SET and CLEAR inputs? What is the active state of each 2, What will be the states of @ and 3. True or false: The SET input can 4. When power is first applied to an Q. What would have to be done t (Ans. A momentary LOW pulse after a FF has been cleared (reset)? Never be used to make Q = 0, 'y FF circuit, it is impossible to predict the initial states of Q and fo ensure that a NAND FF always started off in the Q = 1 state? has to be applied to the SE input). 2 NOR GATE SET-CLEAR FLIP-FLOP Two cross-coupled NOR gates can be used as a SET-CLEAR FF. The arrangement, shown in Figure 5.10(a), is similar to the NAND FF except that the Q and Q outputs have reversed positions. The analysis of the operation of the NOR FF can be performed in exactly the same manner as for the NAND FF. The results are given in the truth table in Figure 5.10(b) and are summarized as follows: 1, SET = CLEAR = 0: This is the normal resting state for the NOR FF and it has no effect on the output state. Q and Q will remain in whatever state they were prior to the occurrence of this input condition. 2. SET = 1, CLEAR = 0: This will always set Q = 1, where it will remain even after SET returns to 0. 3. SET = 0, CLEAR = 1: This will always clear Q = 0, where it will remain even after CLEAR returns to 0. 4, SET = 1, CLEAR = 1: This condition tries to set and clear the FF at the same time, and it produces Q = O = 0. If the inputs are returned to 0 simultaneously, the resulting output state is unpredictable. This input condition should not be used 5 [FF Output i No change z a=1 SET a Q=o Ambiguous a CLEAR (a) FIGURE 5.10 (a) NOR-gate FF; (b) truth table; (c) simplified block symbol. Sec. 5.2 NOR Gate Set-Clear Flip-Flop 1278 ike the NAND FF except that the SEV ang ae LOW, and the normal resting state The NOR-gate FF operates exact |H by a HIGH pulse on the SET input, and CLEAR inputs are active HIGH rather il be set HIG pay is SET = CLEAR OO wiHIGH pulse on the CLEAR input. The simplified block it wll be cleared LOW by ot PTO is shown with no bubbles on the $ and C tive HIGH. symbol for the NOR FF in Figure 5. copie this indicates that these inputs are act EXAMPLE 5.3 Assume Q = 0 initially, and determine the @ waveform for the NOR FF inputs of Figure 5.11. FIGURE 5.11 Example 5.3 Solution: Initially, SET = CLEAR = 0, which has no effect on Q, and Q stays LOW. When SET goes HIGH at time F, Q will be set to 1 and will remain there even after SET returns to 0 at 7. At F the CLEAR input goes HIGH and clears Q to the 0 state, where it remains even after CLEAR returns LOW at %,. The CLEAR pulse at 7; has no effect on Q, since Q is already LOW. The SET pulse at 7; again sets Q back to 1, where it will stay This example shows that the FF “remembers” the last input that was activated, and it will’not change states until the Opposite input is activated EXAMPLE 5.4. << Figure 5.12 shows a simple circuit that can be used to detect the interruption of a light beam. The light is focused on a phototransistor that is connected in the common-emitter configuration to operate as a switch, Assume that the FF has Previously been cleared to the 0 state by momentarily opening switch S$, and describe what happens if the light beam is momentarily interrupted. Solution: With light on the phototransistor, we can assume that it is fully conducting so that the resistance between the collector and emitter is very small. Thus, vo will be close to 0 V. This places a LOW on the SET input of the FF so that SET = CLEAR = 0. Chap.5 Flip-Flops+5V fi] FIGURE 5.12 Example 5.4 When the light beam is interrupted, the phototransistor turns off and its collector-emitter resistance becomes very high (i.e., essentially an open circuit). This causes vo to rise to approximately 5 V; this activates the SET input and turns on the alarm. Now, the alarm will remain on because Q will remain HIGH even if the light beam was only momentarily interrupted, and vp goes back to 0 V. The alarm can be turned off only by momentarily opening $1 to produce a HIGH on the CLEAR input. In this application, the FF's memory characteristic is used to convert a momentary occurrence (beam interruption) into a constant output. REVIEW QUESTIONS 1. What is the normal resung state of the NOR FF inputs? What is the active state? 2. When a FF is sot, what are the states of Q and Q?, 3. What Is the only way to cause the Q output of a NOR-gate FF to change from 1 to 0? 4, Ifthe NOR FF in Figure 5.12 were replaced by a NAND FF, why wouldn't the circuit work properly? 5.3 CLOCK SIGNALS Digital systems can operate either asynchronously or synchronously. In asynchronous systems, the outputs of logic circuits can change state any time one or more of the inputs change. An asynchronous system is difficult to design and troubleshoot. In synchronous systems, the exact times at which any output can change states is determined by a signal commonly called the clock. This clock signal is generally a rectangular pulse train or squarewave as shown in Figure 5.13. The clock sig distributed to all parts of the system, and most (if not all) of the system outputs c: change state only when the clock makes a transition. The transitions (also called edges) are pointed out in Figure 5.13. When the clock changes from a 0 to a 1, this is called the positive-going transition (PGT); when the clock goes from 1 to 0, this is Sec. 5.3 Clock Signals reyvegoing _—Negative-going "eon ‘transition ——— Time (a) pete LS ae ) FIGURE 5.13 Clock signals. the negative-going transition (NGT). We will use the abbreviations PGT and NGT, since these terms appear so often throughout the text. Most digital systems are principally synchronous (although there are always some asynchronous parts), since synchronous circuits are easier to design and trou- bleshoot. They are easier to troubleshoot because the circuit outputs can change only at specific instants of time. In other words, almost everything is synchronized to the clock-signal transitions The synchronizing action of the clock signals is accomplished through the use of clocked flip-flops that are designed to change states on one or the other of the clock’s transitions. 5.4 CLOCKED FLIP-FLOPS We will study several types of clocked flip-flops. First, however, we will discuss the Principal ideas that are common to all of them. \ 1. All clocked FFs have a clock input that is typically labeled CLK, CK, or CP. We : will use CLK as shown in Figure 5.14. The clock input is also symbolized by a small triangle to indicate that the FF responds only to the transitions of the CLK input. The FF represented in Figure 5.14(a) will trigger only on the positive-going transitions (PGT). The FF in Figure 5.14(b) triggers only on the negative-going transitions (NGT), as indicated by the bubble on the CLK input. 2. Alll clocked FFs have one or more control inputs. These control inputs can have Synchronous A Synchronous a control input control input f CLK 1 CLK 1 21 (a) (b) FIGURE 5.14 General symbols for clocked FFs: (a) triggers on PGT; (b) triggers on NGT. a9n 0) Chan 5 Flip-Flopsvarious labels, q the output state their effectis sy called _rehronous inputs. ‘or example, the sy O until the POT Be a is 5.140) will have no eff 3. In other words, the the FF output will c When the appropri epending on the of the FF ©xact function. The control i and CLEAR i \¢ appropriate inputs will determine Inputs discussed earlier), but clock transition. As such, they are also Us inputs to the Clock signal. Likewise rect on Q until the logic levels present hange, while the sigi ate transition (ed FF of Figure 5.14(a) will not affect the synchronous inputs of Figure NGT of the clock at the synchronous inputs will control how nal at CLK will actually trigger the change ze) occurs, Set-Up and Hold Times ‘Two timing to Tespond reliably to its control inputs Tequirements are illustrated in F igur ‘The set-up time, requirements must be met if a clocked FF is when the active CLK transition occurs. These 5.15 for a FF that triggers on a PGT. ' 4s, is the time interval immediately preceding the active transi- Hon of the CLK signal during which the synchronous input has to be maintained at the Proper level. IC manufacturers usually specify the minimum allowable set-up time. If this time requirement is not met, the FF may not respond reliably when the clock edge occurs. The hold time, ty, is the time interval immediately following the active transition of the CLK signal during which the synchronous input has to be maintained at the Proper level. IC manufacturers usually specify the minimum acceptable value of hold time. If this requirement is not met, the FF will not trigger reliably. Thus, to ensure that a clocked FF will respond properly when the active clock transition occurs, the synchronous inputs must be stable (unchanging) for a time interval equal to fs prior to the clock transition, and for a time interval equal to ty after the clock transition. IC flip-flops will have fs and % values in the nanosecond range. Set-up times are usually in the 5- to 50-ns range while hold times are generally from 0 to 10 ns, Notice _ that these times are measured between the 50 percent points on the transitions, ‘These timing requirements are very important in synchronous systems, because, as we shall see, there will be many situations where the synchronous inputs to a FE are changing at approximately the same time as the CLK input. Synchronous control input f \ | T Clock input aes 1 1 1 I \ | i pegs 3) FIGURE 5.15 Set-up and hold te ete times. Sec. 5.4 Clocked Flip-Flops 131. ———— REVIEW QUESTIONS 4. Define set-up time. 2. Define hold time. 3, The control inputs to a clocked FF can change the output state even if CLK is held at a constant level. True or falso? —_—_—————— 5.5. THE CLOCKED S-C FLIP-FLOP Figure 5.16(a) shows the logic symbol for a clocked S-C flip-flop that is triggered by the positive-going edge of the clock signal. This means that the FF can change states only when a signal applied to its clock input makes a transition from 0 to 1. The S and C inputs control the state of the FF in the same manner as described earlier for the NOR-gate FF, but the FF does not respond to these inputs until the occurrence of the PGT of the clock signal The truth table in Figure 5.16(b) shows how the FF output will respond to the PGT at the CLK input for the various combinations of S and C inputs. This truth table uses some new nomenclature to distinguish between the value of Q prior to the PGT (labeled as Qy) and the value of Q after the occurrence of the PGT (labeled as Qy-1). This nomenclature is widely used by IC manufacturers on their IC data sheets. The waveforms in Figure 5.16(c) illustrate the operation ofthe clocked S-C FF. If we assume that the set-up and hold time requirements are being met in all cases, we can analyze these waveforms as follows 1, Initially all inputs are 0 and the Q output is assumed to be 0 2. When the PGT of the first clock pulse occurs (point a), the S and C inputs are both 0, so the FF is not affected and remains in the Q = 0 state (i.e. Qvet = Ov). 3. At the occurrence of the PGT of the second clock pulse (point c), the S input is now high, with C still low. Thus, the FF sets to the 1 state at the rising edge of this clock pulse. 4. When the third clock pulse makes its positive transition (point e), it finds that $= 0 and C = 1, which causes the FF to clear to the 0 state. 5. The fourth pulse sets the FF once again to the Q = 1 state (point g) because $ = 1 and C = 0 when its positive edge oveurs. 6. The fifth pulse also finds that $ = 1 and C = 0 when it makes its positive-going transition. However, Q is already high, so it remains in that state 7, The S = C = 1 condition should not be used, because it results in an ambiguous condition, It should be noted from these waveforms that the FF is not affected by the negative-going transitions of the clock pulses. Also, note that the S and C levels have no effect on the FF, except upon the occurrence of a positive-going transition of the clock signal. The 5 and C inputs are synchronous control inputs; they control which state the FF will go to when the clock pulse occurs; the CLK input is the :rigger input that causes the FF to change states according to what the S and C inputs are when the active clock transition occurs 129°) Chan 5 Flip-Fioos