2020 6th Iranian Conference on Signal Processing and Intelligent Systems (ICSPIS)
High Performance Application-oriented Memory
Management on Multicore Systems
Ahmad Sadigh Baroughi
2020 6th Iranian Conference on Signal Processing and Intelligent Systems (ICSPIS) | 978-1-7281-8629-0/20/$31.00 ©2020 IEEE | DOI: 10.1109/ICSPIS51611.2020.9349590
Department of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
sadighbaroughi_a@elec.iust.ac.ir
Abstract— Due to the evolution of imagining and dealing with
issues and demands that have developed with intelligent systems,
higher performance has become a crucial need for daily growth
of application size and complexities. Currently, most high-
performance computing systems are multi-core, and many kinds
of research have been done toward minimizing the execution time
efficiently. Cache performance impacts on program execution
especially on modern intelligent processing systems, therefore
cache replacement policies in set-associative caches have been
investigated in great depth. We propose an approach to consider
information derived from coherence state of the cache block in a
time-interleaved manner, and our simulations on high-
performance applications of PARSEC2.1 and SPLASH-2
benchmark suits show that our approach has 10% lower miss
rate and up to 10% more instructions per cycle than LRU, MRU
and Random replacement policy without further power
consumption.
Keywords— data- intensive application, cache replacement
policy, coherence state, memory management.
I. INTRODUCTION
Intelligent Systems made revolutionary scientific
discoveries, fed game-changing innovations, and improved
quality of life for billions of people around the globe. Through
the progressions of needs and demands, High-Performance
Computing (HPC) has become not only the foundation for
scientific, industrial, and societal advancements but also a
vital service [1]. As technologies like the Internet of Things
(IoT) [2], artificial intelligence (AI) [3], and 3-D imaging [4],
traffic management [5] evolve, the size and amount of data
that systems have to work with are growing exponentially. For
many purposes, the ability to process this huge amount of data
by an intelligent high performance real-time state is crucial
and one of the best basic block for these systems is multi-core
processors.
Toward the high-performance computers, a range of
parallel structure has been investigated during past years. In
[6] a general structure had been proposed for the massive
parallel processing systems. The proposed structure is
expandable in a vertical and horizontal method and
incorporates many of the previous computer designs. The
queuing theory and Jackson queuing network are applied for
assembling an analytical model for the proposed structure.
978-1-7281-8629-0/20/$31.00 ©2020 IEEE
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Madjid Naderi
Department of Electrical Engineering
Iran University of Science and Technology
Tehran, Iran
m_naderi@iust.ac.ir
Computing systems acknowledge executing tasks in a true
multitasking fashion. Such systems share the reconfigurable
device and processing unit as computing resources which
supervises to highly dynamic allocation situations. [7] and [8]
propose heuristic approaches concentrating on developing a
powerful nexus linking partitioning, scheduling and placement
have and considerable improvement in overall execution time
of the tasks have been achieved. High-performance systems
even at the best configuration endure overheads and penalties
which deteriorates overall performance and execution time
hence an approach toward managing and mitigating them is
highly required [9]. Cache performance plays an essential role
not only in the field of processing systems science which is
used for a wide range of computationally intensive tasks in
various domains but also in the reduction of delay of memory
accesses by giving a momentary fast-access storage unit for
the data that is being reached by the CPU. On a cache miss,
data is fetched from the memory and placed in its analogous
locale in the cache. A prolific cache replacement policy can
naturally reduce the cache miss rate and thus decreasing the
contingency of a penalty of hundreds of cycles expenditure
due to memory accesses. The goal is to depreciate the number
of requests to the slower memory and hence succeeding in the
reduction of memory access latency. A cache hierarchy is used
in various applications such as reconfigurable systems, data
processing units, computing servers, databases and CPUs to
mention but a few.
The current computing systems are parallel in nature, and
they comprise several processors or processing units that share
a single memory address space. Thus, smart designs are
involved with intelligent algorithms aiming much better
execution time, performance and power consumption [10-11]
For intelligent performance and power efficiency plans, these
multi-core systems include caches, raising a new concern:
ensuring cache coherence which traverses to a new category of
conflicts, coherence misses, due to a block having been
evicted as a conclusion of a coherence action, moreover this
eviction may intrude with the local way-replacement policy.
Cache misses can be broadly categorised in 3 classes [12]:
• Compulsory miss: when the block has to be read from
main memory whatever the cache design is, as known as cold
start misses or first references misses.
2020 6th Iranian Conference on Signal Processing and Intelligent Systems (ICSPIS)
• Capacity miss: when it is impossible to hold all the
concurrently used data in the cache because of the cache
reduced size compared to the working set size.
• Conflict miss: when multiple addresses map to the same
set and evict used blocks, due to the fact that even though all
cache blocks may not be occupied, the mapping function
cannot target an empty block in order to map a memory
address to a cache set.
Trade-offs can be accomplished by adjusting the cache
parameters. Increasing cache capacity, for instance, can reduce
conflict and capacity misses, while increasing the associativity
decreases the conflict misses, by increasing block size can
reduce compulsory misses due to spatial locality and increase
conflict misses (for a fixed-size cache).
Recent trends in modern processor design have made
adequate management of cache resources more indispensable
than ever before. As the core count and memory demands of
applications rise, discerning cache architectures and
management policies have become vital to meet the challenges
of area and power limitation. Researchers have recently
investigated cache designs that offer distinct advantages and
disadvantages.
Set-associative caches have been introduced for half a
century ago [13] then way-replacement policies, i.e. choosing
which way should be evicted, have been studied. The most
earliest studies conducted in [14] and [15] which published
surveys and analysis of replacement algorithms. Since then,
new replacement policies have been devised and many
optimizations proposed to fit different hardware related
constraints, such as area, power and number of ways.
When a conflict occurs in a direct-mapped cache, as each
address maps to a unique block and set, the only way to deal
with a full cache set is to replace the block in the set with the
new data. In case of an N-way associative or fully associative
cache, a block must be chosen for eviction when such a
conflict occurs and the set is full. The temporal locality
principle expressed earlier suggests than the most appropriate
block to evict is the Least Recently Used (LRU) one, as it is
the least likely to be used again in the near future.
This replacement scheme can be implemented by adding a
use bit next to the validity bit and indicates if the block in the
corresponding way was the most recently accessed. When one
of the ways is used, this bit is updated, and the way having this
bit high is the one replaced when needed. For a two-way
cache, the least recently used block is actually replaced. In
caches with a higher degree of associativity, a random block
having the used bit low is replaced. Such a policy is called
pseudo-LRU and is often good enough in practice.
In this paper, our aim is not to introduce a new way-
replacement algorithm, but to experiment if any information
relative to cache coherence, can be used to enhance the
performance of existing way-replacement policies. To that
purpose, we propose an approach to take the coherence state
into account, and we appraise our proposal on high-
performance parallel applications from the SPLASH-2 [16]
and PARSEC2.1 benchmark [17] using the Sniper simulator
[18].
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The contributions are the following:
• Elements of our replacement strategy based on the
current coherence state of cache blocks,
• Analysis of our proposal when combined with prominent
replacement policies (LRU, MRU and Random).
• We present probative indication that reinforces such an
approach should be thought in the next span of architectures
that figure on cache coherence.
The remainder of the paper is prepared as follows. Section
II presents related work. Our proposal contemplates cache
coherence state in way-replacement is disclosed in Section III.
Section IV presents simulation outcomes achieved on a state-
of-the-art simulator. Ultimately, Section V critiques the
outcomes and concludes the paper.
II. RELATED WORKS
In multi-core systems, accesses from multiple cores
compete for shared cache capacity. Inadequate management of
the shared cache can deteriorate system performance and end
in an unfair allocation of resources because one perverse
application can deprive the performance of all other
applications sharing the cache. For example, a workload with
streaming memory accesses can evict useful data belonging to
other recency-friendly applications. Shared caches in multi-
core processors introduce serious difficulties in providing
guarantees on the real-time properties of embedded software
due to the interaction and the resulting contention in the
shared caches. Hence recency-based and frequency-based
policies are not proficient about multicore processors [19].
Recency and frequency-based policies have been proposed
a long time ago, new way-replacement policies are still under
investigation. Observing the cache access patterns appeared in
three types: when the working set of application is diminutive
enough to meet in cache namely recency-friendly accesses, by
contrast, when the working set of application surpasses the
size of cache termed trashing accesses and finally when a
sequence of streaming accesses nevermore revolve called
scans[20]. Due to designing trash and scan resistant policy, an
adaptive policy that identifies the application behavior has
been developed [21]. A new cache replacement policy for
shared LLC called Application-aware Cache Replacement
(ACR) was proposed which prevents victimizing low-access
rate application by a high-access rate application. It
dynamically preserves track of maximum life-time of cache
lines in shared LLC for each concurrent application and heals
in efficient utilization of the cache space.
Another cache replacement policy that respects application
behaviour was proposed in [22]. Since the state-of-the-art
replacement policies like Static Re-reference Interval
Prediction (SRRIP) and Application Aware Behaviour Re-
reference Interval Prediction (ABRIP) [23] evict a cache block
based on their re-usability in the near future. SRRIP makes the
replacement decisions per block basis whereas ABRIP also
considers the cache behaviour of an application to minimize
conflicting data demands. Hence, ABRIP outperforms SRRIP
for workload mixes where one application is cache friendly,
and the other one is streaming. However, ABRIP does not
2020 6th Iranian Conference on Signal Processing and Intelligent Systems (ICSPIS)
perform well when the workload mix is Cache Friendly. Their
policy effectively utilizes the shared LLC and outperforms
both SRRIP and ABRIP with performance gains of up to
10.12% and 9.36% respectively.
We encountered only one recent competent study which
addresses replacement policy considering use of the coherence
state of a cache block on a multicore system regarding today’s
standards. A cache replacement policy that takes coherence
state into account is [24]. They proposed an algorithm which
decides on coherence state and sharing of cache blocks to
choose the best amongst the k for eviction in k-way set-
associative caches. They consider two main approaches to
prioritize the eviction of the block contained in one way over
another. The first one consists of counting how many sharers a
single cache block has and take this information into account
when an eviction is needed. In the second one, the decision of
evicting or not the cache block depends on its coherence state.
The main idea is to let the way-replacement algorithm select
the candidate for eviction, and then check if that candidate
should or not be evicted. In essence, by authors’ claim, they
implemented a second chance approach. This research takes
more investigations including miss rate, power consumption
and Instruction per Cycles (IPC) evaluation in comparison
with more well-known replacement policies using ‘Modified’,
‘Shared’, ‘Invalid’ (MSI), cache coherence protocol.
We design and implement a time-interleaved coherence
state aware approach for High-Performance Computing,
Graphics, Animations and Data Mining Application domains,
that differs from the related work. Considering the largest
realizable inputs, the proposed method should be trash
resistance and gains more information about past states of
blocks. This requires supplementary bits per each set
representing the history of blocks’ behaviour.
III. WAY-REPLACEMENT POLICY PROPOSAL
We recognise the main approach to prioritize the eviction
of the block which is basically the decision of evicting or not
the cache block depends on its coherence state in time-
interleaved windows.
For the purpose of this work, we use the ‘Modified’,
‘Exclusive’, ‘Shared’, ‘Invalid’ (MESI), cache coherence
protocol. Cache coherence is one of the main challenges to
tackle while designing a shared-memory multicore system.
Incoherence may happen when multiple associate cores in a
system are working on the same blocks of data without any
coordination. Coordination must be conducted by the
coherence protocol: a set of finite states machines, maintaining
the caches and memory and keeping the coherence invariants
true.
Our proposal is based on Coherence State Eviction in a
windowed time aperture in order to decide evicting or not a
cache block based on its current coherence state. Fig. 1 shows
an overview of the strategy. Each cache block has its own
coherence state, which is updated when there is a coherence
transition in time-interleaved aperture. Each cache set knows
the state of most recently used block was in the aperture of
recent time window. Supplementary bits are required per set,
updated when a cache access occurs on each set.
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Fig. 1. Overview of the proposed coherence state-based eviction strategy
The replacement algorithm is performed after the cache set
selection, accordingly to the set-associative mapping strategy.
A candidate way is chosen, and if the block is valid, its
coherence state is compared to the MRU-State, updated in the
time aperture. The replacement algorithm favours blocks that
are not in the same state than the current MRU-State for
eviction in a time-interleaved window of number of cache
access. If they are equal, the way selection is performed
another time. This is for considering not any cache access in
our strategy since adjacent instructions in time or order are
more in common in respect of their need for data to be fetched
from cache hierarchy. The time aperture is designed to reset
the MRU-State and obtains the advantage of temporal locality
even more.
IV. SIMULATIONS AND RESULT EVALUATION
Finally, we explain the details of the simulation
environment, then results that we obtained by evaluating our
proposal using simulation is exhibited in this section.
A. Simulation environment and benchmarks
To conduct our experiments, we used Sniper [18], a
multicore simulator. Sniper has integrated to its core the
McPAT framework [22], which we handled to measure power
consumption. We adjusted Sniper to set up our test
architectures and way-replacement algorithms. Regarding
McPAT, it uses the design parameters from Sniper, and
simulations output to assess the results. Hence, we did not
modify the power model in the framework. A 32-core
processor based on a Gainestown variant of x86 Nehalem
micro-architecture at 2.66 GHz was set. Some specific
characteristics from this micro-architecture cannot be
reproduced in Sniper though (e.g., Sniper only simulates an
inclusive cache model). Furthermore, data prefetching is
disabled in our simulations. The memory hierarchy has three
levels. L1 has 32kB for data and 32kB for instructions, each
one 4-way associative, private, with 4 cycles data access time,
using LRU replacement policy. L2 has 2MB, 8-way
associative, private cache, with an access time of 8 cycles. We
restricted the policy on last level cache during our
experiments. The last level is L3, with 8MB size, 16-way,
shared by 8, with 35 cycles of access time. The prefetching is
disabled in this experiment.
2020 6th Iranian Conference on Signal Processing and Intelligent Systems (ICSPIS)
TABLE I. WORKLOADS DOMAIN AND INPUT SIZE
Benchmark
Suite Application Domain Program Problem Size

barnes 65,536 particles

High-Performance
cholesky tk29.O
Computing
SPLASH-2 ocean 1026×1026 grid
radiosity Large Room
Graphics
raytrace Car
4 frames, 4,000
Computer Vision bodytrack
particles
1 frame, 372,126
facesim
tetrahedra
Animation
PARSEC2.1 5 frames, 300,000
fluidanimate
particles
freqmine 990,000 transactions
Data Mining 16,384 points per Fig. 2. LLC cache miss rate
streamcluster
block, 1 block

We used some of High-Performance Computing, Graphics,

Animation and Data mining domain of parallel workloads
from both the PARSEC2.1 and SPLASH-2 benchmark
detailed in Table 1 showing problem size for each selected
program which we desired as input size for each related
workload at the possible largest program size. Those
workloads were run using all 32 cores. In order that our
approach is not an exclusive cache replacement policy, we
have to apply our proposal on the basis of a well-known cache
replacement policy. Since the number of simulations would be
mathematical combinatorics of available combinations which
will be plenty, we decided to efficiently minimize the
representation of simulations thus we choose the most infirm
policy per each application for each metrics and evaluation as
the baseline cache replacement policy for that application. In
other words, if replacement policy i shows the most infirm
performance on application k due to metric j, the baseline
cache replacement policy for our proposal on application k in
respect to the metric j is the i cache replacement policy, ergo
our goal is to evaluate our proposal based on the worst-case
then attain the best result toward all other policies. We chose
to evaluate three metrics to understand the behaviour of our
cache replacement proposal: (1) L3 cache miss rate, (2)
Instructions per cycle (IPC) and (3) Power consumption.
1) L3 miss cache rate
We evaluate the miss rate of L3 cache which replacement
policies as our proposal have been implemented on. Results
have been evaluated by calculating the mean value of all
cores’ L3 miss rate while 4 replacement policy including
LRU, MRU, Random and the proposed method has been
chosen individually. Fig. 2 demonstrates that the miss rate per
aforementioned benchmark programs exhibiting the best
reduction concerning the best performance of other policies
has been achieved by 11.6% for cholesky and 10.9% for
bodytrack which are SPLASH-2 and PARSEC programs,
respectively. It should be stated that the proposed strategy
never exacerbates the miss rate and exhibits performance as
LRU in the most unfavourable case. We also evaluated the
MPKI which indicates how many misses per 1000 instructions
has occurred. Fig. 3 depicts MPKI has been never increased
obtaining best reduction by 5% for ocean and 7.5% for
facesim. This should be regarded that the exact values of
MPKI for ocean are 10 times higher and for ease of visual—
Fig. 3. MPKI
comparison concerning the other programs, the values for
ocean program have been divided by 10 individually.
2) Instruction per Cycle evaluation
We evaluated the IPC in order to understand the
performance of our approach. Fig. 4 depicts the evaluated
values of IPC for each application. The proposed strategy
advances IPC for all applications. The improvement rate with
respect to the best IPC is 9% to 10% during all SPLASH-2
programs and toward PARSEC programs we achieved the
highest rate for facesim 20.8% and the lowest for freqmine
0.8% while improvement rate for the other PARSEC programs
is 6.6% to 7.8%.
3) Energy and Power consumption
The energy consumptions have been evoked from McPAT
inside Sniper and illustrated in detail measured in Joules and
power consumption in Watts due to the diversity of execution
time for each program. Fig. 5 and Fig. 6 presents the energy
consumptions with details of core and cache shares for tested
applications of SPLASH-2 and PARSEC benchmarks,
respectively. Each bar in groups shows the value for 4
replacement policies, which are from left to right, LRU, MRU,
Random and proposed policy. These figures describe that the
obtained improvements in L3 cache miss rate and IPC do not
incite more energy consumption. Due to the better IPC for the
proposed strategy, total power consumption measured in
Watts is also improved, illustrated in Fig. 7 represents no
additional power has been employed. It should be noted that,

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2020 6th Iranian Conference on Signal Processing and Intelligent Systems (ICSPIS)
due to the facility of visual comparison, the actual values of
cholesky and raytrace in Fig. 5 are a quarter of depicted
values. Furthermore, the actual values for freqmine in Fig. 6
are 10 times the figured values, due to ease of visual
comparison.

V. CONCLUSIONS
In this paper, we conducted a way-replacement in time-
interleaved approach for the eviction of blocks in cache
memories on a multicore system. We chose to evaluate if the
coherence state conversance in a time aperture of a cache
block considering access patterns can be used to improve the
overall performance and energy consumption. To perform this
evaluation, we considered the cache block state in a time-
interleaved aperture, deciding to evict or not the block. Using
Fig. 6. Energy consumption for PARSEC2.1 applications
the Sniper simulator and applications from PARSEC2.1 and
SPLASH-2 benchmark, our results confirmed that our
proposal improves the cache miss rate and IPC without further
power consumption on high performance computing, graphics,
computer vision, animation and data mining applications. We
conclude that time-interleaved coherence state information of
a cache block can be employed to enhance the performance of
cache way-replacement in high-performance computing
multicore systems.

Fig. 7. Total power consumption

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