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How Can You Rectify it? AuWhat isthe command to find hidden files in the current directory ? ie asiee piping and explain with an example in Unix. : 13, Write down the command to search and replace a pattern into Vi editor. acy is NAND gate preferred over NOR gate for fabrication ? 45-Whhat is the fundamental difference between a MOSFET and BIT ? hat is effect in CMOS inverter if| wil interchange the NMOS and PMOS? 124 What is Latch up in CMOS, how to resolve it? What is threshold voltage and channel length, what are the challenges in lower node technology? 18-Explain about setup time and hold time, what will happen if there is setup time and hold time violation and which will have high priority ? 2oC bln these terminology : DEF, SPEF, SDF, UPF, LEE U/oe w the circuit diagram of 2-input NOR and NAND gate using CMOS logic. ist Out all the inputs for PD and explain the information associated to it. ey hat is sanity check and explain the significance of it with ICC command, E plain the PD flow with flow diagram with importance of each stages. “yn ‘at is importance of SDC file, Write 5 SDC commands and explain the uses of it. ust out all Pre Placed cells and explain its uses. WZeTirite down the guidelines to place the Macros into Core area, Why Macro can’t be flip by 90 degree and how to find the channel . 28. Write down inputs for PT and which net-lst will be used for PT, what is command to fix the timing. violation, 28. Whatis difference between Placement and Place_Opt Explain the commands Place_opt, Psynopt and refine_placement, Scanned with CamScanner3D-What the report we need to check after placement write i's command also. 31 White down the differences between STA and Dynamic timing analysis 32-How to do power planning and to do It’s analysis. 337 What is signoff and what are the checks we do In this stage. ‘347 List the Logleal DRCs and its SDC command. 35. List down commands t extract spef and command to generate sdf fi ification. List down differences between Wvsand dre 367 List down detailed steps in physical ver 37/ist down differences between functional and timing Eco. 38-“What is congestion, Cell density and pin density and how to resolve congestion? 39--Weite a command to see the report of ony all negative slack in sete and hold check? pe also write the command to create a partial blockage (40--Explain the Blockage and its ty ‘317 What is propagation delay and transition delay in clock. 4 p-wyhat is lock latency delay, clock source delay and clock network delay. (27 Explain the NOR and Default routing, write down its advantage and disadvantage? lain source, sink, float and exclude pins in CTS. ‘command. ee is Keep outetfargin and Bounds please explain with secfoe down all the stages after that we can do the STA analysis. Explain the clock exceptions and write its commands. 4g/What is level shifter, Isolation cells and write its uses and type. ip variation and interchip_ variation how to consider this in analysis . 4g-Athat is intrachi , OCV, AOCY and POCV. hich we set before CLOCK_OPT? Explain in deta) i CRPR 51. What we do in PRE-CTS stage, write down all specification w! Write down the steps of routing and explain them. rat is cross talk, how it comes and write down the methods to avoid the crosstalk. out all the possible ways. in terms of VT and Drive Strength, also list out its fow to fix setup and hold violations, 55. Explain the variant of cell present in library ‘advantage and disadvantage in terms of PPA. “ALL THE BEST Scanned with CamScanner