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  • Lenovo Ideapad 320-14IKB LCFC DG425 DG525 NM-B321 Schematic Diagram

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    11 views50 pages

    Lenovo Ideapad 320-14IKB LCFC DG425 DG525 NM-B321 Schematic Diagram

    Uploaded by

    Marcelo Jorquera

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 50

    A B C D E

    LCFC Confidential
    1 1

    G 320 AST M/B Schematics Document


    NM_B321 REV:0.2
    2 2

    AMD FT4 Stoney SOC with DDRIIII


    AMD R17M-M1-70
    2017-02-04
    3 3

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Cover Page
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 1 of 50
    A B C D E
    A B C D E

    LCFC confidential
    File Name : German

    AMD: R17M-M1-70
    Package: S3 PCI-Express Memory BUS (DDR4)
    Page 15~19 PCIe Port 1~4 Single Channel B DDR4-SO-DIMM X1
    4x Gen3 Page 12
    1
    VRAM: 512/256*16 1.2V DDR4 2133 MT/s 1

    GDDR5*4: 4GB/2GB 1866 MT/s UP TO 8G


    Page 20~23
    USB3.0 x1 USB3.0 Left Conn
    USB2.0 x1 USB3.0 Port1
    HDMI Conn. HDMI x4 Lane Port1 USB2.0 Port5 Page 41
    Page 25 AMD FT4 APU
    Stoney 15W USB3.0 x1 USB3.0 Left Conn
    USB2.0 x1 USB3.0 Port3
    USB2.0 Port7 Page 41
    Page 26
    eDP x2 Lane (Integrated FCH)
    eDP Conn USB3.0 x1 USB3.0 Redriver Type-C IC
    USB2.0 1x USB2.0 x1 Parade PS8713 Realtek RTS5449
    Int. Camera Page 43 Page 43
    USB2.0 Port3
    2 2

    Int. MIC Conn. USB2.0 x1 Touch Screen (Optional) Type-C Conn


    USB2.0 Port8 Page 33 Page 43
    Page 23

    SATA HDD SATA Gen3 USB2.0 x1 Finger Print (Optional)


    Page 33 SATA Port0
    BGA-769 USB2.0 Port1 Page 45
    24mm*24mm
    SATA ODD SATA Gen1 USB 2.0 1x NGFF Card
    Page 33 SATA Port1 WLAN&BT
    PCIe 1x Key E
    PCIe Port1
    Page 31 USB2.0 Port2
    LAN Realtek
    RJ45 Conn. PCIe 1x
    Page 29
    Realtek_RTL8111GUL SPI BUS SPI ROM
    3
    8MB Page 08 3
    Page 28 PCIe Port2

    Page 4~11
    Touch Pad
    SD/MMC Conn. Page 36
    Page 24
    Codec & C/R USB2.0 x1
    SPK Conn.
    HD Audio
    Page 34 Realtek RTS5119 EC
    ITE IT8586E-LQFP
    HP&Mic Combo Conn. Page 35
    Page 34
    Page 30 USB2.0 Port4 Sub-board ( for 15")

    Int.KBD Thermal Sensor TPM (Reserved) ODD Board


    4 Page 36 NCT7718W Z32H320TC 4
    Page 30 reserve Page 30

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Block Diagram


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 2 of 50


    A B C D E
    A B C D E

    Voltage Rails ( O --> Means ON , X --> Means OFF )


    SIGNAL
    +5VS STATE SLP_S3# SLP_S5# +VALW +V +VS Clock BOARD
    Config. BOARD_ID1 BOARD_ID2 reserve
    +3VS
    S0 (Full ON) HIGH HIGH ON ON ON ON 0: Dis 0: No KBL
    +1.8VS
    1: UMA 1: KBL
    power +1.5VS S1 (Power On Suspend) HIGH HIGH ON ON ON LOW
    plane B+ +5VALW +2.5V
    (+20VSB) +1.2V +0.95VS
    1 (+VSYSMEM_APU) S3 (Suspend to RAM) LOW HIGH ON ON OFF OFF BOARD 1
    +3VALW +0.6VS Config. BOARD_ID0 BOARD_ID3
    +3VL (+3VALW_APU)
    +APU_CORE S4 (Suspend to Disk) LOW LOW ON OFF OFF OFF 14'' 0 0
    +5VLP +APU_CORE_NB 15'' 0 1
    +1.8VALW S5 (Soft OFF) LOW LOW ON OFF OFF OFF
    +APU_GFX 17'' 1 0
    +0.95VALW +VGA_CORE
    State
    +3VGS
    +0.775VALW
    +1.8VGS USB Port Table for Stoney FT4
    +1.35VGS
    +0.95VGS
    USB 2.0 USB 3.0 Port Port device BOM Structure Table
    0 Finger print BOM Structure BTO Item
    1 Blue Tooth @ Not stuff
    O O O O EHCI
    S0 2 Camera ME@ Connector
    3 Card Reader 14@ For 14" part
    S3
    O O O X 4 LEFT USB (3.0) 15@ For 15" part
    5 Type-C EMC@ EMC Part

    S5 S4/AC
    xHCI 2 6 RighT USB (3.0) upper EMC_NS@ EMC reserve Part
    2 O O X X 7 Touch screen EMC_PX@ EMC GPU part 2

    EMC_CZ@ EMC Carrizo APU part


    S5 S4/ Battery only
    O X X X PCIE PORT LIST EMC_15@ EMC 15 part
    RF_NS@ RF reserve Part

    S5 S4/AC & Battery Port Device RF_PXNS@ RF GPU reserve part


    don't exist X X X X UMA@ UMA SKU ID part
    0 N/A
    PX@ Discrete GPU SKU part
    GPP
    1 WLAN
    EXO@ EXO GPU Part
    2 LAN
    TOPAZ@ TOPAZ GPU Part
    SMBUS Control Table 3 N/A
    TPM@ TPM part
    0 AOAC@ AOAC support part
    SOURCE GPU BATT IT8586E SODIMM WLAN Thermal APU Charger PMIC Touch
    GFX
    1 HDT@ HDT Debug part
    Sensor Pad DIS GPU
    2 TS@ Touch screen part
    EC_SMB_CK1
    3 CZ@ Carrizo Part
    IT8586E
    EC_SMB_DA1 X V X X X X V X X CZL@ CarrizoL part
    +3VL_EC
    CZPX@ Carrizo Discrete Part
    3
    EC_SMB_CK3 V CZLPX@ CarrizoL Discrete Part 3

    EC_SMB_DA3
    IT8586E V X X X V
    APU_SIC
    APU_SID
    1.8VS for AST
    X X X S4GX4@ X76 SAMSUNG 2G
    +3VS +3VS_VGA
    M4GX4@ X76 MICRON 2G
    APU_SMB_CLK APU H4GX4@ X76 HYNIX 2G
    APU_SMB_DATA
    +3VS X X X V V X X X X S2GX4@ X76 SAMSUNG 1G
    M2GX4@ X76 MICRON 1G
    EC_SMB_CK2
    IT8586E
    H2GX4@ X76 HYNIX 1G
    EC_SMB_DA2 X X X X X X X V X S2G@ SAMSUNG 2G
    +3VL_EC
    M2G@ MICRON 2G
    H2G@ HYNIX 2G
    TP_I2C0_SCL_R APU VRAM
    TP_I2C0_SDA_R
    +1.8VS X X X X X X X X V S1G@ SAMSUNG 1G
    M1G@ MICRON 1G
    EC SM Bus1 address EC SM Bus2 address EC SM Bus3 address H1G@ HYNIX 1G

    Device Device Device


    CZLUMA@ CarrizoL UMA Part
    Address Address Address
    Battery 0X16 PMIC 0X34 Thermal Sensor 1001_100xb(reserve)
    CZUMA@ Carrizo UMA Part

    Charger 0001 0010 b GPU 0x41(default) SIVCD@ SIV COST down material
    4 4
    APU SB-TSI releate to F3x1E4[SbiAddr] or HDMI@ HDMI Logo
    Address Select Pins setting STN@ Stoney part

    APU SM Bus1 address APU SM Bus2 APU SM Bus3 address APU SM Bus4 KBL@ Key board backlight part

    Security Classification LC Future Center Secret Data Title


    Device Address Device Address
    Notes List
    No use No use
    Issued Date 2017/02/04 Deciphered Date 2017/02/04
    Touch pad 0x15 DDR DIMM 0xA0h THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 0.2
    WLAN RSVD
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 3 of 50
    A B C D E
    5 4 3 2 1

    D D

    UC2B

    PCIE

    U4 D2
    U5 P_GPP_RXP0 P_GPP_TXP0 D1
    P_GPP_RXN0 P_GPP_TXN0
    PCIE_PRX_DTX_P1 R8 C2 PCIE_PTX_DRX_P1 CC1 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P1
    31 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 31
    R10 C1 1 2 0.1U_0201_6.3V6-K
    WLAN 31 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1
    CC2
    PCIE_PTX_C_DRX_N1 31 WLAN
    PCIE_PRX_DTX_P2 R5 B2 PCIE_PTX_DRX_P2 CC3 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P2
    28 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 P_GPP_RXP2 P_GPP_TXP2 PCIE_PTX_DRX_N2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P2 28
    R4 B1 1 2 0.1U_0201_6.3V6-K
    LAN 28 PCIE_PRX_DTX_N2 P_GPP_RXN2 P_GPP_TXN2
    CC4
    PCIE_PTX_C_DRX_N2 28 LAN
    N4 A3
    N5 P_GPP_RXP3 P_GPP_TXP3 B3
    P_GPP_RXN3 P_GPP_TXN3
    C C

    PCIE_CRX_GTX_P0 L5 A4 PCIE_CTX_GRX_P0 CC5 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0


    15 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 P_GFX_RXP0 P_GFX_TXP0 PCIE_CTX_GRX_N0 PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_P0 15
    L4 B4 CC6 PX@1 2 0.22U_0201_6.3V6-K
    15 PCIE_CRX_GTX_N0 P_GFX_RXN0 P_GFX_TXN0 PCIE_CTX_C_GRX_N0 15
    PCIE_CRX_GTX_P1 J5 A5 PCIE_CTX_GRX_P1 CC7 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
    15 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 P_GFX_RXP1 P_GFX_TXP1 PCIE_CTX_GRX_N1 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_P1 15
    J4 B5 PX@1 2 0.22U_0201_6.3V6-K
    15 PCIE_CRX_GTX_N1 P_GFX_RXN1 P_GFX_TXN1
    CC8
    PCIE_CTX_C_GRX_N1 15 GPU
    GPU PCIE_CRX_GTX_P2 G5 A6 PCIE_CTX_GRX_P2 CC9 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
    15 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 P_GFX_RXP2 P_GFX_TXP2 PCIE_CTX_GRX_N2 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_P2 15
    G4 B6 CC10 PX@1 2 0.22U_0201_6.3V6-K
    15 PCIE_CRX_GTX_N2 P_GFX_RXN2 P_GFX_TXN2 PCIE_CTX_C_GRX_N2 15
    PCIE_CRX_GTX_P3 D7 A7 PCIE_CTX_GRX_P3 CC11 PX@1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
    15 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 P_GFX_RXP3 P_GFX_TXP3 PCIE_CTX_GRX_N3 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_P3 15
    E7 B7 CC12 PX@1 2 0.22U_0201_6.3V6-K
    15 PCIE_CRX_GTX_N3 P_GFX_RXN3 P_GFX_TXN3 PCIE_CTX_C_GRX_N3 15
    +0.95VS

    196_0402_1% 1 2 STN@ RC1 P_TX_ZVDD U8 W8 P_RX_ZVDD


    P_ZVDDP P_ZVSS
    FT4 REV 0.93
    196_0402_1% 1 2 STN@ RC3

    with BOM strcture control, RC1 change to 196_0402_1% for Stoney and Carrizo AMD-STONEY-FT4_BGA769
    @
    CarrizoL not support GFX4-GFX7

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (PCIE I/F)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 4 of 50
    5 4 3 2 1
    5 4 3 2 1

    DDRB_DQS[0..7]
    12 DDRB_DQS[0..7]
    DDRB_DQS#[0..7]
    12 DDRB_DQS#[0..7]

    UC2A
    MEMORY
    12 DDRB_MA[13..0] DDRB_MA0 DDRB_DQ0 DDRB_DQ[63..0] 12
    AG38 A34
    DDRB_MA1 W35 M_ADD0 M_DATA0 B34 DDRB_DQ1
    D DDRB_MA2 W38 M_ADD1 M_DATA1 A38 DDRB_DQ2 D
    DDRB_MA3 W34 M_ADD2 M_DATA2 B38 DDRB_DQ3
    DDRB_MA4 U38 M_ADD3 M_DATA3 A33 DDRB_DQ4
    DDRB_MA5 U37 M_ADD4 M_DATA4 B33 DDRB_DQ5
    DDRB_MA6 U34 M_ADD5 M_DATA5 A37 DDRB_DQ6
    DDRB_MA7 R35 M_ADD6 M_DATA6 B37 DDRB_DQ7
    DDRB_MA8 R38 M_ADD7 M_DATA7
    DDRB_MA9 N38 M_ADD8 B41 DDRB_DQ8
    DDRB_MA10 AG34 M_ADD9 M_DATA8 C40 DDRB_DQ9
    DDRB_MA11 R34 M_ADD10 M_DATA9 F41 DDRB_DQ10
    DDRB_MA12 N37 M_ADD11 M_DATA10 G40 DDRB_DQ11
    DDRB_MA13 AN35 M_ADD12 M_DATA11 A40 DDRB_DQ12
    DDRB_BG1 L38 M_ADD13 M_DATA12 B40 DDRB_DQ13
    12 DDRB_BG1 DDRB_ACT# M_ADD14/M_BG1 M_DATA13 DDRB_DQ14
    L35 E41
    12 DDRB_ACT# M_ADD15/M_ACT_L M_DATA14 DDRB_DQ15
    F40
    DDRB_BA0 AJ38 M_DATA15
    12 DDRB_BA0 DDRB_BA1 M_BANK0 DDRB_DQ16
    AG35 J40
    12 DDRB_BA1 DDRB_BG0 M_BANK1 M_DATA16 DDRB_DQ17
    N34 J41
    12 DDRB_BG0 M_BANK2/M_BG0 M_DATA17 N40 DDRB_DQ22 DATA16--DATA23 Byte internal swap
    12 DDRB_DM[7..0] DDRB_DM0 M_DATA18 DDRB_DQ23
    B35 N41
    DDRB_DM1 D40 M_DM0 M_DATA19 H40 DDRB_DQ20
    DDRB_DM2 K40 M_DM1 M_DATA20 H41 DDRB_DQ21
    DDRB_DM3 T41 M_DM2 M_DATA21 M40 DDRB_DQ19
    DDRB_DM4 AE41 M_DM3 M_DATA22 M41 DDRB_DQ18
    DDRB_DM5 AL40 M_DM4 M_DATA23
    DDRB_DM6 AU40 M_DM5 R40 DDRB_DQ24
    DDRB_DM7 BA37 M_DM6 M_DATA24 T40 DDRB_DQ25
    M_DM7 M_DATA25 W40 DDRB_DQ26
    M_DATA26 Y40 DDRB_DQ27 DATA24--DATA31 Byte internal swap
    DDRB_DQS0 B36 M_DATA27 P40 DDRB_DQ29
    DDRB_DQS#0 A36 M_DQS_H0 M_DATA28 P41 DDRB_DQ28
    DDRB_DQS1 E40 M_DQS_L0 M_DATA29 V40 DDRB_DQ30
    DDRB_DQS#1 D41 M_DQS_H1 M_DATA30 V41 DDRB_DQ31
    DDRB_DQS2 L40 M_DQS_L1 M_DATA31
    DDRB_DQS#2 K41 M_DQS_H2 AD41 DDRB_DQ36
    C DDRB_DQS3 U41 M_DQS_L2 M_DATA32 AD40 DDRB_DQ32 C
    DDRB_DQS#3 U40 M_DQS_H3 M_DATA33 AH41 DDRB_DQ39 DATA32--DATA39 Byte internal swap
    DDRB_DQS4 AF41 M_DQS_L3 M_DATA34 AH40 DDRB_DQ35
    DDRB_DQS#4 AE40 M_DQS_H4 M_DATA35 AB40 DDRB_DQ33
    DDRB_DQS5 AM40 M_DQS_L4 M_DATA36 AC40 DDRB_DQ37
    DDRB_DQS#5 AM41 M_DQS_H5 M_DATA37 AF40 DDRB_DQ34
    DDRB_DQS6 AV40 M_DQS_L5 M_DATA38 AG40 DDRB_DQ38
    DDRB_DQS#6 AV41 M_DQS_H6 M_DATA39
    DDRB_DQS7 BA36 M_DQS_L6 AK41 DDRB_DQ41
    DDRB_DQS#7 AY36 M_DQS_H7 M_DATA40 AK40 DDRB_DQ44
    M_DQS_L7 M_DATA41 AP41 DDRB_DQ43 DATA40--DATA47 Byte internal swap
    M_DATA42 AP40 DDRB_DQ47
    M_DATA43 AJ41 DDRB_DQ45
    DDRB_CLK0 AC35 M_DATA44 AJ40 DDRB_DQ40
    12 DDRB_CLK0 DDRB_CLK0# M_CLK_H0 M_DATA45 DDRB_DQ46
    AC34 AN41
    12 DDRB_CLK0# DDRB_CLK1 M_CLK_L0 M_DATA46 DDRB_DQ42
    AA34 AN40
    12 DDRB_CLK1 DDRB_CLK1# M_CLK_H1 M_DATA47
    AA32
    12 DDRB_CLK1# M_CLK_L1 DDRB_DQ54
    AE38 AT40
    AE37 M_CLK_H2 M_DATA48 AU41 DDRB_DQ53
    AA37 M_CLK_L2 M_DATA49 AY40 DDRB_DQ50 DATA48--DATA55 Byte internal swap
    AA38 M_CLK_H3 M_DATA50 BA40 DDRB_DQ52
    M_CLK_L3 M_DATA51 AR40 DDRB_DQ49
    RC240 1 2 10_0402_5% MEM_MB_RST#_R G38 M_DATA52 AT41 DDRB_DQ48
    12 MEM_MB_RST# MEM_MB_EVENT# AA41 M_RESET_L M_DATA53 DDRB_DQ51
    AW40
    12 MEM_MB_EVENT# M_EVENT_L M_DATA54 DDRB_DQ55
    AY41
    DDRB_CKE0 J38 M_DATA55
    12 DDRB_CKE0 DDRB_CKE1 M0_CKE0 DDRB_DQ60
    J34 BA38
    12 DDRB_CKE1
    L34 M0_CKE1 M_DATA56 AY37 DDRB_DQ57 DATA56--DATA63 Byte internal swap
    J37 M1_CKE0 M_DATA57 BA34 DDRB_DQ58
    M1_CKE1 M_DATA58 BA33 DDRB_DQ59
    DDRB_ODT0 AN37 M_DATA59 AY39 DDRB_DQ61
    12 DDRB_ODT0 DDRB_ODT1 M0_ODT0 M_DATA60 DDRB_DQ56
    AU38 AY38
    12 DDRB_ODT1 M0_ODT1 M_DATA61 DDRB_DQ63
    AL34 AY35
    AN34 M1_ODT0 M_DATA62 AY34 DDRB_DQ62
    B
    M1_ODT1 M_DATA63 B
    DDRB_CS0# AL35
    12 DDRB_CS0# DDRB_CS1# M0_CS_L0
    AR37
    12 DDRB_CS1# M0_CS_L1
    AJ34
    AR38 M1_CS_L0
    M1_CS_L1
    DDRB_MA16_RAS# AJ37
    12 DDRB_MA16_RAS# DDRB_MA15_CAS# AN38 M_RAS_L/M_RAS_L_ADD16 +1.2V
    12 DDRB_MA15_CAS# DDRB_MA14_WE# AL38 M_CAS_L/M_CAS_L_ADD15
    12 DDRB_MA14_WE# M_WE_L/M_WE_L_ADD14
    @ TC86 1 +MEM_VREF AA40
    @ TC70 1 APU_M_VREFDQ Y41 M_VREF AB41 MB_ZVDDIO RC10 1 2 39.2_0402_1%
    M_VREFDQ M_ZVDDIO_MEM_S3
    FT4 REV 0.93

    AMD-STONEY-FT4_BGA769
    @

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (MEM)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 5 of 50
    5 4 3 2 1
    5 4 3 2 1

    APU_SVT

    APU_SVC

    APU_SVD

    +3VS_APU

    0.01U_0201_25V6-K

    0.01U_0201_25V6-K

    0.01U_0201_25V6-K
    1 1 1

    CC1286

    CC1287

    CC1288
    RPC18
    UC2C APU_DDC_CLK 1 4
    APU_DDC_DATA 2 3
    +1.8VS 2 2 2 DISPLAY/SVI2/JTAG/T EST
    @ @ @ RC249 1 2 0_0402_5% APU_SVT_L H27 B23 DP_ENBKL 2.2K_0404_4P2R_5%
    50 APU_SVT 1 2 22_0402_5% APU_SVC_L E27 SVT DP_BLON B24 DP_ENVDD
    RC213
    50 APU_SVC 2 22_0402_5% APU_SVD_L SVC DP_DIGON DP_EDP_PWM
    1

    RC215 1 D27 A24


    50 APU_SVD SVD DP_VARY_BL APU_EDP_HPD
    RC18 RC35 1 2 100K_0402_5%
    300_0402_5% APU_SIC B30 D21 DP_150_ZVSS RC12 1 2 150_0402_1%
    D APU_SID SIC DP_AUX_ZVSS DP_2K_ZVSS D
    B29 B18 RC55 1 2 2K_0402_1%
    ALERT# A30 SID DP_ZVSS
    APU_RST# APU_PROCHOT#_R ALERT_L APU_EDP_AUX
    2

    RC31 1 @ 2 0_0402_5% A31 G15 +1.8VS


    35,47 H_PROCHOT# PROCHOT_L DP0_AUXP H15 APU_EDP_AUX# APU_EDP_AUX 23 RPC11
    PLACE CC16 CAPS CLOSE TO APU,CRB reserve 27pf APU_PWROK G25 DP0_AUXN D15 APU_EDP_HPD APU_EDP_AUX# 23 eDP ALERT# 3 2
    50 APU_PWROK APU_RST# D29 PWROK DP0_HPD APU_EDP_HPD 23 APU_PROCHOT#_R 4 1
    1 RESET_L APU_DDC_CLK
    CC16 G17
    DP1_AUXP H17 APU_DDC_DATA APU_DDC_CLK 24
    150P_0402_50V8-J
    @ APU_SVT_L APU_TDI B25 DP1_AUXN D17 APU_HDMI_HPD APU_DDC_DATA 24 HDMI 1K_0404_4P2R_5%
    2 APU_TDO A27 TDI DP1_HPD APU_HDMI_HPD 24
    APU_TCK TDO

    1
    CC210 B27 G19
    APU_PWROK 1000P_0402_25V7-K APU_TMS B26 TCK DP2_AUXP H19
    APU_TRST# A29 TMS DP2_AUXN D19
    @
    APU_DBRDY TRST_L DP2_HPD To EDP panel

    2
    A26 +3VS_APU
    +1.8VS APU_DBREQ# A25 DBRDY A9 APU_EDP_TX0+
    1 DBREQ_L DP0_TXP0 APU_EDP_TX0- APU_EDP_TX0+ 23
    CC1276 B9
    DP0_TXN0 APU_EDP_TX1+ APU_EDP_TX0- 23

    1
    0.01U_0201_25V6-K A10
    DP0_TXP1 APU_EDP_TX1- APU_EDP_TX1+ 23 eDP
    1

    EMC@ B10 +3VALW_APU RC70


    2 DP0_TXN1 A11 APU_EDP_TX1- 23
    RC19 4.7K_0402_5%
    300_0402_5% DP0_TXP2 B11
    DP0_TXN2

    2
    A12
    DP0_TXP3

    2
    B12 RC71
    DP0_TXN3
    2

    10K_0402_5%
    APU_PWROK +3VALW_APU A14 APU_HDMI_TX2+ PCH_EDP_PWM 23
    Core_type DP1_TXP0 APU_HDMI_TX2- APU_HDMI_TX2+ 24
    100K_0402_5% 2 @ 1 RC239 D9 B14
    RSVD_1 DP1_TXN0 APU_HDMI_TX1+ APU_HDMI_TX2- 24

    1
    PLACE CC17 CAPS CLOSE TO APU,CRB reserve 27pf D11 A15
    RSVD_2 DP1_TXP1 APU_HDMI_TX1- APU_HDMI_TX1+ 24

    3
    D13 B15
    1
    CC17 E4 RSVD_3 DP1_TXN1 A16 APU_HDMI_TX0+ APU_HDMI_TX1- 24 HDMI 5
    D
    QC8B
    150P_0402_50V8-J E31 RSVD_4 DP1_TXP2 B16 APU_HDMI_TX0- APU_HDMI_TX0+ 24 G
    RSVD_5 DP1_TXN2 APU_HDMI_CLK+ APU_HDMI_TX0- 24 DMN5L06DWK-7 2N SOT363-6
    @ H11 A17
    2 RSVD_6 DP1_TXP3 APU_HDMI_CLK- APU_HDMI_CLK+ 24

    6
    H13 B17 D S
    RSVD_7 DP1_TXN3 APU_HDMI_CLK- 24

    4
    L11 2 QC8A
    AE34 RSVD_8 A19 DP_EDP_PWM G
    C RSVD_9 DP2_TXP0 DMN5L06DWK-7 2N SOT363-6 C
    AM15 B19
    +1.8VS +1.8VS AM17 RSVD_10 DP2_TXN0 A20 S
    RSVD_11 DP2_TXP1

    1
    1
    AM19 B20
    AN8 RSVD_12 DP2_TXN1 A21 RC11
    AP13 RSVD_13 DP2_TXP2 B21 100K_0402_5%
    AP15 RSVD_14 DP2_TXN2 A22
    RSVD_15 DP2_TXP3
    4
    3

    AP17 B22
    RSVD_16 DP2_TXN3

    2
    RPC10 AR13 RC2051 @ 2 0_0402_5%
    RSVD_17
    5

    1K_0404_4P2R_5% AR15
    G

    STN@ AR17 RSVD_18 H29


    AU4 RSVD_19 TEST4 G29 TEST5 1 @ TC14
    RSVD_20 TEST5
    1
    2

    AU13 H25 +3VS_APU


    APU_SIC 4 3 EC_SMB_CK3 AU15 RSVD_21 TEST6 R32 TEST9 1 @ TC80
    S

    EC_SMB_CK3 16,30,35 AU17 RSVD_22 TEST9 N32 TEST10 1 @


    D

    TC81
    STN@ AV7 RSVD_23 TEST10 G21 APU_TEST14_BP0 RC21 1 @ 2 1K_0402_5%
    QC6B RSVD_24 TEST14 APU_TEST15_BP1
    2

    1
    AV9 H21 1 @ TC18
    G

    DMN5L06DWK-7 2N SOT363-6 AV11 RSVD_25 TEST15 D23 APU_TEST16_BP2 RC23 1 @ 2 1K_0402_5% +3VALW_APU RC74
    AV13 RSVD_26 TEST16 E23 APU_TEST17_BP3 RC24 1 @ 2 1K_0402_5% RPC14 1K_0404_4P2R_5% 4.7K_0402_5%
    AV15 RSVD_27 TEST17 A28 APU_TEST18_PLLTEST1 4 1 @
    APU_SID EC_SMB_DA3 RSVD_28 TEST18 APU_TEST19_PLLTEST0 +1.8VS

    2
    1 6 AV17 B28 3 2
    S

    EC_SMB_DA3 16,30,35 RSVD_29 TEST19 APU_TEST28_H_PLLCHARZ

    2
    AY3 N8 1 @ RC73
    D

    TC21
    AY7 RSVD_30 TEST28_H N10 APU_TEST28_L_PLLCHARZ 1 @ PCH_ENVDD 23
    STN@ TC23 10K_0402_5%
    QC6A RSVD_31 TEST28_L H31 APU_TEST31_MEM_TEST 1 @ TC25 RC28 1 2 1K_0402_5% @
    DMN5L06DWK-7 2N SOT363-6 TEST31 D25 APU_TEST36_STEREOSYNC RC27 1 2 1K_0402_5%
    DP_STEREOSYNC/TEST36

    3
    B31 TEST41 1 @ TC78 @ D
    TEST41 5 QC9B
    D31 APU_VDDCORE_SEN_H G
    VDDCR_CPU_SENSE APU_VDDNB_SEN_H APU_VDDCORE_SEN_H 50 DMN5L06DWK-7 2N SOT363-6
    E33
    VDDCR_NB_SENSE VDDIO_MEM_S3_SENSE APU_VDDNB_SEN_H 50 @
    D35 1 S
    VDDIO_MEM_S3_SENSE VDD_095_FB_H TC76 @

    4
    6
    AM21 1 D
    VDDP_SENSE TC26 @ DP_ENVDD 2 QC9A
    D33 APU_VSS_SEN_L RC2361 2 0_0402_5% G
    VSS_SENSE_A VSS_SENSE_B APU_VDD_SEN_L 50 DMN5L06DWK-7 2N SOT363-6
    AM23 1
    VSS_SENSE_B TC77 @ @

    1
    B FT4 REV 0.93 S B

    1
    RC13
    100K_0402_5%
    AMD-STONEY-FT4_BGA769 @
    APU_VDDNB_SEN_H 1 @ TC27
    @

    2
    RC2061 2 0_0402_5%
    APU_VDDCORE_SEN_H 1 @ TC28 LCD Power IC can change for PCH_ENVDD for cost down
    APU_VDD_SEN_L 1 @ TC29
    +3VS_APU
    With HDT+ Header
    +1.8VS +1.8VS

    2
    +1.8VS JHDT1 @ RPC5 +1.8VS +1.8VS RC77
    1 2 APU_TCK 8 1 +3VALW_APU
    1 2 2.2K_0402_5%
    7 2
    APU_TMS +1.8VS @
    3 4 6 3 1
    3 4

    1
    2

    2
    5 4
    RC7 5 6 APU_TDI CC25 RC32 RC36 RC75
    5 6 0.1U_0201_6.3V6-K PCH_ENBKL 23
    1K_0402_5% 1K_0804_8P4R_5% 300_0402_5% 300_0402_5% 10K_0402_5%
    APU_TDO 2

    2
    7 8 HDT@ @
    7 8 RC274
    APU_TRST# 2 33_0402_5% APU_TRST#_R APU_PWROK_BUF
    1

    3
    RC76 1 HDT@ 9 10 UC6 39.2_0402_1% D
    9 10 APU_PWROK 3 4 APU_PWROK_BUF 5 QC10B
    11 12 APU_RST#_BUF 2A 2Y G
    2 11 12 DMN5L06DWK-7 2N SOT363-6

    1
    2 5
    APU_DBRDY GND VCC APU_TEST31_MEM_TEST@ @
    CC84 13 14 S
    13 14 APU_RST# APU_RST#_BUF

    4
    6
    0.01U_0201_10V6K 1 6 D
    1 2 33_0402_5% APU_DBREQ# 1A 1Y DP_ENBKL

    2
    15 16 RC273 1 HDT@ 2 QC10A
    15 16 HDT@ SN74LVC2G07YZPR_WCSP6 RC275 G
    APU_TEST19_PLLTEST0 DMN5L06DWK-7 2N SOT363-6
    8
    7
    6
    5

    17 18 39.2_0402_1%
    17 18

    1
    RPC17 S
    APU_TEST18_PLLTEST1

    1
    10K_0804_8P4R_5% 19 20 RC14
    19 20 @

    1
    A HDT@ 100K_0402_5% A
    @
    @
    1
    2
    3
    4

    APU_DBREQ# APU_TDI

    2
    SAMTE_ASP-136446-07-B RC2071 2 0_0402_5%
    Reserve follow CRB PCH_ENBKL con EC 1.8V level GPI pin cost down
    2 2
    CC213 CC212
    1
    0.01U_0201_10V6K
    1
    0.01U_0201_10V6K Security Classification LC Future Center Secret Data Title
    HDT@ @
    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (DISPLAY/CLK/MISC)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 6 of 50


    5 4 3 2 1
    5 4 3 2 1

    +3VALW_APU

    BOARD

    2
    Config. BOARD_ID0 BOARD_ID3

    2
    RC39 RC40 RC41
    10K_0402_5% 10K_0402_5% 10K_0402_5% RC1660 14'' 0 0
    @ UMA@ NOKBL@ 10K_0402_5%
    BOARD_ID0 @ 15'' 0 1

    1
    BOARD_ID1

    1
    PCIE_RST#_R BOARD_ID2 17'' 1 0
    RC38 1 2 33_0402_5%
    15,28,30,31,35 PLT_RST# BOARD_ID3

    2
    1

    2
    D RC43 CC19 RC47 RC48 RC49 D
    @ 100K_0402_5% 150P_0402_50V8-J 2K_0402_5% 2K_0402_5% 2K_0402_5% RC1659
    @ PX@ KBL@ 2K_0402_5%
    2 @
    2

    1
    +1.8VALW

    Connected to 10-ms RC-delay circuit on VDD_18_S5 power rail.


    (CRB PWR Dealy: 22K/0.1uF) UC2D

    1
    RC247 2 1 RC53
    0_0402_5% 10K_0402_5% ACPI/SD/AZ/GPIO/RTC/MISC +3VS_APU
    PCIE_RST#_R AE4 BA28 @1 TC61
    PCIE_RST_L/EGPIO26 SD_WP/EGPIO101 AY29 SD_PWR_CNTL @1
    DC1 TC44
    SD_PWR_CTRL/AGPIO102

    2
    1 2 @ RSMRST#_R RSMRST#_R AG1 AY13 ODD_DETECT# @1
    35 EC_RSMRST# TC89
    RSMRST_L SD_CD/AGPIO25 BA14 @1 PCH_TP_INT# RC1655 1 2 10K_0402_5%
    PBTN_OUT# PWRBTN#_R SD_CLK/EGPIO95 TC45
    1 RC191 2 1 AD2 AY15 @1
    LRB751V-40T1G_SOD323-2 35 PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0 SD_CMD/EGPIO96 SD_LED TC59
    1

    0_0402_5% AE2 BA29


    RC66 CC21 SYS_RESET# AF1 PWR_GOOD SD_LED/EGPIO93
    11 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 SD_DATA0_R
    @ 100K_0402_5% 0.1U_0201_6.3V6-K AE7 AY14 @1 TC62
    2 WAKE_L/AGPIO2 SD_DATA0/EGPIO97 BA13 SD_DATA1_R @1 TC63 RPC9
    SD_DATA1/EGPIO98 BA16 SD_DATA2_R @1 TC64 APU_SMB_CLK 3 2
    SD_DATA2/EGPIO99
    2

    PM_SLP_S3# RC193 2 1 PM_SLP_S3#_R AC2 AY16 SD_DATA3_R @1 TC65 APU_SMB_DATA 4 1


    35 PM_SLP_S3# PM_SLP_S5# PM_SLP_S5#_R SLP_S3_L SD_DATA3/EGPIO100
    RC194 20_0402_5%1 AG4
    35 PM_SLP_S5# SLP_S5_L
    0_0402_5% AGPIO10 AB1 2.2K_0404_4P2R_5%
    APU_S5_MUX_CTRL AA7 S0A3_GPIO/AGPIO10 AY33 APU_SMB_CLK RPC6
    9 APU_S5_MUX_CTRL S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 APU_SMB_DATA APU_SMB_CLK 12,31
    BA32 8 1
    SDA0/I2C2_SDA/EGPIO114 APU_SMB_DATA 12,31
    RPC2 7 2
    TEST0 AF2 AC5 SCL1 1 4 PCH_BT_OFF# 6 3
    with QC16,QC17, EC must set EC_RSMRST# and EC_SYS_PWRGD reversed compare to DC1 and DC2 TEST0 SCL1/I2C3_SCL/AGPIO19 PCH_WLAN_OFF#
    TEST1 AE1 AC4 SDA1 2 3 5 4
    +3VS_APU TEST2 AC8 TEST1/TMS SDA1/I2C3_SDA/AGPIO20 @
    TEST2 10K_0404_4P2R_5% 10K_0804_8P4R_5%
    AC_PRESENT
    1

    C AH2 AJ7 C
    35 AC_PRESENT BOARD_ID0 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO3 AGPIO3 11
    RC72 AA4 AK2
    RC95 2 1 10K_0402_5% BOARD_ID1 AG8 IR_TX0/USB_OC5_L/AGPIO13 AGPIO4 AK1 AGPIO5 @1 TC83
    0_0402_5% @ BOARD_ID3 AL5 IR_TX1/USB_OC6_L/AGPIO14 AGPIO5 AL4 LDT_RST_L @1 TC67 PCH_PWRBT# RC287 1 @ 2 10K_0402_5%
    TC90 @ 1 ODD_EN AE8 IR_RX1/AGPIO15 AGPIO6/LDT_RST_L AJ2 PCH_TP_INT#_L RC1663 2 1
    IR_LED_L/LLB_L/AGPIO12 AGPIO7/LDT_PWROK PCH_TP_INT# 36
    2

    DC2 AJ4 AGPIO8 @1 TC84 0_0402_5% LAN_CLKREQ# RC67 1 2 10K_0402_5%


    1 2 @ SYS_PWRGD_R AGPIO8 AG5 WLAN_CLKREQ# RC78 1 2 10K_0402_5%
    35 EC_SYS_PWRGD PCH_WLAN_OFF# AGPIO9 PCH_PWRBT# GPU_CLKREQ#
    1 AY32 AD1 RC64 1 UMA@2 10K_0402_5%
    31 PCH_WLAN_OFF# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 PCH_PWRBT# 35
    1

    AY31
    LRB751V-40T1G_SOD323-2 31 WLAN_CLKREQ# LAN_CLKREQ# CLK_REQ1_L/AGPIO115
    RC82 CC22 AV29 GATEA20 RC276 1 2 10K_0402_5%
    28 LAN_CLKREQ# PCH_BT_OFF# CLK_REQ2_L/AGPIO116
    @ 100K_0402_5% 0.1U_0201_6.3V6-K AP31
    2 31 PCH_BT_OFF# GPU_CLKREQ# CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
    AV35 AJ8 BLINK
    16 GPU_CLKREQ# CLK_REQG_L/OSCIN/EGPIO132 BLINK/USB_OC7_L/AGPIO11 VR_VGA_PWRGD
    AR29
    GENINT2_L/AGPIO90 VR_VGA_PWRGD 15,49
    2

    AP29
    BOARD_ID2 SPKR/AGPIO91 PCH_BEEP 32
    AB2 AU35
    USB_OC1# USB_OC0_L/TRST_L/AGPIO16 GA20IN/AGPIO126 GATEA20 35
    AG2
    25 USB_OC1# USB_OC1_L/TDI/AGPIO17 PXS_PWREN_R
    AJ1 AV33 RC109 1 PX@ 2 1K_0402_5%
    AH1 USB_OC2_L/TCK/AGPIO18 FANIN0/AGPIO84 AU33 PCH_TP_INT#_R RC1662 2 1 PCH_TP_INT# PXS_PWREN 19,48,49
    @
    USB_OC3_L/TDO/AGPIO24 FANOUT0/AGPIO85 0_0402_5%
    PCIE_WAKE#_RA RC88 2 1 0_0402_5% +1.8VS
    HDA_BITCLK AY6 AP23
    RC201 1 2 0_0402_5% HDA_SDIN0_R BA6 AZ_BITCLK/I2S_BCLK_MIC UART0_CTS_L/EGPIO135 AP25
    2 1 RC92 32 HDA_SDIN0 HDA_SDIN1 AY5 AZ_SDIN0/I2S_DATA_MIC0 UART0_RXD/EGPIO136 AR25 RPC19
    AGPIO5 PCIE_WAKE# 28,31,35
    0_0402_5% HDA_SDIN2 BA5 AZ_SDIN1/I2S_LR_PLAYBACK UART0_RTS_L/EGPIO137 AV25 TP_I2C0_SCL_R 1 4
    HDA_RST# AY4 AZ_SDIN2/I2S_DATA_PLAYBACK UART0_TXD/EGPIO138 AU23 TP_I2C0_SDA_R 2 3
    2 1 DC3 HDA_SYNC BA3 AZ_RST_L/I2S_LR_MIC UART0_INTR/AGPIO139
    HDA_SDOUT BA4 AZ_SYNC/I2S_BCLK_PLAYBACK AP21
    SDM10U45LP-7_DFN1006-2-2 AZ_SDOUT/I2S_DATA_MIC1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140 AV21 2.2K_0404_4P2R_5%
    UART1_RXD/BT_I2S_SDI/EGPIO141
    @ Connect TouchPad to I2C port0 following CRB 10/28 UART1_RTS_L/EGPIO142
    AP19 delete APU_SHUTDOWN# signal for Stoney FT4
    AV23 +3VALW_APU
    TP_I2C0_SCL_R AY22 UART1_TXD/BT_I2S_SDO/EGPIO143 AR21
    36 TP_I2C0_SCL_R TP_I2C0_SDA_R BA22 I2C0_SCL/EGPIO145 UART1_INTR/BT_I2S_LRCLK/AGPIO144
    +3VALW_APU 36 TP_I2C0_SDA_R AU19 I2C0_SDA/EGPIO146
    AV19 I2C1_SCL/EGPIO147 AP27 HVB_EN RPC15
    DC4 RPC3 HVB_EN 11,35
    SYS_RESET# 1 2 @ SYS_PWRGD_R 1 4 I2C1SCL I2C1_SDA/EGPIO148 HVBEN_L PCIE_WAKE#_RA 1 8
    2 3 I2C1SDA AC_PRESENT 2 7
    2

    AN4 3 6
    LRB751V-40T1G_SOD323-2 RTCCLK SUSCLK 11,31 PBTN_OUT# 4 5
    B RC84 RC85 RC20 1 10K_0404_4P2R_5% B
    32K_X1 BA2
    2.2K_0402_5% 1K_0402_5% 2.2K_0402_5% X32K_X1
    @ @ @ CC38 10K_0804_8P4R_5%
    0.1U_0201_6.3V6-K Max ESR < 65K ohm !!
    1

    TEST0 2 USB_OC1# RC285 1 2 10K_0402_5%


    TEST1 RC102 32K_X2 AY2
    TEST2 1 2 X32K_X2
    20M_0402_5%
    2

    FT4 REV 0.93


    YC1
    RC195 RC196 RC197 1 2 PM_SLP_S3# RC203 1 @ 2 2.2K_0402_5%
    PM_SLP_S5# RC208 1 @ 2 2.2K_0402_5%
    15K_0402_5% 15K_0402_5% 15K_0402_5%
    32.768KHZ_12.5PF_202740-PG14 AMD-STONEY-FT4_BGA769
    20P_0402_50V8

    20P_0402_50V8

    @
    1

    APU_S5_MUX_CTRL RC248 1 2 100K_0402_5%


    1 1 APU_S5_MUX_CTRL 100K pull high follow CRB
    STN@
    CC23

    CC24

    BLINK isn't strap pin, don't need pull high BLINK RC277 1 @ 2 10K_0402_5%
    2 2

    PCH_TP_INT# RC1661 1 @ 2 10K_0402_5%

    SD_LED RC97 1 @ 2 10K_0402_5%

    AGPIO10 RC80 1 2 10K_0402_5%

    +3VS_APU RPC4
    GPU_CLKREQ# RC65 1 PX@ 2 2K_0402_5%
    1 8 HDA_RST#
    PXS_PWREN_R 32 HDA_RST_AUDIO# HDA_SYNC
    RC98 1 PX@ 2 10K_0402_5% 2 7
    32 HDA_SYNC_AUDIO HDA_BITCLK HDA_SDIN0_R
    3 6 RC91 1 @ 2 10K_0402_5%
    VR_VGA_PWRGD 32 HDA_BITCLK_AUDIO HDA_SDOUT
    RC100 1 @ 2 10K_0402_5% 4 5
    32 HDA_SDOUT_AUDIO
    RC101 1 @ 2 100K_0402_5% PXS_PWREN_R 33_0804_8P4R_5% RSMRST#_R RC87 1 2 100K_0402_5%
    SYS_PWRGD_R RC89 1 2 100K_0402_5%
    A A
    RC104 1 UMA@2 2K_0402_5% VR_VGA_PWRGD
    HDA_SDIN2
    CRB: CARRIZO NEED 10K PD ON UNUSED SDIN HDA_SDIN1
    RC241
    RC242
    1
    1
    2 10K_0402_5%
    2 10K_0402_5%
    HDA_RST# RC282 1 2 1K_0402_5%
    DG: 10K PD
    HDA_SYNC RC283 1 2 1K_0402_5%
    HDA_SDOUT RC284 1 2 1K_0402_5%
    HDA_BITCLK RC90 1 2 1K_0402_5%
    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (GEVENT/GPIO/SD/AZ)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    PXS_PWREN_R/PXS_RST#_R/VR_VGA_PWRGD internal pull up 40k DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 7 of 50


    5 4 3 2 1
    5 4 3 2 1

    UC2E

    CLK/SATA/USB/SPI/LPC
    SATA_PTX_DRX_P0 BA10 AL8 CLK_USB48M 1 @ TC69
    34 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 AY10 SATA_TX0P USBCLK/25M_48M_OSC
    34 SATA_PTX_DRX_N0 SATA_TX0N AN7 USB_RCOMP 1 2 11.8K_0402_1%
    HDD SATA_PRX_DTX_N0 USB_ZVSS
    RC112
    AY12
    34 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 BA12 SATA_RX0N AW1 USB20_P7
    34 SATA_PRX_DTX_P0 SATA_RX0P USB_HSD0P AW2 USB20_N7 USB20_P7 25
    SATA_PTX_DRX_P1 USB_HSD0N USB20_N7 25 RighT USB (2.0) upper
    AY9
    34 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 BA9 SATA_TX1P AV1 USB20_P4
    34 SATA_PTX_DRX_N1 SATA_TX1N USB_HSD1P AV2 USB20_N4 USB20_P4 31
    ODD SATA_PRX_DTX_N1 USB_HSD1N USB20_N4 31 Blue Tooth
    D BA8 D
    34 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 AY8 SATA_RX1N AU1 USB20_P5
    34 SATA_PRX_DTX_P1 SATA_RX1P USB_HSD2P AU2 USB20_N5 USB20_P5 23
    SATA_CALRN USB_HSD2N USB20_N5 23 Camera
    +0.95VS RC113 1 2 1K_0402_1% AU11
    RC114 1 2 1K_0402_1% SATA_CALRP AP11 SATA_ZVSS AT1 USB20_P3
    SATA_ZVDDP USB_HSD3P AT2 USB20_N3 USB20_P3 32
    USB_HSD3N USB20_N3 32 Card Reader
    1 2 10K_0402_5% APU_TS_ON#
    RC147
    RPC13 APU_TS_ON# AY30 AR1 USB20_P2 USB3.0 port0 must map to USB2.0 port4,
    USB20_P2 25
    3 2 SATA0_DEVSLP_R AV31 SATA_ACT_L/AGPIO130
    DEVSLP0/EGPIO67
    USB_HSD4P
    USB_HSD4N
    AR2 USB20_N2
    USB20_N2 25 LEFT USB (3.0) USB3.0
    upper port1 must map to USB2.0 port5,
    4 1 EGPIO70 AU31
    DEVSLP1/EGPIO70 AP1 USB3.0 port2 must map to USB2.0 port6
    10K_0404_4P2R_5% USB_HSD5P AP2
    CLK_PCIE_GPUSTN@ RC117 1 2 0_0402_5% CLK_PCIE_GPU_R H2 USB_HSD5N
    15 CLK_PCIE_GPU CLK_PCIE_GPU# 2 0_0402_5% CLK_PCIE_GPU#_R GFX_CLKP
    RC118 1 H1 AN1
    15 CLK_PCIE_GPU# GFX_CLKN USB_HSD6P AN2
    USB_HSD6N Remove Finger print
    M2
    M1 GPP_CLK0P AM1
    GPP_CLK0N USB_HSD7P Remove Touch Screen
    AM2
    CLK_PCIE_WLAN RC119 1 2 0_0402_5% CLK_PCIE_WLAN_R L2 USB_HSD7N
    31 CLK_PCIE_WLAN CLK_PCIE_WLAN# 1 2 0_0402_5% CLK_PCIE_WLAN#_R L1 GPP_CLK1P
    RC120
    31 CLK_PCIE_WLAN# GPP_CLK1N W4 USBSS_CALRN 1 2 1K_0402_1% +0.95VALW
    RC123
    CLK_PCIE_LAN 1 2 0_0402_5% CLK_PCIE_LAN_R K2 USB_SS_ZVSS W5 USBSS_CALRP 1 2 1K_0402_1%
    28 CLK_PCIE_LAN CLK_PCIE_LAN#
    RC121
    GPP_CLK2P USB_SS_ZVDDP
    RC124 Connect the four USB 3.0 ports to onboard devices first
    RC122 1 2 0_0402_5% CLK_PCIE_LAN#_R K1 starting from the lower ports and then the remaining
    28 CLK_PCIE_LAN# GPP_CLK2N T1 USB30_TX_P1
    J2 USB_SS_0TXP T2 USB30_TX_N1 USB30_TX_P1 25 ports can be used for routing to USB 3.0 connectors.
    J1 GPP_CLK3P USB_SS_0TXN USB30_TX_N1 25 Less than four USB 3.0 ports can be utilized provided
    GPP_CLK3N V2 USB30_RX_P1 the (3.0)
    unusedupper
    ports are higher-numbered consecutive
    USB_SS_0RXP USB30_RX_N1 USB30_RX_P1 25 LEFT USB
    V1
    USB30_RX_N1 25
    ports.
    48M_X1 F2 USB_SS_0RXN
    X48M_X1
    None of the four USB 3.0 ports can be configured
    R1 as USB 2.0 external ports.
    48M_X2 F1 USB_SS_1TXP R2
    X48M_X2 USB_SS_1TXN
    C W2 C
    TC53 @ 1 X14M_25M_48M_OSC AU27 USB_SS_1RXP W1
    X25M_48M_OSC USB_SS_1RXN
    P1
    USB_SS_2TXP P2
    USB_SS_2TXN
    RC125 1 TPM@ 2 22_0402_5% Y2
    30 TPM_CLK USB_SS_2RXP
    RC126 1 2 3.3_0402_1% LPCCLK0 BA25 Y1
    11,35 CLK_PCI_EC 1 2 0_0402_5% BA24 LPCCLK0/EGPIO74 USB_SS_2RXN
    RC127 LPCCLK1
    11 LPC_CLK1 AY24 LPCCLK1/EGPIO75
    11,30,35 LPC_FRAME# BA26 LFRAME_L AY17 SPI_CLK_R 2 1 SPI_CLK
    0_0402_5% RC209
    30,35 LPC_AD0 AY28 LAD0 SPI_CLK/ESPI_CLK/EGPIO117 AY20 SPI_SI_R 2 1 SPI_SI
    0_0402_5% RC198
    30,35 LPC_AD1 AY25 LAD1 SPI_DO/ESPI_DAT0/EGPIO121 BA17 SPI_SO_R 2 1 SPI_SO
    30,35 LPC_AD2 0_0402_5% RC199
    AY23 LAD2 SPI_DI/ESPI_DAT1/EGPIO120 BA18 SPI_HOLD#_R 0_0402_5% 2 1 RC133 SPI_HOLD#
    30,35 LPC_AD3 LAD3 SPI_HOLD_L/ESPI_DAT3/EGPIO133 SPI_WP#_R SPI_WP#
    BA20 0_0402_5% 2 1 RC132
    LPC_RST#_R AY27 SPI_WP_L/ESPI_DAT2/EGPIO122 AY21 SPI_CS0#_R 0_0402_5% 2 1 RC202 SPI_CS0#
    AY26 LPC_RST_L SPI_CS1_L/EGPIO118 BA21 AGPIO76 0_0402_5% 2 1 RC243
    1 2 10K_0402_5% 30 LPC_CLKRUN# AC1 LPC_CLKRUN_L/AGPIO88 SPI_TPM_CS_L/AGPIO76 PXS_RST# 15
    RC149 AGPIO21
    AA8 LPC_PD_L/AGPIO21 AY18 1 @ TC54
    35 EC_SCI# ODD_DA# LPC_PME_L/AGPIO22 ESPI_ALERT_L/LDRQ0_L
    TC91 @ 1 BA27 BA30 KBRST#
    AV27 LPC_SMI_L/AGPIO86 ESPI_RESET_L/KBRST_L/AGPIO129 AY19 KBRST# 35
    30,35 SERIRQ EGPIO119 10K_0402_5% 2STN@ 1 RC144
    SERIRQ/AGPIO87 SPI_CS2_L/ESPI_CS_L/EGPIO119

    +3VS_APU
    FT4 REV 0.93

    RC46 1 2 33_0402_5% LPC_RST#_R


    35 APU_LPC_RST#
    AMD-STONEY-FT4_BGA769 KBRST# RC2791 2 10K_0402_5%
    1 @ PXS_RST#
    CC20 10K_0402_5% 2 @ 1 RC280
    150P_0402_50V8-J 10K_0402_5% 2 1 RC281
    2
    B B

    48M_X1 +VCC_SPI

    48M_X2 8M ROM +VCC_SPI


    1
    +3VALW_APU
    RC140 1 2 1M_0402_5% CC27 +1.8VS
    +VCC_SPI RC1351 @ 2 0_0402_5%
    0.1U_0201_6.3V6-K
    2 SPI_CLK KBRST#
    YC2 UC3 RC1921 STN@ 2 0_0402_5%
    SPI_CS0# 1 8
    SPI_SO /CS VCC SPI_HOLD#

    2
    1 4 2 7
    OSC1 NC2 SPI_WP# 3 DO(IO1) /HOLDor/RESET(IO3) 6 SPI_CLK +VCC_SPI
    2 3 4 /WP(IO2) CLK 5 SPI_SI RC139
    NC1 OSC2 GND DI(IO0) 10_0402_5%
    1 1 RPC8 EMC_NS@

    1
    SPI_WP# 1 4

    1000P_0402_25V7-K
    48MHZ 10PF X1E000021083400 W25Q64FWSSIQ_SO8
    CC28 CC29 SPI_HOLD# 2 3
    12P_0402_50V8-J 12P_0402_50V8-J 2
    2 2

    2
    10K_0404_4P2R_5% CC26

    CC1274
    10P_0402_50V8J EMC_NS@
    SPI_CS0# RC138 1 2 10K_0402_5% EMC_NS@

    1
    with BOM strcture control, UC3 change to 1.8V SPI ROM for CZ 1
    EMC

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (SATA/USB/LPC/SPI)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 8 of 50
    5 4 3 2 1
    5 4 3 2 1

    +1.2V

    +1.2V UC2F +APU_CORE_NB

    180P_0402_50V8-J
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    POWER
    1 1 1 1 3A J35 E9
    +1.2V L32 VDDIO_MEM_S3_1 VDDCR_NB_1 E11

    CC258

    CC185

    CC214

    CC165
    L37 VDDIO_MEM_S3_2 VDDCR_NB_2 E13
    N35 VDDIO_MEM_S3_3 VDDCR_NB_3 E15
    2 2 2 2 R37 VDDIO_MEM_S3_4 VDDCR_NB_4 E17
    U32 VDDIO_MEM_S3_5 VDDCR_NB_5 E19 +APU_CORE_NB
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    U35 VDDIO_MEM_S3_6 VDDCR_NB_6 G7
    1 1 1 1 1 1 1 1 1 SIVCD@ VDDIO_MEM_S3_7 VDDCR_NB_7
    W32 J7
    CC42

    CC54

    CC55

    CC56

    CC57

    CC58

    CC59

    CC60

    CC53
    W37 VDDIO_MEM_S3_8 VDDCR_NB_8 K11

    180P_0402_50V8-J

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K
    D D
    AA35 VDDIO_MEM_S3_9 VDDCR_NB_9 K13

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    1U_0402_6.3V6K
    2 2 2 2 2 2 2 2 2 AC32 VDDIO_MEM_S3_10 VDDCR_NB_10 K15
    VDDIO_MEM_S3_11 VDDCR_NB_11 1 1 1 1 1 1 1 1 1 1 1 1 1
    AC37 K17

    CC237

    CC238

    CC239

    CC240

    CC241

    CC242

    CC243

    CC244

    CC145

    CC195

    CC196

    CC199

    CC200
    AE32 VDDIO_MEM_S3_12 VDDCR_NB_12 K19
    AE35 VDDIO_MEM_S3_13 VDDCR_NB_13 L7
    SIVCD@ SIVCD@ SIVCD@ VDDIO_MEM_S3_14 VDDCR_NB_14
    AG32 L10 2 2 2 2 2 2 2 2 2 @ 2 @ 2 @ 2 @ 2
    AG37 VDDIO_MEM_S3_15 VDDCR_NB_15 L15
    AJ32 VDDIO_MEM_S3_16 VDDCR_NB_16 L17
    AJ35 VDDIO_MEM_S3_17 VDDCR_NB_17 N7
    VDDIO_MEM_S3_18 VDDCR_NB_18 SIVCD@ SIVCD@ SIVCD@
    AL32 N11 follow CRB reserve
    AL37 VDDIO_MEM_S3_19 VDDCR_NB_19 N13
    AR35 VDDIO_MEM_S3_20 VDDCR_NB_20 N15
    +0.95VS +APU_CORE VDDIO_MEM_S3_21 VDDCR_NB_21 N17
    OK
    VDDCR_NB_22 N19
    K21 VDDCR_NB_23 R7

    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K
    K23 VDDCR_CPU_1 VDDCR_NB_24 U7
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    180P_0402_50V8-J

    180P_0402_50V8-J
    K25 VDDCR_CPU_2 VDDCR_NB_25 U11

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    1 1 1 1 1 1 1 2 1 1 VDDCR_CPU_3 VDDCR_NB_26

    2
    CC220 K27 U13
    CC221

    CC222

    CC223

    CC224

    CC225

    CC174

    CC226

    CC227

    CC228

    CC229

    CC230

    CC203
    1 1 1 VDDCR_CPU_4 VDDCR_NB_27
    47P_0402_50V8J K29 U15

    CC215

    CC216

    CC137
    RF@ K31 VDDCR_CPU_5 VDDCR_NB_28 U17 +1.8VS +1.8VALW +3VALW_APU
    VDDCR_CPU_6 VDDCR_NB_29
    1

    1
    2 2 2 2 2 2 2 2 2 N21 U19
    2 2 2 N23 VDDCR_CPU_7 VDDCR_NB_30 U21
    N25 VDDCR_CPU_8 VDDCR_NB_31 W7
    SIVCD@ SIVCD@ N27 VDDCR_CPU_9 VDDCR_NB_32 AA11

    1000P_0402_25V7-K

    1000P_0402_25V7-K

    1000P_0402_25V7-K
    SIVCD@ SIVCD@ SIVCD@ SIVCD@ VDDCR_CPU_10 VDDCR_NB_33
    N29 AA13

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    N31 VDDCR_CPU_11 VDDCR_NB_34 AA15
    VDDCR_CPU_12 VDDCR_NB_35 1 1 1 1 1 1

    2
    U23 AA17

    CC246

    CC247

    CC245

    CC249

    CC250

    CC248

    CC255

    CC256

    CC254
    U25 VDDCR_CPU_13 VDDCR_NB_36 AA19
    U27 VDDCR_CPU_14 VDDCR_NB_37 AA21
    VDDCR_CPU_15 VDDCR_NB_38

    1
    U29 AA23 2 2 2 2 2 2
    U31 VDDCR_CPU_16 VDDCR_NB_39 AE11
    AA25 VDDCR_CPU_17 VDDCR_NB_40 AE13
    AA27 VDDCR_CPU_18 VDDCR_NB_41 AE15 SIVCD@ SIVCD@ SIVCD@
    AA29 VDDCR_CPU_19 VDDCR_NB_42 AE17
    AA31 VDDCR_CPU_20 VDDCR_NB_43 AE19
    +VDDCR_FCH_S5 VDDCR_CPU_21 VDDCR_NB_44 AE21
    VDDCR_NB_45 AE23
    AR4 VDDCR_NB_46 AE25
    AR5 VDDCR_FCH_S5_1 VDDCR_NB_47 AE27
    AR7 VDDCR_FCH_S5_2 VDDCR_NB_48 AE29
    C +0.95VALW AU7 VDDCR_FCH_S5_3 VDDCR_NB_49 AE31 C
    +RTCBATT +RTCBATT_APU VDDCR_FCH_S5_4 VDDCR_NB_50 +1.8VS
    RC6 1 2 AJ11
    AL11 VDDP_S5_1 AJ15

    1000P_0402_25V7-K
    1K_0402_5%
    AL13 VDDP_S5_2 VDD_18_1 AL17 +1.8VALW

    10U_0603_6.3V6M

    1U_0402_6.3V6K
    +0.95VS VDDP_S5_3 VDD_18_2
    1U_0402_6.3V6K

    1 1

    2
    AJ13 +3VS_APU +3VS

    CC182

    CC219

    CC231
    1 VDD_18_S5_1
    AJ21 AL15
    CC192

    AJ23 VDDP_1 VDD_18_S5_2 RC214


    VDDP_2

    1
    2 2 AJ25 AJ19 1 2
    2 AJ27 VDDP_3 VDD_33_1 AL21

    1000P_0402_25V7-K
    0_0402_5%
    AL23 VDDP_4 VDD_33_2 +3VALW_APU

    10U_0603_6.3V6M

    1U_0402_6.3V6K
    SIVCD@ AL25 VDDP_5 AJ17
    VDDP_6 VDD_33_S5_1 1 1

    2
    AL27 AL19

    CC252

    CC253

    CC251
    AL29 VDDP_7 VDD_33_S5_2
    VDDP_8

    1
    +1.8VS +VDDIO_AZ_APU AM11 2 2
    RC212 1 2 AM13 VDDBT_RTC_G
    VDDIO_AUDIO
    1000P_0402_25V7-K

    1000P_0402_25V7-K

    0_0402_5%
    SIVCD@
    1U_0402_6.3V6K

    FT4 REV 0.93

    1
    2

    2
    CC236

    CC234

    CC235

    AMD-STONEY-FT4_BGA769
    @
    1

    SIVCD@

    UC5
    VCCRTC
    RC231 1 2 10K_0402_5% 1
    Vin +0.95VALW
    3 +RTCBATT
    Vout
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1 2 1
    GND
    1

    JCMOS1 RC8 @
    CC37

    CC194

    SHORT PADS 470_0603_5%


    AP2138N-1.5TRG1_SOT23-3 @
    2

    B 2 2 B
    2 2 2 2 2 2
    12

    D QC7
    2.2U_0402_6.3V6M

    CC1280

    2.2U_0402_6.3V6M

    CC1281

    2.2U_0402_6.3V6M

    CC1282

    2.2U_0402_6.3V6M

    CC1283
    2.2U_0402_6.3V6M

    CC1284

    2.2U_0402_6.3V6M

    CC1285
    2 EC_RTCRST#_ON
    G EC_RTCRST#_ON 35
    1 1 1 1 1 1
    1

    S
    L2N7002KWT1G_SOT323-3 RC15 Design Guide G FT4 CRB
    3

    100K_0402_5%
    @
    @ 7*22uf 0603 11*22uf 0805 11*22uf 0603
    VDDCR_CPU 2*1uf 0402 2*1uf 0402 1*1uf 0402
    2

    EMC@ EMC_NS@ EMC@ EMC_NS@


    EMC_NS@ EMC@ 1*180pf 0402 1*180pf 0402 1*180pf 0402
    11*22uf 0603 11*22uf 0603 15*22uf 0603
    VDDCR_NB 1*1uf 0402 1*1uf 0402 8*0.22uf 0402 split *5
    1*180pf 0402 1*180pf 0402 1*180pf 0402

    VDDCR_GFX
    9*22uf 0603 9*22uf 0603 2*1uf 0402 9*22uf 0603 2*1uf 0402
    VDDIO_MEM_S3 3*1uf 0402 split*4 0.22uf 0402 split*4 0.22uf 0402
    3*180pf 0402 1*180pf 0402 split*2 1*180pf 0402 split*2
    1*10uf 0402 1*10uf 0402 2*10uf 0603
    VDDCR_FCH_S5 2*1uf 0402 2*1uf 0402 1*0.22uf 0402
    2*1000pf 0402 2*1000pf 0402
    5*22uf 0603 2*10uf 0603 5*22uf 0603 2*10uf 0603 4*10uf 0603
    VDDP 4*1000pf 0402 4*1000pf 0402 1*0.22uf 0402
    1*180pf 0402 1*180pf 0402 1*180pf 0402

    VDDP_GFX
    +1.2V 1*10uf 0402 1*10uf 0402 1*10uf 0603
    VDDP_S5 1*1uf 0402 1*1uf 0402 1*0.22uf 0402
    +APU_CORE_NB +VDDCR_FCH_S5 1*1000pf 0402 1*1000pf 0402
    UC7 1*10uf 0402 1*10uf 0402 1*22uf 0603
    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    0.22U_0201_6.3V6-K

    1 8 1*1uf 0402 1*1uf 0402 1*10uf 0603


    180P_0402_50V8-J

    180P_0402_50V8-J

    VIN1_1 VOUT_1 VDD_18


    1*1000pf 0402 1*1000pf 0402
    10U_0603_6.3V6M

    1 1 1 1 1 1
    2 7 1*10uf 0402 1*10uf 0402 1*10uf 0603
    CC168

    CC169

    CC170

    CC172

    CC179

    CC176

    VIN1_2 VOUT_2
    1

    +0.775VALW

    1000P_0402_25V7-K

    1000P_0402_25V7-K
    VDD_18_S5 1*1uf 0402 1*1uf 0402 1*0.22uf 0402
    CC207

    3 6 APU_S5_MUX_CTRL 1*1000pf 0402 1*1000pf 0402


    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    2 2 2 2 2 2 +5VALW VIN2 SEL APU_S5_MUX_CTRL 7


    1*10uf 0402 1*10uf 0402
    10U_0603_6.3V6M

    1 1 1
    2

    2
    SDVCD@ 4 5 VDD_33 1*1uf 0402 1*1uf 0402 1*10uf 0603
    CC162

    CC217

    CC218

    CC232

    CC233
    VCC EN
    1

    1*1000pf 0402 1*1000pf 0402


    CC208

    1U_0402_6.3V6K

    SIVCD@ SIVCD@ SIVCD@ 1 9 1*10uf 0402 1*10uf 0402 1*10uf 0603


    A GND A
    1

    2 2 2 1*1uf 0402 1*1uf 0402 1*0.22uf 0402


    DECOUPLING BETWEEN PROCESSOR AND DIMMs VDD_33_S5
    CC209
    2

    SDVCD@ 1*1000pf 0402 1*1000pf 0402


    ACROSS VDDIO AND VSS SPLIT G5018RD1U_TDFN8_3X3 1*10uf 0402 1*10uf 0402
    2
    SDVCD@ STN@ STN@ SIVCD@ SIVCD@ STN@ 2*1000pf 0402 2*1000pf 0402 3*1uf 0402
    STN@ VDDIO_AUDIO

    VDDBT_RTC_G 1*1000pf 0402 1*1000pf 0402 1*0.22uf 0402

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (POWER&DECOUPLING)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 9 of 50


    5 4 3 2 1
    5 4 3 2 1

    UC2G UC2H

    GND GND
    D AJ31 L13 AC21 AU39 D
    R19 VSS_215 VSS_59 L19 AC23 VSS_120 VSS_182 AW3
    H23 VSS_214 VSS_60 L21 AC25 VSS_121 VSS_183 AW5
    A2 VSS_213 VSS_61 L23 AC27 VSS_122 VSS_184 AW7
    A8 VSS_1 VSS_62 L25 AC29 VSS_123 VSS_185 AW9
    A13 VSS_2 VSS_63 L27 AC31 VSS_124 VSS_186 AW11
    A18 VSS_3 VSS_64 L29 AC38 VSS_125 VSS_187 AW13
    A23 VSS_4 VSS_65 L31 AC39 VSS_126 VSS_188 AW15
    A32 VSS_5 VSS_66 L39 AC41 VSS_127 VSS_189 AW17
    A35 VSS_6 VSS_67 L41 AE3 VSS_128 VSS_190 AW19
    A39 VSS_7 VSS_68 N1 AE5 VSS_129 VSS_191 AW21
    B8 VSS_8 VSS_69 N2 AE10 VSS_130 VSS_192 AW23
    B13 VSS_9 VSS_70 N3 AE39 VSS_131 VSS_193 AW25
    B32 VSS_10 VSS_71 N39 AG3 VSS_132 VSS_194 AW27
    B39 VSS_11 VSS_72 R3 AG7 VSS_133 VSS_195 AW29
    C3 VSS_12 VSS_73 R11 AG10 VSS_134 VSS_196 AW31
    C5 VSS_13 VSS_74 R13 AG11 VSS_135 VSS_197 AW33
    C7 VSS_14 VSS_75 R15 AG13 VSS_136 VSS_198 AW35
    C9 VSS_15 VSS_76 R17 AG15 VSS_137 VSS_199 AW37
    C11 VSS_16 VSS_77 R21 AG17 VSS_138 VSS_200 AW39
    C13 VSS_17 VSS_78 R23 AG19 VSS_139 VSS_201 AW41
    C15 VSS_18 VSS_79 R25 AG21 VSS_140 VSS_202 AY1
    C17 VSS_19 VSS_80 R27 AG23 VSS_141 VSS_203 AY11
    C19 VSS_20 VSS_81 R29 AG25 VSS_142 VSS_204 BA7
    C21 VSS_21 VSS_82 R31 AG27 VSS_143 VSS_205 BA11
    C
    C23 VSS_22 VSS_83 R39 AG29 VSS_144 VSS_206 BA15 C
    C25 VSS_23 VSS_84 R41 AG31 VSS_145 VSS_207 BA19
    C27 VSS_24 VSS_85 U1 AG39 VSS_146 VSS_208 BA23
    C29 VSS_25 VSS_86 U2 AG41 VSS_147 VSS_209 BA31
    C31 VSS_26 VSS_87 U3 AJ3 VSS_148 VSS_210 BA35
    C33 VSS_27 VSS_88 U10 AJ5 VSS_149 VSS_211 BA39
    C35 VSS_28 VSS_89 U39 AJ10 VSS_150 VSS_212
    C37 VSS_29 VSS_90 W3 AJ29 VSS_151
    C39 VSS_30 VSS_91 W10 AJ39 VSS_152
    C41 VSS_31 VSS_92 W11 AL1 VSS_153
    E1 VSS_32 VSS_93 W13 AL2 VSS_154
    E2 VSS_33 VSS_94 W15 AL3 VSS_155
    E3 VSS_34 VSS_95 W17 AL7 VSS_156
    E21 VSS_35 VSS_96 W19 AL10 VSS_157
    E25 VSS_36 VSS_97 W21 AL31 VSS_158
    E29 VSS_37 VSS_98 W23 AL39 VSS_159
    E35 VSS_38 VSS_99 W25 AL41 VSS_160
    E38 VSS_39 VSS_100 W27 AM25 VSS_161
    E39 VSS_40 VSS_101 W29 AM27 VSS_162
    G1 VSS_41 VSS_102 W31 AM29 VSS_163
    G2 VSS_42 VSS_103 W39 AM31 VSS_164
    G3 VSS_43 VSS_104 W41 AN3 VSS_165
    G11 VSS_44 VSS_105 AA1 AN5 VSS_166
    G13 VSS_45 VSS_106 AA2 AN39 VSS_167
    G23 VSS_46 VSS_107 AA3 AR3 VSS_168
    B B
    G27 VSS_47 VSS_108 AA5 AR11 VSS_169
    G31 VSS_48 VSS_109 AA10 AR19 VSS_170
    G35 VSS_49 VSS_110 AA39 AR23 VSS_171
    G37 VSS_50 VSS_111 AC3 AR27 VSS_172
    G39 VSS_51 VSS_112 AC7 AR31 VSS_173
    G41 VSS_52 VSS_113 AC10 AR39 VSS_174
    J3 VSS_53 VSS_114 AC11 AR41 VSS_175
    J8 VSS_54 VSS_115 AC13 AU3 VSS_176
    J39 VSS_55 VSS_116 AC15 AU9 VSS_177
    L3 VSS_56 VSS_117 AC17 AU21 VSS_178
    L8 VSS_57 VSS_118 AC19 AU25 VSS_179
    VSS_58 VSS_119 AU29 VSS_180
    VSS_181
    FT4 REV 0.93
    FT4 REV 0.93

    AMD-STONEY-FT4_BGA769 AMD-STONEY-FT4_BGA769
    @ @

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (VSS)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 10 of 50
    5 4 3 2 1
    5 4 3 2 1

    +3VS +3VALW_APU +3VS +3VALW_APU +3VS +3VALW_APU +3VALW_APU +3VALW_APU +3VALW_APU +3VS_APU

    2
    RC152 RC169 RC153 RC200 RC154 RC173 RC155 RC156 RC157 RC81
    10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
    @ @ @ @ @
    D D

    1
    8,30,35 LPC_FRAME#

    8 LPC_CLK1

    8,35 CLK_PCI_EC

    7 AGPIO3

    7 SYS_RESET#

    7,31 SUSCLK

    7,35 HVB_EN

    1
    RC79
    C RC159 RC160 RC161 RC162 RC163 RC164 C
    2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 0_0402_5%
    @ @ @ @ @

    2
    @

    STRAP PINS

    LFRAME_L LPCCLK1 LPCCLK0 RTCCLK SYS_RESET_L AGPIO3 HVB_EN


    Signal
    Int pull-up Int pull-up Int pull-up

    Type II II II I I I

    SPI ROM Internal Boot Fail Timer RTC Coin Battery is Normal Power Up Enhanced reset floating
    B PULL CLK Gen Enabled implemented &Reset Timing logic (for quicker B
    HIGH S5 resume) Disable HVB
    Default Default Default on FT4 platforms
    Default Default
    Default

    Boot Fail Timer Reserved traditional connected to VSS


    PULL LPC ROM Reserved Disabled RTC Coin Battery is reset logic
    LOW not implemented Enable HVB
    Default on FT4 platforms

    Type I straps become valid immediately after capture with the rising edge of RSMRST_L,they are captured only once when power is first applied to the processor
    Type II straps become valid after PWR_GOOD is asserted,straps are captured every time the systems powers up from the S5 state. A transition from S3 to S0 does not trigger capture.
    Type II straps should be pulled up to S0 power rail to prevent leakage when the signal is connected to a device in S0 power domain.
    If the LPC bus is connected to devices that are on S0 power rail, then a pull-up resistor to VDD_33 is implemented.

    All Strap pins must be configured with either external pull-up or pull-down resistors.
    Platforms that are designed for AOAC complaint are recommended to use the Alternate Reset by strapping this pin to ‘ 1’ for C
    Z
    AGPIO3

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 FT4 (STRAPS)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 11 of 50
    5 4 3 2 1
    5 4 3 2 1

    DDRB_DQ[0..63]
    DDRB_DQ[0..63] 5
    DDRB_DQS[0..7]
    DDRB_DQS[0..7] 5
    DDRB_DQS#[0..7]
    DDRB_DQS#[0..7] 5
    DDR4 SO-DIMM A DDRB_MA[0..13]
    DDRB_MA[0..13] 5
    +1.2V +1.2V DDRB_DM[0..7]
    DDRB_DM[0..7] 5
    JDDR1B

    JDDR1A DDRB_MA3 131 132 DDRB_MA2


    DDRB_MA1 133 A3 A2 134 MEM_MB_EVENT#
    A1 EVENT_n MEM_MB_EVENT# 5
    135 136
    1 2 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
    D
    DDRB_DQ0 VSS_1 VSS_2 DDRB_DQ5 5 DDRB_CLK0 DDRB_CLK0# CK0_t CK1_t DDRB_CLK1# DDRB_CLK1 5 D
    3 4 139 140
    DQ5 DQ4 5 DDRB_CLK0# CK0_c CK1_c DDRB_CLK1# 5
    5 6 141 142
    DDRB_DQ1 7 VSS_3 VSS_4 8 DDRB_DQ4 RD259 1 2 0_0402_5% 143 VDD_11 VDD_12 144 DDRB_MA0
    9 DQ1 DQ0 10 Parity A0
    DDRB_DQS#0 11 VSS_5 VSS_6 12 DDRB_DM0
    DDRB_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_BA1 145 146 DDRB_MA10
    DQS0_t VSS_7 DDRB_DQ7 5 DDRB_BA1 BA1 A10/AP
    15 16 147 148
    DDRB_DQ3 17 VSS_8 DQ6 18 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BA0
    DQ7 VSS_9 DDRB_DQ2 5 DDRB_CS0# DDRB_MA14_WE# CS0_n BA0 DDRB_MA16_RAS# DDRB_BA0 5
    19 20 5 DDRB_MA14_WE#
    151 152
    DDRB_DQ6 21 VSS_10 DQ2 22 153 WE_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 5
    23 DQ3 VSS_11 24 DDRB_DQ12 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
    DDRB_DQ9 25 VSS_12 DQ12 26 5 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 5
    DQ13 VSS_13 DDRB_DQ8 5 DDRB_CS1# CS1_n A13
    27 28 159 160
    DDRB_DQ13 29 VSS_14 DQ8 30 DDRB_ODT1 161 VDD_17 VDD_18 162 +VREF_CA
    31 DQ9 VSS_15 32 DDRB_DQS#1 5 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164
    DDRB_DM1 33 VSS_16 DQS1_c 34 DDRB_DQS1 165 VDD_19 VREFCA 166 DDRB0_SA2
    35 DM1_n/DBl1_n/NC DQS1_t 36 167 C1/CS3_n/NC SA2 168
    DDRB_DQ10 37 VSS_17 VSS_18 38 DDRB_DQ11 DDRB_DQ37 169 VSS_53 VSS_54 170 DDRB_DQ38
    39 DQ15 DQ14 40 171 DQ37 DQ36 172
    DDRB_DQ14 41 VSS_19 VSS_20 42 DDRB_DQ15 DDRB_DQ33 173 VSS_55 VSS_56 174 DDRB_DQ36
    43 DQ10 DQ11 44 175 DQ33 DQ32 176
    DDRB_DQ16 45 VSS_21 VSS_22 46 DDRB_DQ21 DDRB_DQS#4 177 VSS_57 VSS_58 178 DDRB_DM4
    47 DQ21 DQ20 48 +1.2V DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180
    DDRB_DQ17 49 VSS_23 VSS_24 50 DDRB_DQ20 181 DQS4_t VSS_59 182 DDRB_DQ39
    51 DQ17 DQ16 52 DDRB_DQ32 183 VSS_60 DQ39 184
    DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DM2 185 DQ38 VSS_61 186 DDRB_DQ34
    DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 RC9 1 2 1K_0402_5% MEM_MB_EVENT# DDRB_DQ35 187 VSS_62 DQ35 188
    57 DQS2_t VSS_27 58 DDRB_DQ18 189 DQ34 VSS_63 190 DDRB_DQ45
    DDRB_DQ22 59 VSS_28 DQ22 60 DDRB_DQ44 191 VSS_64 DQ45 192
    61 DQ23 VSS_29 62 DDRB_DQ19 193 DQ44 VSS_65 194 DDRB_DQ40
    DDRB_DQ23 63 VSS_30 DQ18 64 DDRB_DQ46 195 VSS_66 DQ41 196
    65 DQ19 VSS_31 66 DDRB_DQ25 197 DQ40 VSS_67 198 DDRB_DQS#5
    DDRB_DQ28 67 VSS_32 DQ28 68 DDRB_DM5 199 VSS_68 DQS5_c 200 DDRB_DQS5
    69 DQ29 VSS_33 70 DDRB_DQ24 201 DM5_n/DBl5_n/NC DQS5_t 202
    DDRB_DQ29 71 VSS_34 DQ24 72 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ42
    73 DQ25 VSS_35 74 DDRB_DQS#3 205 DQ46 DQ47 206
    DDRB_DM3 75 VSS_36 DQS3_c 76 DDRB_DQS3 DDRB_DQ43 207 VSS_71 VSS_72 208 DDRB_DQ41
    C DM3_n/DBl3_n/NC DQS3_t DQ42 DQ43 C
    77 78 209 210
    DDRB_DQ31 79 VSS_37 VSS_38 80 DDRB_DQ26 DDRB_DQ53 211 VSS_73 VSS_74 212 DDRB_DQ49
    81 DQ30 DQ31 82 213 DQ52 DQ53 214
    DDRB_DQ30 83 VSS_39 VSS_40 84 DDRB_DQ27 DDRB_DQ54 215 VSS_75 VSS_76 216 DDRB_DQ48
    85 DQ26 DQ27 86 217 DQ49 DQ48 218
    87 VSS_41 VSS_42 88 DDRB_DQS#6 219 VSS_77 VSS_78 220 DDRB_DM6
    89 CB5/NC CB4/NC 90 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n/NC 222
    +1.2V +1.2V 91 VSS_43 VSS_44 92 +1.2V 223 DQS6_t VSS_79 224 DDRB_DQ55
    93 CB1/NC CB0/NC 94 DDRB_DQ52 225 VSS_80 DQ54 226
    RD273 1 @ 2 240_0402_1% 95 VSS_45 VSS_46 96 227 DQ55 VSS_81 228 DDRB_DQ51
    RD274 1 @ 2 240_0402_1% 97 DQS8_c DM8_n/DBI8_n/NC 98 DDRB_DQ50 229 VSS_82 DQ50 230
    99 DQS8_t VSS_47 100 231 DQ51 VSS_83 232 DDRB_DQ57
    101 VSS_48 CB6/NC 102 DDRB_DQ61 233 VSS_84 DQ60 234
    103 CB2/NC VSS_49 104 for MEM_MB_RST# overshoot issue 235 DQ61 VSS_85 236 DDRB_DQ60
    105 VSS_50 CB7/NC 106 DDRB_DQ56 237 VSS_86 DQ57 238
    107 CB3/NC VSS_51 108 MEM_MB_RST# 239 DQ56 VSS_87 240 DDRB_DQS#7
    DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 MEM_MB_RST# 5 DDRB_DM7 241 VSS_88 DQS7_c 242 DDRB_DQS7
    5 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 5 DM7_n/DBl7_n/NC DQS7_t
    111 112 243 244
    0.1U_0201_6.3V6-K
    DDRB_BG1 113 VDD_1 VDD_2 114 DDRB_ACT# DDRB_DQ58 245 VSS_89 VSS_90 246 DDRB_DQ63
    5 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDR4_ALERT DDRB_ACT# 5 1 DQ62 DQ63
    115 116 247 248
    CD120

    5 DDRB_BG0 BG0 ALERT_n DDRB_DQ59 VSS_91 VSS_92 DDRB_DQ62


    117 118 249 250
    DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 251 DQ58 DQ59 252
    DDRB_MA9 121 A12 A11 122 DDRB_MA7 2 +VDDSPD APU_SMB_CLK 253 VSS_93 VSS_94 254 APU_SMB_DATA
    123 A9 A7 124 7,31 APU_SMB_CLK 255 SCL SDA 256 DDRB0_SA0 APU_SMB_DATA 7,31
    @
    DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 257 VDDSPD SA0 258
    DDRB_MA6 A8 A5 DDRB_MA4 +2.5V VPP_1 Vtt DDRB0_SA1 +0.6VS
    127 128 1 1 259 260
    129 A6 A4 130 CD28 CD29 VPP_2 SA1
    VDD_7 VDD_8 1
    1U_0402_6.3V6K 0.1U_0201_6.3V6-K CD121 261 262
    22P_0402_50V8-J GND_1 GND_2
    2 2 RFNS@ ARGOS_D4AS0-26001-1P60
    RF 2
    ARGOS_D4AS0-26001-1P60 ME@
    ME@

    +3VS +VDDSPD
    RD271 1 2 0_0402_5%
    +2.5VS
    B B
    +1.2V
    +1.2V RD272 1 @ 2 0_0402_5%
    +2.5V +2.5VS
    1
    1

    RD10 3 1

    D
    RD258 +VREF_CA QD1
    1K_0402_1%
    1K_0402_1% LP2301ALT1G_SOT23-3

    G
    15mil Layout Note: Place near JDDR1
    2

    2
    @
    2

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    DDR4_ALERT
    2

    1000P_0201_50V7-K

    24,37 SUSP
    RD11 1 1 1
    1K_0402_1% +0.6VS +1.2V
    CD262

    CD116

    CD117

    follow CRB 1pcs 4.7uf + 1pcs 0.1uf follow CRB 8pcs 0.1uf
    1

    2 2 2

    180P_0402_50V8-J
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    4.7U_0402_6.3V6M

    1 1 1 1 1 1 1 1 1 1 1 1 1
    1 1 1 1 CD16 CD17 CD18 CD20 CD21 CD22 CD23 CD58 CD59 CD60 CD61 CD62 CC211
    CD249 CD251 CD250 CD248 @ @ @ @
    @ @
    2 2 2 2 2 2 2 2 2 2 2 2 2
    2 2 2 2

    +3VS +3VS +3VS


    1

    RD26 RD269 RD270 +2.5V +1.2V

    @10K_0402_5% 10K_0402_5% 10K_0402_5% follow CRB 1pcs 1uf + 2pcs 0.1uf + 1pcs 180pf
    @ @
    2

    DDRB0_SA0 DDRB0_SA1 DDRB0_SA2


    10U_0603_6.3V6M

    10U_0603_6.3V6M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    1U_0402_6.3V6K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    180P_0402_50V8-J

    1 1 1 1 1 1 1
    1

    RD268 RD28 RD29 1 1 1 1 CD261 CD63 CD66 CD67 CD19 CD260 CD12
    A CD122 CD123 CD124 CC206 22P_0402_50V8-J 22P_0402_50V8-J 22P_0402_50V8-J A
    0_0402_5% 0_0402_5% 0_0402_5% RFNS@ RFNS@ RFNS@
    2 2 2 2 2 2 2
    2 2 2 2
    RF
    2

    SITCD@ SITCD@

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 DDRIII SO-DIMM A
    SPD Address = A0H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 12 of 50


    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 DDRIII SO-DIMM B
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 13 of 50


    5 4 3 2 1
    5 4 3 2 1

    Power-Up/Down Sequence
    "Topaz" has the following requirements with regards to power-supply sequencing to
    avoid damaging the ASIC:
    D D
    All the ASIC supplies must reach their respective nominal voltages within 20 ms
    of the start of the ramp-up sequence, though a shorter ramp-up duration is
    preferred. The maximum slew rate on all rails is 50 mV/μ s. VRAM ID config
    It is recommended that the 3.3-V rail ramp up first.
    The 3.3-V, 1.8-V, and 0.95-V rails must reach their ready state at least 10 μ s VRAM ID PU resistor PD resistor
    Memory Type
    before VDDC, VDDCI, and VMEMIO start to ramp up. PS_3[3:1] RV63 RV70
    The power rails that are shared with other components on the system should be
    gated for the dGPU so that when the dGPU is powered down (for example
    AMD PowerXpress idle state), all the power rails are removed from the dGPU. NA 100 4.53K 4.99K
    The gate circuits must meet the slew rate requirement (such as ≤ 50 mV/μ s).
    For power down, reversing the ramp-up sequence is recommended. 128Mx16
    NA 111 4.75K NC

    NA 110 3.4K 10K


    0 ~ 20ms
    Hynix
    000 NC 4.75K
    VDDR3(+3VGS) H5TC4G63CFR-N0C 4Gb 900(1G)
    0 ~ 20ms
    C C
    Micron
    256Mx16 010 4.53K 2K
    VDD_CT(+1.8VGS) MT41J256M16LY-091G:N 4Gb 900(1G)

    Samsung
    001 8.45K 2K
    PCIE_VDDC(+0.95VGS) K4W4G1646E-BC1A 4Gb 900(1G)

    10us min.

    VDDR1(+1.35VGS)

    VDDC/VDDCI(+VGA_CORE) 100ms min.

    PERSTb(GPU_RST#) 100us min.

    REFCLK(CLK_PCIE_VGA)

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 VGA Notes List
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 14 of 50
    5 4 3 2 1
    5 4 3 2 1

    PCIE_CTX_C_GRX_P[0..3] PCIE_CRX_GTX_P[0..3]
    4 PCIE_CTX_C_GRX_P[0..3] PCIE_CRX_GTX_P[0..3] 4
    UV1A
    PCIE_CTX_C_GRX_N[0..3] PCIE_CRX_GTX_N[0..3]
    4 PCIE_CTX_C_GRX_N[0..3] PCIE_CRX_GTX_N[0..3] 4

    PCIE_CTX_C_GRX_P0 AF30 AH30 PCIE_CRX_C_GTX_P0 0.22U_0201_6.3V6-K 1 2 PX@ CV1 PCIE_CRX_GTX_P0


    PCIE_CTX_C_GRX_N0 AE31 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 0.22U_0201_6.3V6-K 1 2 PX@ CV2 PCIE_CRX_GTX_N0
    PCIE_RX0N PCIE_TX0N

    PCIE_CTX_C_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.22U_0201_6.3V6-K 1 2 PX@ CV3 PCIE_CRX_GTX_P1


    D PCIE_RX1P PCIE_TX1P D
    PCIE_CTX_C_GRX_N1 AD28 AF28 PCIE_CRX_C_GTX_N1 0.22U_0201_6.3V6-K 1 2 PX@ CV4 PCIE_CRX_GTX_N1
    PCIE_RX1N PCIE_TX1N

    PCIE_CTX_C_GRX_P2 AD30 AF27 PCIE_CRX_C_GTX_P2 0.22U_0201_6.3V6-K 1 2 PX@ CV5 PCIE_CRX_GTX_P2


    PCIE_CTX_C_GRX_N2 AC31 PCIE_RX2P PCIE_TX2P AF26 PCIE_CRX_C_GTX_N2 0.22U_0201_6.3V6-K 1 2 PX@ CV6 PCIE_CRX_GTX_N2
    PCIE_RX2N PCIE_TX2N

    PCIE_CTX_C_GRX_P3 AC29 AD27 PCIE_CRX_C_GTX_P3 0.22U_0201_6.3V6-K 1 2 PX@ CV7 PCIE_CRX_GTX_P3


    PCIE_CTX_C_GRX_N3 AB28 PCIE_RX3P PCIE_TX3P AD26 PCIE_CRX_C_GTX_N3 0.22U_0201_6.3V6-K 1 2 PX@ CV8 PCIE_CRX_GTX_N3
    PCIE_RX3N PCIE_TX3N

    AB30 AC25
    AA31 PCIE_RX4P PCIE_TX4P AB25
    PCIE_RX4N PCIE_TX4N

    AA29 Y23
    Y28 PCIE_RX5P PCIE_TX5P Y24
    PCIE_RX5N PCIE_TX5N

    Y30 AB27
    W31 PCIE_RX6P PCIE_TX6P AB26
    PCIE_RX6N PCIE_TX6N

    W29 Y27
    V28 PCIE_RX7P PCIE_TX7P Y26
    PCIE_RX7N PCIE_TX7N

    C C
    V30 W24
    U31 NC#V30 NC#W24 W23
    NC#U31 NC#W23

    U29 V27 with BOM strcture control, CV1--CV8 change to 0.22uf for CZ
    T28 NC#U29 NC#V27 U26
    NC#T28 NC#U26

    PCI EXPRESS INTERFACE


    T30 U24
    R31 NC#T30 NC#U24 U23
    NC#R31 NC#U23

    R29 T26
    P28 NC#R29 NC#T26 T27
    NC#P28 NC#T27

    P30
    NC#P30 NC#T24
    T24 change the GPU PN to AMD(EXO-S3 PRO), symbol check ok
    N31 T23
    NC#N31 NC#T23

    N29
    NC#N29 NC#P27
    P27 11/4 change to PC sample SA000074V10
    M28 P26
    NC#M28 NC#P26

    M30 P24
    L31 NC#M30 NC#P24 P23
    NC#L31 NC#P23
    B B
    L29 M27
    PXS_RST# K30 NC#L29 NC#M27 N26
    NC#K30 NC#N26

    CLOCK
    0.1U_0201_6.3V6-K

    CLK_PCIE_GPU AK30
    8 CLK_PCIE_GPU CLK_PCIE_GPU# PCIE_REFCLKP
    1 AK32
    8 CLK_PCIE_GPU# PCIE_REFCLKN
    +0.95VGS
    CALIBRATION
    2 Y22 RV3 1 PX@ 2 1.69K_0402_1%
    CV632

    PCIE_CALR_TX
    1K_0402_1% 1 PX@ 2 RV4 N10 AA22 RV5 1 PX@ 2 1K_0402_1%
    TEST_PG PCIE_CALR_RX

    GPU_RST# DV3
    AL27
    16 GPU_RST# PERSTB GPU_RST# 2
    1 VGA_PWROK
    VR_VGA_PWRGD VGA_PWROK 49
    1

    @ 3
    7,49 VR_VGA_PWRGD
    RV7 1 @ 2 0_0402_5% RV6
    100K_0402_5% LBAT54AWT1G SOT323
    +3VGS PX@ PX@
    2
    5

    UV2
    A A
    VCC

    1
    8 PXS_RST# IN1 GPU_RST#
    4
    2 OUT
    GND

    7,28,30,31,35 PLT_RST# IN2


    Security Classification LC Future Center Secret Data Title
    MC74VHC1G08DFT2G_SC70-5
    Issued Date Deciphered Date 2017/02/04 ATI_EXO-PRO_PCIE
    3

    PX@ 2017/02/04
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 15 of 50
    5 4 3 2 1
    5 4 3 2 1
    RECOMMENDED SETTINGS
    CONFIGURATION STRAPS 0= DO NOT INSTALL RESISTOR
    UV1B 1 = INSTALL 10K RESISTOR
    ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE X = DESIGN DEPENDANT
    GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET NA = NOT APPLICABLE

    AF2
    NC#AF2 AF4
    NC#AF4 MLPS Bit Strap Name Description RECOMMENDED
    SETTINGS
    N9 AG3 PS_0[1] ROM_CONFIG[0] Define the ROM type when STRAP_BIOS_ROM_EN = 1,
    L9 DBG_DATA16 NC#AG3 AG5 PS_0[2] ROM_CONFIG[1] Define the primary memory-aperture size when STRAP_BIOS_ROM_EN = 0.
    AE9 DBG_DATA15 NC#AG5 PS_0[3] ROM_CONFIG[2] X
    DPA
    Y11 DBG_DATA14 AH3 001 = 256MB
    AE8 DBG_DATA13 NC#AH3 AH1
    AD9 DBG_DATA12 NC#AH1 PS_0[4] N/A Reserved for internal use only. Must be 1 at reset. 1
    AC10 DBG_DATA11 AK3
    AD7 DBG_DATA10 NC#AK3 AK1 AUD_PORT_CONN_ The LSB (least significant bit) of the strap option that
    AC8 DBG_DATA9 NC#AK1 PS_0[5] PINSTRAP[0] indicates the number of audio-capable display outputs. 1
    DVO
    AC7 DBG_DATA8 AK5
    AB9 DBG_DATA7 NC#AK5 AM3 1 = PCIe GEN3 is supported.
    AB8 DBG_DATA6 NC#AM3 PS_1[1] STRAP_BIF_GEN3_EN_A 0 = PCIe GEN3 is not supported. 1= GEN3 is supported X
    AB7 DBG_DATA5 AK6
    AB4 DBG_DATA4 NC#AK6 AM5 0 = The CLKREQB power management capability is disabled
    AB2 DBG_DATA3 NC#AM5 PS_1[2] STRAP_BIF_CLK_PM_EN 1 = The CLKREQB power management capability is enabled 0
    DPB
    Y8 DBG_DATA2 AJ7
    D
    Y7 DBG_DATA1 NC#AJ7 AH6 PS_1[3] N/A Reserved for internal use only. Must be 0 at reset. 0
    D

    +3VGS DBG_DATA0 NC#AH6


    AK8 STRAP_TX_CFG_DRV_ 0 = The transmitter half-swing is enabled
    NC#AK8 AL7 PS_1[4] FULL_SWING 1 = The transmitter full-swing is enabled 1
    10K_0402_5% 1 @ 2 RV8 GPU_GPIO5 NC#AL7
    0 = Tx deemphasis disabled.
    W6 PS_1[5] STRAP_TX_DEEMPH_EN 1 = Tx deemphasis enabled. 1= Enable X
    V6 NC#W6
    1 2 GPU_GPIO0 NC#V6 V4
    10K_0402_5% @ RV9 PS_2[1] N/A Reserved. 0
    10K_0402_5% 1 @ 2 RV12 GPU_GPIO8 AC6 NC#V4 U5
    10K_0402_5% 1 @ 2 RV13 GPU_GPIO9 AC5 NC#AC6 NC#U5 PS_2[2] N/A Reserved. 0
    10K_0402_5% 1 @ 2 RV14 GPU_GPIO10 NC#AC5 W3 VGA_VSSI_SEN 1 TV10 PAD @
    10K_0402_5% 1 @ 2 RV25 GPU_GPIO11 AA5 NC#W3 V2 0 = Disable the external BIOS ROM device.
    10K_0402_5% 1 @ 2 RV96 GPU_GPIO12 AA6 NC#AA5 NC#V2 1 = Enable the external BIOS ROM device.
    DPC PS_2[3] STRAP_BIOS_ROM_EN 0= Disable X
    10K_0402_5% 1 @ 2 RV34 GPU_GPIO13 +1.8VGS NC#AA6 Y4
    10K_0402_5% 1 @ 2 RV81 GPU_GPIO22 NC#Y4 W5 0 = VGA controller capacity enabled.
    1 2 GPU_VID1 NC#W5 1 = The device will not be recognized as the system’ s V GA
    10K_0402_5% @ RV97 PS_2[4] STRAP_BIF_VGA_DIS 1
    10K_0402_5% 1 @ 2 RV98 GPU_GPIO21 RV93 1 2 TOPAZ@ BP_0 U1 AA3 PLL_ANALOG_OUT RV94 1 @ 2 controller.
    10K_0402_5% 1 @ 2 RV99 GPU_VID5 1 VGA_VDDCI_SEN W1 NC#U1 NC#AA3 Y2
    10K_0402_5% TV11 16.2K_0402_1% PS_2[5] N/A Reserved 1
    10K_0402_5% 1 @ 2 RV106 GPU_VID2 RV95 1 2 TOPAZ@ @ PAD BP_1 U3 NC#W1 NC#Y2
    10K_0402_5% Y6 NC#U3 J8 Board configuration related strapping, such as for memory ID
    GPU_GPIO17 PLL_ANALOG_IN NC#Y6 NC#J8 Reserve for Topaz
    10K_0402_5% 1 @ 2 RV1011 TV12 1 AA1 PS_3[1] BOARD_CONFIG[0] 100 = Hynix 1G 000 = Hynix 2G X
    @ PAD NC#AA1 PS_3[2] BOARD_CONFIG[1] 111 = Micron 1G 010 = Micron 2G
    5.11K_0402_1% 1 @ 2 RV1039 TESTEN PS_3[3] BOARD_CONFIG[2] 110 = Samsung 1G 001 = Samsung 2G

    Determines the maximum number of digital display audio endpoints


    Reserve I2C that will be presented to the OS and user.(Combine with PS_0[5])
    111 = No usable endpoints.
    R1 AUD_PORT_CONN_ 110 = One usable endpoint.
    R3 SCL PS_3[4] PINSTRAP[1] 101 = Two usable endpoints. 111= No usable endpoints.
    +VGA_CORE SDA 100 = Three usable endpoints. 11
    AM26 DIECRACKMON RV120 1 2 TOPAZ@ PS_3[5] AUD_PORT_CONN_ 011 = Four usable endpoints.
    NC_R AK26 10K_0402_5% PINSTRAP[2] 010 = Five usable endpoints.
    GPU_GPIO0 U6 GENERAL PURPOSE I/ONC_AVSSN#AK26 001 = Six usable endpoints.
    U10 GPIO_0 AL25 000 = All endpoints are usable.
    T10 NC_GPIO_1 NC_G AJ25
    VGA_SMB_DATA U8 NC_GPIO_2 NC_AVSSN#AJ25
    RB751V-40_SOD323-2 VGA_SMB_CLK U7 SMBDATA AH24
    DV1 1 2 @ GPU_GPIO5 T9 SMBCLK NC_B AG25 +1.8VGS +1.8VGS
    35 VGA_AC_DET GPU_VID5 T8 GPIO_5_AC_BATT NC_AVSSN#AG25
    T7 GPIO_6 DAC1 AH26
    GPU_VR_HOT# GPU_GPIO8 NC_GPIO_7 NC_HSYNC

    1
    RV104 1 2 PX@ P10 AJ27 RV22 1 2 4.7K_0402_5%
    0_0402_5% GPU_GPIO9 P4 GPIO_8_ROMSO NC_VSYNC TOPAZ@ RV71 RV74
    GPU_GPIO10 P2 GPIO_9_ROMSI 8.45K_0402_1% 8.45K_0402_1%
    +VGA_CORE GPU_GPIO11 N6 GPIO_10_ROMSCK AD22 PX@ PX@
    GPU_GPIO12 NC_GPIO_11 NC_RSET Pull down for none OBFF design
    @ PAD TV3 1 N5
    GPU_GPIO13 NC_GPIO_12 PS_0 PS_1

    2
    N3 AG24
    Y9 NC_GPIO_13 NC_AVDD AE22
    GPU_SVD GPU_VID3 NC_GPIO_14 NC_AVSSQ

    1
    0_0402_5% 1 EXO@ 2 RV103 N1 1 1
    C 10K_0402_5% 1 @ 2 RV67 GPU_GPIO16 M4 GPIO_15_PWRCNTL_0 AE23 RV77 CV15 RV80 CV16 C
    0_0402_5% 1 @ 2 RV107 GPU_GPIO17 R6 GPIO_16 NC_VDD1DI AD23 2K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
    35,49 GPU_VR_HOT# GPIO_17_THERMAL_INT NC_VSS1DI
    W10 PX@ @ PX@ @
    10K_0402_5% 1 PX@ 2 RV68 GPIO_19_CTF M2 NC_GPIO_18 2 2
    GPU_SVC GPU_VID4 GPIO_19_CTF FutureASIC/SEYMOUR/PARK CEC_1

    2
    0_0402_5% 1 EXO@ 2 RV105 P8 AM12 1 TV5
    GPU_GPIO21 P7 GPIO_20_PWRCNTL_1 CEC_1 PAD @
    GPU_GPIO22 N8 GPIO_21
    GPU_VID2 AK10 GPIO_22_ROMCSB AK12 GPU_SVD_R RV110 1 TOPAZ@ 2 0_0402_5% +1.8VGS +1.8VGS
    GPU_VR_HOT# 0_0402_5% 1 2 RV1012 GPU_VID1 AM10 GPIO_29 NC_SVI2#AK12 AL11 GPU_SVT_R GPU_SVD 49
    @ RV109 1 TOPAZ@ 2 0_0402_5%
    1 2 RV124 GPU_CLKREQ#_R N7 GPIO_30 NC_SVI2#AL11 AJ11 GPU_SVC_R GPU_SVT 49
    0_0402_5% @ RV111 1 TOPAZ@ 2 0_0402_5%
    7 GPU_CLKREQ# CLKREQB NC_SVI2#AJ11 GPU_SVC 49

    1
    JTAG_TRSTB L6 RV60 RV63
    +3VGS JTAG_TDI L5 JTAG_TRSTB 10K_0402_5% 8.45K_0402_1%
    JTAG_TCK L3 JTAG_TDI @ @
    JTAG_TMS L1 JTAG_TCK AL13 GENLK_CLK 1
    @ PAD TV1 PAD @
    JTAG_TRSTB 1JTAG_TDO JTAG_TMS NC_GENLK_CLK GENLK_VSYNC 1 PS_2 PS_3

    2
    10K_0402_5% 1 @ 2 RV72 TV7 K4 AJ13 TV2 PAD @
    10K_0402_5% 1 @ 2 RV75 JTAG_TDI RV64 1 PX@ 2 TESTEN K7 JTAG_TDO NC_GENLK_VSYNC
    JTAG_TMS TESTEN

    1
    10K_0402_5% 1 @ 2 RV78 1K_0402_5% AF24 1 1
    NC#AF24 AG13 RV69 CV18 RV70 CV19
    10K_0402_5% 1 @ 2 RV40 JTAG_TCK NC_SWAPLOCKA AH12 4.75K_0402_1% .01U_0402_16V7-K 2K_0402_1% .01U_0402_16V7-K
    AB13 NC_SWAPLOCKB PX@ @ @ @
    +VGA_CORE NC_GENERICA 2 2
    W8
    GPU_CLKREQ# NC_GENERICB

    2
    470_0402_5% 1 @ 2 RV1040 W9
    W7 NC_GENERICC AC19 PS_0
    AD10 NC_GENERICD PS_0
    2016/09/02: Pull-down GPU_CLKREQ# at GPU side NC_GENERICE_HPD4 PS_1
    AJ9 AD19
    AL9 NC#AJ9 PS_1
    DBG_CNTL0 PS_2 Bit BOM
    AE17 MLPS
    AC14 PS_2
    PX_EN NC_HPD1 PS_3 5 4 3 2 1 R_pu( ) R_pd( ) C(nF)
    @ PAD TV6 1 AB16 AE20
    PX_EN PS_3
    PS_0[5:1] 1 1 0 0 1 RV71=8.45k RV77=2K CV15=NC
    4.7K_0402_5% 1 @ 2 RV54
    PX@ 1 2 CV25 XTALIN AE19 PS_1[5:1] 1 1 0 0 1 RV74=8.45K RV80=2K CV16=NC
    @ PAD TV15 1 NC_DBG_VREFG AC16 TS_A
    NC_DBG_VREFG
    PS_2[5:1] 1 1 0 0 0 RV60=NC RV69=4.75K CV18=NC
    10P_0201_50V8-D
    PS_3[5:1] 1 1 X X X RV63=X76 RV70=X76 CV19=NC
    DDC/AUX
    2

    AE6
    PLL/CLOCK NC_DDC1CLK AE5
    YV1 with BOM strcture control, R_pu (Ω ) R_pd (Ω ) Bits [3:1]
    27MHZ_10PF_7V27000050
    GND1

    OSC1

    PX@ NC_DDC1DATA
    RV63,RV70 change to different value to
    1

    AD2 +VGA_CORE NC 4750 000


    RV46 NC_AUX1P AD4 1 adjust VRAM config
    NC_AUX1N
    1M_0402_5% RV24 with BOM strcture control, 8450 2000 001
    AC11
    GND2

    PX@ 100_0402_5%
    OSC2

    NC_DDC2CLK when config PEG3


    AC13 TOPAZ@ 4530 2000 010
    NC_DDC2DATA RV74 change to 8.45K,
    2

    RV80 change to 2K
    2

    XTALIN AM28 AD13 6980 4990 011


    XTALIN NC_AUX2P
    3

    XTALOUT AK28 AD11


    XTALOUT NC_AUX2N 4530 4990 100
    B XO_IN VGA_VSS_SEN_R Capacitor Value (nF) Bits [5:4] B
    10K_0402_5% 1 PX@ 2 RV45 AC22 AD20 RV125 1 TOPAZ@ 2 0_0402_5%
    1 XO_IN2 XO_IN NC#AD20 VGA_CORE_SEN_R VGA_VSS_SEN 49
    10K_0402_5% PX@ 2 RV50 AB22 AC20 RV126 1 TOPAZ@ 2 0_0402_5% 680 00 3240 5620 101
    XO_IN2 NC#AC20 VGA_CORE_SEN 49
    PX@ 1 2 CV32 XTALOUT AE16 82 01 3400 10000 110
    NC#AE16 AD16
    NC#AD16 10 10 4750 NC 111
    1

    10P_0201_50V8-D SEYMOUR/FutureASIC AC1


    @ PAD TV13 1 GPU_DPLUS T4 NC_DDCVGACLK AC3 RV23 NC 11
    no symbol for 8pf cap, PLM has PN,change the PN GPU_DMINUS DPLUS THERMAL NC_DDCVGADATA Note: 0402 1% resistors are required.
    @ PAD TV14 1 T2 100_0402_5%
    DMINUS TOPAZ@
    +3VGS +VDDIO_GPU
    GPIO_28_FDO
    2

    +3VGS RV41 1 @ 2 R5
    10K_0402_5% LV3 1 2 PX@ +TSVDD AD17 GPIO28_FDO RV234 1 2 EXO@
    +1.8VGS TSVDD SVC SVD Output Voltage (V)
    BLM15PD121SN1D_2P AC17 +1.8VGS 0_0402_5%
    TSVSS +VGA_CORE 0 0 1.1
    2

    (1.8V@20mA TSVDD) RV203 1 2 TOPAZ@


    RV42 1 0 1 1.0 0_0402_5%
    10K_0402_5% CV21 @
    EXO@ 1U_0402_6.3V6K For Topaz, RV23/RV24 stuff 100ohm 1 0 0.9
    PX@ For EXO, RV23/RV24 stuff 0hm
    2
    1

    2
    1 1 0.8
    RV205 RV204 RV209
    10K_0402_5% 10K_0402_5% 10K_0402_5%
    Connect GPIO_28 to 10K pull @ PX@ @
    down to enable MLPS. GPU_SVD

    1
    GPU_SVC
    GPU_SVT
    RV242 2 @ 1 0_0402_5% WRST# 35

    2
    RV206 RV207 RV210
    10K_0402_5% 10K_0402_5% 10K_0402_5%
    PX@ @ @

    1
    1

    C QV13
    GPU_RST# @ 1 2 DV2 RV128 1 @ 2 2 MMBT3904WH_SOT323-3 Internal VGA Thermal Sensor
    15 GPU_RST#
    2.2K_0402_5% B @
    0.1U_0201_6.3V6-K

    SDM10U45LP-7_DFN1006-2-2 @ E
    3

    +3VGS
    1

    1
    RV131 +3VGS
    GPIO_19_CTF 1 @ 2 RV132 100K_0402_5%
    47K_0402_5% @
    2
    1

    A A
    CV215
    2

    RV43 RV44
    2

    47K_0402_5% 47K_0402_5%
    G

    PX@ PX@
    2

    VGA_SMB_CLK QV4A 1 6 PX@


    S

    EC_SMB_CK3 6,30,35
    D

    2N7002KDWH_SOT363-6
    G

    VGA_SMB_DATA QV4B 4 3 PX@


    S

    EC_SMB_DA3 6,30,35
    D

    2N7002KDWH_SOT363-6

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_Main_MSIC


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Re v
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 16 of 50
    5 4 3 2 1
    5 4 3 2 1

    UV1F
    +VGA_CORE

    D AB11 D
    NC_VARY_BL AB12
    NC_DIGON

    AL15
    NC_UPHYAB_TMDPA_TX0N AK14
    NC_UPHYAB_TMDPA_TX0P
    AH16
    NC_UPHYAB_TMDPA_TX1N AJ15
    NC_UPHYAB_TMDPA_TX1P
    AL17
    NC_UPHYAB_TMDPA_TX2N AK16
    NC_UPHYAB_TMDPA_TX2P
    AH18
    NC_UPHYAB_TMDPA_TX3N AJ17
    NC_UPHYAB_TMDPA_TX3P
    AL19
    NC_TXOUT_L3P AK18
    NC_TXOUT_L3N

    C TMDP C

    AH20
    NC_UPHYAB_TMDPB_TX0N AJ19
    NC_UPHYAB_TMDPB_TX0P
    AL21
    NC_UPHYAB_TMDPB_TX1N AK20
    NC_UPHYAB_TMDPB_TX1P
    AH22
    NC_UPHYAB_TMDPB_TX2N AJ21
    NC_UPHYAB_TMDPB_TX2P
    AL23
    NC_UPHYAB_TMDPB_TX3N AK22
    NC_UPHYAB_TMDPB_TX3P
    AK24
    NC_TXOUT_U3P AJ23
    NC_TXOUT_U3N

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_TMDP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 17 of 50
    5 4 3 2 1
    5 4 3 2 1

    +1.8VGS (1.8V@425mA DP_VDDR)


    RV48 1 @ 2 0_0603_5% +DP_VDDR
    UV1G UV1E

    PX@

    PX@
    DP POWER NC/DP POWER

    10U_0603_6.3V6M

    1U_0402_6.3V6K
    1 1
    AG15 AE11 AA27 A3
    AG16 NC_DP_VDDR#AG15 NC#AE11 AF11 AB24 GND_1 GND_65 A30
    AF16 NC_DP_VDDR#AG16 NC#AF11 AE13 AB32 GND_2 GND_66 AA13
    D D
    2 2 AG17 NC_DP_VDDR#AF16 NC#AE13 AF13 AC24 GND_3 GND_67 AA16

    CV39

    CV40
    AG18 NC_DP_VDDR#AG17 NC#AF13 AG8 AC26 GND_4 GND_68 AB10
    AG19 NC_DP_VDDR#AG18 NC#AG8 AG10 AC27 GND_5 GND_69 AB15
    AF14 NC_DP_VDDR#AG19 NC#AG10 AD25 GND_6 GND_70 AB6
    DP_VDDR#AF14 AD32 GND_7 GND_71 AC9
    AE27 GND_8 GND_72 AD6
    +0.95VGS AF32 GND_9 GND_73 AD8
    (0.95V@560mA DP_VDDC) GND_10 GND_74
    AG27 AE7
    RV47 1 @ 2 0_0603_5% +DP_VDDC AG20 AF6 AH32 GND_11 GND_75 AG12
    AG21 NC_DP_VDDC#AG20 NC#AF6 AF7 K28 GND_12 GND_76 AH10
    NC_DP_VDDC#AG21 NC#AF7 GND_13 GND_77

    PX@

    PX@
    AF22 AF8 K32 AH28

    0.1U_0201_6.3V6-K
    AG22 NC_DP_VDDC#AF22 NC#AF8 AF9 L27 GND_14 GND_78 B10

    1U_0402_6.3V6K
    AD14 NC_DP_VDDC#AG22 NC#AF9 M32 GND_15 GND_79 B12
    1 1 DP_VDDC#AD14 GND_16 GND_80
    N25 B14
    N27 GND_17 GND_81 B16
    P25 GND_18 GND_82 B18
    2 2 AG14 AE1 P32 GND_19 GND_83 B20

    CV38

    CV37
    AH14 NC_DP_VSSR_1 NC#AE1 AE3 R27 GND_20 GND_84 B22
    AM14 NC_DP_VSSR_2 NC#AE3 AG1 T25 GND_21 GND_85 B24
    AM16 NC_DP_VSSR_3 NC#AG1 AG6 T32 GND_22 GND_86 B26
    AM18 NC_DP_VSSR_4 NC#AG6 AH5 U25 GND_23 GND_87 B6
    AF23 NC_DP_VSSR_5 NC#AH5 AF10 U27 GND_24 GND_88 B8
    AG23 NC_DP_VSSR_6 NC#AF10 AG9 V32 GND_25 GND_89 C1
    AM20 NC_DP_VSSR_7 NC#AG9 AH8 W25 GND_26 GND_90 C32
    C
    AM22 NC_DP_VSSR_8 NC#AH8 AM6 W26 GND_27 GND_91 E28 C
    AM24 NC_DP_VSSR_9 NC#AM6 AM8 W27 GND_28 GND_92 F10
    AF19 NC_DP_VSSR_10 NC#AM8 AG7 Y25 GND_29 GND_93 F12
    AF20 NC_DP_VSSR_11 NC#AG7 AG11 Y32 GND_30 GND_94 F14
    AE14 NC_DP_VSSR_12 NC#AG11 GND_31 GND_95 F16
    DP_VSSR_13 GND_96 F18
    GND_97 F2
    GND_98 F20
    RV49 1 @ 2 AF17 AE10 M6 GND_99 F22
    150_0402_1% NC_UPHYAB_DP_CALR NC#AE10 N13 GND_32 GND_100 F24
    N16 GND_33 GND_101 F26
    N18 GND_34 GND_102 F6
    @ N21 GND_35 GND
    GND_103 F8
    P6 GND_36 GND_104 G10
    P9 GND_37 GND_105 G27
    R12 GND_38 GND_106 G31
    R15 GND_39 GND_107 G8
    R17 GND_40 GND_108 H14
    R20 GND_41 GND_109 H17
    T13 GND_42 GND_110 H2
    T16 GND_43 GND_111 H20
    T18 GND_44 GND_112 H6
    T21 GND_45 GND_113 J27
    T6 GND_46 GND_114 J31
    U15 GND_47 GND_115 K11
    B B
    U17 GND_48 GND_116 K2
    U20 GND_49 GND_117 K22
    U9 GND_50 GND_118 K6
    V13 GND_51 GND_119
    V16 GND_52
    V18 GND_53
    Y10 GND_54
    Y15 GND_55
    Y17 GND_56
    Y20 GND_57
    R11 GND_58 A32
    T11 GND_59 VSS_MECH_1 AM1
    AA11 GND_60 VSS_MECH_2 AM32
    M12 GND_61 VSS_MECH_3
    N11 GND_62
    V11 GND_63
    GND_64

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_DP Power
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 18 of 50
    5 4 3 2 1
    5 4 3 2 1

    +1.35VGS
    For DDR3/GDDR5, 1500mA@1.5V

    CV48

    CV51

    CV52

    CV53

    CV54

    CV55

    CV56

    CV217
    10U_0603_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    0.01U_0201_10V6K
    0.1U_0201_6.3V6-K
    1 1 1 1 1 1 1 1 1 UV1D +1.8VGS
    CV501 (1.8V@100mA PCIE_PVDD)
    33P_0402_50V8J AM30
    MEM I/O PCIE_PVDD

    PCIE
    RF_PXNS@

    CV46

    CV47
    2 2 2 2 2 2 2 2 2 H13 AB23

    10U_0603_6.3V6M
    1U_0402_6.3V6K
    H16 VDDR1_1 NC#AB23 AC23

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    VDDR1_2 NC#AC23 1 1
    RF H19 AD24
    J10 VDDR1_3 NC#AD24 AE24
    J23 VDDR1_4 NC#AE24 AE25
    J24 VDDR1_5 NC#AE25 AE26 2 2
    J9 VDDR1_6 NC#AE26 AF25

    PX@

    PX@
    K10 VDDR1_7 NC#AF25 AG26
    +1.8VGS +VDD_CT K23 VDDR1_8 NC#AG26 +0.95VGS
    (1.8V@13mA VDD_CT) VDDR1_9
    D K24 (0.95V@2500mA PCIE_VDDC) D
    LV7 1 @ 2 0_0402_5% K9 VDDR1_10 L23
    L11 VDDR1_11 PCIE_VDDC_1 L24

    CV144
    L12 VDDR1_12 PCIE_VDDC_2 L25

    CV64

    CV65

    CV66

    CV67

    CV68

    CV69

    CV71
    1U_0402_6.3V6K
    L13 VDDR1_13 PCIE_VDDC_3 L26

    10U_0603_6.3V6M
    1

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    L20 VDDR1_14 PCIE_VDDC_4 M22
    VDDR1_15 PCIE_VDDC_5 1 1 1 1 1 1 1 1
    L21 N22 CV502
    L22 VDDR1_16 PCIE_VDDC_6 N23 33P_0402_50V8J
    2 VDDR1_17 PCIE_VDDC_7 N24

    PX@
    RF_PXNS@
    PCIE_VDDC_8 R22 2 2 2 2 2 2 2 2
    PCIE_VDDC_9

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    T22 RF
    LEVEL PCIE_VDDC_10 U22
    TRANSLATION PCIE_VDDC_11 V22
    AA20 PCIE_VDDC_12 +VGA_CORE
    AA21 VDD_CT_1
    AB20 VDD_CT_2 AA15
    +3VGS AB21 VDD_CT_3 CORE VDDC_1 N15
    (3.3V@25mA VDDR3) VDD_CT_4 VDDC_2 N17

    CV73

    CV74

    CV75

    CV76

    CV77

    CV84
    CV141

    CV143

    CV146

    CV148

    CV150

    CV152

    CV159

    CV133

    CV137

    CV151
    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M

    2.2U_0402_6.3V6M
    LV8 1 @ 2 0_0402_5% +VDDR3 VDDC_3 R13
    I/O VDDC_4 R16

    CV149
    VDDC_5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    change LV4 to SM01000MK00 (S SUPPRE_ BLM15AG221SN1 122) AA17 R18

    1U_0402_6.3V6K
    AA18 VDDR3_1 VDDC_6 Y21
    as DFC suggest, footprint with 1
    AB17 VDDR3_2 VDDC_7 T12
    MURAT_BLM15PD121SN1D_2P AB18 VDDR3_3 VDDC_8 T15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    VDDR3_4 VDDC_9 T17

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    2 VDDC_10

    PX@
    V12 T20
    Y12 NC_VDDR4_1 VDDC_11 U13
    +1.8VGS U12 NC_VDDR4_2 VDDC_12 U16
    NC_VDDR4_3 VDDC_13 U18
    (1.8V@130mA MPLL_PVDD) VDDC_14 V21
    LV4 1 2 PX@ +MPLL_PVDD VDDC_15 V15
    BLM15AG221SN1 VDDC_16 V17

    CV139

    CV153

    CV156

    CV160

    CV134

    CV135
    VDDC_17 V20
    CV26

    CV34

    CV27

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    VDDC_18 Y13

    POWER
    CV24

    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1 1 1 1 1 1 1
    1U_0402_6.3V6K
    0.1U_0201_6.3V6-K

    VDDC_19 Y16 CV503


    1 1 1 VDDC_20
    1 Y18 33P_0402_50V8J
    VDDC_21 AA12 RF_PXNS@
    VDDC_22 M11 2 2 2 2 2 2 2
    2 2 2 VDDC_23 N12

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    2 VDDC_24 U11
    PX@

    PX@

    PX@

    VDDC_25
    RF
    @

    C
    For EMC C
    PLL
    +0.95VGS
    (0.95V@1400mA BIF_VDDC)
    +1.8VGS R21
    BIF_VDDC_1 U21
    (1.8V@75mA SPLL_PVDD) BIF_VDDC_2
    +SPLL_PVDD +MPLL_PVDD 1
    LV5 1 2 PX@ L8 CV41
    BLM15PD121SN1D_2P MPLL_PVDD +VGA_CORE 1U_0402_6.3V6K
    PX@
    CV29

    CV30

    ISOLATED
    (GDDR3/DDR3 8.8A@1.12V VDDCI) 2
    CV28

    10U_0603_6.3V6M

    1U_0402_6.3V6K
    0.1U_0201_6.3V6-K

    CORE I/O
    1 1 M13
    +SPLL_PVDD H7 VDDCI_1 M15
    1 SPLL_PVDD VDDCI_2 M16

    CV218

    CV219

    CV158

    CV132

    CV136

    CV138

    CV220
    +0.95VGS VDDCI_3 M17

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    2 2 VDDCI_4 M18
    (0.95V@100mA SPLL_VDDC)

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    2 VDDCI_5 M20
    +SPLL_VDDC VDDCI_6 1 1 1 1 1 1 1 1
    LV6 1 2 PX@ H8 M21
    PX@

    PX@

    CV504
    @

    BLM15PD121SN1D_2P SPLL_VDDC VDDCI_7 N20 33P_0402_50V8J


    For EMC J7 VDDCI_8 RF_PXNS@
    SPLL_PVSS 2 2 2 2 2 2 2 2
    CV35

    CV36
    0.1U_0201_6.3V6-K

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@

    PX@
    1U_0402_6.3V6K

    1 1 1 RF
    CV33 @
    0.1U_0201_6.3V6-K
    @
    2 2 2
    PX@

    PX@

    For EMC

    MOS. AO3402 VGS MAX is 12V +1.8VALW TO +1.8VGS +0.95VALW to +0.95VGS


    +1.8VALW QV2 +1.8VGS Can change to low cost and small Can change to low cost and +0.95VALW
    AO3402_SOT-23-3 QV3 +0.95VGS
    PX@
    size MOS. AO3402 small size MOS.Rdson<22mohm AON6414AL_DFN8-5
    +1.8VGS /0.5A Rdson<65mohm Reserve for GPU support +0.95VS /2A PX@
    1 3
    B D S 1 B
    CV518

    CV519

    CV241

    CV243

    CV242
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    2
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1
    G

    5 3

    CV521
    1 1 1 1 1

    0.1U_0201_6.3V6-K

    1
    RV1001

    CV240

    CV238

    CV239
    2

    +5VALW 470_0603_5% RV1002

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    1 1

    1U_0402_6.3V6K
    @ PXS_PW REN#_H 1 @ 2 RV245 CV520 470_0603_5%
    1 1 1

    4
    1 PX@ 2 RV1015 2 2 2 2 2 15K_0402_5% 0.1U_0201_6.3V6-K @
    2
    PX@

    PX@

    V20B+ 20K_0402_5% @
    @

    2
    2 2
    @

    PXS_PW REN#_H 2 2 2
    1

    1 @ 2 RV202 D QV20 130K_0402_5% 1 PX@ 2 RV1006

    @
    PXS_PW REN# V20B+

    1
    2

    PX@

    PX@

    PX@
    120K_0402_5% D QV21
    G 120K_0402_5% 1 @ 2 RV1016 2 PXS_PW REN#
    +5VALW
    1

    1
    1 G
    1

    QV31 D RV123 S 2N7002KW_SOT323-3 RV1004 CV221


    PXS_PW REN# 1
    3

    2 150K_0402_5% CV237 @ QV23 D 1M_0402_5% 0.1U_0201_25V6-K S 2N7002KW_SOT323-3


    PXS_PW REN#

    3
    G @ 0.1U_0201_25V6-K 2 PX@ PX@ @
    PX@ G 2
    2

    2
    2N7002KW_SOT323-3 S 2
    3

    PX@ 2N7002KW_SOT323-3 S
    3

    PX@

    change MOS from 7408 to 6414 for Rds on consider

    +3VGS +3.3VS TO +3VGS +VGA_CORE +1.35VGS


    +3VALW
    +3.3VGS /25mA
    +3VS RV1014 1 PX@ 2 0_0603_5% LP2301ALT1G_SOT23-3
    1

    RV1013 1 @ 2 0_0603_5% QV6 3 1 PX@ RV166 RV1005


    S

    470_0603_5% 470_0603_5%
    CV513

    CV511
    10U_0603_6.3V6M

    @ @
    1U_0402_6.3V6K

    1 1
    G
    2

    RV1007
    470_0603_5%
    +5VALW @
    2 2
    1

    1
    PX@

    PX@

    D D QV25
    PXS_PW REN# PXS_PW REN# 2 PXS_PW REN#
    2

    RV1009 1 PX@ 2 RV1010 2 PX@ 1 QV19 2


    A 20K_0402_5% 15K_0402_5% G 2N7002KW_SOT323-3 G A

    1 @
    1

    CV517 D QV28 S S 2N7002KW_SOT323-3


    PXS_PW REN#
    3

    3
    1

    QV27 D 0.1U_0201_6.3V6-K 2 @
    PXS_PW REN 2 PX@ G
    7,48,49 PXS_PW REN G 2
    S 2N7002KW_SOT323-3
    3

    2N7002KW_SOT323-3 S @
    3

    PX@

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_Power
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 19 of 50


    5 4 3 2 1
    5 4 3 2 1

    UV1C
    DQA0_[31..0]
    DQA0_[31..0] 21 GDDR5/DDR3 GDDR5/DDR3
    DQA0_0 K27 K17 MAA0_0
    DQA1_[31..0] DQA0_1 J29 DQA0_0 MAA0_0/MAA_0 J20 MAA0_1
    DQA1_[31..0] 22 DQA0_2 DQA0_1 MAA0_1/MAA_1 MAA0_2
    H30 H23
    DQA0_3 H32 DQA0_2 MAA0_2/MAA_2 G23 MAA0_3
    DQA0_4 G29 DQA0_3 MAA0_3/MAA_3 G24 MAA0_4
    DQA0_5 F28 DQA0_4 MAA0_4/MAA_4 H24 MAA0_5
    DQA0_6 F32 DQA0_5 MAA0_5/MAA_5 J19 MAA0_6
    D DQA0_6 MAA0_6/MAA_6 D
    DQA0_7 F30 K19 MAA0_7
    DQA0_8 C30 DQA0_7 MAA0_7/MAA_7 G20 MAA0_8
    MAA0_[8..0] DQA0_9 F27 DQA0_8 MAA0_8/MAA_13 L17
    MAA0_[8..0] 21 DQA0_10 A28 DQA0_9 MAA0_9/MAA_15
    DQA0_11 C28 DQA0_10 J14 MAA1_0
    MAA1_[8..0] DQA0_12 E27 DQA0_11 MAA1_0/MAA_8 K14 MAA1_1
    MAA1_[8..0] 22 DQA0_13 G26 DQA0_12 MAA1_1/MAA_9 J11 MAA1_2
    DQA0_14 D26 DQA0_13 MAA1_2/MAA_10 J13 MAA1_3
    DQA0_15 F25 DQA0_14 MAA1_3/MAA_11 H11 MAA1_4
    DQA0_16 A25 DQA0_15 MAA1_4/MAA_12 G11 MAA1_5
    DQA0_17 C25 DQA0_16 MAA1_5/MAA_BA2 J16 MAA1_6
    DQA0_18 E25 DQA0_17 MAA1_6/MAA_BA0 L15 MAA1_7
    DQA0_19 D24 DQA0_18 MAA1_7/MAA_BA1 G14 MAA1_8
    DQA0_20 E23 DQA0_19 MAA1_8/MAA_14 L16

    MEMORY INTERFACE
    DQA0_21 F23 DQA0_20 MAA1_9/RSVD
    DQA0_22 D22 DQA0_21 E32 WCKA0_0
    DQA0_23 F21 DQA0_22 W CKA0_0/DQMA0_0 E30 WCKA0#_0 WCKA0_0 21
    DQA0_24 DQA0_23 W CKA0B_0/DQMA0_1 WCKA0_1 WCKA0#_0 21
    E21 A21
    DQA0_25 D20 DQA0_24 W CKA0_1/DQMA0_2 C21 WCKA0#_1 WCKA0_1 21
    DQA0_26 DQA0_25 W CKA0B_1/DQMA0_3 WCKA1_0 WCKA0#_1 21
    F19 E13
    DQA0_27 DQA0_26 W CKA1_0/DQMA1_0 WCKA1#_0 WCKA1_0 22
    A19 D12
    DQA0_28 D18 DQA0_27 W CKA1B_0/DQMA1_1 E3 WCKA1_1 WCKA1#_0 22
    DQA0_29 F17 DQA0_28 W CKA1_1/DQMA1_2 F4 WCKA1#_1 WCKA1_1 22
    DQA0_30 A17 DQA0_29 W CKA1B_1/DQMA1_3 WCKA1#_1 22
    DQA0_31 C17 DQA0_30 H28 EDCA0_0
    DQA1_0 E17 DQA0_31 EDCA0_0/QSA0_0 C27 EDCA0_1 EDCA0_0 21
    DQA1_1 D16 DQA1_0 EDCA0_1/QSA0_1 A23 EDCA0_2 EDCA0_1 21
    C DQA1_1 EDCA0_2/QSA0_2 EDCA0_2 21 C
    +1.35VGS DQA1_2 F15 E19 EDCA0_3
    DQA1_3 A15 DQA1_2 EDCA0_3/QSA0_3 E15 EDCA1_0 EDCA0_3 21
    DQA1_4 D14 DQA1_3 EDCA1_0/QSA1_0 D10 EDCA1_1 EDCA1_0 22
    DQA1_5 DQA1_4 EDCA1_1/QSA1_1 EDCA1_2 EDCA1_1 22
    1

    F13 D6
    DQA1_6 A13 DQA1_5 EDCA1_2/QSA1_2 G5 EDCA1_3 EDCA1_2 22
    RV61
    DQA1_7 DQA1_6 EDCA1_3/QSA1_3 EDCA1_3 22
    40.2_0402_1% C13
    PX@ DQA1_8 E11 DQA1_7 H27 DDBIA0_0
    DQA1_9 DQA1_8 DDBIA0_0/QSA0_0B DDBIA0_1 DDBIA0_0 21
    A11 A27
    DQA1_9 DDBIA0_1/QSA0_1B DDBIA0_1 21
    2

    MVREFD_A DQA1_10 C11 C23 DDBIA0_2


    DQA1_11 F11 DQA1_10 DDBIA0_2/QSA0_2B C19 DDBIA0_3 DDBIA0_2 21
    DQA1_12 DQA1_11 DDBIA0_3/QSA0_3B DDBIA1_0 DDBIA0_3 21
    1

    1 A9 C15
    DQA1_13 C9 DQA1_12 DDBIA1_0/QSA1_0B E9 DDBIA1_1 DDBIA1_0 22
    RV65 CV154
    DQA1_14 F9 DQA1_13 DDBIA1_1/QSA1_1B C5 DDBIA1_2 DDBIA1_1 22
    100_0402_1% 1U_0402_6.3V6K
    DQA1_15 D8 DQA1_14 DDBIA1_2/QSA1_2B H4 DDBIA1_3 DDBIA1_2 22
    PX@ PX@
    2 DQA1_16 E7 DQA1_15 DDBIA1_3/QSA1_3B DDBIA1_3 22
    DQA1_16
    2

    DQA1_17 A7 L18 ADBIA0


    DQA1_18 C7 DQA1_17 ADBIA0/ODTA0 K16 ADBIA0 21
    ADBIA1
    DQA1_19 F7 DQA1_18 ADBIA1/ODTA1 ADBIA1 22
    DQA1_20 A5 DQA1_19 H26 CLKA0
    DQA1_21 E5 DQA1_20 CLKA0 H25 CLKA0 21
    CLKA#0
    DQA1_22 DQA1_21 CLKA0B CLKA#0 21
    C3
    DQA1_23 E1 DQA1_22 G9 CLKA1
    DQA1_24 DQA1_23 CLKA1 CLKA1 22
    G7 H9 CLKA#1
    DQA1_25 DQA1_24 CLKA1B CLKA#1 22
    +1.35VGS G6
    DQA1_26 G1 DQA1_25 G22 RASA#0
    DQA1_27 G3 DQA1_26 RASA0B G17 RASA#0 21
    RASA#1
    DQA1_28 DQA1_27 RASA1B RASA#1 22
    1

    B J6 B
    RV62 DQA1_29 J1 DQA1_28 G19 CASA#0
    DQA1_30 J3 DQA1_29 CASA0B G16 CASA#0 21
    40.2_0402_1% CASA#1
    DQA1_31 J5 DQA1_30 CASA1B CASA#1 22
    PX@
    DQA1_31 H22 CSA0#_0
    CSA0B_0 CSA0#_0 21
    2

    MVREFS_A MVREFD_A K26 J22


    MVREFS_A J26 MVREFDA CSA0B_1
    MVREFSA CSA1#_0
    1

    1 G13
    J25 CSA1B_0 K13 CSA1#_0 22
    RV66 CV157
    100_0402_1% 1U_0402_6.3V6K RV55 1 PX@ 2 MEM_CALRP0 K25 NC#J25 CSA1B_1
    PX@ PX@ 120_0402_1% MEM_CALRP0 K20 CKEA0
    2 CKEA0 CKEA0 21
    J17 CKEA1
    CKEA1 CKEA1 22
    2

    G25 WEA#0
    W EA0B WEA#0 21
    DRAMRST L10 H10 WEA#1
    DRAM_RST W EA1B WEA#1 22
    PAD @ TV8 1 CLKTESTA K8
    PAD @ TV9 1 CLKTESTB L7 CLKTESTA
    CLKTESTB

    A DRAMRST RV56 1 PX@ 2 RV57 1 2 PX@ A


    DRAM_RST 21,22
    10_0402_5% 51.1_0402_1%
    1

    RV58 1
    4.99K_0402_1% CV147
    PX@ 120P_0402_50V8-J Title
    PX@
    Security Classification LC Future Center Secret Data
    2

    2
    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_MEM IF
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 20 of 50


    5 4 3 2 1
    5 4 3 2 1

    Lower 32 bits
    DQA0_[31..0] 20
    MF=0 No Mirror MF=1 Mirror
    MAA0_[8..0] 20
    UV5 UV6

    MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

    +1.35VGS A4 DQA0_30 A4 DQA0_7


    EDCA0_3 C2 DQ24 DQ0 A2 DQA0_28 EDCA0_0 C2 DQ24 DQ0 A2 DQA0_5
    20 EDCA0_3 EDC0 EDC3 DQ25 DQ1 DQA0_31 20 EDCA0_0 EDC0 EDC3 DQ25 DQ1 DQA0_6
    C13 B4 C13 B4
    EDCA0_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_29 EDCA0_2 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA0_4
    D D
    20 EDCA0_1 EDC2 EDC1 DQ27 DQ3 DQA0_27 20 EDCA0_2 EDC2 EDC1 DQ27 DQ3 DQA0_3
    1

    1 R2 E4 R2 E4
    RV1018 CV522 EDC3 EDC0 DQ28 DQ4 E2 DQA0_26 EDC3 EDC0 DQ28 DQ4 E2 DQA0_2 +1.35VGS
    2.37K_0402_1% 1U_0402_6.3V6K DQ29 DQ5 F4 DQA0_24 DQ29 DQ5 F4 DQA0_1
    @ @ DDBIA0_3 D2 DQ30 DQ6 F2 DQA0_25 DDBIA0_0 D2 DQ30 DQ6 F2 DQA0_0
    2 20 DDBIA0_3 DBI0# DBI3# DQ31 DQ7 20 DDBIA0_0 DBI0# DBI3# DQ31 DQ7
    D13 A11 D13 A11
    +1.35VGS DDBIA0_1 DBI1# DBI2# DQ16 DQ8 +1.35VGS DDBIA0_2 DBI1# DBI2# DQ16 DQ8
    2

    P13 A13 P13 A13 CLKA0 60.4_0402_1% 1 PX@ 2 RV1031


    VREFD1_A0 20 DDBIA0_1 DBI2# DBI1# DQ17 DQ9 20 DDBIA0_2 DBI2# DBI1# DQ17 DQ9
    +1.35VGS P2 B11 +1.35VGS P2 B11
    DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13 CLKA#0 60.4_0402_1% 1 PX@ 2 RV1036
    DQ19 DQ11 DQ19 DQ11
    1

    1 CLKA0 J12 E11 CLKA0 J12 E11


    20 CLKA0 CK DQ20 DQ12 CK DQ20 DQ12
    RV1019 CV361 CLKA#0 J11 E13 CLKA#0 J11 E13
    20 CLKA#0 CK# DQ21 DQ13 CK# DQ21 DQ13
    5.49K_0402_1% 1U_0402_6.3V6K CKEA0 J3 F11 CKEA0 J3 F11
    20 CKEA0 CKE# DQ22 DQ14 CKE# DQ22 DQ14
    @ @ F13 F13
    2 DQ23 DQ15 U11 DQA0_14 DQ23 DQ15 U11 DQA0_16
    DQ8 DQ16 DQ8 DQ16
    2

    MAA0_2 H11 U13 DQA0_12 MAA0_4 H11 U13 DQA0_18


    MAA0_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_15 MAA0_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA0_17
    MAA0_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_13 MAA0_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA0_19
    MAA0_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_10 MAA0_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA0_22
    BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_9 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA0_20
    DQ13 DQ21 M11 DQA0_8 DQ13 DQ21 M11 DQA0_23
    MAA0_7 K4 DQ14 DQ22 M13 DQA0_11 MAA0_0 K4 DQ14 DQ22 M13 DQA0_21
    MAA0_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MAA0_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4
    +1.35VGS MAA0_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MAA0_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2
    MAA0_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MAA0_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4
    MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MAA0_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2
    A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
    DQ4 DQ28 DQ4 DQ28
    1

    1 A5 N2 A5 N2
    RV1020 CV524 U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
    2.37K_0402_1% 1U_0402_6.3V6K VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
    @ @ DQ7 DQ31 DQ7 DQ31
    2 J1 +1.35VGS J1 +1.35VGS
    MF +1.35VGS MF
    2

    J10 J10
    VREFD2_A0 1 PX@ 2 RV1017 J13 SEN B1 1 PX@ 2 RV1024 J13 SEN B1
    120_0402_1% ZQ VDDQ1 D1 120_0402_1% ZQ VDDQ1 D1
    VDDQ2 VDDQ2
    1

    1 F1 F1
    C
    RV1021 CV523 ADBIA0 J4 VDDQ3 M1 ADBIA0 J4 VDDQ3 M1 C
    20 ADBIA0 ABI# VDDQ4 ABI# VDDQ4
    5.49K_0402_1% 1U_0402_6.3V6K RASA#0 G3 P1 CASA#0 G3 P1
    20 RASA#0 CSA0#_0 RAS# CAS# VDDQ5 RAS# CAS# VDDQ5
    @ @ G12 T1 WEA#0 G12 T1
    2 20 CSA0#_0 CS# WE# VDDQ6 CS# WE# VDDQ6
    CASA#0 L3 G2 RASA#0 L3 G2
    20 CASA#0 CAS# RAS# VDDQ7 CAS# RAS# VDDQ7
    2

    WEA#0 L12 L2 CSA0#_0 L12 L2


    20 WEA#0 WE# CS# VDDQ8 WE# CS# VDDQ8
    B3 B3
    VDDQ9 D3 VDDQ9 D3
    VDDQ10 F3 VDDQ10 F3
    WCKA0#_1 D5 VDDQ11 H3 WCKA0#_0 D5 VDDQ11 H3
    20 WCKA0#_1 WCKA0_1 WCK01# WCK23# VDDQ12 WCKA0_0 WCK01# WCK23# VDDQ12
    D4 K3 D4 K3
    20 WCKA0_1 WCK01 WCK23 VDDQ13 WCK01 WCK23 VDDQ13
    M3 M3 UV6 SIDE
    WCKA0#_0 P5 VDDQ14 P3 WCKA0#_1 P5 VDDQ14 P3 +1.35VGS
    +1.35VGS 20 WCKA0#_0 WCKA0_0 WCK23# WCK01# VDDQ15 WCKA0_1 WCK23# WCK01# VDDQ15
    P4 T3 P4 T3
    20 WCKA0_0 WCK23 WCK01 VDDQ16 WCK23 WCK01 VDDQ16
    E5 E5
    VDDQ17 N5 VDDQ17 N5
    VREFD2_A0 A10 VDDQ18 VREFD1_A0 A10 VDDQ18

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@

    PX@

    PX@
    E10 E10

    CD@

    CD@

    CD@

    CD@
    VREFD1_A0 U10 VREFD1 VDDQ19 VREFD2_A0 U10 VREFD1 VDDQ19
    1

    1 N10 N10 1 1 1 1 1 1 1 1
    RV1023 CV526 VREFC_A0 J14 VREFD2 VDDQ20 B12 VREFC_A0 J14 VREFD2 VDDQ20 B12 CV562
    2.37K_0402_1% 1U_0402_6.3V6K VREFC VDDQ21 D12 VREFC VDDQ21 D12 33P_0402_50V8J
    PX@ @ VDDQ22 F12 VDDQ22 F12 RF_PX@
    2 VDDQ23 H12 VDDQ23 H12 2 2 2 2 2 2 2 2

    CV561

    CV553

    CV566

    CV555

    CV567

    CV554

    CV629
    DRAM_RST VDDQ24 DRAM_RST VDDQ24
    2

    J2 K12 J2 K12
    VREFC_A0 20,22 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
    M12 M12
    VDDQ26 P12 VDDQ26 P12
    VDDQ27 VDDQ27
    1

    1 T12 T12
    RV1022 CV525 VDDQ28 G13 VDDQ28 G13
    5.49K_0402_1% 1U_0402_6.3V6K H1 VDDQ29 L13 H1 VDDQ29 L13 +1.35VGS
    VSS1 VDDQ30 VSS1 VDDQ30 UV6 SIDE
    PX@ PX@ K1 B14 K1 B14
    2 B5 VSS2 VDDQ31 D14 B5 VSS2 VDDQ31 D14
    VSS3 VDDQ32 VSS3 VDDQ32
    2

    G5 F14 G5 F14
    VSS4 VDDQ33 VSS4 VDDQ33

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@
    L5 M14 L5 M14

    CD@

    CD@

    CD@

    CD@

    CD@

    CD@

    CD@
    T5 VSS5 VDDQ34 P14 T5 VSS5 VDDQ34 P14
    VSS6 VDDQ35 VSS6 VDDQ35 1 1 1 1 1 1 1 1
    B10 T14 B10 T14
    D10 VSS7 VDDQ36 D10 VSS7 VDDQ36
    G10 VSS8 G10 VSS8
    B B
    L10 VSS9 A1 L10 VSS9 A1 2 2 2 2 2 2 2 2

    CV565

    CV556

    CV559

    CV558

    CV560

    CV557

    CV563

    CV564
    P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1
    +1.35VGS T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1
    UV5 SIDE VSS12 VSSQ3 VSS12 VSSQ3
    H14 N1 H14 N1
    K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
    VSS14 VSSQ5 U1 VSS14 VSSQ5 U1
    VSSQ6 VSSQ6
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@

    PX@

    H2 H2
    CD@

    CD@

    CD@

    CD@

    CD@

    +1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2


    1 1 1 1 1 1 1 1 VDD1 VSSQ8 VDD1 VSSQ8 UV6 SIDE
    CV505 L1 A3 L1 A3 +1.35VGS
    33P_0402_50V8J G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3
    RF_PX@ L4 VDD3 VSSQ10 E3 L4 VDD3 VSSQ10 E3
    2 2 2 2 2 2 2 2 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
    CV85

    CV86

    CV87

    CV88
    CV552

    CV155

    CV628

    VDD5 VSSQ12 VDD5 VSSQ12

    PX@

    PX@

    PX@

    PX@
    R5 R3 R5 R3

    CD@

    CD@

    CD@

    CD@
    VDD6 VSSQ13 VDD6 VSSQ13

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    C10 U3 C10 U3 1 1 1 1 1 1 1 1
    R10 VDD7 VSSQ14 C4 R10 VDD7 VSSQ14 C4
    D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
    G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
    L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5 2 2 2 2 2 2 2 2

    CV573

    CV572

    CV571

    CV575

    CV574

    CV568

    CV569

    CV570
    +1.35VGS P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10
    UV5 SIDE VDD12 VSSQ19 VDD12 VSSQ19
    G14 M10 G14 M10
    L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
    VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
    VSSQ22 VSSQ22
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@

    PX@

    A12 A12
    CD@

    CD@

    CD@

    CD@

    CD@

    CD@

    VSSQ23 C12 VSSQ23 C12 +1.35VGS


    1 1 1 1 1 1 1 1 VSSQ24 VSSQ24
    E12 E12
    VSSQ25 N12 VSSQ25 N12
    VSSQ26 R12 VSSQ26 R12
    2 2 2 2 2 2 2 2 VSSQ27 VSSQ27

    PX@
    170-BALL U12 170-BALL U12

    CD@
    CV551

    CV533

    CV537

    CV535

    CV538

    CV534

    CV549

    CV550

    VSSQ28 VSSQ28

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    H13 H13 1 1
    SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
    VSSQ30 A14 VSSQ30 A14
    VSSQ31 C14 VSSQ31 C14
    VSSQ32 E14 VSSQ32 E14 2 2

    CV577

    CV576
    VSSQ33 N14 VSSQ33 N14
    A
    +1.35VGS VSSQ34 R14 VSSQ34 R14 A
    UV5 SIDE VSSQ35 VSSQ35
    U14 U14
    VSSQ36 VSSQ36
    H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
    PX@

    PX@

    PX@

    PX@

    PX@

    @ @
    CD@

    CD@

    CD@

    CD@

    CD@
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1 1 1 1 1 1 1 1 1 1

    2 2 2 2 2 2 2 2 2 2 Security Classification LC Future Center Secret Data Title


    CV78

    CV79

    CV80

    CV81

    CV82

    CV83
    CV548

    CV545

    CV546

    CV547

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_VRAM_A


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 21 of 50
    5 4 3 2 1
    5 4 3 2 1

    Upper 32 bits
    MF=1 Mirror MF=0 No Mirror
    DQA1_[31..0] 20

    MAA1_[8..0] 20
    UV7 UV8

    MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

    +1.35VGS A4 DQA1_19 A4 DQA1_7


    EDCA1_2 C2 DQ24 DQ0 A2 DQA1_18 EDCA1_0 C2 DQ24 DQ0 A2 DQA1_4
    20 EDCA1_2 EDC0 EDC3 DQ25 DQ1 DQA1_16 20 EDCA1_0 EDC0 EDC3 DQ25 DQ1 DQA1_6
    C13 B4 C13 B4
    EDCA1_1 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_17 EDCA1_3 R13 EDC1 EDC2 DQ26 DQ2 B2 DQA1_5
    D D
    20 EDCA1_1 EDC2 EDC1 DQ27 DQ3 DQA1_23 20 EDCA1_3 EDC2 EDC1 DQ27 DQ3 DQA1_3
    1

    1 R2 E4 R2 E4
    RV1025 CV528 EDC3 EDC0 DQ28 DQ4 E2 DQA1_21 EDC3 EDC0 DQ28 DQ4 E2 DQA1_2
    2.37K_0402_1% 1U_0402_6.3V6K DQ29 DQ5 F4 DQA1_22 DQ29 DQ5 F4 DQA1_0 +1.35VGS
    @ @ DDBIA1_2 D2 DQ30 DQ6 F2 DQA1_20 DDBIA1_0 D2 DQ30 DQ6 F2 DQA1_1
    2 20 DDBIA1_2 DBI0# DBI3# DQ31 DQ7 20 DDBIA1_0 DBI0# DBI3# DQ31 DQ7
    D13 A11 D13 A11
    +1.35VGS DDBIA1_1 DBI1# DBI2# DQ16 DQ8 +1.35VGS DDBIA1_3 DBI1# DBI2# DQ16 DQ8
    2

    P13 A13 P13 A13


    VREFD2_A1 20 DDBIA1_1 DBI2# DBI1# DQ17 DQ9 20 DDBIA1_3 DBI2# DBI1# DQ17 DQ9
    +1.35VGS P2 B11 +1.35VGS P2 B11
    DBI3# DBI0# DQ18 DQ10 B13 DBI3# DBI0# DQ18 DQ10 B13 CLKA1 60.4_0402_1% 1 PX@ 2 RV1037
    DQ19 DQ11 DQ19 DQ11
    1

    1 CLKA1 J12 E11 CLKA1 J12 E11


    20 CLKA1 CK DQ20 DQ12 CK DQ20 DQ12
    RV1026 CV527 CLKA#1 J11 E13 CLKA#1 J11 E13 CLKA#1 60.4_0402_1% 1 PX@ 2 RV1038
    20 CLKA#1 CK# DQ21 DQ13 CK# DQ21 DQ13
    5.49K_0402_1% 1U_0402_6.3V6K CKEA1 J3 F11 CKEA1 J3 F11
    20 CKEA1 CKE# DQ22 DQ14 CKE# DQ22 DQ14
    @ @ F13 F13
    2 DQ23 DQ15 U11 DQA1_11 DQ23 DQ15 U11 DQA1_30
    DQ8 DQ16 DQ8 DQ16
    2

    MAA1_4 H11 U13 DQA1_13 MAA1_2 H11 U13 DQA1_28


    MAA1_3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_10 MAA1_5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 DQA1_29
    MAA1_2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_12 MAA1_4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 DQA1_31
    MAA1_5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_9 MAA1_3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 DQA1_26
    BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_15 BA3/A3 BA1/A5 DQ12 DQ20 N13 DQA1_27
    DQ13 DQ21 M11 DQA1_8 DQ13 DQ21 M11 DQA1_24
    MAA1_0 K4 DQ14 DQ22 M13 DQA1_14 MAA1_7 K4 DQ14 DQ22 M13 DQA1_25
    MAA1_6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MAA1_1 H5 A8/A7 A10/A0 DQ15 DQ23 U4
    +1.35VGS MAA1_7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MAA1_0 H4 A9/A1 A11/A6 DQ0 DQ24 U2
    MAA1_1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MAA1_6 K5 A10/A0 A8/A7 DQ1 DQ25 T4
    MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MAA1_8 J5 A11/A6 A9/A1 DQ2 DQ26 T2
    A12/RFU/NC DQ3 DQ27 N4 A12/RFU/NC DQ3 DQ27 N4
    DQ4 DQ28 DQ4 DQ28
    1

    1 A5 N2 A5 N2
    RV1028 CV530 U5 VPP/NC1 DQ5 DQ29 M4 U5 VPP/NC1 DQ5 DQ29 M4
    2.37K_0402_1% 1U_0402_6.3V6K VPP/NC2 DQ6 DQ30 M2 VPP/NC2 DQ6 DQ30 M2
    @ @ DQ7 DQ31 DQ7 DQ31
    2 J1 +1.35VGS J1 +1.35VGS
    +1.35VGS MF MF
    2

    J10 J10
    VREFD1_A1 1 PX@ 2 RV1032 J13 SEN B1 1 PX@ 2 RV1035 J13 SEN B1
    120_0402_1% ZQ VDDQ1 D1 120_0402_1% ZQ VDDQ1 D1
    VDDQ2 VDDQ2
    1

    1 F1 F1
    C
    RV1027 CV529 ADBIA1 J4 VDDQ3 M1 ADBIA1 J4 VDDQ3 M1 C
    20 ADBIA1 ABI# VDDQ4 ABI# VDDQ4
    5.49K_0402_1% 1U_0402_6.3V6K CASA#1 G3 P1 RASA#1 G3 P1
    20 CASA#1 RAS# CAS# VDDQ5 CSA1#_0 RAS# CAS# VDDQ5
    @ @ WEA#1 G12 T1 G12 T1
    2 20 WEA#1 CS# WE# VDDQ6 CS# WE# VDDQ6
    RASA#1 L3 G2 CASA#1 L3 G2
    20 RASA#1 CAS# RAS# VDDQ7 CAS# RAS# VDDQ7
    2

    CSA1#_0 L12 L2 WEA#1 L12 L2


    20 CSA1#_0 WE# CS# VDDQ8 WE# CS# VDDQ8
    B3 B3
    VDDQ9 D3 VDDQ9 D3
    VDDQ10 F3 VDDQ10 F3
    WCKA1#_1 D5 VDDQ11 H3 WCKA1#_0 D5 VDDQ11 H3
    20 WCKA1#_1 WCKA1_1 WCK01# WCK23# VDDQ12 WCKA1_0 WCK01# WCK23# VDDQ12
    D4 K3 D4 K3
    20 WCKA1_1 WCK01 WCK23 VDDQ13 WCK01 WCK23 VDDQ13
    M3 M3
    WCKA1#_0 P5 VDDQ14 P3 WCKA1#_1 P5 VDDQ14 P3
    +1.35VGS 20 WCKA1#_0 WCKA1_0 WCK23# WCK01# VDDQ15 WCKA1_1 WCK23# WCK01# VDDQ15 UV8 SIDE
    P4 T3 P4 T3 +1.35VGS
    20 WCKA1_0 WCK23 WCK01 VDDQ16 WCK23 WCK01 VDDQ16
    E5 E5
    VDDQ17 N5 VDDQ17 N5
    VREFD2_A1 A10 VDDQ18 E10 VREFD1_A1 A10 VDDQ18 E10
    VREFD1_A1 U10 VREFD1 VDDQ19 VREFD2_A1 U10 VREFD1 VDDQ19

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    1

    PX@

    PX@
    N10 N10

    CD@

    CD@

    CD@

    CD@

    CD@
    1 VREFC_A1 J14 VREFD2 VDDQ20 VREFC_A1 J14 VREFD2 VDDQ20
    RV1029 CV532 B12 B12 1 1 1 1 1 1 1 1
    2.37K_0402_1% 1U_0402_6.3V6K VREFC VDDQ21 D12 VREFC VDDQ21 D12 CV613
    PX@ @ VDDQ22 F12 VDDQ22 F12 33P_0402_50V8J
    2 VDDQ23 H12 VDDQ23 H12 RF_PX@
    DRAM_RST VDDQ24 DRAM_RST VDDQ24 2 2 2 2 2 2 2 2
    2

    J2 K12 J2 K12

    CV611

    CV603

    CV617

    CV605

    CV616

    CV604

    CV631
    VREFC_A1 20,21 DRAM_RST RESET# VDDQ25 RESET# VDDQ25
    M12 M12
    VDDQ26 P12 VDDQ26 P12
    VDDQ27 VDDQ27
    1

    1 T12 T12
    RV1030 CV531 VDDQ28 G13 VDDQ28 G13
    5.49K_0402_1% 1U_0402_6.3V6K H1 VDDQ29 L13 H1 VDDQ29 L13
    PX@ PX@ K1 VSS1 VDDQ30 B14 K1 VSS1 VDDQ30 B14 +1.35VGS
    2 VSS2 VDDQ31 VSS2 VDDQ31 UV8 SIDE
    B5 D14 B5 D14
    VSS3 VDDQ32 VSS3 VDDQ32
    2

    G5 F14 G5 F14
    L5 VSS4 VDDQ33 M14 L5 VSS4 VDDQ33 M14
    VSS5 VDDQ34 VSS5 VDDQ34

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@

    PX@
    T5 P14 T5 P14

    CD@

    CD@

    CD@

    CD@

    CD@

    CD@
    B10 VSS6 VDDQ35 T14 B10 VSS6 VDDQ35 T14
    VSS7 VDDQ36 VSS7 VDDQ36 1 1 1 1 1 1 1 1
    D10 D10
    G10 VSS8 G10 VSS8
    B B
    L10 VSS9 A1 L10 VSS9 A1
    P10 VSS10 VSSQ1 C1 P10 VSS10 VSSQ1 C1 2 2 2 2 2 2 2 2

    CV614

    CV606

    CV610

    CV608

    CV609

    CV607

    CV612

    CV615
    +1.35VGS T10 VSS11 VSSQ2 E1 T10 VSS11 VSSQ2 E1
    UV7 SIDE VSS12 VSSQ3 VSS12 VSSQ3
    H14 N1 H14 N1
    K14 VSS13 VSSQ4 R1 K14 VSS13 VSSQ4 R1
    VSS14 VSSQ5 U1 VSS14 VSSQ5 U1
    VSSQ6 VSSQ6
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@

    PX@

    H2 H2
    CD@

    CD@

    CD@

    CD@

    CD@

    +1.35VGS G1 VSSQ7 K2 +1.35VGS G1 VSSQ7 K2


    1 1 1 1 1 1 1 1 VDD1 VSSQ8 VDD1 VSSQ8
    CV596 L1 A3 L1 A3
    33P_0402_50V8J G4 VDD2 VSSQ9 C3 G4 VDD2 VSSQ9 C3 +1.35VGS
    VDD3 VSSQ10 VDD3 VSSQ10 UV8 SIDE
    RF_PX@ L4 E3 L4 E3
    2 2 2 2 2 2 2 2 C5 VDD4 VSSQ11 N3 C5 VDD4 VSSQ11 N3
    CV586

    CV579

    CV601

    CV580

    CV602

    CV578

    CV630

    R5 VDD5 VSSQ12 R3 R5 VDD5 VSSQ12 R3


    VDD6 VSSQ13 VDD6 VSSQ13

    PX@

    PX@

    PX@

    PX@
    C10 U3 C10 U3

    CD@

    CD@

    CD@

    CD@
    VDD7 VSSQ14 VDD7 VSSQ14

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K
    R10 C4 R10 C4 1 1 1 1 1 1 1 1
    D11 VDD8 VSSQ15 R4 D11 VDD8 VSSQ15 R4
    G11 VDD9 VSSQ16 F5 G11 VDD9 VSSQ16 F5
    L11 VDD10 VSSQ17 M5 L11 VDD10 VSSQ17 M5
    +1.35VGS P11 VDD11 VSSQ18 F10 P11 VDD11 VSSQ18 F10 2 2 2 2 2 2 2 2
    UV7 SIDE

    CV623

    CV621

    CV622

    CV625

    CV624

    CV618

    CV619

    CV620
    G14 VDD12 VSSQ19 M10 G14 VDD12 VSSQ19 M10
    L14 VDD13 VSSQ20 C11 L14 VDD13 VSSQ20 C11
    VDD14 VSSQ21 R11 VDD14 VSSQ21 R11
    VSSQ22 VSSQ22
    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    PX@

    PX@

    A12 A12
    CD@

    CD@

    CD@

    CD@

    CD@

    CD@

    VSSQ23 C12 VSSQ23 C12


    1 1 1 1 1 1 1 1 VSSQ24 VSSQ24
    E12 E12 +1.35VGS
    VSSQ25 N12 VSSQ25 N12
    VSSQ26 R12 VSSQ26 R12
    2 2 2 2 2 2 2 2 170-BALL VSSQ27 U12 170-BALL VSSQ27 U12
    CV600

    CV581

    CV585

    CV582

    CV584

    CV583

    CV598

    CV599

    VSSQ28 VSSQ28

    PX@
    H13 H13

    CD@

    10U_0603_6.3V6M

    10U_0603_6.3V6M
    SGRAM GDDR5 VSSQ29 K13 SGRAM GDDR5 VSSQ29 K13
    VSSQ30 VSSQ30 1 1
    A14 A14
    VSSQ31 C14 VSSQ31 C14
    VSSQ32 E14 VSSQ32 E14
    VSSQ33 N14 VSSQ33 N14 2 2

    CV627

    CV626
    A
    +1.35VGS VSSQ34 R14 VSSQ34 R14 A
    UV7 SIDE VSSQ35 VSSQ35
    U14 U14
    VSSQ36 VSSQ36
    H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
    PX@

    PX@

    PX@

    PX@

    PX@

    @ @
    CD@

    CD@

    CD@

    CD@

    CD@
    10U_0603_6.3V6M

    10U_0603_6.3V6M

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1U_0402_6.3V6K

    1 1 1 1 1 1 1 1 1 1

    2 2 2 2 2 2 2 2 2 2 Security Classification LC Future Center Secret Data Title


    CV597

    CV595

    CV591

    CV592

    CV590

    CV593

    CV594

    CV587

    CV588

    CV589

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 ATI_EXO-PRO_VRAM_B


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 22 of 50
    5 4 3 2 1
    5 4 3 2 1

    LCD POWER CIRCUIT B+ to +LEDVDD POWER CMOS Camera


    V20B+ +LEDVDD +3VS
    Need Short
    J1 @
    +3VS +LCDVDD_CON 1 2
    U7 2A 80 mil 2A 80 mil 1 2
    2 R22 1
    5 1

    C1106 22P_0402_50V8-J

    4.7U_0805_25V6-K

    0.1U_0201_25V6-K
    0_0805_5% C25 JUMP_43X39
    IN OUT
    1 1 1 C23
    2
    1 1U_0402_6.3V6K GND 1
    C23 0.1u for G HSW panel blink issue LP2301ALT1G_SOT23-3 +3VS_CMOS
    C1
    PCH_ENVDD 4 3 C2
    EN OCB W=40 mils
    4.7U_0603_6.3V6K2 2 2 Q7 3 1

    RFNS@

    D
    D 2 2 D
    W=40mils
    SY6288C20AAC_SOT23-5 1
    CD@ 1 1

    G
    2
    C3
    C5 @ C6 0.1U_0201_6.3V6-K
    PCH_ENVDD 0.1U_0201_6.3V6-K 2
    0.1U_0201_6.3V6-K
    6 PCH_ENVDD 2 2 @

    1
    @ @
    R35
    100K_0402_5% R5 1 2
    35 CMOS_ON#
    100K_0402_5%
    +3VS
    2 2 @ 1
    C14 For EMI C10
    0.01U_0201_6.3V7-K
    1
    Close to R5 2
    0.1U_0201_6.3V6-K

    2
    @
    @
    APU output enable Voh min is 1.8V-0.45V=1.35V R8 R9
    100K_0402_1% 100K_0402_1%

    @ @

    1
    +3VS EDP_AUX
    EDP_AUX#
    2

    2
    R10
    PCH_ENBKL R11 1 @ 2 4.7K_0402_5% R13 R15
    0_0402_5% @ 100K_0402_1% 100K_0402_1%
    1

    C @ @ JEDP1 C

    1
    R12 1 2 0_0402_5% DISPOFF# R19 1 2 0_0402_5% INVT_PWM 1
    35 BKOFF# 6 PCH_EDP_PWM +LEDVDD 1
    @ @ 2
    3 2
    3

    1
    R14 1 2 0_0402_5% ENBKL 4
    6 PCH_ENBKL ENBKL 35 APU_EDP_TX0+ 1 2 0.1U_0201_6.3V6-K EDP_TX0+ 5 4
    @ can cost down R20 for CZ R20
    6 APU_EDP_TX0+ APU_EDP_TX0-
    C19
    EDP_TX0- 5
    1

    100K_0402_5% C16 1 2 0.1U_0201_6.3V6-K 6


    6 APU_EDP_TX0- 7 6
    R16
    100K_0402_5% APU_EDP_TX1+ C17 1 2 0.1U_0201_6.3V6-K EDP_TX1+ 8 7
    6 APU_EDP_TX1+ 8

    2
    APU_EDP_TX1- C18 1 2 0.1U_0201_6.3V6-K EDP_TX1- 9
    6 APU_EDP_TX1- 10 9
    10
    2

    APU_EDP_AUX C20 1 2 0.1U_0201_6.3V6-K EDP_AUX 11


    6 APU_EDP_AUX APU_EDP_AUX# C21 EDP_AUX# 11
    1 2 0.1U_0201_6.3V6-K 12
    6 APU_EDP_AUX# 13 12
    DISPOFF# 14 13
    15 14
    INVT_PWM 16 15
    17 16
    +3VS 18 17
    19 18
    Touch Screen R21 1 @
    0_0402_5%
    2 6 APU_EDP_HPD
    20
    21
    19
    20
    1 +LCDVDD_CON 21
    W=60mils 22
    C22 23 22
    +3VS 23
    680P_0402_50V7K 24
    2 32 DMIC_DATA 24
    @ 32 DMIC_CLK 25
    26 25
    27 26
    R182 1 @ 2 0_0402_5% USB20_P5_R 28 27
    8 USB20_P5 2 0_0402_5% USB20_N5_R 28
    R183 1 @ 29
    B 8 USB20_N5 30 29 B
    +3VS_CMOS 30
    1 31
    32 G1
    C24 W=40mils G2
    .047U_0201_6.3V6K
    Remove Touch screen for 320 AST

    EMC@
    DRAPH_FC5AF301-3181H
    2
    ME@

    L12 EMC_NS@
    USB20_N5 1 2 USB20_N5_R
    1 2

    USB20_P5 4 3 USB20_P5_R
    4 3
    EXC24CH900U_4P
    DMIC_CLK DISPOFF# INVT_PWM

    C11

    100P_0402_50V8J

    C12

    C13
    EMC@
    1 1 1

    EMC_NS@

    EMC_NS@
    470P_0201_50V7-K

    470P_0201_50V7-K
    2 2 2

    A A
    EMC

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 eDP/CMOS/Touch screen


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 23 of 50


    5 4 3 2 1
    5 4 3 2 1

    D3
    HDMI_DET 1 1 HDMI_DET
    10 9
    L2 EMC@
    HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2 EMC_NS@ HDMIDAT_R 2 2 9 8 HDMIDAT_R
    1 2 C26 3.3P_0201_50V8-C
    HDMICLK_R 4 4 7 7 HDMICLK_R
    HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 EMC_NS@ +3VS
    4 3 +5VS_HDMI 5 5 +5VS_HDMI
    C27 3.3P_0201_50V8-C 6 6
    EXC24CH900U_4P
    D 3 3 D
    L3 EMC@
    HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 EMC_NS@ 8
    1 2

    5
    C28 3.3P_0201_50V8-C

    G
    Q1B
    HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@ AZ1045-04F_DFN2510P10E-10-9
    4 3 C29 3.3P_0201_50V8-C
    APU_DDC_CLK HDMICLK_R EMC_NS@
    EXC24CH900U_4P 4 3

    S
    6 APU_DDC_CLK

    D
    EMC
    L4 EMC@ L2N7002KDW1T1G_SOT363-6
    HDMI_TX1-_C HDMI_TX1-_CON 1

    2
    1 2 2 EMC_NS@

    G
    1 2 C30 3.3P_0201_50V8-C Q1A
    HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 EMC_NS@
    4 3 C31 3.3P_0201_50V8-C APU_DDC_DATA 1 6 HDMIDAT_R

    S
    6 APU_DDC_DATA

    D
    EXC24CH900U_4P
    L2N7002KDW1T1G_SOT363-6
    L5 EMC@
    HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@
    1 2 C32 3.3P_0201_50V8-C +5VS_HDMI
    +5VS +5VS_HDMI_F +5VS_HDMI
    HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@ D5
    4 3

    2
    C33 3.3P_0201_50V8-C 2 F1
    EXC24CH900U_4P D4 1 1 2
    3
    +3VS
    EMC RB491D_SOT23-3 0.5A_6V_1206L050YRHF
    @ LBAT54SWT1G_SOT323-3 @

    1
    1 3 Q22

    S
    1
    LP2301ALT1G_SOT23-3 2 1
    Follow Zx05 and beema C34
    Q43 CC1279 @

    G
    2

    4
    3
    C LMBT3904WT1G_SOT323-3 B 2 R202 1 2 150K_0402_5% 10U_0402_6.3V6M 0.1U_0201_6.3V6-K C
    1 2 RP2
    12,37 SUSP

    1
    2.2K_0404_4P2R_5%
    HDMI_CLK-_C 1 2 499_0402_1%

    E
    R29 R257
    6 APU_HDMI_HPD
    100K_0402_5%

    1
    2
    HDMI_CLK+_C HDMI_DET

    1
    1 2 499_0402_1%

    3
    R30
    R260

    2
    HDMI_TX0-_C R31 1 2 499_0402_1% 100K_0402_5%
    +5VS_HDMI
    HDMI_TX0+_C R32 1 2 499_0402_1% JHDMI1 ME@

    2
    HDMI_TX1-_C R33 1 2 499_0402_1% 18 15 HDMICLK_R
    +5V_Power SCL 16 HDMIDAT_R
    HDMI_TX1+_C R34 1 2 499_0402_1% SDA
    C38 1 2 0.1U_0201_6.3V6-K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
    HDMI_TX2-_C 1 2 499_0402_1% 6 APU_HDMI_TX0+ 1 2 HDMI_TX0-_C HDMI_TX0-_CON TMDS_Data0+
    R37 C37 0.1U_0201_6.3V6-K R45 2 @ 1 0_0402_5% 9 13
    6 APU_HDMI_TX0- 1 2 HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
    C40 0.1U_0201_6.3V6-K R48 2 @ 1 0_0402_5% 4 17
    HDMI_TX2+_C 1 2 499_0402_1% 6 APU_HDMI_TX1+ 1 2 HDMI_TX1-_C HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
    R38 C39 0.1U_0201_6.3V6-K R47 2 @ 1 0_0402_5% 6 19
    6 APU_HDMI_TX1- 1 2 HDMI_TX2+_C HDMI_TX2+_CON TMDS_Data1- Hot_Plug_Detect
    C42 0.1U_0201_6.3V6-K R50 2 @ 1 0_0402_5% 1
    6 APU_HDMI_TX2+ 1 2 HDMI_TX2-_C HDMI_TX2-_CON TMDS_Data2+
    C41 0.1U_0201_6.3V6-K R49 2 @ 1 0_0402_5% 3
    6 APU_HDMI_TX2- TMDS_Data2-
    1

    Q13 D 8 14
    2 5 TMDS_Data0_Shield Utility
    +3VS TMDS_Data1_Shield
    G 2
    TMDS_Data2_Shield
    L2N7002KWT1G_SOT323-3 S 20
    GND1
    3

    11 21
    R42 1 @ 2 C36 1 2 0.1U_0201_6.3V6-K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
    6 APU_HDMI_CLK+ 1 2 0.1U_0201_6.3V6-K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 TMDS_Clock+ GND3 23
    C35
    6 APU_HDMI_CLK- TMDS_Clock- GND4
    100K_0402_5%

    B ALLTO_C128S9-K1935-L B

    D6 D7
    HDMI_CLK+_CON 1 1 HDMI_CLK+_CON HDMI_TX1-_CON HDMI_TX1-_CON
    10 9 1 1 10 9
    HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

    HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

    HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON

    3 3 3 3

    8 8

    AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
    EMC_NS@ EMC_NS@

    EMC

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 HDMI_CONN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 24 of 50
    5 4 3 2 1
    A B C D E

    +USB_VCCA

    C55 1 2

    +
    220U_6.3V_M

    C1117 1 2
    @ 47U_0805_6.3V6-M
    LEFT SIDE USB3.0 PORT x2 C125 1 2
    @ 1U_0402_10V6K
    +5VALW +USB_VCCA C127 1 2
    U2 @ 1U_0402_10V6K
    5 1
    1 IN OUT JUSB1 ME@
    1
    1
    C128 2
    1U_0402_6.3V6K GND USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
    4 3 USB_OC1# 8 USB30_TX_P1 1 StdA_SSTX+
    2 35 USB_ON# ENB OCB USB_OC1# 7 USB30_TX_N1 USB30_TX_C_N1 USB30_TX_R_N1 VBUS
    C124 1 2 0.1u_0201_10V6K R96 1 @ 2 0_0402_5% 8
    8 USB30_TX_N1 USB20_P2 USB20_P2_R StdA_SSTX-
    SY6288D20AAC_SOT23-5 1 R97 1 @ 2 0_0402_5% 3
    8 USB20_P2 7 D+
    C2078
    1000P_0201_50V7-K USB20_N2 R93 1 @ 2 0_0402_5% USB20_N2_R 2 GND_DRAIN 10
    8 USB20_N2 USB30_RX_P1 1 2 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11
    Low Active 2A EMC_NS@ R94 @
    2 8 USB30_RX_P1 StdA_SSRX+ GND_3
    4 12
    USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
    8 USB30_RX_N1 StdA_SSRX- GND_5

    ALLTO_C190AG-10939-L

    09/05 Update USBConn. P/N DC021609011 wei

    L13 EMC@
    USB30_RX_N1 1 2 USB30_RX_R_N1
    1 2

    USB30_RX_P1 4 3 USB30_RX_R_P1
    4 3
    EXC24CH900U_4P USB20_P2_R
    +USB_VCCA
    USB20_N2_R D12 EMC@
    L16 EMC@ USB30_RX_R_N1 9 1USB30_RX_R_N1
    10 1
    USB30_TX_C_N1 1 2 USB30_TX_R_N1

    AZ5725-01F.R7GR_DFN1006P2X2
    1 2 USB30_RX_R_P1 8 2 USB30_RX_R_P1

    2
    D11 9 2
    D13

    1
    USB30_TX_C_P1 4 3 USB30_TX_R_P1 AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 4USB30_TX_R_N1
    7 4
    4 3 EMC@
    EXC24CH900U_4P USB30_TX_R_P1 6 5 USB30_TX_R_P1
    6 5

    2
    3
    2 EMC@ 2

    2
    L8 EMC@ 8
    USB20_P2 1 2 USB20_P2_R
    1 2 AZ1045-04F_DFN2510P10E-10-9
    USB20_N2 USB20_N2_R

    1
    4 3
    4 3
    EXC24CH900U_4P
    EMC
    EMC

    +USB_VCCA

    C2060 1 2
    @ 1U_0402_10V6K

    C2059 1 2
    @ 1U_0402_10V6K

    JUSB3
    1
    USB20_N7 R942 1 @ 2 0_0402_5% USB20_N7_R 2 VBUS
    8 USB20_N7 USB20_P7 USB20_P7_R D-
    R3103 1 @ 2 0_0402_5% 3
    8 USB20_P7 D+
    4 5
    GND GND1 6
    GND2 7
    3 GND3 8 3
    GND4
    ALLTO_C147L3-40439-L
    ME@

    L17 EMC@ 09/05 Update USBConn. P/N DC021609011 wei


    USB20_P7 1 2 USB20_P7_R
    1 2

    USB20_N7 4 3 USB20_N7_R
    4 3
    EXC24CH900U_4P
    FOR ESD Close to Connector
    USB20_P7_R +USB_VCCA

    USB20_N7_R
    3

    D43

    AZ5725-01F.R7GR_DFN1006P2X2
    AZC199-02S.R7G_SOT23-3

    1
    EMC@
    D34

    1
    EMC_NS@
    2
    2
    1

    4 4

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 USB3.0 PORT (LEFT)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 25 of 50


    A B C D E
    5 4 3 2 1

    D D

    C C

    Remove USB Type-C follow OD

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 3D Camera


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 26 of 50
    5 4 3 2 1
    5 4 3 2 1

    +3VALW +3VALW +APU_CORE

    D D
    1 1 1
    CS33 CS34 CS30
    0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
    2 2 2

    CS36

    1 2
    +3VS +3VALW
    0.1U_0201_6.3V6-K

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 DP to CRT Convert(IT6515FN)
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 27 of 50
    5 4 3 2 1
    5 4 3 2 1

    +3VALW TO +3VALW_LAN
    +3VALW_LAN rising t i me ( 10 %~90 %):
    +3VALW +3VALW_LAN
    0.5ms＜s pec＜ 10 0m s +3VALW_LAN +LAN_VDDREG
    Need short
    @
    JL1 1 2 @ width : 40 mils RL1 1 2 0_0603_5%
    1 2
    JUMP_43X79
    D 1 1 D
    +3VALW LP2301ALT1G_SOT23-3 CL1 CL2

    4.7U_0402_6.3V6M

    4.7U_0402_6.3V6M

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    1 1 1 1 4.7U_0402_6.3V6M 0.1U_0201_6.3V6-K
    Q14 3 1 @ CL4 CL5 CL6 CL7

    D
    2 2

    0.01U_0201_10V6K
    SIT1CD@ SIT1CD@
    RL2 1 1
    100K_0402_5% CL8 CL9 2 2 2 2

    G
    2
    @ 0.1U_0201_6.3V6-K
    @ @

    2
    2 2
    SIT1CD@ SIT1CD@
    RL3 1 @ 2
    35 LAN_PWR_ON#
    47K_0402_5%
    Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

    +3VALW_LAN +3VS

    2
    +3VALW_LAN

    2
    RL4

    G
    10K_0402_5% QL1
    2

    @
    RL5

    1
    10K_0402_5% LAN_CLKREQ#_R 1 3 @
    LAN_CLKREQ# 7
    @

    S
    2N7002KW_SOT323-3
    UL1
    1

    RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R


    7,31,35 PCIE_WAKE#
    C
    31,35 LAN_WAKE# RL6 1 @ 2 0_0402_5% RL18 1 2 C
    33
    32 +3VALW_LAN GND 16 CLK_PCIE_LAN# 0_0402_5%
    AVDD33 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 8
    RL8 1 2 31 RSET 15
    +LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N2 CLK_PCIE_LAN 8
    2.49K_0402_1% 30 14 APU CLKREQ all both 3VS power plane
    29 LAN_XTALO AVDD10_1 HSIN 13 PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 4
    28 LAN_XTALI CKXTAL2 HSIP 12 LAN_CLKREQ#_R PCIE_PTX_C_DRX_P2 4
    +3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
    LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 NC_4 10 LAN_MDI3-
    GPO NC_3 LAN_MDI3+ LAN_MDI3- 29
    0_0402_5% TL4 @ 1 25 9
    +LAN_REGOUT LED1 NC_2 +LAN_VDD10 LAN_MDI3+ 29
    1

    24 8
    RL9 +LAN_VDDREG 23 NC_6 AVDD10_0 7 LAN_MDI2-
    +LAN_VDD10 DVDD33 NC_1 LAN_MDI2+ LAN_MDI2- 29
    1K_0402_1% 22 6
    PCIE_WAKE#_R 21 NC_5 NC_0 5 LAN_MDI1- LAN_MDI2+ 29
    20 LANW AKEB MDIN1 4 LAN_MDI1+ LAN_MDI1- 29
    ISOLATE#
    ISOLATEB MDIP1 LAN_MDI1+ 29
    2

    PLT_RST# 19 3 +LAN_VDD10
    7,15,30,31,35 PLT_RST# PCIE_PRX_C_DTX_N2 PERSTB NC_7 LAN_MDI0-
    4 PCIE_PRX_DTX_N2 CL10 2 1 0.1U_0201_6.3V6-K 18 2
    LAN_PWR_ON# HSON MDIN0 LAN_MDI0- 29
    ISOLATE# RL10 1 @ 2 CL11 2 1 0.1U_0201_6.3V6-K PCIE_PRX_C_DTX_P2 17 1 LAN_MDI0+
    4 PCIE_PRX_DTX_P2 HSOP MDIP0 LAN_MDI0+ 29
    0_0402_5% CL10 close to Pin18
    1

    RL11 CL11 close to Pin17


    15K_0402_5% RTL8106E-CG_QFN32_4X4
    @ 8106E@
    2

    B B

    For RTL8111GUL/ RTL8106EUL (SWR mode)


    LAN_XTALI
    For RTL8111H (LDO mode) RL19 stuf f
    YL1 LAN_XTALO 8107E@ +LAN_VDD10
    RL20 1 2 0_0805_5%
    1 4
    OSC1 GND2
    2 3 +LAN_REGOUT LL1 1 2
    GND1 OSC2 2.2UH_NLC252018T-2R2J-N_5%
    1 1 @ 1 1 1 1 1 1 1 1
    Layout Note: LL1 must be CL15 CL16 CL17 CL18 CL19 CL20 CL22
    CL12 25MHZ_10PF_7V25000014 CL13 4.7U_0603_6.3V6K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K CL21 0.1U_0201_6.3V6-K
    10P_0402_50V8J 12P_0402_50V8-J within 200mil to Pin24, 1U_0402_6.3V6K @
    2 2 CL15,CL16 must be within 2 2 2 2 2 2 2 @ 2
    @ @
    200mil to LL1
    +LAN_REGOUT: Width =60mil
    Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
    follow G CarrizoL 10pf

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 LAN_RTL8111GUL


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320ABR 0.2

    Date: Saturday, February 04, 2017 Sheet 28 of 50


    5 4 3 2 1
    5 4 3 2 1

    DL1/DL2
    1'S PN:SC300003M00

    D TL1 D
    24 1 MCT
    MCT1 TCT1
    DL1 LAN_MDI0+ 23 2 LAN_MDO0+
    LAN_MDI2+ 1 10 LAN_MDI2+ 28 LAN_MDI0+ MX1+ TD1+
    LINE1IN LINE1OUT LAN_MDI0- 22 3 LAN_MDO0-
    LAN_MDI2- LAN_MDI2- 28 LAN_MDI0- MX1- TD1-

    1
    2 9
    LINE2IN LINE2OUT 21 4 MCT RL17
    3 8 MCT2 TCT2 20_0603_5%
    GND1 GND2 LAN_MDI1+ LAN_MDO1+

    1
    20 5
    LAN_MDI3+ LAN_MDI3+ 28 LAN_MDI1+ MX2+ TD2+
    4 7 DL3

    1
    LINE3IN LINE3OUT

    2
    LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
    LAN_MDI3- 5 6 LAN_MDI3- 28 LAN_MDI1- MX2- TD2-
    LINE4IN LINE4OUT 18 7 MCT

    2
    11 13 MCT3 TCT3
    GND3 GND5

    2
    LAN_MDI2+ 17 8 LAN_MDO2+
    12 28 LAN_MDI2+ MX3+ TD3+ EMC@
    GND4 LAN_MDI2- 16 9 LAN_MDO2-
    28 LAN_MDI2- MX3- TD3-
    AZ3133-08F.R7G_DFN3020P10E10
    EMC_NS@ 15 10 MCT
    MCT4 TCT4
    1 1
    LAN_MDI3+ 14 11 LAN_MDO3+ CL25
    28 LAN_MDI3+ MX4+ TD4+ CL32 1000P_1206_2KV7-K
    LAN_MDI3- 13 12 LAN_MDO3- 0.022U_0603_50V7K EMC@
    C 28 LAN_MDI3- MX4- TD4- 2 2 C
    DL2 1
    LAN_MDI1- LAN_MDI1- EMC@
    1 10 CL24
    LINE1IN LINE1OUT 0.01U_0201_25V6-K MS241-A218-1H
    LAN_MDI1+ 2 9 LAN_MDI1+ EMC@
    LINE2IN LINE2OUT 2
    3 8
    GND1 GND2
    LAN_MDI0- LAN_MDI0-
    EMC
    4 7
    LINE3IN LINE3OUT CHASSIS1_GND
    LAN_MDI0+ 5 6 LAN_MDI0+
    LINE4IN LINE4OUT
    11 13
    GND3 GND5
    12
    GND4
    AZ3133-08F.R7G_DFN3020P10E10
    EMC_NS@
    JRJ1 ME@
    12
    GND_4
    Place Close to TL1
    11
    GND_3
    EMC
    10
    LAN_MDO0+ 1 GND_2
    B B
    TX_DA+ 9
    LAN_MDO0- 2 GND_1
    TX_DA-
    LAN_MDO1+ 3
    @ RX_DB+ CHASSIS1_GND
    RL14 1 2 0_0603_5% LAN_MDO2+ 4
    @ BI_DC+
    RL15 1 2 0_0603_5% LAN_MDO2- 5
    @ BI_DC-
    RL16 1 2 0_0603_5% LAN_MDO1- 6
    RX_DB-
    LAN_MDO3+ 7
    BI_DD+
    LAN_MDO3- 8
    CHASSIS1_GND BI_DD-
    Reserve for EMI go rural solution
    ALLTO_C10235-10839-L

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 LAN_Transformer
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    320ABR 0.2

    Date: Saturday, February 04, 2017 Sheet 29 of 50


    5 4 3 2 1
    5 4 3 2 1

    R175 1 @ 2 0_0402_5% REMOTE1+

    Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+


    Near GPU&VRAM REMOTE2+
    Near CPU core
    REMOTE+_R

    1
    1
    1
    C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- Q16

    C
    1 1
    2200P_0402_50V7K C45 Q15 C46 2 B LMBT3904WT1G_SOT323-3

    C
    100P_0402_50V8J 2 B LMBT3904WT1G_SOT323-3 100P_0402_50V8J
    2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- @ @
    @ 2 2

    E
    @
    @

    E
    REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

    3
    D D

    3
    REMOTE2-
    Trace width/space:10/10 mil REMOTE1-
    Trace length:<8"

    SMSC thermal sensor


    placed near DIMM +3VALW
    +3VALW
    Near CPU
    +3VS
    U1
    EC_SMB_CK3

    1
    1 8
    VDD SCL EC_SMB_CK3 6,16,35
    R17 R25
    REMOTE+_R 2 7 EC_SMB_DA3 13.7K_0402_1% 13.7K_0402_1%
    1 D+ SDA EC_SMB_DA3 6,16,35
    C47 REMOTE-_R 3 6
    D- ALERT#

    2
    NTC_V1 NTC_V2
    0.1U_0201_6.3V6-K
    2 @ +3VS R51 2 @ 1 4 5
    T_CRIT# GND

    1
    10K_0402_5% @
    NCT7718W_MSOP8 R1 R3
    Address 1001_101xb 100K_0402_1%_TSM0B104F4251RZ
    PX@
    100K_0402_1%_TSM0B104F4251RZ

    2
    2

    2
    R184 R185 R191 R192
    +5VLP +5VLP 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
    C +5VLP PX@ C
    @ @

    1
    HW thermal sensor

    2
    1 R252 R253
    21.5K_0402_1% 21.5K_0402_1% EC_AGND EC_AGND
    C4 @ @
    0.1U_0201_6.3V6-K

    1
    2 @ @
    U4
    1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
    VCC TMSNS1 NTC_V1 35 +3VS +3VS_TPM
    2 7 PHYST1 R6 1 @ 2 10K_0402_5%
    GND RHYST1 RTPM1 1 TPM@ 2 0_0603_5% 1A
    3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
    46 EC_ON_R OT1 TMSNS2 NTC_V2 35 1 1
    1 CTPM3
    4 5 PHYST2 R7 1 @ 2 10K_0402_5% CTPM4 CTPM1 0.1u_0201_10V6K
    OT2 RHYST2 0.1u_0201_10V6K 10U_0603_6.3V6M TPM@
    G718TM1U_SOT23-8 TPM@ 2 TPM@ 2
    2
    over temperature threshold:
    RSET=3*RTMH TPM
    92+/-30C
    Hysteresis temperature threshold. UTPM1 TPM@
    +3VS_TPM

    RHYST=(RSET*RTML)/(3*RTML-RSET) 1
    NC_1 VDD3
    24
    2 10
    56+/-30C 3 NC_2 VDD1
    Reserve for Nationz TPM
    B
    RTPM12 1 TPM@ 2 7 NC_3 28 RTPM2 1 TPM@ 2 4.7K_0402_5% B
    0_0402_5% PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
    SERIRQ LPC_AD0_TPM SERIRQ 8,35
    6 26 RTPM6 1 TPM@ 2 0_0402_5%
    NC_4 LAD0 LPC_AD1_TPM LPC_AD0 8,35
    Reserve for Nationz TPM 9 23 RTPM7 1 TPM@ 2 0_0402_5%
    NC_7 LAD1 LPC_FRAME#_TPM LPC_AD1 8,35
    22 RTPM8 1 TPM@ 2 0_0402_5%
    Nationz TPM Nuvoton TPM 4
    GND_1
    LFRAME#
    LAD2
    20 LPC_AD2_TPM RTPM9 1 TPM@ 2 0_0402_5%
    LPC_FRAME# 8,11,35
    LPC_AD2 8,35
    11 17 LPC_AD3_TPM RTPM10 1 TPM@ 2 0_0402_5%
    +3VALW GND_2 LAD3 LPC_AD3 8,35
    18
    GND_3 25 +3VS_TPM
    1 TPM@ 2 5 GND_4 21
    RTPM2 Stuff NC RTPM11
    NC_5 LCLK TPM_CLK 8
    0_0603_5% 8 19
    12 NC_6 VDD2 15 TPM_CLKRUN# RTPM13 1 @ 2
    NC_8 CLK_RUN# LPC_CLKRUN# 8
    Add for Nuvoton TPM 13 0_0402_5%
    14 NC_9 16
    NC_10 LRESET# PLT_RST# 7,15,28,31,35
    RTPM12 Stuff NC Reserve for Nuvoton TPM

    1
    Z32H320TC-LPC-T28-LT1_TSSOP28 RTPM4
    0_0402_5%
    TPM@
    RTPM11 NC Stuff

    2
    A A
    +5VS
    JFAN1
    R52 1 @ 2 0_0603_5% +5VS_FAN 1
    2 1
    35 EC_FAN_SPEED 2
    1 1 35 EC_FAN_PWM 3
    C50 4 3
    4 Security Classification LC Future Center Secret Data Title
    C49 5
    0.1u_0201_10V6K 6 GND1
    10U_0805_10V6K
    2 GND2 Issued Date 2017/02/04 Deciphered Date 2017/02/04 Thermal sensor/FAN CONN/TPM
    @ 2
    ACES_85205-04001
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    ME@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 30 of 50
    5 4 3 2 1
    A B C D E

    Mini-Express Card(WLAN/WiMAX)
    +3VS_W LAN

    JW LAN1 ME@
    1 1 2 1
    3 GND1 3.3VAUX1 4
    8 USB20_P4 USB_D+ 3.3VAUX2
    5 6 1 @ T2
    8 USB20_N4 USB_D- LED1#
    7 8
    9 GND2 PCM_CLK/I2S_SCK 10
    11 SDIO_CLK PCM_SYNC/I2S_WS 12
    13 SDIO_CMD PCM_IN/I2S_SD_IN 14
    15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ T3
    17 SDIO_DATA1 LED#2 18
    19 SDIO_DATA2 GND11 20
    21 SDIO_DATA3 UART_WAKE# 22
    23 SDIO_WAKE# UART_RXD
    SDIO_RESET#

    KEY E
    25 PIN24~PIN31 NC PIN 24
    27 26
    29 28
    31 30

    33 32
    35 GND3 UART_TXD 34
    4 PCIE_PTX_C_DRX_P1 PETP0 UART_CTS
    37 36
    4 PCIE_PTX_C_DRX_N1 PETN0 UART_RTS EC_TX_RSVD
    39 38 R62 1 @ 2 0_0402_5%
    41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
    4 PCIE_PRX_DTX_P1 PERP0 VENDOR_DEFINED2
    43 42
    4 PCIE_PRX_DTX_N1 PERN0 VENDOR_DEFINED3
    45 44 R88 1 2 0_0402_5%
    GND5 COEX3 EC_RX 35
    47 46 @
    8 CLK_PCIE_W LAN REFCLKP0 COEX2
    49 48
    8 CLK_PCIE_W LAN# REFCLKN0 COEX1 SUSCLK_R
    51 50 R55 1 2 0_0402_5%
    W LAN_CLKREQ_Q# GND6 SUSCLK SUSCLK 7,11
    2 53 52 @ 2
    CLKREQ0# PERST0# BT_OFF# PLT_RST# 7,15,28,30,35
    R4686 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
    7,28,35 PCIE_W AKE# PEWAKE0# W_DISABLE2# W LAN_OFF# PCH_BT_OFF# 7
    57 56 R56 1 2 0_0402_5%
    GND7 W_DISABLE1# PCH_W LAN_OFF# 7
    R57 1 @ 2 0_0402_5% @
    28,35 LAN_W AKE#
    59 58 APU_SMB_DATA_R R58 1 @ 2 0_0402_5%
    RSRVD/PETP1 I2C_DATA APU_SMB_CLK_R APU_SMB_DATA 7,12
    61 60 R59 1 @ 2 0_0402_5%
    RSRVD/PETN1 I2C_CLK APU_SMB_CLK 7,12
    63 62
    65 GND8 ALERT# 64 EC_TX_R R89 1 2 0_0402_5%
    RSRVD/PERP1 RSRVD EC_TX 35
    67 66 @
    69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_W LAN
    GND9 UIM_POWER_SNK/CLKREQ1#

    1
    71 70
    73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 R186
    75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5%
    GND10 3.3VAUX4
    77 76
    GND15 GND14

    2
    ARGOS_NASE0-S6701-TS40

    3 3

    +3VS Need short +3VS_W LAN


    R61 1 2 0_0402_5% W LAN_CLKREQ_Q# J2 @
    7 W LAN_CLKREQ#
    @ 1 2
    1 2
    JUMP_43X79

    If support AOAC, NC R61; Not support AOAC, delete AOAC power circuit 1015
    if not support AOAC, stuff R61.

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 NGFF WLAN
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 31 of 50
    A B C D E
    5 4 3 2 1

    +VAUDIO +5VS +5VA

    +1.8VS RA7 1 2 0_0603_5%

    DVDD_IO RA213 1 2 0_0402_5%


    2 2
    +3VS

    0.1U_0201_6.3V6-K

    1U_0402_6.3V6K
    CA42 CA20
    +VAUDIO
    RA216 1 @ 2 0_0402_5% U24 1 1
    DMIC_DATA
    1 RA19 1 DMIC_DATA_R
    2 0_0402_5% 30
    23 DMIC_DATA DMIC_CLK DMIC_CLK_R HD-GPIO0/DMIC-DATA CR-GPIO SD_CD#
    2 RA18 1 2 0_0402_5% 31
    D 23 DMIC_CLK HDA_SDOUT_AUDIO HD-GPIO1/DMIC-CLK CR-SD-CD SD_WP SD_CD# 33 D
    RA214 1 2 0_0402_5% 3 32
    7 HDA_SDOUT_AUDIO HDA_BITCLK_AUDIO 4 HD-SDATA-OUT CR-SD-WP 33 SD_D1_R SD_WP 33
    7 HDA_BITCLK_AUDIO HD-BCLK CR-SD-DAT[1] SD_D0_R SD_D1_R 33
    2.2U_0402_6.3V6M 1 2 CA1 5 34
    1 RA38 2 2.2K_0402_5% HDA_SDIN0 SDATA_IN HD-LDO3-CAP CR-SD-DAT[0] SD_CLK_R SD_D0_R 33
    MICBIASB 33_0402_5% 1 2 RA16 6 35
    7 HDA_SDIN0 HD-SDATA-IN CR-SD-CLK SD_CLK_R 33
    2 1 RA37 2 2.2K_0402_5% DVDD_IO 7 36 +5VA
    HDA_SYNC_AUDIO 8 HD-DVDD-IO HD-AVDD1 37 LDO1_CAP CA43
    1 2 2.2U_0402_6.3V6M CA48 1 2 1U_0402_6.3V6K
    7 HDA_SYNC_AUDIO PC_BEEP HD-SYNC HD-LDO1-CAP
    CA2 +3VS 100K_0402_1% 1 RA205 2 9 38 2
    CA44 1 1U_0402_6.3V6K
    PLUG_IN 200K_0402_1% 2 RA204 1 JSENSE 10 HD-PCBEEP HD-VREF 39 MICBIASB
    0.1U_0201_6.3V6-K HD-JD1(HP/LINE1) HD-MIC2-VREFO
    Close to1 Pin7 RING2_CONN 11 40 LINE1_VREF_L +1.8VS
    RING3_CONN 12 HD-MIC2-L(RING) HD-LINE1-VREFO-L 41 HPOUT_L
    VDD_STB 13 HD-MIC2-R(SLEEVE) HD-HPOUT-L 42 HPOUT_R
    2.2U_0402_6.3V6M 1 2 CA41 14 HD-3V5V-STB HD-HPOUT-R 43 1U_0402_6.3V6K 2 1 CA47 +1.8VS
    LINE1_R 15 HD-MIC2-CAP HD-CPVEE 44
    LINE1_L 16 HD-LINE1-R HD-CBN 45 4.7U_0603_6.3V6K 2 1 CA4
    17 HD-LINE1-L HD-CPVDD 46
    18 HD-LINE2-R HD-CBP 47 10U_0402_6.3V6M 1 2 CC167 @
    SD_CMD_R 19 HD-LINE2-L HD-LDO2-CAP 48
    33 SD_CMD_R SD_D3_R CR-SD-CMD HD-AVDD2
    20 49 +5VD
    33 SD_D3_R SD_D2_R 21 CR-SD-DAT[3] HD-PVDD1 50 SPK_L+
    33 SD_D2_R CR-SD-DAT[2] HD-SPKOUT-LP SPK_L-
    DA1 1U_0402_6.3V6K 1 2 CW1 22 51 2
    2 23 CR-SDREG HD-SPKOUT-LN 52 SPK_R- +3VS
    35 BEEP# CR-TEST1 HD-SPKOUT-RN
    1PC_BEEP1 1 @ 2 CA40 1 2 PC_BEEP 1U_0402_6.3V6K 1 2 CW2 24 53 SPK_R+ CC257
    3 RA211 0_0402_5% 0.1U_0201_6.3V6-K 6.2K_0402_1% 1 2 RW11 RREF 25 CR-V18-CAP HD-SPKOUT-RP 54 +5VD
    7 PCH_BEEP CR-RREF HD-PVDD2 10U_0402_6.3V6M
    USB20_N3 2 0_0402_5%USB20_N3_R 26 SPKR_MUTE# 1
    1

    RW12 1 55
    8 USB20_N3 USB20_P3 CR-DM HD-PDB
    LBAT54CWT1G_SOT323-3 RA14 RW13 1 2 0_0402_5%USB20_P3_R 27 56
    8 USB20_P3 CR-DP HD-DVDD
    10K_0402_5% 28
    +3VS_CARD CR-3V3-IN
    29
    CARD_3V3 CR-SD-3V3 57 2 2
    GNDPAD
    2

    1 1

    0.1U_0201_6.3V6-K

    1U_0402_6.3V6K
    CW18 CW19 RTS5199-CG_QFN56_7X7 CA180 CA179
    4.7U_0402_6.3V6M 0.1u_0201_10V6K
    1 1
    DA4 2 2
    EC_MUTE# 1 2 @ SPKR_MUTE#
    35 EC_MUTE#
    1

    LRB751V-40T1G_SOD323-2
    RA35 1 @ 2 0_0402_5% RA43
    C 10K_0402_5% C
    +5VS +5VD
    2

    EMC_NS@
    LINE1_L CA45 2 1 1U_0402_6.3V6K LA25 1 2 BLM15PD600SN1D_2P
    LW2
    USB20_N3 1 2 USB20_N3_R LINE1_VREF_L RA411 2 4.7K_0402_5% RA10 1EMC@ 2 0_0603_5%
    +3VL 1 2
    RA203 1 2 0_0402_5% VDD_STB HPOUT_L RA21 1 2 51_0402_1% A_HP_OUTL_R
    USB20_P3 4 3 USB20_P3_R HPOUT_R RA20 1 2 51_0402_1% A_HP_OUTR_R

    CA178
    10U_0805_10V6K

    CA18

    CA19
    4 3 1 2 2
    EXC24CH900U_4P LINE1_VREF_L RA421 2 4.7K_0402_5%
    To solve the background noise while combojack connecting to an

    0.1U_0201_6.3V6-K

    0.1U_0201_6.3V6-K
    active speaker and system entry into S3/S4/S5 without analog power. EMC_NS@ LINE1_R 2 1 1
    FOR EMI CA46 2 1 1U_0402_6.3V6K

    RA217 1 @ 2 0_0402_5% @1 TC87


    7 HDA_RST_AUDIO#

    +3VALW
    +3VS +3VS_CARD

    RA220 1 2 0_0402_5% JSPK1 ME@


    RA223 1 CD@ 2 15_0402_5% SPK_R+ RA222 1 2 0_0402_5% SPK_R+_CONN 1
    RA219 1 @ 2 0_0402_5% RA224 1 CD@ 2 15_0402_5% SPK_R- RA221 1 2 0_0402_5% SPK_R-_CONN 2 1
    RA32 1 CD@ 2 15_0402_5% SPK_L+ RA30 1 2 0_0402_5% SPK_L+_CONN 3 2
    RA33 1 CD@ 2 15_0402_5% SPK_L- RA34 1 2 0_0402_5% SPK_L-_CONN 4 3
    4
    5
    6 GND1

    470P_0201_50V7-K

    470P_0201_50V7-K

    470P_0201_50V7-K

    470P_0201_50V7-K
    CA29

    CA30
    CA183

    CA184
    220P_0201_25V7-K

    220P_0201_25V7-K

    220P_0201_25V7-K

    220P_0201_25V7-K
    GND2
    1U_0402_6.3V6K

    CA31

    CA32

    CA181

    CA182
    B 1 2 2 2 2 B
    ACES_88231-04001
    C1110

    1 1 1 1

    2 1 1 1 1

    EMC@

    EMC@

    EMC@

    EMC@
    2 2 2 2

    @ CD@ CD@ CD@ CD@

    8/16 Update Audio Jack P/N SP011509163 wei


    RING3_CONN

    RA1 1 2 0_0402_5%
    RING2_CONN
    A_HP_OUTL_R
    Audio Jack JHP1 ME@

    EMC_NS@ A_HP_OUTR_R RING2_CONN 3


    RA4 1 2 0_0402_5% PLUG_IN A_HP_OUTL_R 1 G/M
    EMC_NS@ L
    PLUG_IN 5
    5
    RA9 1 2 0_0402_5% 6
    6
    1

    1
    47P_0201_25V8-J

    RA12 1 2 0_0402_5% DA5 DA6 DA7 DA8 DA9 A_HP_OUTR_R 2


    1
    1

    R
    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    AZ5123-01F.R7GR_DFN1006P2X2

    EMC_NS@ C185
    RING3_CONN 4
    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@
    M/G
    2 7
    MS
    2

    GND GNDA SINGA_2SJ3095-140111F

    100P_0201_25V8J

    100P_0201_25V8J
    2

    1 1
    C182 C183
    EMC@ EMC@
    2 2

    A A
    HDA_SYNC_AUDIO
    DMIC_CLK HDA_SDOUT_AUDIO
    RA27 1 EMC_NS@ 2 HDA_BITCLK_AUDIO
    DMIC_DATA 27_0402_5% HDA_SDIN0

    R266 1 2 C232 1 2 A_HP_OUTL_R


    CA38

    CA39

    CA23

    CA24

    CA25

    CA26
    100P_0201_25V8J

    100P_0201_25V8J

    0_0402_5% @ 470P_0201_50V7-K
    EMC_NS@

    EMC_NS@

    1 1
    22P_0201_258J

    22P_0201_258J

    33P_0201_50V8-J

    33P_0201_50V8-J

    R265 1 2 C184 1 @ 2 A_HP_OUTR_R


    1 1 1 1
    0_0402_5% @ 470P_0201_50V7-K
    2 2 @ Security Classification LC Future Center Secret Data Title
    2 2 2 2
    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Codec_CX11802_33Z
    EMC_NS@

    EMC_NS@

    EMC_NS@

    EMC_NS@

    For EMI THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    For EMI AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 32 of 50


    5 4 3 2 1
    5 4 3 2 1

    D D

    CARD_3V3

    SD / MMC

    0.1u_0201_10V6K
    4.7U_0402_6.3V6M
    C C
    1 1
    SD_D0_R RW3 1 2 0_0402_5% SD_D0 CW9 CW17
    32 SD_D0_R
    CW5 1 2 5.6P_0402_50V8-D @
    2 2
    EMC@ JREAD1 ME@
    SD_D3 1
    SD_CMD 2 CD/DAT3
    SD_D1_R RW4 1 2 0_0402_5% SD_D1 3 CMD
    32 SD_D1_R VSS1
    CW6 1 2 5.6P_0402_50V8-D 4
    SD_CLK 5 VDD
    6 CLK
    EMC@
    SD_D0 7 VSS2
    SD_D1 8 DAT0
    SD_D2_R RW5 1 2 0_0402_5% SD_D2 SD_D2 9 DAT1
    32 SD_D2_R Close to Connector DAT2
    CW7 1 2 5.6P_0402_50V8-D

    EMC@ SD_CD# 10 12
    32 SD_CD# SD_WP 11 CARDDETECT SH1 13
    32 SD_WP WRITEPROTECT SH2 14
    SD_D3_R RW6 1 2 0_0402_5% SD_D3 SH3 15
    32 SD_D3_R SH4
    CW8 1 2 5.6P_0402_50V8-D
    T-SOL_5-251301001000-6_NR
    B EMC@ B

    SD_CMD_R SD_CMD
    Close to Connector
    RW7 1 2 0_0402_5%
    32 SD_CMD_R
    CW11 1 2 5.6P_0402_50V8-D

    EMC@ CARD_3V3

    SD_CLK_R SD_CLK

    1
    RW8 1 2 0_0402_5%
    32 SD_CLK_R
    CW12 1 2 5.6P_0402_50V8-D DW1

    AZ5123-01F.R7GR_DFN1006P2X2
    EMC_NS@
    EMC@

    2
    2
    FOR ESD

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 CardReader
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 33 of 50


    5 4 3 2 1
    A B C D E F G H

    1 SATA HDD Conn. 1

    +5VS_HDD

    C1107 22P_0402_50V8-J

    C1108 22P_0402_50V8-J
    JHDD1 ME@

    C78 10U_0805_10V6K
    1 1 1 1 1 1 1
    10

    C75 0.1U_0201_6.3V6-K

    C76 1U_0603_25V6M

    C77 10U_0805_10V6K
    C74
    1000P_0201_50V7-K SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
    8 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
    1 2 0.01U_0201_10V6K 8

    @
    EMC_NS@ @ 8 SATA_PTX_DRX_N0 C67
    2 2 2 2 2 2 2 7 8 12

    RF@

    RF@
    @ SATA_PRX_DTX_N0 SATA_PRX_C_DTX_N0 7 GND2
    C68 1 2 0.01U_0201_10V6K 6
    8 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6
    8 SATA_PRX_DTX_P0 4 5
    EMC 4
    3 11
    2 3 GND1
    1 2
    +5VS +5VS_HDD 1
    Need short ELCO_006809610010846

    J3 1 2 @
    1 2
    JUMP_43X79

    2 2

    +5VS +5V_ODD

    SATA 15 ODD P/N pin assgin is different from G SKL


    Need Short
    J4 @
    1 2
    1 2
    C2084 22P_0402_50V8-J

    JUMP_43X79
    10U_0603_10V6K

    0.1u_0201_10V6K

    1 1 1
    CD@
    C85

    2 2 2
    RF@
    C86

    3 3

    FOR 14"
    SATA ODD Conn. JODD2
    1 ME@
    SATA_PTX_DRX_N1 15@ C79 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 2 1
    JODD1 ME@ SATA_PTX_DRX_P1 15@ C80 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_15 3 2
    1 4 3
    SATA_PTX_DRX_P1 14@ C70 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_14 2 GND_1 SATA_PRX_DTX_P1 15@ C81 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 5 4
    8 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1_14 RX+ SATA_PRX_DTX_N1 SATA_PRX_C_DTX_N1_15 5
    8 SATA_PTX_DRX_N1 14@ C71 1 2 0.01U_0201_10V6K 3 15@ C82 1 2 0.01U_0201_10V6K 6
    4 RX- 7 6
    SATA_PRX_DTX_N1 14@ C72 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_14 5 GND_2 +5V_ODD 8 7
    8 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_14 6 TX- 8
    8 SATA_PRX_DTX_P1 7 TX+ 9
    GND_3 10 GND1
    8 GND2
    9 DP HIGHS_FC5AF081-2931H
    +5V_ODD 10 +5V_1
    11 +5V_2 14
    12 MD GND1 15
    13 GND_4 GND2
    GND_5
    SUYIN_127382FB013S255ZL

    4 4
    8/16 Update Conn. P/N SP01001YV00 wei

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 HDD/ODD CONN


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 34 of 50
    A B C D E F G H
    5 4 3 2 1

    RE1 1 2 0_0603_5% +3VL

    +3VL_EC +3VL_EC_R

    RE3 1 @ 2 0_0603_5% +3VALW LE1 1 2 0_0603_5%


    Close EC
    1 1
    CE3 0.1U_0201_6.3V6-K +3VL_EC CE4 CE5
    1 2 VCOREVCC 1000P_0201_50V7-K
    0.1U_0201_6.3V6-K
    All capacitors close to EC LE2 1 2 0_0603_5% 2 EC_AGND 2

    1 1 1 1 1 1 EC_AGND
    +3VS +3VL_EC_R CE21 CE22 CE23 CE24 CE25
    CE11
    0.1U_0201_6.3V6-K
    0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
    D
    @ 2 2 2 2
    0.1U_0201_6.3V6-K 2 2 0.1U_0201_6.3V6-K
    0.1U_0201_6.3V6-K @
    D

    RE6 1 2 0_0402_5%

    +3VS
    minimum trace width 12 mil

    114
    121
    127
    12

    11

    26
    50
    92

    74
    EC_FAN_SPEED

    3
    UE1 RE10 1 2 10K_0402_5%
    EC_FAN_PWM RE11 1 @ 2 10K_0402_5%

    VCORE

    VSTBY1
    VSTBY2
    VSTBY3
    VSTBY4
    VSTBY5
    VCC

    AVCC
    VSTBY(PLL)
    VBAT
    ENBKL RE9 1 @ 2 100K_0402_5%
    EC_LID_OUT# RE93 1 @ 2 10K_0402_5%
    EC_GFX_PWRGD RE279 1 2 10K_0402_5%

    16 WRST# 4 24
    +3VL_EC 8 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 36
    8,30 SERIRQ 6 SERIRQ/GPM6 PWM1/GPA1 28 BATT_CHG_LED# 36
    8,11,30 LPC_FRAME# 7 LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# 36 +5VALW
    DE1 8,30 LPC_AD3 VGA_AC_DET 16
    1 2 @ 8 LAD3/GPM3 PWM3/GPA3 30
    8,30 LPC_AD2 LAD2/GPM2 PW M PWM4/GPA4 EC_FAN_PWM LED_KB_PWM 36
    9 31
    8,30 LPC_AD1 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 30 USB_ON# RE15 1 2 10K_0402_5%
    LRB751V-40T1G_SOD323-2 8,30 LPC_AD0 CLK_PCI_EC 13 LAD0/GPM0 PWM6/SSCK/GPA6 34 EC_APU_ALWEN BEEP# 32
    8,11 CLK_PCI_EC LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7 EC_APU_ALWEN 47 1
    RE8 1 2 100K_0402_5% WRST# 14 120 RE29 @ 2 0_0402_5%
    15 WRST# TMRI0/GPC4 124 SUSP# HVB_EN 7,11 +3VL_EC
    28 LAN_PWR_ON# EC_RX 16 ECSMI#/GPD4 TMRI1/GPC6 SUSP# 37,47
    1 31 EC_RX EC_TX PWUREQ#/BBO/SMCLK2ALT/GPC7
    17 66 SUSP# RE18 1 @ 2 100K_0402_5%
    CE12 31 EC_TX APU_LPC_RST# 22 LPCPD#/GPE6 ADC0/GPI0 67 NTC_V1 30 LAN_WAKE# RE5 1 2 10K_0402_5%
    1U_0402_6.3V6K 8 APU_LPC_RST# 23 LPCRST#/GPD2 ADC1/GPI1 68 NTC_V2 30
    2 8 EC_SCI# 126 ECSCI#/GPD3 ADC2/GPI2 69 BATT_TEMP 44,45 +3VL
    7 GATEA20 GA20/GPB5 ADC ADC3/GPI3 ENBKL 23
    70 RE276 1 2 0_0402_5%
    IT8586E/AX ADC4/GPI4
    ADC5/DCD1#/GPI5
    71
    72
    ADP_I 45
    RE275 1
    @

    2 0_0402_5%
    IDCHG 45
    LID_SW# RE38 1 2 100K_0402_5%

    KSI0 58
    LQFP-128L ADC6/DSR1#/GPI6
    ADC7/CTS1#/GPI7
    73 RE71 1 2 0_0402_5% PSYS 45 2_5VEN

    KSI[0..7] KSI1 59 KSI0/STB# 78 EC_APU_ALWEN RE278 1 2 100K_0402_5%


    36 KSI[0..7] 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 MAINPWON1_EC VR_APU_PWRGD 50 2_5VEN
    KSI2 RE26 1 @ 2 1K_0402_5% RE277 1 @ 2 100K_0402_5%
    KSO[0..17] 61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC MAINPWON 46
    KSI3 DAC SUSP# RE19 1 2 100K_0402_5%
    36 KSO[0..17] 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81
    KSI4 RE58 1 2 100K_0402_5%+3VL_EC SYSON RE21 1 2 100K_0402_5%
    63 KSI4 DAC5/RIG0#/GPJ5 EC_RTCRST#_ON 9
    KSI5 BKOFF# RE40 1 2 10K_0402_5%
    C KSI6 64 KSI5 85 RE57 1 2 0_0402_5% C
    +3VL_EC +3VALW 65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 46,47
    KSI7
    36 KSI7 PS2DAT0/TMB1/GPF1 87 PBTN_OUT# 7
    KSO0 RE91 1 2 0_0402_5%
    37 KSO0/PD0 GPF2 88
    KSO1
    KSO1/PD1 Int. K/B PS2 GPF3 APUALW_PWRGD 47
    KSO2 38 89 1 @ TE2
    KSO2/PD2 Matrix PS2CLK2/GPF4 EC_LID_OUT#
    1

    KSO3 39 90 RE90 1 2 0_0402_5% GPU_VR_HOT# 16,49


    40 KSO3/PD3 PS2DAT2/GPF5 EC_LID_OUT# 36
    RE274 RE273 KSO4
    KSO5 41 KSO4/PD4 96 GPU_EC_HOT#
    0_0402_5% 0_0402_5%
    KSO5/PD5 EXTERNAL SERIAL FLASH GPH3/ID3 CAPS_LED# 36

    1
    @ KSO6 42 97 QE6 D 1
    KSO7 43 KSO6/PD6 GPH4/ID4 98 ACOFF @1 EC_VR_ON 50 2
    TC88 CE26
    KSO7/PD7 GPH5/ID5
    2

    KSO8 44 99 G 47P_0201_25V8-J
    45 KSO8/ACK# GPH6/ID6 EC_SYS_PWRGD 7
    KSO9 @
    KSO10 46 KSO9/BUSY 101 2
    KSO10/PE NC1 Need EC modify GPH6 to OD output 2N7002KW_SOT323-3 S

    3
    KSO11 51 102
    KSO11/ERR# NC2 @
    2
    1

    KSO12 52 SPI Flash ROM 103


    RPE5 KSO13 53 KSO12/SLCT NC3 105
    KSO14 54 KSO13 NC4
    2.2K_0404_4P2R_5% KSO14
    KSO15 55 GPG0 def mode GPO H
    KSO15
    KSO16 56
    KSO16/SMOSI/GPC3 AC_IN#
    108 ACIN# GPG1 def mode GPO L internal Pull down H_PROCHOT#
    3
    4

    EC_SMB_CK2 KSO17 57 109 LID_SW# 1 2 0_0402_5%


    EC_SMB_DA2 KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 36 45,50 VR_HOT#
    RE34 @ H_PROCHOT# 6,47

    1
    ON/OFF 110 82 QE1 D 1
    EC_ON 36 ON/OFF EC_ON_L PWRSW# EGAD/GPE1 EC_MUTE# 32 H_PROCHOT#_EC
    RE59 1 @ 2 0_0402_5% 111 SM Bus 83 2 CE14
    EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 G 47P_0402_50V8J
    44,45 EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3 CMOS_ON# 23
    44,45 EC_SMB_DA1 SMDAT1/GPC2 Nano G not support adapt ID( GPI7) 10/20 2
    @
    117 77
    Add SMBUS for POWER 47 EC_SMB_CK2 SMCLK2/PECI/GPF6 GPIO GPJ1 PM_SLP_S5# 7 L2N7002KWT1G_SOT323-3 S

    3
    118 100 GPG2
    47 EC_SMB_DA2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 @
    core IC 10/20 6,16,30 EC_SMB_CK3
    EC_SMB_CK3
    EC_SMB_DA3
    94
    95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0
    106
    104
    EC_GFX_PWRGD
    1 @
    PIN 106 add pull high resistor for EC_GFX_PWRGD to share EC code with 320 ABR
    TE1
    +3VL_EC 6,16,30 EC_SMB_DA3 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON
    +3VL DTR1#/SBUSY/GPG1/ID7 119 BKOFF#
    CRX0/GPC0 123 BKOFF# 23
    RE89 2 1 0_0402_5%
    RE27 1 @ 2 0_0402_5% 112 CTX0/TMA0/GPB2 18
    LAN_WAKE# VSTBY0 RI1#/GPD0 PM_SLP_S3# 7
    28,31 LAN_WAKE# 125 21 PIN 21, NANO is 4 pin FAN, so delete EC_FAN_ANTI Need EC modify GPJ4 to OD output
    GPE4 RI2#/GPD1 76
    WAKE UP TACH2/GPJ0 NOVO# 36
    2
    1

    48
    RPE2
    Change PCH_CMOSP form PIN117 to pin35 TACH1A/TMA1/GPD7 47 EC_FAN_SPEED
    USB_ON# TACH0A/GPD6 EC_FAN_SPEED 30
    2.2K_0404_4P2R_5% 33 19 RE92 1 2 0_0402_5%
    25 USB_ON# 35 GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 20 PCH_PWRBT# 7
    B 37 PCH_CMOSP RTS1#/GPE5 GPIO L80LLAT/GPE7 NUM_LED# 36
    @
    B
    93
    7 EC_RSMRST# CLKRUN#/GPH0/ID0
    3
    4

    EC_SMB_CK1
    EC_SMB_DA1 PIN 48 20 ，CZL and ST N have no VDDCR_ GFX, so del et e VDDFX_ PD and EC_ GFX_ PD
    Need EC modify GPH0 to OD output
    2
    7,28,31 PCIE_WAKE# 128 CK32KE/GPJ7 +3VL
    +3VS 7 AC_PRESENT CK32K/GPJ6 Clock

    1
    RE56
    2
    1

    100K_0402_5% Change GPIO setting, high active NOVO#


    AVSS
    VSS1

    VSS2
    VSS3
    VSS4
    VSS5
    VSS6

    RPE3
    7,15,28,30,31 PLT_RST#
    2.2K_0404_4P2R_5%

    2
    IT8586E-AX_LQFP128_14X14 ACIN# RE88 2 1 0_0402_5% 1
    1

    27
    49
    91
    113
    122

    75

    CC1277

    1000P_0402_25V7-K
    3
    4

    EC_SMB_CK3 0.01U_0201_25V6-K
    EC_SMB_DA3

    1
    D QE2 EMC@
    2

    2
    2

    CC1278
    G ACIN 45
    EMC_NS@
    AMD request SIC/SID（ ）
    EC_SMB2 pul l hig h K
    1 EC_AGND

    1
    L2N7002KWT1G_SOT323-3 S
    3

    @
    DE2 1 2 RB751V-40_SOD323-2

    SYSON RE86 2 1 0_0402_5% Factory EC flash for STN


    1_2VEN 47
    Mirror Core strap CLK_PCI_EC RE2 1 2 10_0402_5% EMC_NS@ CE2 1 2 10P_0402_50V8J
    +3VL_EC EC_SMB_CK1 PAD 1 @ VR_APU_PWRGD EMC_NS@ +3VS
    EC_SMB_DA1 1 IT1 APU_LPC_RST# 1 2 220P_0402_50V7K
    @ PAD @ EMC_NS@ CE1
    1 2 RB751V-40_SOD323-2 1 IT2
    DE3 PAD @ 1
    1 IT3
    PAD @ CE20 SYSON EMC_NS@ CE13 1 2 0.1U_0201_6.3V6-K
    IT4
    GPG2 RE44 2 @ 1 10K_0402_5% PAD 1 @ 1U_0402_6.3V6K
    2_5VEN IT5 BATT_TEMP
    RE87 1 @ 2 1K_0402_5% EMC_NS@ CE16 1 2 100P_0402_50V8J 1
    2_5VEN 47 2
    RE46 2 STN@ 1 10K_0402_5%
    ACIN# EMC_NS@ CE17 1 2 100P_0402_50V8J CE19
    A KSI7 PAD 1 @ 0.1U_0201_6.3V6-K A
    when mirror, GPG2 pull high KSI6 PAD 1 @
    IT6
    ON/OFF EMC_NS@ CE18 1 2 1U_0402_6.3V6K 2
    when no mirror, GPG2 pull low WRST# PAD 1 @
    IT7 for VR_APU_PWRGD undershoot issue EMC_NS@
    IT8 PM_SLP_S3# EMC_NS@ CE27 1 2 0.1U_0201_6.3V6-K
    PM_SLP_S5# EMC_NS@ CE28 1 2 0.1U_0201_6.3V6-K

    EMC

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 EC ITE8586LQFP


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 35 of 50


    5 4 3 2 1
    5 4 3 2 1

    ON/OFF switch
    PWR_LED#
    +3VL +3VALW

    K/B Connector

    2
    JKB1

    1
    R82 R83
    1 2 0_0402_5% NOVO_BTN# 32 33
    100K_0402_5% 100K_0402_5% R268 D46 32 GND1

    1
    AZ5123-01F.R7GR_DFN1006P2X2 ON/OFFBTN# 31 34
    PWR_LED# R285 1 2 0_0402_5% 30 31 GND2
    KSI[0..7] EMC_NS@ NUM_LED#_R 30
    KSI[0..7] 35 R279 1 15@ 2 0_0402_5% 29

    2
    D15 SW2 35 NUM_LED# KSO17_R 29
    @ KSO17 R281 1 15@ 2 0_0402_5% 28

    1
    NOVO# 2 KSO[0..17] KSO16_R 28
    35 NOVO# NOVO_BTN# KSO[0..17] 35 KSO16 R280 1 15@ 2 0_0402_5% 27
    1 4

    2
    @ D29 27

    1
    1 2 0_0402_5% 3 KSI1 26
    ON/OFF R85 AZ5123-01F.R7GR_DFN1006P2X2 26
    KSI7 25

    2
    5 EMC@ 25
    LBAT54CWT1G_SOT323-3 KSI6 24
    KSO9 23 24
    D @ KSI4 22 23 D

    2
    KSI5 21 22
    NTC325-EKJ-A160T_3P 21
    KSO0 20

    2
    KSI2 19 20
    KSI3 18 19
    +3VALW +3VL 18
    KSO5 17
    KSO1 16 17
    KSI0 15 16

    2
    EMC_NS@ 15
    R111 R114 PWR_CAPS_LED C133 1 2 100P_0201_25V8J KSO2 14
    CAPS_LED# NUM_LED#_R KSO4 13 14
    100K_0402_5% 100K_0402_5% ON/OFFBTN# 13
    KSO7 12
    @ 12
    KSO8 11
    KSO6 10 11

    1
    @ 10
    KSO3 9

    1
    ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF 9
    ON/OFF 35 KSO12 8
    D23 D22 D30 8

    1
    KSO13 7
    AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 7
    J5 1 2 @ KSO14 6
    EMC@ EMC_15@ EMC_NS@ 6
    KSO11 5
    KSO10 4 5
    SHORT PADS 4
    EMC@ KSO15 3

    2
    CAPS_LED# 3
    J6 1 2 @ CAPS_LED#
    C117 1 2 100P_0201_25V8J R275 1 2 0_0402_5% 2
    35 CAPS_LED# PWR_CAPS_LED 2
    R84 1 2 1

    2
    +3VALW 1
    SHORT PADS NUM_LED#_R C118 1 2 100P_0201_25V8J 200_0402_1%
    CVILU_CF32321D0RONH
    EMC_15@ For EMC ME@

    C +3VS TP_PWR
    TP/B Connector LID Connector Finger Print Connector C

    R141 1 2 Change from PS2 mode to I2C mode 10/19


    0_0402_5%
    0.1u_0201_10V6K

    1
    JTP1 ME@
    R4677 1 2 0_0402_5% EC_LID_OUT#_R 1
    35 EC_LID_OUT# TP_INT# 1
    R4678 1 2 0_0402_5% 2 7
    2 7 PCH_TP_INT# 2 GND1
    3
    C114

    TP_I2C0_SDA_R TP_I2C0_SDA 3 1
    RC1657 1 @ 2 0_0402_5% 4 8
    TP_I2C0_SCL_R RC1656 1 @ 2 0_0402_5% TP_I2C0_SCL 5 4 GND2 C1105
    6 5 U23 0.01U_0201_6.3V7-K
    TP_PWR 6 2
    1
    GND
    100P_0201_25V8J

    100P_0201_25V8J

    1 1 ELCO_04-6809-606-110-846-+ 1
    EMC_NS@

    EMC_NS@

    3 LID_SW#
    OUTPUT LID_SW# 35
    C1104
    0.01U_0201_6.3V7-K
    2 2 2

    1
    2
    C115

    C116

    VCC D17

    1
    0_0402_5% AZ5123-01F.R7GR_DFN1006P2X2
    TP_PWR R267 1 2 +VCC_LID AH9247-W-7_SC59-3 EMC_NS@
    +3VL
    +1.8VS

    2
    2
    1

    2
    RPC20
    2.2K_0404_4P2R_5%
    TP_I2C0_SCL
    5

    For EMC
    G

    TP_I2C0_SDA
    3
    4

    TP_I2C0_SDA_R 4 3 TP_I2C0_SDA DT1


    S

    7 TP_I2C0_SDA_R
    D

    EMC_NS@

    Q158B
    2
    G

    DMN5L06DWK-7 2N SOT363-6

    7 TP_I2C0_SCL_R TP_I2C0_SCL_R 1 6 TP_I2C0_SCL


    S

    B B
    D

    Q158A AZC199-02S.R7G_SOT23-3
    1

    DMN5L06DWK-7 2N SOT363-6
    EMC
    Reserve level shift as I2C at APU side is 1.8V Level 10/28

    LED PWR_LED#
    LED1 1 2 R142 1 2 1.5K_0402_5%
    35 PWR_LED# +5VALW
    KB Backlight Connector
    1

    L-C192WDT-LCFC_WHITE
    D31
    1

    AZ5725-01F.R7GR_DFN1006P2X2
    EMC_NS@
    +5VS To be confirm Pin define
    +5VALW
    2

    +VCC_KB_LED
    2

    Q31 JKBL1 ME@


    +VCC_KB_LED

    1
    R4681 LP2301ALT1G_SOT23-3 1
    10K_0402_5% KBL@ 2 1
    BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5% KBL@ 3 1 3 2 6

    D
    35 BATT_LOW_LED# +3VALW 3 GND2
    4 5
    4 GND1
    1

    L-C192JFCT-LCFC_SUPER_AMBER 1 1 1

    2
    D32 R4680 C2080 C2082 C2079 CVILU_CF50041D0RN-10-NH

    G
    1

    2
    AZ5725-01F.R7GR_DFN1006P2X2 1 2 10U_0603_6.3V6M 0.1u_0201_10V6K 0.1u_0201_10V6K
    EMC_NS@ KBL@ KBL@ @
    100K_0402_5% 2 2 2
    1
    KBL@ C2081
    0.01U_0201_10V6K
    2

    A A
    KBL@
    2
    2

    8/31 Update KBL Conn. P/N SP011608241 wei


    BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%
    35 BATT_CHG_LED# +5VALW
    1

    D
    LED_KB_PWM
    1

    L-C192WDT-LCFC_WHITE 2 Q32
    35 LED_KB_PWM
    D33 G 2N7002KW_SOT323-3
    1

    AZ5725-01F.R7GR_DFN1006P2X2 KBL@
    2

    EMC_NS@ 1 S
    3

    C2083 R4685
    0.1u_0201_10V6K 10K_0402_5% Title
    KBL@ @ Security Classification LC Future Center Secret Data
    2

    2
    Issued Date 2017/02/04 Deciphered Date 2017/02/04 KBD/PWR/IO/LED/TP Conn.
    2

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Re v
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 36 of 50
    5 4 3 2 1
    A B C D E

    Load Switch
    +5VLP +5VALW
    +5VALW To +5VS +3VS, C173 --> 2.74ms
    +3VALW To +3VS +5VS, C176 --> 2.03ms

    1
    VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
    R156 R157
    100K_0402_5% 100K_0402_5% R4 1 @ 2 0_0402_5% 3VSON +5VALW U13 +5VS
    @ 1 14 J12 @
    1 2 IN1_1 OUT1_2 13 +5VS_LS 1 2 1
    IN1_2 OUT1_1 1 2

    2
    SUSP 1 5VSON 3 12 C176 1 2 1000P_0201_50V7-K JUMP_43X118 1
    12,24 SUSP EN1 CT1 C174
    SUSP# R2 1 @ 2 0_0402_5% 5VSON C177 4 11 0.1u_0201_10V6K
    +5VALW VBIAS GND
    1U_0402_6.3V6K @
    +3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
    EN2 CT2

    1
    Q6 D 1 1 J11 @
    2 6 9 +3VS_LS 1 2
    35,47 SUSP# G 7 IN2_1 OUT2_2 8 1 2
    C180 C179
    1U_0402_6.3V6K 1U_0402_6.3V6K IN2_2 OUT2_1 JUMP_43X118
    2 2 1 1
    L2N7002KWT1G_SOT323-3 S 15 C175
    GPAD

    3
    C178 Need Short 0.1u_0201_10V6K
    1U_0402_6.3V6K G5016KD1U_TDFN14_2X3 @
    2 @ 2
    Change the main source to SA000067600 (GMT) 7/16

    +1.8VALW to +1.8VS AON6414AL


    VDS=30V VGS=20V, ID=50A,
    +0.95VALW to +0.95VS AON6414AL
    +1.8VALW Q39 +1.8VS +/- 5% 1.5A Rds=8mohm @ VGS=10V
    VDS=30V VGS=20V, ID=50A,
    +/- 2% AON6414AL_DFN8-5
    VGS(th)=2.5V Max
    Q41
    2
    +0.95VALW +0.95VS +/-5% 3.6A Rds=8mohm @ VGS=10V 2

    1 +/- 1.5% AON6414AL_DFN8-5


    VGS(th)=2.5V Max
    2 1 1
    1 5 3 1
    C141 C140 C142 2 1 1
    10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_25V6M 1 5 3
    2 2

    1
    C146 C145 C147
    4

    @ 2 R213 @ 10U_0805_25V6K 10U_0603_6.3V6M 1U_0603_25V6M


    2 2

    1
    470_0603_5% @

    4
    2 R188 @
    470_0603_5%

    2
    R206

    2
    R211 R194 2 1 1.8VS_GATE
    1.8VS_GATE_R 1 2 1 2 1.8VS_GATE 1 R214 2 @ 0_0402_5%
    @ @ 270K_0402_5% V20B+ R193
    0_0402_5% 0_0402_5% 0.95VS_GATE_R 1 2 1 R190 2 0.95VS_GATE 2 R189 1
    V20B+
    1

    1
    1 D Q45 Q46 D @ 0_0402_5% 470K_0402_5%
    R212 2 SUSP 2 0_0402_5% @
    @

    1
    C143 820K_0402_5% G G 1 D Q37 Q40 D
    0.01U_0201_25V6-K R187 2 SUSP 2
    2 S L2N7002KWT1G_SOT323-3 S
    L2N7002KWT1G_SOT323-3 C144 820K_0402_5% G G
    2

    3
    0.01U_0201_25V6-K
    @ 2 S L2N7002KWT1G_SOT323-3 S
    L2N7002KWT1G_SOT323-3

    3
    @ @ @
    3 3

    +3VALW to +3VALW_APU +3VALW Need Short +3VALW_APU For DisCharge


    J7 @
    1 2 +0.6VS +2.5V +1.8VS
    1 2

    JUMP_43X79

    1
    Id=3.2A R159 R935 R939
    47_0603_5% 47_0603_5% 47_0603_5%
    LP2301ALT1G_SOT23-3 @ @
    @

    2
    Q29 3 1
    S

    1
    1 1 D Q8 D Q156 D Q157
    2 SUSP 2 SUSP 2 SUSP
    G
    2

    C129 C130 G G G
    0.1U_0201_6.3V6-K 0.01U_0201_6.3V7-K
    2 @ 2 S L2N7002KWT1G_SOT323-3 2N7002KW_SOT323-3 S @ 2N7002KW_SOT323-3 S @
    @

    3
    35 PCH_CMOSP R158 1 @ 2 0_0402_5%
    1

    4 1 4

    R164 C131
    100K_0402_5% 0.1U_0201_6.3V6-K
    @ 2 @
    Security Classification LC Future Center Secret Data Title
    2

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 DC V TO VS INTERFACE


    reserve to cut off APU 3VALW when clear CMOS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 37 of 50


    A B C D E
    5 4 3 2 1

    D D

    CPU Thermal Holex3 GPU Thermal Holex2 PCB Fedical Mark PAD
    Close to RJ45 Close to Audio jack
    H1 H2 H3 H4 H5 H6 H7
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4 FD5 FD6

    1
    pad_c6p0d4p0 pad_c6p0d4p0 pad_c6p0d4p0 pad_c7p0d3p3 pad_c7p0d3p3 CHASSIS1_GND
    pad_ct7p0b8p0d3p0 pad_ct7p0b8p0d3p0

    WLAN Standoff
    H10 H11 H12 H13 H15 H16
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

    1
    pad_ct5p5d2p5 pad_ct7p0b6p0d3p3 pad_ct7p0d3p0 pad_ct7p0d3p0 pad_ct5p0d2p5 pad_cb5p5d2p5

    C C
    H17 H18 H19 H20
    HOLEA HOLEA HOLEA HOLEA
    1

    1
    pad_o2p6x2p9d2p6x2p9n PAD_CT7P0D3P0 PAD_CT7P0D3P0 pad_c3p3d3p3n

    SH1 ME@ SH2 ME@ SH3 ME@


    SH7 ME@ SH8 ME@ SH14 ME@
    1 1 1 SH12 ME@
    1 1 1 1 1 1
    1 1 1 1
    1
    SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64
    SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
    SPRING_FINGER_6.2X1.64

    SH4 ME@ SH5 ME@ SH6 ME@

    1 1 1 SH13 ME@ SH9 ME@


    1 1 1 SH10 ME@ SH11 ME@
    1 1
    1 1 1 1
    1 1
    SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64 SPRING_FINGER_6.2X1.64

    SPRING_FINGER_6.2X1.64 SHIELDING_SUL-35A2M_9P2X3P3_1P
    SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
    B USB3.0 Shielding B
    DDR4 Shielding

    +VGA_CORE +3VS
    A
    For EMC A

    1 1
    C168 C169
    0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
    2 @ 2 @

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Hole


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 38 of 50


    5 4 3 2 1
    5 4 3 2 1

    HDMI@
    ZZZ1 ZZZ2 UL1 8107E@ UV1 PX@

    PCB PN HDMI PN RTL8107E-CG R17M-M1-70 GPU


    DA600013D00 RO00000040J SA00007FR00 SA000086K00
    D PCB HDMI LAN Chip GPU D

    Board ID
    BOARD
    BD14@
    Config. BOARD_ID0 BOARD_ID3
    UC2 UC2 RC47 RC1659 BD14@
    14'' 0 0
    15'' 0 1
    17'' 1 0
    AMD A6-9220 2.5G/2C/1M/FT4 AMD E2-9000 1.8G/2C/1M/FT4 2K_0402_5% 2K_0402_5%
    A6@ E2@ SD02820018J SD02820018J
    SA00008A600 SA00007WW10

    BD15@ BD15@
    RC47 RC1660

    UC2
    UC2

    2K_0402_5% 10K_0402_5%
    SD02820018J SD02810028J
    AMD A9-9420 3.0G/2C/1M/FT4
    A9@ AMD A4-9120 2.2G/2C/1M/FT4
    SA00008A500 A4@ BD17@
    C C
    SA00008A700 APU type RC39 RC1659 BD17@

    10K_0402_5% 2K_0402_5%
    SD02810028J SD02820018J

    ZZZ3 S4GX4@ ZZZ3 H4GX4@ ZZZ3 M4GX4@

    Samsung Hynix Micron


    X7643P12001 X7643Q12001 X7643T12001

    VRAM X76 BOM

    UV5 S4G_VR@ UV6 S4G_VR@ UV7 S4G_VR@ UV8 S4G_VR@ RV63 S4G_VR@ RV70 S4G_VR@

    B B
    K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 K4G41325FE-HC28 3.4K_0402_1% 10K_0402_1%
    SA00007VQ10 SA00007VQ10 SA00007VQ10 SA00007VQ10 SD03434018J SD03410028J

    VRAM_Samsung 4GX4

    UV5 H4G_VR@ UV6 H4G_VR@ UV7 H4G_VR@ UV8 H4G_VR@ RV63 H4G_VR@ RV70 H4G_VR@

    H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C H5GC4H24AJR-R0C 4.53K_0402_1% 4.99K_0402_1%


    SA000081A00 SA000081A00 SA000081A00 SA000081A00 SD03445318J SD03449918J

    VRAM_Hynix 4GX4

    UV5 M4G_VR@ UV6 M4G_VR@ UV7 M4G_VR@ UV8 M4G_VR@ RV63 M4G_VR@

    EDW4032BABG-70-F EDW4032BABG-70-F EDW4032BABG-70-F EDW4032BABG-70-F 4.75K_0402_1%


    SA000081800 SA000081800 SA000081800 SA000081800 SD03447518J
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Virtual symbol


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 39 of 50
    5 4 3 2 1
    5 4 3 2 1

    EC_APU_ALWEN 1 +0.775VALW

    V V
    PU604 Compare
    UC4
    APUALW_PWRGD 2 V V QC1/QC2/QC3/QC4
    PU603 PU601
    A3 ACIN#
    V

    V
    D D

    AC A1 +VDDCR_FCH_S5
    M ODE APU_S5_MUX_CTRL
    VIN B5
    +0.95VALW +1.8VALW
    A2 A5
    V V
    PU301 +3VALW

    V
    V V

    V
    BATT B2
    B+
    PU401 A5 B5 V
    BATT 3
    MODE ALW_PWRGD EC_RSMRST#
    B1

    V
    V +APU_CORE_NB

    V V
    EC 4 PBTN_OUT#
    EC_ON A4

    V
    +APU_CORE

    B4
    PM_SLP_S3#
    PM_SLP_S5# 5 APU

    V
    VR_GFX_PWRGD

    V V
    10 EC_SYS_PWRGD

    V
    +APU_GFX

    B3
    PLT_RST# 11

    V
    A5

    V
    ON/OFF 12 VVVVV
    B5
    KBRST# V

    V
    C C

    PXS_PWREN
    V SYSON 6 PU501
    +VSYSMEM

    V
    +5VALW +3VGS

    V
    QV6

    V
    7
    V SUSP#,SUSP
    U13 +1.35VGS

    V
    SUSP# 6 U13

    V
    +3VS QV9
    V

    +5VS

    PU10 +1.8VGS

    V
    +1.5VS QV2
    PU501
    V

    +0.675VS VGA
    Q39 +0.95VGS

    V
    +1.8VS QV3

    B
    +VGA_CORE B

    V
    Q41

    V
    PU701
    +0.95VS

    VGA_PWRGD
    VDDGFX_PD
    8
    EC_GFX_ON V +APU_GFX
    V

    PU901
    +APU_GFX

    8 VR_GFX_PWRGD

    EC_VR_ON
    +APU_CORE
    V

    PU801
    +APU_CORE

    +APU_CORE_NB
    V

    A PU801 A
    +APU_CORE_NB

    9
    VR_APU_PWRGD

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Power sequence Block


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date: Saturday, February 04, 2017 Sheet 40 of 50
    5 4 3 2 1
    5 4 3 2 1

    D D

    C C

    B B

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 DP to CRT Convert(IT6515FN)


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 41 of 50


    5 4 3 2 1
    5 4 3 2 1

    B+
    +5VLP/ 100mA
    Silergy
    SY8288C +5VALW/8A
    Adaptor Converter
    EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD

    +3VLP/ 100mA
    D
    Silergy D

    SY8286B
    Converter +3VALW/6A

    EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD

    LCFC +1.2V/6A
    LCFC5075B
    1.2VEN S5 PMIC +0.6VS/1A
    SUSP# S3
    TI FOR SYS PGOOD

    BQ24780SRUYR +5VALW
    Battery Charger +0.95VALW/6A
    EC_APU_ALWEN EN
    PGOOD APUALW_PWRGD
    Switch Mode
    C
    +3VALW +1.8VALW/3A C

    EC_APU_ALWEN EN PGOOD APUALW_PWRGD

    SMBus +1.8VALW
    +0.775VALW/0.5A
    EC_APU_ALWEN EN

    +3.3VALW

    Battery 2.5VEN EN
    +2.5V/0.5A

    Li-ion
    2S1P
    MPS
    NB685GQ-Z +1.35VGA /8A
    Converter
    B
    FOR 1.35VGS B

    PXS_PWREN EN PGOOD

    Richtek
    RT3662EBGQW
    Switch Mode +VGA_CORE/28A
    FOR VGA_CORE
    PXS_PWREN EN PGOOD VR_VGA_PWRGD

    02 APU_CORE/22A
    RT3661AB
    Switch Mode
    APU_SVID VIDs
    APU_CORE_NB/18A
    EN FOR CPU CORE&NB PGOOD
    EC_VR_ON VR_APU_PWRGD
    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 Power Diagram


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Custom
    320AST 0.2

    Date: Saturday, February 04, 2017 Sheet 42 of 50


    5 4 3 2 1
    5 4 3 2 1

    Cost down PL101,PL102 if EMC test pass

    PL101 EMC_NS@
    HCB2012KF-121T50_0805
    1 2
    EMC_NS@
    PL102
    HCB2012KF-121T50_0805
    VIN
    1 2

    D PJ101 @ D
    JDCIN1 PF101 JUMP_43X79
    1 APDIN 1 2 APDIN1 1 2
    1 2 1 2
    GND1 3 7A_24VDC_429007.WRML
    GND2 4
    GND3 5

    1000P_0402_50V7K

    1000P_0402_50V7K
    100P_0402_50V8J

    100P_0402_50V8J
    GND4 6

    PC101 EMC@

    PC102 EMC@

    PC103 EMC@

    PC104 EMC@
    GND5

    1
    7
    GND6

    2
    HIGHS_PJSS0026-8B01H
    ME@

    C C
    VCCRTC
    +3VL

    2
    RTC_VCC
    1
    JRTC1
    3 2 1 1
    PR104 2 1
    2 2
    BAT54CW_SOT323-3 1K_0603_5% 3
    PC105 PD101 4 GND1
    1U_0402_10V6K GND2
    1 @
    HIGHS_WS33020-S0351-HF
    ME@

    JRTC2 PRTC1
    1
    2 1
    3 2
    4 GND1
    B GND2 B

    BATT CR2032 3V 220MAH


    HIGHS_WS33020-S0351-HF
    RTC@
    ME@
    35mm cable

    RTC Battery for GCM BOM


    (2nd source and quoted price )

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 DCIN / RTC


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    Custom 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
    Date: Saturday, February 04, 2017 Sheet 43 of 50
    5 4 3 2 1
    5 4 3 2 1

    D D

    PL103 EMC@
    VMB HCB2012KF-121T50_0805
    1 2
    SUYIN_125022HB008M202ZL Cost down BATT fuse
    PL104 EMC@
    BATT+
    JBATT1
    HCB2012KF-121T50_0805
    1 1 2
    1 2
    9 2 3 EC_SMCA
    10 GND1 3 4 EC_SMDA
    GND2 4 5
    5 6
    6

    1
    7 PC106 PC107
    7 8 1000P_0402_50V7K 0.01U_0402_25V7K
    8
    EMC@ EMC@

    2
    ME@

    100_0402_1%
    PR105
    C C

    100_0402_1%
    PR106

    2
    2

    1
    PD103 EC_SMB_CK1 35,45
    AZC199-02S.R7G_SOT23-3
    EMC_NS@
    EC_SMB_DA1 35,45

    PR107 1 2 100K_0402_1%
    +3VALW

    BATT_TEMP_IN 1 2
    BATT_TEMP 35,45 A/D
    PR108
    10K_0402_5%

    B B

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 BATTERY CONN/OTP
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    B
    320ABR 0.2

    Date: Saturday, February 04, 2017 Sheet 44 of 50


    5 4 3 2 1
    5 4 3 2 1

    PQ201 P3 PJ201
    AON6414AL_DFN8-5
    PQ202
    AON7408L_DFN8-5 JUMP_43X79 PR201 V20B+
    P2 @ 0.01_1206_1%
    VIN 1 1
    S1
    2 2 5 2 1 1 4
    5 3 3 S2 D 2 1
    S3 2 3

    10U_0603_25V6-M

    10U_0603_25V6-M
    4

    4
    1

    1
    EMC_NS@

    EMC_NS@
    D D
    1

    1
    PC202
    PC201 PR202 0.022U_0402_25V7K

    PC203

    PC204
    2

    2
    4.7_0603_5%
    2

    470P_0402_50V7K

    5
    2

    1 2

    PC205 780s_BATDRV 4

    1
    PC206 0.1U_0402_25V6

    1
    1U_0603_25V6K PC207 PQ203
    0.1U_0402_25V6 AON6324_DFN8-5

    1
    VIN BATT+

    3
    2
    1
    1
    PR203
    499K_0402_1% PC208
    0.01U_0402_25V7K

    2
    BAT54CW_SOT323-3

    2
    780s_ACDRV_R

    PD201
    2

    3
    V20B+

    1780s_VCC_R 1
    VIN

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    1

    2
    EMC_NS@

    PC211
    4.02K_0603_1%

    4.02K_0603_1%

    ACN
    ACP
    PR206

    PR207

    PC212
    BQ24780S_VDD

    PC209
    2

    1
    1

    5
    PR209
    2

    1
    PR208 PC213 10_1206_5% PQ205

    D
    7.15K_0402_1% 43K_0402_1% 1U_0603_25V6K AON7408L_DFN8-5

    ACN
    ACP
    1 2
    780s_VCC

    2
    C PR210 1 2 28 24 1 2 C
    VCC REGN
    2

    2.2U_0603_10V6-K PC214 4
    1 2 780s_ACDET 6 PC216 G
    PC215 ACDET 0.047U_0603_16V7K

    S3
    S2
    S1
    0.01U_0402_25V7K 25 780s_BS
    1 2780s_BS_R
    2 1
    780s_CMSRC BTST PR211 PR213
    780s_ACDRV BATT+

    3
    2
    1
    2.2_0603_5% 0.01_1206_1%
    3 26 780s_HG
    @ CMSRC HIDRV
    PL201
    PR212 1 2 10K_0402_5% 1 2 1 4
    4 4.7UH_PCMB053T-4R7MS_4A_20%
    ACDRV 2 3
    @ 780s_LX

    1
    PR214 1 2 100K_0402_5% 27
    BQ24780S_VDD

    10U_0805_25V6K

    10U_0805_25V6K

    0.1U_0402_25V6
    PHASE

    EMC_NS@
    PR216

    D
    780s_ACOK

    1
    PR215 1 2 0_0402_5% 5 PQ206 4.7_0805_5%

    PC221

    PC217

    PC218
    35 ACIN ACOK
    780s_SDA
    PU201 AON7408L_DFN8-5 EMC_NS@
    PR217 1 2 0_0402_5% 11
    35,44 EC_SMB_DA1 SDA 780s_LG

    2
    23 4

    780s_SN
    LODRV G
    PR218 1 2 0_0402_5% 780s_SCL 12 22

    S3
    S2
    S1
    35,44 EC_SMB_CK1 SCL GND

    1
    PC222
    780s_IADP

    3
    2
    1
    PR219 1 2 0_0402_5% 7 29 1000P_0402_50V9-J
    35 ADP_I

    0.1U_0402_25V6

    0.1U_0402_25V6
    IADP PAD

    2
    780s_IDCHG 780s_BATDRV
    EMC_NS@

    1
    PR220 1 2 0_0402_5% 8 18

    PC223

    PC224
    35 IDCHG IDCHG BATDRV
    PR221 1 2 0_0402_5% 780s_PMON 9
    35 PSYS PMON 780s_BATSRC 780s_BATSRC_R

    2
    @ 17 1 2
    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    PR223 1 2 BATSRC PR222 10_0603_5%


    +3VALW 780s_SRP 780s_SRP_R
    10K_0402_1% 20 1 2
    10 SRP PR224 10_0603_5%
    35,50 VR_HOT# PROCHOT#

    1
    1

    13 PC228
    PR231 CMPIN
    0.1U_0402_25V6

    2
    BATPRES#
    1

    14
    TB_STAT#

    20K_0402_1%
    CMPOUT 19 780s_SRN 1 2 780s_SRN_R
    780s_ILIM 21 SRN PR225 10_0603_5%
    PC225

    PC226

    PC227

    ILIM
    2

    B B
    PR226
    780s_TB# 16

    15

    0_0402_5% BQ24780SRUYR_QFN28_4X4
    2

    1 2 780s_ILIM_R 1 2
    +3VALW BATT_TEMP 35,44
    PR227 14.7K_0402_1%
    316K_0402_1% PR228
    1
    1

    PR230
    PC229 100K_0402_1%
    0.1U_0402_25V6
    2

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 CHARGER


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    320ABR 0.2

    Date: Saturday, February 04, 2017 Sheet 45 of 50


    5 4 3 2 1
    5 4 3 2 1

    +3VALW

    1
    PR601
    V20B+ 100K_0402_5%
    D
    @ D
    @ PU601

    2
    1.5A 2
    PJ601
    1 +3VALW_VIN 5 9 +3VALW_PG
    2 1 4 IN1 PG 1 +3VALW_BS 1 2
    3 IN2 BS PC602

    PC601 EMC@
    +3VALW

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0201_25V6-K
    IN3

    1
    JUMP_43X79 2 0.1U_0603_25V7-M
    IN4 6 @

    PC603

    PC604
    LX1
    7
    GND1 LX2
    19
    +3VALW_LX
    PL601
    +3VALW_P
    PJ602
    5A

    2
    8 20 1 2 2 1
    18 GND2 LX3 2.2UH_PCMB053T-2R2MS_5.5A_20% 2 1

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    GND3

    1
    21
    GND4

    1
    PR602 JUMP_43X79
    +3VALW_EN 12 14 +3VALW_P 4.7_0805_5%

    PC605

    PC606

    PC607

    PC608
    +3VALW_VIN 11 EN1 OUT
    EN2 +3VALW_FB
    EMC_NS@

    2
    13
    FF

    2
    10
    Vout=3.3V± 5%
    100mA+3VLP
    16 NC1
    NC2

    +3VALW_SN
    @ 15 17
    Vset=3.37V± 1.5%

    1M_0402_5%
    0.1U_0201_25V6-K
    NC3 LDO

    PR603

    4.7U_0603_6.3V6K
    1
    OCP=12A

    PC610
    SY8286BRAC_QFN20_3X3

    1
    PC611
    OVP=(1.15~1.25)*Vout

    1
    PC612
    1000P_0402_50V9-J UVP=(0.55~0.65)*Vout
    EMC_NS@ Fsw=600Khz

    2
    PC613
    PR604
    PR605 PR611 1 2 +3VALW_FB_C 1 2
    0_0402_5% 0_0402_5%
    EC_ON 1 2 EC_ON_R 1 2 +3VALW_EN 1K_0402_1%
    35,47 EC_ON +3VL 1000P_0201_25V7K
    PR612 +3VLP @
    PD601 @ 0_0402_5% PJ603
    LRB751V-40T1G_SOD323-2 1 2 +5VALW_EN 2 1
    1 2 2 1
    C 35 MAINPWON C
    JUMP_43X39

    30 EC_ON_R

    +3VALW

    1
    PR606
    100K_0402_5%
    V20B+ @

    2
    @ PU602
    2.5A 2
    PJ604
    1 +5VALW_VIN 5 9
    2 1 4 IN1 PG 1 +5VALW_BS 1 2 ALW_PWRGD 47
    3 IN2 BS PC615 0.1U_0603_25V7-M @ +5VALW
    PC614 EMC@

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0201_25V6-K

    IN3
    1

    2
    JUMP_43X79 PL602 PJ605
    8A
    PC616

    PC617

    IN4 6 +5VALW_LX 1 2 +5VALW_P 2 1


    7 LX1 19 2.2UH_PCMB063T-2R2MS_8A_20% 2 1

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    GND1 LX2
    2

    8 20
    GND2 LX3
    1

    1
    18 JUMP_43X79
    B
    21 GND3 PR608 PR607
    B

    PC618

    PC619

    PC620

    PC621
    GND4 14 +5VALW_OUT 1 2 +5VALW_P 4.7_0805_5%
    +5VALW_EN OUT

    2
    12 0_0402_5% EMC_NS@
    +5VALW_VIN 11 EN1 13 +5VALW_FB
    EN2 FF Vout=5V± 3%
    2

    15
    100mA +5VLP
    LDO Vset=5.1V± 1.5%
    1+5VALW_SN

    @ 10
    0.1U_0201_25V6-K

    NC1
    4.7U_0603_6.3V6K

    +5VALW_VCC
    1

    16 17
    OCP=12A
    1M_0402_5%

    NC2 VCC
    1
    PC625

    PC624
    1U_0603_25V6M
    1

    OVP=(1.15~1.25)*Vout
    PR609

    PC626

    SY8288CRAC_QFN20_3X3
    PC627
    UVP=(0.55~0.65)*Vout
    2

    1000P_0402_50V9-J
    2

    EMC_NS@ Fsw=600Khz
    2

    PC628
    PR610
    1 2 +5VALW_FB_C 1 2

    1K_0402_1%
    1000P_0201_25V7K

    A A

    Security Classification LC Future Center Secret Data Title

    Issued Date 2017/02/04 Deciphered Date 2017/02/04 PWR_3VALW/5VALW


    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    C
    320ABR 0.2

    Date: Saturday, February 04, 2017 Sheet 46 of 50


    5 4 3 2 1
    5 4 3 2 1

    +5VALW LV5075_VCC

    @
    PR1903 1 2 10_0603_5% PR1901 1 2 0_0402_5%
    EC_ON 35,46
    PR1902 1 2 0_0402_5% LV5075_VDDQ_EN +5VLP
    35 1_2VEN

    LV5075_VTT_EN @
    PR1904 1 2 0_0402_5% PR1907 1 2 10_0603_5% PR1905 1 2 0_0402_5%
    35,37 SUSP# ALW_PWRGD 46

    PR1906 1 2 0_0402_5% LV5075_1P0VA_EN

    0.1U_0402_10V7K
    2.2U_0603_6.3V6K
    35 EC_APU_ALWEN

    PC1902

    PC1903
    D D
    LV5075_1P8VA_EN

    1
    PR1908 1 2 0_0402_5%

    +1.2V_B+
    2 10K_0402_5% LV507_0.775ALW_EN

    2
    PR1910 1 @

    LV5075_PMIC_EN
    PR1909 1 2 10_0402_5%
    LV5075_2.5V_EN

    LV5075_VSYS
    PR1911 1 2 0_0402_5%

    1 0.1U_0402_10V7K

    1 0.1U_0402_10V7K

    1 0.1U_0402_10V7K

    1 0.1U_0402_10V7K

    1 0.1U_0402_10V7K

    1 0.1U_0402_10V7K

    0.1U_0402_25V6
    35 2_5VEN

    PC1901
    2
    Vout=1.05V± 5% for ABR platform

    28

    27

    41
    PU1901

    9
    @ @ @ @ @ @ Vout=0.95V± 5% for AST platform

    VSYS

    PMIC_EN

    GND
    VCC
    LV507_0.775ALW_EN LV5075_EC_SMB_DA2 OCP=8~10A

    PC19042

    PC19052

    PC19062

    PC19072

    PC19082

    PC19092
    29 25 PR1925 1 2 0_0201_5%
    EN_LDO1 SDA EC_SMB_DA2 35
    LV5075_2.5V_EN 1 26 LV5075_EC_SMB_CK2 PR1926 1 2 0_0201_5%
    OVP=(1.15~1.25)*Vout
    EN_LDO2 SCL EC_SMB_CK2 35
    +3VALW
    LV5075_1P0VA_EN LV5075_ALERT# UVP=(0.55~0.65)*Vout
    11
    EN_V1P0A T_ALERT_B
    24 PR1912 1 2 0_0402_5%
    H_PROCHOT# 6,35 ABR:1.05V
    LV5075_1P8VA_EN 16 22 APUALW_PWRGD @
    AST:0.95V Fsw=1.2MHZ
    EN_V1P8A POK_V1P0A
    LV5075_VDDQ_EN 31 21 APUALW_PWRGD 4pcs 22uf for +/-5% tolerance
    +5VALW LV5075_VTT_EN
    EN_VDDQ POK_V1P8A
    LV5075_VDDQ_PGOOD1
    6pcs 22uf for +/-3% tolerance
    36 23
    EN_VTT POK_VDDQ
    PTC1901 @ Need change reference for BOM and standard +0.95VALW
    100K_0402_5%

    PAD
    1

    1.5A @
    12 LV5075_LX_1P0 @ 6A
    PR1915

    PJ1901 PL1901 PJ1902


    LV5075_V1P0_VIN LX_V1P0A_12 +1.05VS_P2
    1 2 7 13 1 2 1
    Vout=1.8V± 90mV

    LV5075AGQV_VQFN40_5X5
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    1 2 8 VIN_V1P0A_7 LX_V1P0A_13 14 0.47UH_CMMB062D-R47MS_15A_20% 2 1

    0.1U_0402_25V6
    VIN_V1P0A_8 LX_V1P0A_14

    1
    EMC_NS@
    15
    OCP=4.8~6A

    PC1910

    PC1911

    PC1912

    PC1913

    PC1914

    PC1915

    PC1916

    PC1917
    JUMP_43X39 JUMP_43X79
    LX_V1P0A_15
    2

    APUALW_PWRGD 35 +3VALW 10 +1.8VALW OVP=(1.15~1.25)*Vout


    VO_V1P0A

    2
    1.5A PJ1903
    @
    17 LV5075_LX_1P8 PL1902
    @ @
    PJ1904
    @ 3A UVP=(0.55~0.65)*Vout
    LV5075_V1P8_VIN LX_V1P8A_17 +1.8VA_P
    1
    1 2
    2 19
    VIN_V1P8A_19 LX_V1P8A_18
    18 1 2 2
    2 1
    1
    Fsw=1.2MHZ

    EMC_NS@
    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    1UH_PH041H-1R0MS_3.8A_20%

    0.1U_0402_25V6
    C C

    1
    20
    2pcs 22uf for +/-5% tolerance

    PC1918

    PC1919

    PC1920

    PC1921

    PC1922

    PC1923
    JUMP_43X39 JUMP_43X79
    VO_V1P8A_20

    LV5075_UG_1.2V
    3pcs 22uf for +/-3% tolerance

    2
    33
    38 UGATE_VDDQ
    +1.2V_PWM VIN_VTT LV5075_BST_1.2V
    PR1916
    LV5075_BST_1.2V_R @ @
    PC1924 1 2 10U_0603_6.3V6M 32 1 2
    BOOT_VDDQ
    1A PJ1905
    Vout=0.6V± 30mV +0.6VS
    2
    2 1
    1 +0.6VSP 39
    VTT 34 LV5075_LX_1.2V
    0_0603_5% PC1925
    1 2

    LV5075_LX_1P0

    LV5075_LX_1P8
    @ PHASE_VDDQ

    1
    Current Limit :Min 1.44A JUMP_43X39 PC1926 40 35 LV5075_LG_1.2V 0.1U_0603_25V7-M
    VSNS_VTT LGATE_VDDQ
    22U_0603_6.3V6-M
    +1.2V_PWM LDO1 Vout=0.775V

    2
    PR1917 @ 37
    +1.8VALW 1 2 LV5075_CS 30 VSNS_VDDQ
    Current Limit :Min 1.5A
    33K_0402_1% CS_VDDQ +0.775VALW
    @ UVP=(0.55~0.65)*Vout

    2
    1A 1
    PR1923
    2 LV5075_0.775VALW_VIN 5 6 +0.775VALW_P 1
    PJ1907
    2
    1A

    10U_0603_6.3V6M
    PR1918 PR1919
    VIN_LDO1 LDO1 1 2 4.7_0603_5% 4.7_0603_5%
    1

    1
    EMC_NS@ EMC_NS@

    PC1928
    0_0603_5%
    +3VALW PC1927 JUMP_43X39
    LDO2 Vout=2.5V

    1P0_SN 1

    1P8_SN 1
    10U_0603_6.3V6M
    2

    2
    +2.5V_P +2.5V FB reference=0.75V
    1A PR1924
    LV5075_2.5V_VIN LDO2
    3
    1 2 4
    VIN_LDO2 2
    Current Limit :Min 1.5A
    @
    FB_LDO2 V20B+
    1

    1
    0_0603_5%
    1
    PJ1910
    2
    1A UVP=(0.55~0.65)*Vout PC1930
    680P_0402_50V7K
    PC1931
    680P_0402_50V7K

    10U_0603_6.3V6M
    24.9K_0402_1%
    PC1934

    +2.5V_FB
    1 2

    1
    10U_0603_6.3V6M EMC_NS@ EMC_NS@

    PR1920
    2

    2
    FB=0.75V JUMP_43X39 @ 1A

    PC1935
    PJ1908
    +1.2V_B+ 1 2
    1 2

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    2

    EMC_NS@
    JUMP_43X39

    1
    PC1929

    PC1932

    PC1933
    1

    10.5K_0402_1%

    2
    PR1921
    @

    5
    B PQ1901 B

    D
    2
    AON7408L_DFN8-5

    LV5075_UG_1.2V 4
    G
    +1.2V

    S3
    S2
    S1
    @ 6A

    3
    2
    1
    PL1903 PJ1911
    LV5075_LX_1.2V 1 2 +1.2V_PWM 2 1
    0.47UH_CMMB062D-R47MS_15A_20% 2 1
    JUMP_43X79

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    5
    PR1922

    1
    PC1937

    PC1938

    PC1939

    PC1940

    PC1941

    PC1942
    PQ1902 4.7_0805_5%
    AON7506_DFN EMC_NS@

    2
    LV5075_LG_1.2V 4 @ @

    1.2V_SN
    3
    2
    1

    1
    PC1943
    680P_0402_50V7K
    Vout=1.2V± 60mV
    EMC_NS@ OCP=9A

    2
    OVP=(1.15~1.25)*Vout
    UVP=(0.55~0.65)*Vout
    Fsw=1MHZ
    4pcs 22uf for +/-5% tolerance
    6pcs 22uf for +/-3% tolerance

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 System PMIC
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    A2
    320ABR 0.2

    Date: Saturday, February 04, 2017 Sheet 47 of 50


    5 4 3 2 1
    A B C D

    1 1

    V20B+
    @
    2A 2
    PJ1401
    1 +1.35VGS_VIN
    2 1

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    PU1401
    +1.35VGS

    1
    JUMP_43X79 PX@ PR1401 PX@ PC1404 PX@

    PC1401

    PC1402

    PC1403
    0_0603_5% 0.1U_0603_25V7-M
    1 10 +1.35V_BST
    1 2+1.35V_BST_R 1 2 PL1401 PX@ @
    2 VIN BST

    2
    PR1451 PX@
    100K_0402_1% 9 +1.35V_LX
    0.47UH_PCMB053T-R47MS_13A_20%
    1 2 +1.35V_P 8A 2
    PJ1402
    1
    @ PX@ PX@ 2 1+1.35VGS_S3 16 SW 2 1

    NB685GQ-Z_QFN16_3X3
    EN1

    1
    JUMP_43X79

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    EN_1.35VGS +1.35V_FB

    1
    15 13 @
    EN2 FB

    1
    PR1402 PR1404 PC1405
    2.2_0805_5% 1M_0402_5% 220P_0402_50V7K

    PC1406

    PC1407

    PC1408

    PC1409

    PC1410
    PR1405 PX@ 12 6 +1.35V_P EMC_NS@ @ @
    PG VDDQ

    2
    4.7_0402_5%

    +1.35V_SN

    2
    1 2 +1.35VGS_3V3 3
    +3VALW 3V3 MPS_VTT

    2
    5
    VTT +1.35V_COMP PX@ PX@ PX@ PX@ PX@

    1
    PC1411 4 PC1412 PR1407
    1U_0402_6.3V6K AGND 8 1200P_0402_50V7-K 41.2K_0402_1%
    VTTS

    1
    PX@ 2 EMC_NS@
    2 PGND

    1
    7 MPS_VTTREF PR1406
    VTTREF 499_0402_1%

    22U_0603_6.3V6-M
    +1.35V_Mode
    14 11 @ @

    1U_0402_6.3V6K
    2
    MODE OTW# 2

    2
    1

    1
    Vout=1.35V± 5%

    PC1415

    PC1413
    1.35V_GND 2
    Vset=1.35V± 2%

    2
    PR1410 PX@
    0_0402_5% PX@
    OCP=13A

    1
    PR1408 PX@
    1

    7,19,49 PXS_PW REN


    200K_0402_1%
    1 2 EN_1.35VGS
    1.35V_GND PX@
    PR1411
    Vref=0.6V
    1.35V_GND
    PJ1404 @
    32.4K_0402_1%
    OVP=(1.25~1.35)*Vref
    1M_0402_5%

    .1U_0402_10V6-K

    2
    2

    1 2
    UVP=(0.7~0.8)*Vref
    1
    PR1412

    PC1416

    JUMPER
    Fsw=700Khz(Rmode=0)
    2

    1.35V_GND 1.35V_GND
    Fsw=500Khz(Rmode=150K)
    1

    PX@ PX@

    3 3

    4 4

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 1.35VGS
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
    A3 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320ABR
    Date: Saturday, February 04, 2017 Sheet 48 of 50
    A B C D
    5 4 3 2 1

    +VGA_B+ PJ2401 @ V20B+


    JUMP_43X79

    2 1
    5A
    2 1

    +5VALW +VDDIO_GPU
    EMC_PX@ PX@ PX@

    10U_0805_25V6K

    10U_0805_25V6K
    0.1U_0402_25V6
    PR2402 PX@

    1
    PX@ VGA_VCC VGA_VDDIO
    4.7_0402_5%
    1 2 2 1

    PC2402

    PC2403
    2

    2
    PX@

    PC2401
    PR2401

    AON6380_DFN8-5
    1 1
    For 196K resistor shortage, 4.7_0603_5%
    PC2404
    PC2405 PX@
    2.2U_0402_6.3V6-K
    D D
    change PR2408 to 100K,

    PQ2401
    2.2U_0402_6.3V6-K
    change PR2410 to 95.3K for SDV SMT. 2 2 +VGA_B+ VGA_UGATE1 4
    14 19
    VCC VDDIO VGA_VIN 2 1
    PX@ PX@ PX@ VGA_PVCC
    PR2405 PR2406 1 2 PR2404 PX@

    1
    0_0402_5% 11.3K_0402_1% PX@ 4.7_0402_5% PX@ PL2401
    2VGA_SET1_11

    3
    2
    1
    1 2 PR2403 1
    27 1
    PC2408
    VGA_PHASE1
    0.22UH_CMMS063T-R22MS2R107_26A_20%
    1 2
    21A
    0_0603_5% PX@ 1U_0402_25V6-K
    PVCC VIN +VGA_CORE

    2
    PC2407 PX@

    1
    EMC_PXNS@
    PX@ 2
    2.2U_0402_6.3V6-K

    1
    4.7_0805_5%
    PR2408 PX@ PR2410 PR2433

    330U_D2_2V_Y
    21

    PR2412

    330U_2.0V_M
    196K_0402_1% 0_0402_5% 0_0402_5%

    AON6324_DFN8-5

    AON6324_DFN8-5

    330U_D2_2V_Y
    VSEN 1 1 1
    1 VGA_SET1_2 VGA_SET1 11

    1
    2 2 1 PX@
    SET1 + + +
    PX@

    PC2413

    PC2406

    PC2410
    100P_0402_50V8J 150P_0402_50V8-J PR2434

    1VGA_ISEN1P_R2
    PX@ PC2411 2 1 2 1 PC2412

    PQ2403

    PQ2402
    PU2401 0_0402_5%
    VGA_LGATE1

    VGA_SN2
    PR2409 PX@ PR2413 PX@ PH2401 PX@ RT3662EBGQW_WQFN32_4X4 PX@ 4 4 PX@ 2 2 2
    69.8K_0402_1% 0_0402_5% 100K_0402_1%_TSM0B104F4251RZ PX@
    1 VGA_TSEN_2 2 1 VGA_TSEN_1 VGA_COMP

    2
    2 2 1 3 2 PR2414 1 2 1 PX@ @ PX@
    COMP
    VGA_FB
    30K_0402_1% PX@

    2
    4

    680P_0402_50V7K
    PR2415 PC2416 PX@ PX@ PX@
    VGA_TSEN 10 FB

    3
    2
    1

    3
    2
    1

    EMC_PXNS@
    10K_0402_1% 100P_0201_25V8J
    TSEN 2

    PC2417
    PR2417 PX@ PR2418 PX@ PR2419 PX@
    RGND

    1
    1
    0_0402_5% 32.4K_0402_1% 60.4K_0402_1% PR2407
    2 VGA_TSEN_3 1

    2
    1 2 2 1 PC2419 1.43K_0402_1%
    PX@ 0.1U_0402_25V6 PX@ PC2414 PX@

    2
    PR2411 @ 0.47U_0402_25V6K

    0.1U_0402_25V6
    2
    22 2.2_0603_5% 2 1 2 1
    VGA_VREF 13 NC 23 VGA_BOOT1 1 2
    VREF_PINSET BOOT1 @

    2
    PR2416 PX@

    PC2415
    PC2418
    VGA_UGATE1
    1

    24
    PR2420 PH2402 PX@ PX@ PX@
    UGATE1
    VGA_PHASE1 1
    0.1U_0402_25V6
    Close to PU2401 VGA_ISEN1P
    357_0402_1%
    2 1
    2VGA_BOOT1_R

    1
    3.9_0402_1% 100K_0402_1%_TSM0B104F4251RZ PR2422 PR2423 25
    PHASE1
    PX@ 12.1K_0402_1% 7.87K_0402_1% PX@
    1 2VGA_IMON_2 1 2 2 1 VGA_IMON 12 26 VGA_LGATE1 PC2409 PX@ PX@
    1VRFF_R_1

    IMON LGATE1
    2

    C 0.22U_0603_25V7K PR2436 C
    PR2425 PX@ 0_0201_5% VGA_ISEN1N
    14.3K_0402_1% VGA_CORE_SEN_L 1 2
    1 2 VGA_IMON_1 VGA_CORE_SEN 16
    7 VGA_ISEN1P
    PC2420 ISEN1P
    8 VGA_ISEN1N
    0.47U_0402_25V6K
    ISEN1N PX@
    2

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    PX@ PR2437
    9 0_0402_5% @ @ @ @ PX@ PX@ PX@ PX@
    16,35 GPU_VR_HOT# VRHOT_L VGA_VSS_SEN_L 1 2

    1
    15 VGA_VSS_SEN 16
    15 VGA_PWROK PWROK
    PX@

    PC2423

    PC2424
    PR2438
    1 2 VGA_PGOOD 20 31

    PC2421

    PC2422

    PC2425

    PC2426

    PC2427

    PC2428
    PGOOD BOOT2

    2
    7,15 VR_VGA_PWRGD 0_0201_5%

    30
    PR2426 PX@ UGATE2
    0_0402_5% +3VGS
    1 2 VGA_SVC 16 29
    16 GPU_SVC SVC PHASE2
    PR2427 PX@ +VDDIO_GPU
    0_0402_5% 28
    1 2 VGA_SVD 17 LGATE2
    16 GPU_SVD SVD
    PR2428 PX@
    1 2 VGA_SVT 18 VGA_CORE
    16 GPU_SVT SVT
    0_0402_5%

    2
    7,19,48 PXS_PWREN
    2 1 VGA_EN 32
    EN ISEN2P
    5 VGA_VCC
    PX@ PX@ PX@ Vboot=0.9V（CL K=1, DAT=0)
    PR2429 PX@
    PR2430
    10K_0402_5%
    PR2432
    10K_0402_5%
    PR2431
    10K_0402_5% Loadline=1.0mohm
    Ripple SEPC: DC=+-15mV AC=+50mV -30mV
    2

    200K_0402_1% PX@ 33
    GND

    VR_VGA_PWRGD1

    1
    6
    PC2429 ISEN2N TDC :21A

    GPU_VR_HOT#
    1

    1 2
    EDC=42A

    VGA_PWROK
    .1U_0402_10V6-K
    B B
    PD2401 @ OCP :50A(TBD)
    RB751V-40_SOD323-2
    OVP:1.8V
    UVP:VID-500mV
    FSW:400KH
    CHOKE DCR=2.1+-7% mohm

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 PWR-XXXX
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Size Document Number
    Custom 320ABR Rev
    0.2
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
    Date: Saturday, February 04, 2017 Sheet 49 of 50
    5 4 3 2 1
    5 4 3 2 1

    V20B+
    PR2269
    4.7_0603_5%
    1 2

    1
    PC2290
    .1U_0402_10V6-K

    +1.8VS

    2
    PR2225
    2.2_0603_5%
    1 2
    1
    +APU_CORE
    +5VALW PC2289
    FSW=400KHz
    2
    1U_0402_10V6K Close to APU TDC=22A
    PR2226
    4.7_0603_5% Close to PU2201 PR2253
    EDC=29A
    APU_VREF_PINSET 1 2 100_0402_1% OCP:40A
    1 2 +APU_CORE OVP=1.85V

    1
    PC2226
    PU2201
    1U_0603_6.3V7-K PR2290
    0_0402_5%
    PR2254
    0_0402_5%
    UVP=VID-500mV
    APU_CORE_VSEN
    Load Line=4mohm

    2
    PC2239 1 2 82P_0402_50V9-G PC2238 1 2 150P_0402_50V8-J 1 2 1 2 APU_VDDCORE_SEN_H 6
    APU_VCC APU_VIN
    17 28
    PR2224
    0_0402_5% VCC VIN Ripple:+/-20mv

    316K_0402_1%
    34.8K_0402_1%

    69.8K_0402_1%

    330P_0402_50V8J
    MAX AC: VID_APU_CORE +70mv
    1

    D 1 1 2 PR2250 1 2 37.4K_0402_1% PR2249 1 2 10K_0402_1% PR2256 D


    APU_VDDIO_R

    1
    22 100_0402_1%
    PR2271

    PR2272

    PR2273

    PC2255
    VDDIO MIN AC: VID_APU_CORE -20mv

    1
    PC2227 1 2
    APU_PVCC
    1U_0603_6.3V7-K 34
    PVCC APU_CORE_VSEN_R

    2
    8 PR2202 PR2255
    VSEN
    Choke DCR=0.98+-5%mohm
    2

    2
    @ 0_0402_5% 0_0402_5%
    APU_CORE_RGND

    1
    PC2292 1 2 1 2
    0.1U_0402_25V6 APU_VDD_SEN_L 6
    APU_SET1 13
    SET1 APU_CORE_COMP @

    2
    PR2232 5
    60.4K_0402_1% COMP
    1 2 6 APU_CORE_FB V20B+
    APU_TSEN_CORE_R
    PH2203
    APU_TSEN_CORE
    FB APU_CORE_VIN @
    1 2 12
    TSEN 4 APU_CORE_RGND_R 2
    PJ2202
    1
    4A
    RGND 2 1

    5
    100K_0402_1%_TSM0B104F4251RZ 1

    10U_0805_25V6K

    10U_0805_25V6K

    EMC_NS@
    JUMP_43X79

    68U_25V_M
    0.1U_0402_25V6
    AON6380_DFN8-5

    1
    PR2218 +

    PC2229

    PC2230

    PC2232

    PC2231
    APU_CORE_BOOT1 CORE_BOOT_R
    60.4K_0402_1% 38 1 2 1 2
    APU_TSEN_NB_R 1 2 APU_TSEN_NB 23 BOOT

    PQ2203
    TSEN_NB +APU_CORE

    2
    PR2237 PC2233 4 2
    APU_VREF_PINSET 1 2 PH2202 2.2_0603_5% 0.1U_0603_25V7-M
    1

    100K_0402_1%_TSM0B104F4251RZ
    15K_0402_1%

    33K_0402_1%

    24K_0402_1%

    37 APU_CORE_UGATE1
    PR2201
    PR2270

    PR2235

    PR2219

    0_0402_5% UGATE
    APU_VREF_PINSET_R

    3
    2
    1
    1 2 15 PL2202
    VREF_PINSET
    APU_IMON_CORE_R APU_CORE_PHASE1 APU_CORE_PHASE1
    0.22UH_PCME064T-R22MS0R985_28A_20%
    22A
    2

    PR2275 1 2 14.7K_0402_1% 36 1 2
    PR2287 PR2231 PHASE

    1
    3.9_0402_1% PH2205 8.87K_0402_1% PR2284

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    APU_IMON_CORE_NTC APU_IMON_CORE
    1 2 1 2 1 2 14 PR2283 0_0402_5% 1 1@ 1 @

    330U_2.0V_M
    330U_D2_2V_Y

    330U_D2_2V_Y
    APU_CORE_LGATE1 PR2268

    AON6324_DFN8-5

    AON6324_DFN8-5
    PR2276 11.8K_0402_1% IMON 35

    PC2251
    LGATE 4.7_0805_5% 0_0402_5%
    2

    1
    100K_0402_1%_TSM0B104F4251RZ PR2242 PC2244 + + +

    PC2249

    PC2250

    PC2253

    PC2276

    PC2277
    PR2227 EMC_NS@ 1.24K_0402_1% 0.47U_0402_25V6K

    PQ2204

    PQ2205
    APU_CORE_ISEN+

    1CORE_SN 2

    2
    1

    6.34K_0402_1% 4 4 1 2 1 2
    APU_IMON_NB_R APU_IMON_NB

    2
    PC2286 PR2277 1 2 13.7K_0402_1% 1 2 16 2 2 2
    IMON_NB APU_CORE_ISEN1P
    0.47U_0402_25V6K 9 PR2243
    ISEN1P
    2

    1.24K_0402_1%
    1 2 APU_IMON_NB_NTC 1 2 APU_CORE_ISEN1P 1 2
    PH2206
    APU_CORE_ISEN1N

    3
    2
    1

    3
    2
    1
    PR2278 13K_0402_1% 100K_0402_1%_TSM0B104F4251RZ 10 PC2234
    +3VS ISEN1N 680P_0402_50V7K

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    APU_VR_HOT_L

    1
    1 2 11 @
    VRHOT_L EMC_NS@ APU_CORE_ISEN1N

    2
    1

    35,45 VR_HOT# PR2222 0_0402_5% PC2237

    1
    PR2233

    PC2278

    PC2279

    PC2280

    PC2281

    PC2282

    PC2283

    PC2284

    PC2285
    APU_PWROK_R 0.1U_0402_25V6

    2
    1.91K_0402_1% 1 2 18
    6 APU_PWROK PWROK APU_NB_VSEN_R
    PR2230 0_0402_5% 7 PR2289 1 2 0_0402_5%
    VSEN_NB

    2
    VR_APU_PGOOD_R
    2

    1
    1 2 3
    35 VR_APU_PWRGD PR2234 0_0402_5% PGOOD PC2291 Close to PU2201 Close to APU
    0.1U_0402_25V6

    2
    @ PC2206 1 2 82P_0402_50V9-G PC2205 1 2 150P_0402_50V8-J PR2204
    100_0402_1%
    APU_SVC_R APU_NB_COMP APU_NB_VSEN
    1 2 19 27 PR2206 1 2 43K_0402_1% PR2205 1 2 10K_0402_1% 1 2 +APU_CORE_NB
    6 APU_SVC SVC COMP_NB
    PR2220 0_0402_5%
    PR2208
    APU_SVD_R APU_NB_FB
    1 2 20 26 0_0402_5%
    6 APU_SVD SVD FB_NB 1 2
    PR2223 0_0402_5% APU_VDDNB_SEN_H 6
    C 1 2 APU_SVT_R 21 C
    PR2211 PC2211
    6 APU_SVT SVT
    PR2228 0_0402_5% 2.2_0603_5% 0.1U_0603_25V7-M
    APU_NB_BOOT BOOT_NB_R
    30 1 2 1 2
    BOOT_NB

    APU_CORE_NB_VIN V20B+
    @
    +APU_CORE_NB
    APU_EN_R
    FSW=400KHz

    5
    1 2 29
    35 EC_VR_ON
    0_0402_5% EN 31 APU_NB_UGATE 2
    PJ2201
    1
    2A
    PR2229
    TDC=18A

    AON6380_DFN8-5
    UGATE_NB 2 1

    10U_0805_25V6K

    10U_0805_25V6K
    1

    EMC_NS@
    JUMP_43X79
    EDC=24A

    0.1U_0402_25V6
    1

    PC2209
    PC2207

    PC2208
    PQ2201
    PR2288
    1M_0402_5%

    1
    NC1 APU_NB_PHASE
    4
    +APU_CORE_NB OCP:35A
    32
    PHASE_NB OVP=1.85V

    2
    2

    2
    NC2 0.36UH_PCMB063T-R36MS_20A_20%
    UVP=VID-500mA
    Load Line=4mohm

    3
    2
    1
    39 33 APU_NB_LGATE APU_NB_PHASE
    PL2201
    1 2
    18A
    NC3 LGATE_NB Ripple:+/-20mv
    MAX AC: VID_APU_CORE_NB +70mv

    1
    5
    40 PR2214 PR2215
    NC4 25 APU_NB_ISENP PR2212
    4.7_0805_5% 0_0402_5% 0_0402_5% MIN AC: VID_APU_CORE_NB -40mv

    AON6324_DFN8-5
    ISENP_NB PR2280 PC2287 1 1

    330U_2.0V_M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M

    22U_0603_6.3V6-M
    330U_D2_2V_Y
    EMC_NS@ 1.5K_0402_1% 0.47U_0402_25V6K @ @
    APU_NB_ISENN APU_NB_ISEN+
    Choke DRC=3.3(typ)~3.9(max)mohm

    NB_SN 2

    1
    41 24 1 2 1 2 + +

    PQ2202

    PC2214

    PC2215
    GND ISENN_NB 4

    PC2270

    PC2271

    PC2272

    PC2273

    PC2274

    PC2275
    2

    2
    2 2

    1
    RT3661ABGQW_WQFN40_5X5
    PC2288

    1
    0.1U_0402_25V6 PC2222

    3
    2
    1
    680P_0402_50V7K
    EMC_NS@

    2
    PR2281
    374_0402_1%
    1 2

    +1.8VS

    PRE-PWROK METAL VID CODES

    SVC SVD Boot Voltage +1.8VS


    @ @ @
    1

    0 0 1.1V
    1K_0402_1%

    1K_0402_1%

    1K_0402_1%
    PR2262

    PR2263

    PR2264

    0 1 1.0V
    1 0 0.9V(Default)
    2

    @ @
    1U_0402_6.3V6K
    .1U_0402_10V6-K

    B B
    1 1 0.8V
    1

    1
    PC2268

    PC2269

    APU_SVC_R

    APU_SVD_R
    2

    APU_SVT_R

    @ @ @
    1

    1
    220_0402_5%

    220_0402_5%

    220_0402_5%
    PR2265

    PR2266

    PR2267
    2

    A A

    Security Classification LC Future Center Secret Data Title


    Issued Date 2017/02/04 Deciphered Date 2017/02/04 PWR_CPU Core
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
    A1 0.2
    DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. 320AST
    Date : Saturday, February 04, 2017 Sheet 50 of 50

    5 4 3 2 1

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