Ug1075 Zynq Ultrascale PKG Pinout

Zynq UltraScale+ Device
Packaging and Pinouts
Product Specification User Guide
UG1075 (v1.11) January 18, 2022
Xilinx is creating an environment where employees, customers,

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standards. Follow this link for more information.
Revision History
The following table shows the revision history for this document.
Date Version Revision

1/18/2022 1.11 Added the XCZU1CG, XCZU1EG, XCZU42DR, XCZU65DR, and XCZU67DR devices
throughout document. Added XQZU48DR and XQZU49DR. Added the UBVA494,
FSRG1517, and FSRF1760 packages where applicable.
Chapter 1, Packaging Overview: Added Note 1 to Table 1-5 and updated links to
Note 2 in Table 1-6. Updated and corrected bank diagrams Figure 1-36 and
Figure 1-54.
Chapter 2, PS Memory Interface Pin Guidelines: Corrected the Important note on
page 100. Updated some of the descriptions in Table 2-1 and Table 2-2 to avoid
confusion. In Table 2-4, corrected the PS_DDR_ODT1 for LPDDR3 64-bit entry (can be
left unconnected).
Chapter 5, Mechanical Drawings: Added links to the MDDS file information. Updated
Figure 5-21 with the correct diagram.
Chapter 8, Soldering Guidelines: Updated the Important note on page 271.
Chapter 10, Edge Bonding Guidelines: Added the Important note on page 286.
Chapter 12, Thermal Management Strategy: Updated the Applied Pressure from Heat Sink
to the Package via Thermal Interface Materials and added Table 12-1.
7/01/2021 1.10 Added InFO package (UBVA530) throughout.
Chapter 5, Mechanical Drawings: Added Figure 5-21 and Figure 5-22. Updated A 3
and A 4 dimensions in Figure 5-21, Figure 5-29, and Figure 5-34.
Chapter 8, Soldering Guidelines: Updated Pb-Free Reflow Soldering to include
Table 8-2, Figure 8-3, and Figure 8-4. Added the Strain Gauge Measurement, Solder
Paste, and Component Placement sections.
Chapter 9, Recommended PCB Design Rules for BGA Packages: Added Stencil section.
Chapter 10, Edge Bonding Guidelines: Added chapter.
6/24/2020 1.9 Added the XCZU43DR, XCZU47DR, XCZU46DR, XCZU48DR, and XCZU49DR devices
throughout document. Added the FFVH1760 and FSVH1760 packages throughout
document.
Chapter 2, PS Memory Interface Pin Guidelines: Updated the DDR3/3L Pinout
Example for Supported Configurations, DDR4 Pin Rules, DDR4 Pinout Example for
Supported Configurations, and LPDDR3 Pinout Example for Supported
Configurations sections. Clarified the headings in Table 2-4 and updated the LPDDR3
64-bit column for PS_DDR_CKE0, PS_DDR_CKE1, PS_DDR_CS_N0, and PS_DDR_ODT0.
Chapter 6, Package Marking: Added a new top-mark diagram (Figure 6-1).
Chapter 8, Soldering Guidelines: Updated and removed notes linking to data sheets
for reflow body temperatures.
Chapter 11, Thermal Specifications: Added links to Package Thermal Data Query for
thermal simulation data.
Zynq UltraScale+ Packaging and Pinouts Send Feedback

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UG1075 (v1.11) January 18, 2022 www.xilinx.com
7/12/2019 1.8 Added the XAZU7EV, XAZU11EG, XCZU39DR, XQZU3EG, XQZU9EG, XQZU11EG,
XQZU19EG, XQZU21DR, XQZU28DR, and XQZU29DR devices throughout. Added the
SFRA484, FFRD1156, FFRE1156, FFRB1517, FFRG1517, FFRC1760, and FFRF1760
packages where applicable.
Updated the recommended applied pressure range on page 300.
1/31/2019 1.7 Chapter 1: Added an Important Note about XQ devices with eutectic BGA balls on
page 13. Added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156),
and XQZU15EG (FFRC900, FFRB1156) device/package combinations to Table 1-1,
Table 1-2, Table 1-3, Table 1-6, Table 1-7, and the associated bank diagram figures in
this section. In Table 1-4, added the type and direction data for VCCO_PSIO[0:3]_
[500:503] and VCCO_PSDDR. Added a note for XQ ruggedized packages to
VCCAUX_IO. Revised the GTH Quad 229 coordinates in Figure 1-21. Fixed GTH Quad
location errors in Figure 1-27 through Figure 1-29.
Chapter 2: Updated the DDR3/3L Pinout Example for Supported Configurations
description and added VCCO_PSDDR and Note 1 to Table 2-1. Updated the DDR4
Pinout Example for Supported Configurations description and added VCCO_PSDDR
to Table 2-2 and Note 1. Also in Table 2-2, added to guidelines for PS_DDR_A17, and
PS_DDR_DQ32 to PS_DDR_DQ63. Updated the LPDDR4 Pinout Example for Supported
Configurations description and added VCCO_PSDDR to Table 2-3 and Note 1.
Updated the LPDDR3 Pinout Example for Supported Configurations description and
added VCCO_PSDDR to Table 2-4 and Note 1.
Chapter 3: Added an Important Note about XQ devices with eutectic BGA balls on
page 123. Added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900, FFRC1156),
and XQZU15EG (FFRC900, FFRB1156) device/package combinations to Table 3-1
labeled as production.
page 128. In Table 4-1, added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900,
FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations.
page 224. In Table 5-1, added the XQZU5EV (SFRC784, FFRB900), XQZU7EV (FFRB900,
FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package combinations.
Added Figure 5-8, Figure 5-13, Figure 5-16, and Figure 5-17.
Chapter 6: Updated Table 6-1 and added Figure 6-3.
page 270. In Table 7-1, added the ruggedized packages (SFRC784, FFRB900, FFRC900,
FFRB1156, and FFRC1156).
Chapter 8: Updated the chapter with more information on eutectic packages
including adding the Sn/Pb Reflow Soldering section. In Table 8-3, added the
ruggedized packages (SFRC784, FFRB900, FFRC900, FFRB1156, and FFRC1156).
page 291. In Table 11-1, added the XQZU5EV (SFRC784, FFRB900), XQZU7EV
(FFRB900, FFRC1156), and XQZU15EG (FFRC900, FFRB1156) device/package
combinations.

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8/20/2018 1.6 Chapter 1: Added the XAZU4EV and XAZU5EV devices in the SFVC784 package. This
includes updates to Table 1-2, Table 1-3, Table 1-5, Table 1-6, Table 1-7, Figure 1-12,
and Figure 1-13. Corrected the VCCO_PSDDR pin name (from VCCO_PSDDR_504) in
Table 1-4. Added a note to Figure 1-8 on page 51.
Chapter 2: Clarified what a byte lane includes in the pin swapping restrictions
discussions on page 100 and page 104.
Chapter 3: Added the XAZU4EV and XAZU5EV devices to Table 3-1. Labeled all of the
devices in Table 3-2 as production.
Chapter 4: In Table 4-1, added the XAZU4EV and XAZU5EV devices and changed the
XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR device labels to
production. Added a note above Figure 4-3 on page 136. Added the XAZU4EV and
XAZU5EV devices in the SFVC784 package to Figure 4-19 and Figure 4-20.
Chapter 5: Added the XAZU4EV and XAZU5EV devices to Table 5-1 and Figure 5-9.
Labeled all of the devices in Table 5-2 as production.
Chapter 11: Added the XAZU4EV and XAZU5EV devices to Table 11-1.
4/10/2018 1.5 Chapter 1: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR
devices. This includes updates to Table 1-1, Table 1-2, Table 1-3, Table 1-4, Table 1-5,
Table 1-6, and Table 1-7. Added Figure 1-36 through Figure 1-47.
Chapter 3: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and XCZU29DR
ASCII file links, see Table 3-2.
devices to Table 4-1.
mechanical drawings, see Table 5-2.
Chapter 7: Added the FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517,
FFVF1760, and FSVF1760 packages to Table 7-1.
Chapter 8: Revised the guidelines in Table 8-1 for Ramp-up rate, Peak temperature
(lead/ball), and Peak temperature (body). Revised the same information in Figure 8-2.
Added the FFVD1156, FFVE1156, FSVE1156, FFVG1517, FSVG1517, FFVF1760, and
FSVF1760 packages to Table 8-3.
Chapter 11: Added the XCZU21DR, XCZU25DR, XCZU27DR, XCZU28DR, and
XCZU29DR devices to Table 11-1 and added Note 1.
Chapter 12: Updated the System Level Heat Sink Solutions section and added the
Heat Sink Removal and Measurement Debug sections.

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12/21/2017 1.4 Added the XAZU2EG and XAZU3EG devices throughout the document.
Chapter 1: Revise the VCCINT_VCU description in Table 1-4. Updated the ZU11EG
(Figure 1-22 through Figure 1-26) PCIE4 bank coordinates.
Chapter 2: Updated LPDDR4 Pin Swapping Restrictions and DDR4 Pin Swapping
Restrictions and removed Figure 2-1: DDR Controller Implementation of DQ
Mapping. In Table 2-2, updated the PS_DDR_ZQ connections.
Chapter 5: Revised Figure 5-10: Symbol A from (2.57/2.77/2.97) to (2.48/2.68/2.88)
and Symbol A2 from (1.27/1.42/1.62) to (1.18/1.33/1.48).
Chapter 6: Revised the top mark diagram to show both older device versions and
newer ones with a 2D bar code.
Chapter 8: Added an Important note on page 271 about reflow rework.
Chapter 11: Updated the SFVC784, FFVC900, FFVB1156, FFVC1156, FFVB1517,
FFVF1517 data to account for the stamped lid in Table 11-1.
8/29/2017 1.3 In Chapter 1, updated Figure 1-8, Figure 1-19, Figure 1-20, Figure 1-21, Figure 1-27,
Figure 1-28, Figure 1-29, Figure 1-30, Figure 1-31, Figure 1-32, Figure 1-33, and
Figure 1-34. Revise the VCCINT_VCU description in Table 1-4.
In Chapter 2, updated the DDR4 Pin Rules and the DDR4 Pin Swapping Restrictions.
In Table 2-2, updated the configurations for PS_DDR_CK_N1 (DDR4 1Rank).
In Chapter 3, updated the package specification designation of many of the packages
listed in Table 3-1.
In Chapter 4, updated Table 4-1 and added the following device diagrams: SFVC784
Package–XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG, SFVC784 Package–XCZU4EV,
XCZU5EV, XAZU4EV, and XAZU5EV, FBVB900 Package–XCZU4CG, XCZU4EG, XCZU5CG,
and XCZU5EG, FBVB900 Package–XCZU4EV and XCZU5EV, FFVF1517
Package–XCZU7CG and XCZU7EG, FFVC1156 Package–XCZU7EV, FFVC1156
Package–XCZU11EG, FFVB1517 Package–XCZU11EG, FFVF1517 Package–XCZU11EG,
and FFVC1760 Package–XCZU11EG.
In Chapter 5, replaced Figure 5-9, added Figure 5-10, Figure 5-11, Figure 5-25, and
Figure 5-36.
In Table 8-3, update the FFV packages to a mass reflow of 245°C.
1/13/2017 1.2 Added the following devices throughout: XCZU2CG, XCZU3CG, XCZU4CG, XCZU4EG,
XCZU5CG, XCZU5EG, XCZU6CG, XCZU7CG, XCZU7EG, and XCZU9CG. In Table 1-3,
revised the available PS I/O pin values for the SBVA484 and SFVA625 packages. In
Table 1-4, updated the PS_MODE directions and the pin descriptions in the
Power/Ground Pins section. In Table 1-6, revised the XCZU4 bank numbers and
updated the FBVB900 mapping. Revised the mapping for the FBVB900 package in
Table 1-7. Revised the Bank Locations of Dedicated and Multi-Function Pins section.
Updated the HD I/O bank numbers in Figure 1-26.
Added Chapter 2, PS Memory Interface Pin Guidelines. Added the Chapter 3, Package
Specifications Designations section. In Table 3-1, updated links. Chapter 4, Device
Diagrams and Chapter 5, Mechanical Drawings have updated tables and new
diagrams. Revised the Bar Code section of Table 6-1 to include changes outlined in
XCN16014: Top Marking change for 7 Series, UltraScale, and UltraScale+ Products.
Updated the AUTOMOTIVE APPLICATIONS DISCLAIMER.

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6/14/2016 1.1 In Table 1-3, updated Note 1 and the SBVA484 package total user HP I/Os. Clarified
the I2C_SCLK and I2C_SDA descriptions and added SMBALERT and VCCINT_VCU to
Table 1-4. Also updated the Multi-gigabit Serial Transceiver Pins (GTHE4, GTYE4, and
PS-GTR) descriptions, Added further descriptions in the Die Level Bank Numbering
Overview including adding an example device diagram (Figure 1-1). In Chapter 4,
added new figures and updated all of the graphics because the PERSTN pins and
SMBALERT pins have moved. Updated Figure 5-16 and added Figure 5-18. Added the
bar code description in Chapter 6.
1/20/2016 1.0.2 Replaced the missing graphics in Chapter 1.
12/18/2015 1.0.1 Updated the package file links in Chapter 3.
11/24/2015 1.0 Initial Xilinx release.

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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Packaging Overview

Introduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Zynq UltraScale+ Device Packaging and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device/Package Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Gigabit Transceiver Channels by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
User I/O Pins by Device/Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Footprint Compatibility between Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Die Level Bank Numbering Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 2: PS Memory Interface Pin Guidelines

Introduction to PS Memory Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DDR3/3L Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DDR4 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LPDDR4 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LPDDR3 Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Chapter 3: Package Files

About ASCII Package Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Package Specifications Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
ASCII Pinout Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Chapter 4: Device Diagrams

Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
SBVA484 Package–XCZU1CG, XCZU1EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
SBVA484 Package–XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 136
UBVA494 Package–XCZU1CG, XCZU1EG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
UBVA530 Package–XCZU2CG, XCZU2EG, XCZU3CG, and XCZU3EG . . . . . . . . . . . . . . . . . . . . . . . . 140
SFVA625 Package–XCZU1CG, XCZU1EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SFVA625 Package–XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 144

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SFVC784 Package–XCZU1CG, XCZU1EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
SFVC784 Package–XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and XAZU3EG . . . . . . . 148
SFVC784 Package–XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG . . . . . . . . . . . . . . . . . . . . . . . . . 150
SFVC784 Package–XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV . . . . . . . . . . . . . . . . . . . . . . . . . 152
FBVB900 Package–XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG . . . . . . . . . . . . . . . . . . . . . . . . . 154
FBVB900 Package–XCZU4EV and XCZU5EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
FBVB900 Package–XCZU7CG and XCZU7EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
FBVB900 Package–XCZU7EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
FFVC900 Package–XCZU6EG, XCZU9EG, and XCZU15EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
FFVB1156 Package–XCZU6EG, XCZU9EG, and XCZU15EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
FFVC1156 Package–XCZU7CG and XCZU7EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
FFVC1156 Package–XCZU7EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
FFVC1156 Package–XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
FFVD1156 Package–XCZU21DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
FFVE1156 and FSVE1156 Packages–XCZU25DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
FFVE1156 and FSVE1156 Packages–XCZU27DR and XCZU28DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
FFVB1517 Package–XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
FFVB1517 Package–XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
FFVF1517 Package–XCZU7CG and XCZU7EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
FFVF1517 Package–XCZU7EV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
FFVF1517 Package–XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
FFVG1517 and FSVG1517 Packages–XCZU25DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
FFVG1517 and FSVG1517 Packages–XCZU27DR and XCZU28DR . . . . . . . . . . . . . . . . . . . . . . . . . . 202
FFVG1517, FSVG1517 Packages–XCZU48DR FSRG1517 Package–XQZU48DR . . . . . . . . . . . . . . . . 208
FFVC1760 Package–XCZU11EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
FFVC1760 Package–XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
FFVD1760 Package–XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
FFVF1760 and FSVF1760 Packages–XCZU29DR and XCZU39DR . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
FFVF1760 and FSVF1760 Packages–XCZU49DR
FSRF1760 Package–XQZU49DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
FFVH1760 and FSVH1760 Packages–XCZU46DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
FFVE1924 Package–XCZU17EG and XCZU19EG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

8
Chapter 5: Mechanical Drawings
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SBVA484 Flip-Chip, Fine-Pitch BGA (XCZU1CG and XCZU1EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
SBVA484 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3, XAZU2EG, and XAZU3EG) . . . . . . . . . . . . . . 231
SFRA484 Flip-Chip, Fine-Pitch BGA (XQZU3EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
UBVA494 Flip-Chip, Fine-Pitch BGA (XCZU1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
UBVA530 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
SFVA625 Flip-Chip, Fine-Pitch BGA (XCZU1CG and XCZU1EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
SFVA625 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3, XAZU2EG, and XAZU3EG). . . . . . . . . . . . . . . 236
SFRC784 Ruggedized Flip-Chip BGA (XQZU3EG and XQZU5EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
SFVC784 Flip-Chip, Fine-Pitch BGA (XCZU1, XCZU2, XAZU2EG, XCZU3, XAZU3EG, XCZU4, XAZU4EV,
XCZU5, and XAZU5EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU4CG, XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, and
XCZU5EV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU7CG, XCZU7EG, XCZU7EV, and XAZU7EV) . . . . . . . . . . 240
FFRB900 (XQZU7EV) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and XQZU15EG) Ruggedized Flip-Chip BGA . . . . . 242
FFVC900 Flip-Chip, Fine-Pitch BGA (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG). 243
FFRB1156 Ruggedized Flip-Chip BGA (XQZU9EG and XQZU15EG) . . . . . . . . . . . . . . . . . . . . . . . . . 244
FFVB1156 Flip-Chip, Fine-Pitch BGA (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG) 245
FFRC1156 Ruggedized Flip-Chip BGA (XQZU7EV and XQZU11EG) . . . . . . . . . . . . . . . . . . . . . . . . . 246
FFVC1156 Flip-Chip, Fine-Pitch BGA
(XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
FFRD1156 (XQZU21DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
FFRE1156 (XQZU28DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
FFVD1156 (XCZU21DR) and FFVE1156 (XCZU25DR–XCZU27DR, XCZU42DR–XCZU48DR,
XCZU65DR–XCZU67DR) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
FSVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip,
Fine-Pitch, Lidless w/Stiffener Ring BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
FSVE1156 (XCZU42DR, XCZU65DR, XCZU67DR) Flip-Chip, Fine-Pitch, Lidless w/Stiffener Ring BGA. .
252
FFRB1517 (XQZU19EG) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV,
XCZU11EG, and XAZU11EG) Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
FFRG1517 (XQZU28DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
FFVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR)
Flip-Chip, Fine-Pitch BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
FSRG1517 (XQZU48DR) Ruggedized Flip Chip, Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . 257
FSVG1517 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip,
Fine-Pitch, Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
FFVC1760 and FFVD1760 Flip-Chip, Fine-Pitch BGA
(XCZU11EG, XCZU17EG, and XCZU19EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

9
FFRC1760 Ruggedized Flip-Chip BGA
(XQZU11EG and XQZU19EG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
FFVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FFVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch BGA
261
FFRF1760 (XQZU29DR) Ruggedized Flip-Chip BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
FSVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and FSVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch,
Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
FSRF1760 (XQZU49DR) Ruggedized Flip Chip, Lidless with Stiffener Ring BGA . . . . . . . . . . . . . . . 264
FFVE1924 Flip-Chip, Fine-Pitch BGA (XCZU17EG, and XCZU19EG) . . . . . . . . . . . . . . . . . . . . . . . . . 265
Chapter 6: Package Marking

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Chapter 7: Packing and Shipping

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Chapter 8: Soldering Guidelines

Soldering Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Conformal Coating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Strain Gauge Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Solder Paste . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Chapter 9: Recommended PCB Design Rules for BGA Packages

BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Stencil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Chapter 10: Edge Bonding Guidelines

Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Edge Bonding Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Edge Bond Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Chapter 11: Thermal Specifications

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Thermal Resistance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Support for Thermal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Chapter 12: Thermal Management Strategy

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Thermal Interface Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Heat Sink Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

10
Measurement Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Chapter 13: Heat Sink Guidelines for Bare-die Flip-Chip Packages

Heat Sink Attachments for Bare-die FB Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Types of Heat Sink Attachments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Appendix A: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

11
Chapter 1
Packaging Overview
Introduction to the UltraScale Architecture

The Xilinx® UltraScale™ architecture is the first ASIC-class architecture to enable
multi-hundred gigabit-per-second levels of system performance with smart processing,
while efficiently routing and processing data on-chip. UltraScale architecture-based devices
address a vast spectrum of high-bandwidth, high-utilization system requirements by using
industry-leading technical innovations, including next-generation routing, ASIC-like
clocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new power
reduction features. The devices share many building blocks, providing scalability across
process nodes and product families to leverage system-level investment across platforms.
Virtex® UltraScale+™ devices provide the highest performance and integration capabilities
in a FinFET node, including both the highest serial I/O and signal processing bandwidth, as
well as the highest on-chip memory density. As the industry's most capable FPGA family,
the Virtex UltraScale+ devices are ideal for applications including 1+Tb/s networking and
data center and fully integrated radar/early-warning systems.
Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET

node, delivering the most cost-effective solution for high-end capabilities, including
transceiver and memory interface line rates as well as 100G connectivity cores. Our newest
mid-range family is ideal for both packet processing and DSP-intensive functions and is well
suited for applications including wireless MIMO technology, Nx100G networking, and data
center.
Zynq® UltraScale+ MPSoC devices provide 64-bit processor scalability while combining
real-time control with soft and hard engines for graphics, video, waveform, and packet
processing. Integrating an Arm®-based system for advanced analytics and on-chip
programmable logic for task acceleration creates unlimited possibilities for applications
including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.
Zynq UltraScale+ RFSoC integrate the key subsystems required to implement a complete
software-defined radio including direct RF sampling data converters, enabling CPRI and
gigabit Ethernet-to-RF on a single, highly programmable SoC. Each device offers multiple
RF-sampling analog-to-digital (RF-ADC) and RF-sampling digital-to-analog (RF-DAC) data
converters. The data converters are high-precision, high-speed and power efficient.
For the latest Zynq UltraScale+ device descriptions, specifications, data sheets, and user
guides are available at www.xilinx.com/documentation.

12
Zynq UltraScale+ Device Packaging and Pinouts

This section describes the packages and pinouts for the in various organic flip-chip 0.5 mm,
0.8 mm, and 1.0 mm pitch BGA packages.
IMPORTANT: All standard packages are lead-free (signified by an additional V in the package name).
All devices supported in a particular package are footprint compatible. Each device is split into I/O
banks to allow for flexibility in the choice of I/O standards. See the UltraScale Architecture SelectIO
Resources User Guide (UG571) [Ref 6].
The flip-chip assembly materials for the Zynq UltraScale+ devices are manufactured using
ultra-low alpha (ULA) materials defined as <0.002 cph/cm2 or materials that emit less than
0.002 alpha-particles per square centimeter per hour.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Differences from Previous Generations

The packaging and pinout specifications for Zynq UltraScale+ devices differ from past
generations, including the Zynq-7000 SoCs. These details are outlined in this section.
• All package and die components, including flip-chip solder bumps, are lead-free.
• Package names contain a single-character alphabetic designator followed by the exact
number of pins found on the package.
• VCCAUX_IO pins are not divided into bank groups. VCCAUX_IO must be connected to
VCCAUX at the board level.
• Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins.
VCCINT_IO must be connected to VCCBRAM (depending on the device speed grade
and voltage settings) at the board level.
• Groups of gigabit serial transceiver (GT) power pins are separated by column for each
column of GT Quads.
• Standard HP I/O banks each have a total of 52 SelectIO™ pins, optionally configurable
as (up to) 24 differential pairs.
• Standard HD I/O banks each have a total of 24 SelectIO pins, optionally configurable as
(up to) 12 differential pairs.
• Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.

13
• Four differential clock pin pairs per bank consist of a single type of global clock (GC or
HDGC) input.
• Four memory byte groups per HP I/O bank are each separated into an upper and a
lower memory byte group.
• Multiple PL configuration pins are removed.
• A POR_OVERRIDE pin is used to override the default power-on-reset delay. See
Table 1-4.
Device/Package Combinations
Table 1-1 shows the size and BGA pitch of the Zynq UltraScale+ device packages. All
packages are available with eutectic BGA balls. For these packages, the Pb-free signifier in
the package name is a Q.
Table 1‐1: Package Specifications

Package Specifications
Packages Description
Package Type Pitch (mm) Size (mm)
UBVA494 Flip-chip, integrated fan out (InFO), bare-die 0.5 15 x 9.5
SBVA484 Flip-chip, bare-die 19 x 19
SFRA484 Ruggedized flip-chip, bare-die 19 x 19
SBVA625 Flip-chip, bare-die
0.8 21 x 21
SFVA625 Flip-chip
SFVC784 Flip-chip BGA
23 x 23
SFRC784 Ruggedized flip-chip
FBVB900 Flip-chip, bare-die
FFRB900 Ruggedized flip-chip
1.0 31 x 31
FFVC900 Flip-chip
FFRC900 Ruggedized flip-chip

14
Table 1‐1: Package Specifications (Cont’d)

Package Specifications
Packages Description
Package Type Pitch (mm) Size (mm)
FFVB1156 Flip-chip
FFVC1156 Flip-chip
35 x 35
FFVD1156 Flip-chip
FFRD1156 Ruggedized flip-chip
FFVE1156 Flip-chip
FFRE1156 Ruggedized flip-chip
FFVB1517 Flip-chip
FFVF1517 Flip-chip 40 x 40
FFVG1517 Flip-chip
FFRG1517 Ruggedized flip-chip
BGA 1.0
FFVC1760 Flip-chip
FFVD1760 Flip-chip
42.5 x 42.5
FFVF1760 Flip-chip
FFVH1760 Flip-chip
FFRF1760 Ruggedized flip-chip
FFVE1924 Flip-chip 45 x 45
FSVE1156 35 x 35
FSVG1517 40 x 40
Flip-chip, lidless with stiffener ring
FSVF1760
42.5 x 42.5
FSVH1760
FSRG1517 Ruggedized flip-chip, lidless with stiffener 40 x 40
FSRF1760 ring 42.5 x 42.5

15
Gigabit Transceiver Channels by Device/Package

Table 1-2 lists the quantity of gigabit transceiver channels for the Zynq UltraScale+ devices.
In all devices, a PS-GTR, GTH, or GTY channel is one set of MGTRXP, MGTRXN, MGTTXP, and
MGTTXN pins. All packages are available with eutectic BGA balls. For these packages, the
device type is XQ and the Pb-free signifier in the package name is a Q.
Table 1‐2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package

Device Package PS-GTR Channels GTH Channels GTY Channels
XCZU1CG 4 0 0
XCZU1EG 4 0 0
XCZU2CG 4 0 0
XCZU2EG 4 0 0
SBVA484
XCZU3CG 4 0 0
XCZU3EG 4 0 0
XAZU2EG 4 0 0
XAZU3EG 4 0 0
XQZU3EG SFRA484 4 0 0
XCZU1CG 4 0 0
UBVA494
XCZU1EG 4 0 0
XCZU2CG 4 0 0
XCZU2EG 4 0 0
UBVA530
XCZU3CG 4 0 0
XCZU3EG 4 0 0
XCZU1CG 4 0 0
XCZU1EG 4 0 0
XCZU2CG 4 0 0
XCZU2EG 4 0 0
SFVA625
XCZU3CG 4 0 0
XCZU3EG 4 0 0
XAZU2EG 4 0 0
XAZU3EG 4 0 0

16
Table 1‐2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package (Cont’d)
XCZU1CG 4 0 0
XCZU1EG 4 0 0
XCZU2CG 4 0 0
XCZU2EG 4 0 0
XCZU3CG 4 0 0
XCZU3EG 4 0 0
XCZU4CG 4 4 0
XCZU4EG 4 4 0
SFVC784
XCZU4EV 4 4 0
XCZU5CG 4 4 0
XCZU5EG 4 4 0
XCZU5EV 4 4 0
XAZU2EG 4 0 0
XAZU3EG 4 0 0
XAZU4EV 4 4 0
XAZU5EV 4 4 0
XQZU21DR 4 0 0
SFRC784
XQZU5EV 4 4 0
XCZU4CG 4 16 0
XCZU4EG 4 16 0
XCZU4EV 4 16 0
XCZU5CG 4 16 0
XCZU5EG 4 16 0
FBVB900
XCZU5EV 4 16 0
XCZU7CG 4 16 0
XCZU7EG 4 16 0
XCZU7EV 4 16 0
XAZU7EV 4 16 0
XQZU5EV 4 16 0
FFRB900
XQZU7EV 4 16 0
XCZU6CG 4 16 0
XCZU6EG 4 16 0
XCZU9CG FFVC900 4 16 0
XCZU9EG 4 16 0
XCZU15EG 4 16 0

17
XQZU9EG 4 16 0
FFRC900
XQZU15EG 4 16 0
XCZU6CG 4 24 0
XCZU6EG 4 24 0
XCZU9CG FFVB1156 4 24 0
XCZU9EG 4 24 0
XCZU15EG 4 24 0
XQZU9EG 4 24 0
FFRB1156
XQZU15EG 4 24 0
XCZU7CG 4 20 0
XCZU7EG 4 20 0
FFVC1156
XCZU7EV 4 20 0
XCZU11EG 4 20 0
XQZU7EV 4 20 0
FFRC1156
XQZU11EG 4 20 0
XCZU21DR FFVD1156 4 0 16
XQZU21DR FFRD1156 4 0 16
XCZU25DR 4 0 8
XCZU27DR 4 0 8
XCZU28DR 4 0 8
XCZU42DR 4 0 8
XCZU43DR FFVE1156 4 0 8
XCZU47DR 4 0 8
XCZU48DR 4 0 8
XCZU65DR 4 0 8
XCZU67DR 4 0 8
XQZU28DR FFRE1156 4 0 8

18
XCZU25DR 4 0 8
XCZU27DR 4 0 8
XCZU28DR 4 0 8
XCZU42DR 4 0 8
XCZU43DR FSVE1156 4 0 8
XCZU47DR 4 0 8
XCZU48DR 4 0 8
XCZU65DR 4 0 8
XCZU67DR 4 0 8
XCZU11EG 4 16 0
XCZU17EG FFVB1517 4 16 0
XCZU19EG 4 16 0
XQZU19EG FFRB1517 4 16 0
XCZU7CG 4 24 0
XCZU7EG 4 24 0
XCZU7EV FFVF1517 4 24 0
XCZU11EG 4 32 0
XAZU11EG 4 32 0
XCZU25DR 4 0 8
XCZU27DR 4 0 16
XCZU28DR 4 0 16
FFVG1517
XCZU43DR 4 0 16
XCZU47DR 4 0 16
XCZU48DR 4 0 16
XQZU28DR FFRG1517 4 0 16
XCZU25DR 4 0 8
XCZU27DR 4 0 16
XCZU28DR 4 0 16
FSVG1517
XCZU43DR 4 0 16
XCZU47DR 4 0 16
XCZU48DR 4 0 16
XQZU48DR FSRG1517 4 0 16

19
XCZU11EG 4 32 16
XCZU17EG FFVC1760 4 32 16
XCZU19EG 4 32 16
XQZU11EG 4 32 16
FFRC1760
XQZU19EG 4 32 16
XCZU17EG 4 44 28
FFVD1760
XCZU19EG 4 44 28
XCZU29DR 4 0 16
XCZU39DR FFVF1760 4 0 16
XCZU49DR 4 0 16
XCZU46DR FFVH1760 4 0 16
XQZU29DR FFRF1760 4 0 16
XCZU29DR 4 0 16
XCZU39DR FSVF1760 4 0 16
XCZU49DR 4 0 16
XQZU49DR FSRF1760 4 0 16
XCZU46DR FSVH1760 4 0 16
XCZU17EG 4 44 0
FFVE1924
XCZU19EG 4 44 0

20
User I/O Pins by Device/Package

Table 1-3 lists the number of available PS I/Os, 3.3V-capable high-density (HD), and
1.8V-capable high-performance (HP) I/Os and the number of HD or HP differential I/O for
each device/package combination. All packages are available with eutectic BGA balls. For
these packages, the device type is XQ and the Pb-free signifier in the package name is a Q.
Table 1‐3: Available I/O Pins by Device/Package

Total User I/O Differential I/O
Device Package PS I/Os
HD(1) HP(1) HD HP
XCZU1CG 170 24 58 24 52
XCZU1EG 170 24 58 24 52
XCZU2CG 170 24 58 24 52
XCZU2EG 170 24 58 24 52
SBVA484
XCZU3CG 170 24 58 24 52
XCZU3EG 170 24 58 24 52
XAZU2EG 170 24 58 24 52
XAZU3EG 170 24 58 24 52
XQZU3EG SFRA484 170 24 58 24 52
XCZU1CG 170 24 58 24 52
UBVA494
XCZU1EG 170 24 58 24 52
XCZU2CG 170 24 58 24 52
XCZU2EG 170 24 58 24 52
UBVA530
XCZU3CG 170 24 58 24 52
XCZU3EG 170 24 58 24 52
XCZU1CG 170 24 156 24 144
XCZU1EG 170 24 156 24 144
XCZU2CG 170 24 156 24 144
XCZU2EG 170 24 156 24 144
SFVA625
XCZU3CG 170 24 156 24 144
XCZU3EG 170 24 156 24 144
XAZU2EG 170 24 156 24 144
XAZU3EG 170 24 156 24 144

21
Table 1‐3: Available I/O Pins by Device/Package (Cont’d)

HD(1) HP(1) HD HP
XCZU1CG 170 24 156 24 144
XCZU1EG 170 24 156 24 144
XCZU2CG 214 96 156 96 144
XCZU2EG 214 96 156 96 144
XCZU3CG 214 96 156 96 144
XCZU3EG 214 96 156 96 144
XCZU4CG 214 96 156 96 144
XCZU4EG 214 96 156 96 144
SFVC784
XCZU4EV 214 96 156 96 144
XCZU5CG 214 96 156 96 144
XCZU5EG 214 96 156 96 144
XCZU5EV 214 96 156 96 144
XAZU2EG 214 96 156 96 144
XAZU3EG 214 96 156 96 144
XAZU4EV 214 96 156 96 144
XAZU5EV 214 96 156 96 144
XQZU3EG 214 96 156 96 144
SFRC784
XQZU5EV 214 96 156 96 114
XCZU4CG 214 48 156 48 144
XCZU4EG 214 48 156 48 144
XCZU4EV 214 48 156 48 144
XCZU5CG 214 48 156 48 144
XCZU5EG 214 48 156 48 144
FBVB900
XCZU5EV 214 48 156 48 144
XCZU7CG 214 48 156 48 144
XCZU7EG 214 48 156 48 144
XCZU7EV 214 48 156 48 144
XAZU7EV 214 48 156 48 144
XQZU5EV 214 48 156 48 144
FFRB900
XQZU7EV 214 48 156 48 144

22

HD(1) HP(1) HD HP
XCZU6CG 214 48 156 48 144
XCZU6EG 214 48 156 48 144
XCZU9CG FFVC900 214 48 156 48 144
XCZU9EG 214 48 156 48 144
XCZU15EG 214 48 156 48 144
XQZU9EG 214 48 156 48 144
FFRC900
XQZU15EG 214 48 156 48 144
XCZU6CG 214 120 208 120 192
XCZU6EG 214 120 208 120 192
XCZU9CG FFVB1156 214 120 208 120 192
XCZU9EG 214 120 208 120 192
XCZU15EG 214 120 208 120 192
XQZU9EG 214 120 208 120 192
FFRB1156
XQZU15EG 214 120 208 120 192
XCZU7CG 214 48 312 48 288
XCZU7EG 214 48 312 48 288
FFVC1156
XCZU7EV 214 48 312 48 288
XCZU11EG 214 48 312 48 288
XQZU7EV 214 48 312 48 288
FFRC1156
XQZU11EG 214 48 312 48 288
XCZU21DR FFVD1156 214 72 208 72 192
XQZU21DR FFRD1156 214 72 208 72 192
XCZU25DR 214 48 104 48 96
XCZU27DR 214 48 104 48 96
XCZU28DR 214 48 104 48 96
XCZU42DR 214 24 130 24 120
XCZU43DR FFVE1156 214 48 104 48 96
XCZU47DR 214 48 104 48 96
XCZU48DR 214 48 104 48 96
XCZU65DR 214 24 130 24 120
XCZU67DR 214 24 130 24 120
XQZU28DR FFRE1156 214 48 104 48 96

23

HD(1) HP(1) HD HP
XCZU25DR 214 48 104 48 96
XCZU27DR 214 48 104 48 96
XCZU28DR 214 48 104 48 96
XCZU42DR 214 24 130 24 120
XCZU43DR FSVE1156 214 48 104 48 96
XCZU47DR 214 48 104 48 96
XCZU48DR 214 48 104 48 96
XCZU65DR 214 24 130 24 120
XCZU65DR 214 24 130 24 120
XCZU11EG 214 72 416 72 384
XCZU17EG FFVB1517 214 72 572 72 528
XCZU19EG 214 72 572 72 528
XQZU19EG FFRB1517 214 72 572 72 528
XCZU7CG 214 48 416 48 384
XCZU7EG 214 48 416 48 384
XCZU7EV FFVF1517 214 48 416 48 384
XCZU11EG 214 48 416 48 384
XAZU11EG 214 48 416 48 384
XCZU25DR 214 48 299 48 276
XCZU27DR 214 48 299 48 276
XCZU28DR 214 48 299 48 276
FFVG1517
XCZU43DR 214 48 299 48 276
XCZU47DR 214 48 299 48 276
XCZU48DR 214 48 299 48 276
XQZU28DR FFRG1517 214 48 299 48 276
XCZU25DR 214 48 299 48 276
XCZU27DR 214 48 299 48 276
XCZU28DR 214 48 299 48 276
FSVG1517
XCZU43DR 214 48 299 48 276
XCZU47DR 214 48 299 48 276
XCZU48DR 214 48 299 48 276
XQZU48DR FSRG1517 214 48 299 48 276

24

HD(1) HP(1) HD HP
XCZU11EG 214 96 416 96 384
XCZU17EG FFVC1760 214 96 416 96 384
XCZU19EG 214 96 416 96 384
XQZU11EG 214 96 416 96 384
FFRC1760
XQZU19EG 214 96 416 96 384
XCZU17EG 214 48 260 48 240
FFVD1760
XCZU19EG 214 48 260 48 240
XCZU29DR 214 96 312 96 288
XCZU39DR FFVF1760 214 96 312 96 288
XCZU49DR 214 96 312 96 288
XQZU49DR FSRF1760 214 96 312 96 288
XCZU46DR FFVH1760 214 48 312 48 288
XQZU29DR FFRF1760 214 96 312 96 288
XCZU29DR 214 96 312 96 288
FSVF1760
XCZU39DR 214 96 312 96 288
XCZU46DR FSVH1760 214 48 312 48 288
XCZU17EG 214 96 572 96 528
FFVE1924
XCZU19EG 214 96 572 96 528
Notes:
1. The maximum user I/O numbers do not include the GT serial transceiver pins or the PUDC_B and POR_OVERRIDE
pins used for configuration.

25
Pin Definitions
Table 1-4 lists the pin definitions.
Table 1‐4: Pin Definitions

Pin Name Type Direction Description
User I/O Pins
IO_L[1 to 24][P or N]_T[0 to 3] [U or L]_N[0 to 12]_ [multi-function]_[bank number] or
IO_T[0 to 3][U or L]_N[0 to 12]_[multi-function]_[bank number]
Most user I/O pins are capable of differential
signaling and can be implemented as pairs. Each
user I/O pin name consists of several indicator
labels, where:
• IO indicates a user I/O pin.
• L[1 to 24] indicates a unique differential pair with
P (positive) and N (negative) sides. User I/O pins
without the L indicator are single-ended.
Input/ • T[0 to 3][U or L] indicates the assigned byte group
Dedicated
Output and nibble location (upper or lower portion)
within that group for the pin.
• N[0 to 12] the number of the I/O within its byte
group.
• [multi-function] indicates any other functions that
the pin can provide. If not used for this function,
the pin can be a user I/O.
• [bank number] indicates the assigned bank for the
user I/O pin.
User I/O Multi-Function Pins
Four global clock (GC or HDGC) pin pairs are in each
bank. HDGC pins have direct access to the global
clock buffers. GC pins have direct access to the
global clock buffers and the MMCMs and PLLs that
are in the clock management tile (CMT) adjacent to
the same I/O bank. GC and HDGC inputs provide
dedicated, high-speed access to the internal global
Multi-
GC or HDGC Input and regional clock resources. GC and HDGC inputs
function
use dedicated routing and must be used for clock
inputs where the timing of various clocking features
is imperative.
Up-to-date information about designing with the GC
(or HDGC) pin is available in the UltraScale
Architecture Clocking Resources User Guide (UG572)
[Ref 7]
This pin is for the DCI voltage reference resistor of P
Multi-
VRP (1) N/A transistor (per bank, to be pulled Low with a
function
reference resistor).

26
Table 1‐4: Pin Definitions (Cont’d)

Byte lane clock (DBC and QBC) input pin pairs are
clock inputs directly driving source synchronous
DBC Multi- clocks to the bit slices in the I/O banks. In memory
Input
QBC function applications, these are also known as DQS. For more
information, consult the UltraScale Architecture
SelectIO Resources User Guide (UG571) [Ref 6].
Multi- Default reset pin locations for the integrated block
PERSTN[0 to 1] Input
function for PCI Express.
Configuration Pins
For more information on configuration and recommended external pull-up/pull-down resistors, see the Zynq
UltraScale+ Device Technical Reference Manual (UG1085) [Ref 10] and the UltraScale Architecture PCB and Pin
Planning User Guide (UG583) [Ref 14].
Active-Low input enables internal pull-ups during
configuration on all SelectIO pins:
0 = Weak preconfiguration I/O pull-up resistors
PUDC_B Dedicated Input enabled.
1 = Weak preconfiguration I/O pull-up resistors
disabled.
PUDC_B is powered by V CCAUX.
Power-on reset delay override.
0 = Standard PL power-on delay time
(recommended default).
1 = Faster PL power-on delay time.
POR_OVERRIDE Dedicated Input
CAUTION! Do not allow this pin to float before and
during configuration. This pin must be tied to
VCCINT or GND.
PS DONE signal. Requires an external pull-up

PS_DONE Dedicated Output
resistor.
PS_ERROR_OUT Dedicated Output PS error indication.
PS_ERROR_STATUS Dedicated Output PS error status.
Initialization completion indicator after POR. High
PS_INIT_B Dedicated Input/Output voltage indicates completion of initialization (PL).
Requires an external pull-up resistor.
PS_JTAG_TCK Dedicated Input JTAG data clock.
PS_JTAG_TDI Dedicated Input JTAG data input.
PS_JTAG_TDO Dedicated Output JTAG data output.
PS_JTAG_TMS Dedicated Input JTAG mode select.
PS_MODE Dedicated Input/Output PS MIO mode selection pins.
PS_PADI Dedicated Input Crystal pad input. Real-time clock (RTC).
PS_PADO Dedicated Output Crystal pad output. Real-time clock (RTC).

27

Power on reset. PS_POR_B must be held at 0 until all
PS power supplies meet voltage requirements and
PS_POR_B Dedicated Input
the PS_CLK reference is within specification. When
deasserted the PS begins the boot process.
PROG_B signal to reset configuration block. Requires
PS_PROG_B Dedicated Input
an external pull-up resistor.
System reference clock. PS_CLK must be between
PS_REF_CLK Dedicated Input
27 MHz and 60 MHz.
System reset. For use when debugging. When 0,
PS_SRST_B Dedicated Input
forces the PS to enter the system reset sequence.
Power/Ground Pins
For more information on voltage specifications see the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching
Characteristics [Ref 8] or the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9].
GND Dedicated N/A Ground.
Reserved pins that must be tied to GND.
Note: These pins are labeled differently depending upon
RSVDGND Dedicated N/A the device. They can serve a different purpose between
footprint compatible devices. To migrate to a footprint
compatible device, account for any variation in pin
functionality.
RSVD Dedicated N/A Reserved pin. Leave floating.

VCCINT Dedicated N/A Power-supply pins for the PL internal logic.
Power-supply pins for the I/O banks. VCCINT_IO
VCCINT_IO Dedicated N/A
must be connected to VCCBRAM on the board.
Power-supply pins for the video codec unit (EV
devices only).
Note: If the video codec unit is not used, then connect
the VCCINT_VCU pins to GND to reduce power. In the
CG and EG devices, the EV device VCCINT_VCU pins
appear as RSVDGND pins.
Note: When migrating from an EV device to a CG or EG
device in the same package, Xilinx recommends
connecting the VCCINT_VCU pins to GND to reduce
VCCINT_VCU Dedicated N/A power. Further VCCINT_VCU migration guidelines are
available in UltraScale Architecture PCB and Pin
Planning User Guide (UG583) [Ref 14].
IMPORTANT: V CCINT_VCU requires its own

dedicated power supply. Do not combine with
other power rails on the PCB.
VCCAUX Dedicated N/A Power-supply pins for auxiliary circuits.

28

Auxiliary power-supply pins for the I/O banks.
VCCAUX_IO must be connected to VCCAUX on the
board.
VCCAUX_IO Dedicated N/A Note: Package files for XQ ruggedized devices

(for example: FFRC784) have unique pin names
for VCCAUX_HPIO and VCCAUX_HDIO. These pins
can be connected to a common VCCAUX_IO
supply.
VCCBRAM Dedicated N/A Power-supply pins for PL block RAM logic.
VCCO_[bank number] (2) Dedicated N/A Power-supply pins for the output drivers (per bank).
VREF_[bank number] Dedicated N/A Voltage reference for input pins (per bank).
VCCADC Dedicated N/A System Monitor analog supply voltage.
GNDADC Dedicated N/A System Monitor analog ground.
VCC_PSADC Dedicated N/A PS ADC supply voltage.
GND_PSADC Dedicated N/A PS ADC analog ground.
VCC_PSAUX Dedicated N/A PS auxiliary circuits supply voltage.
PS RTC battery supply voltage. When not used, tie to
VCC_PSBATT Dedicated N/A
GND.
VCC_PSDDR_PLL Dedicated N/A PS DDR PLL supply voltage.
PS PLL (DPLL, RPLL, APLL, VPLL, IOPLL) supply
VCC_PSPLL Dedicated N/A
voltage.
VCC_PSINTFP Dedicated N/A PS full-power domain supply voltage.
VCC_PSINTFP_DDR Dedicated N/A PS DDR full-power domain supply voltage.
VCC_PSINTLP Dedicated N/A PS low-power domain supply voltage.
VCCO_PSIO[0:3]_
Dedicated N/A PS I/O supply voltage.
[500:503]
VCCO_PSDDR Dedicated N/A PS DDR controller I/O supply voltage.
PS MIO Pins
Multiplexed I/O can be configured to support
multiple I/O interfaces. These interfaces include SPI
PS_MIO Multi-function Input/Output
and Quad-SPI flash, NAND, USB, Ethernet, SDIO,
UART, SPI, and GPIO interfaces.
PS DDR Pins
PS_DDR_DQ Dedicated Input/Output DRAM data.
PS_DDR_DQS_P Dedicated Input/Output DRAM differential data strobe positive.
PS_DDR_DQS_N Dedicated Input/Output DRAM differential data strobe negative.
PS_DDR_ALERT_N Dedicated Input DRAM alert signal.
PS_DDR_ACT_N Dedicated Output DRAM activation command.

29

PS_DDR_A Dedicated Output DRAM row and column address.
PS_DDR_BA Dedicated Output DRAM bank address.
PS_DDR_BG Dedicated Output DRAM bank group.
PS_DDR_CK_N Dedicated Output DRAM differential clock negative.
PS_DDR_CK Dedicated Output DRAM differential clock positive.
PS_DDR_CKE Dedicated Output DRAM clock enable.
PS_DDR_CS Dedicated Output DRAM chip select.
PS_DDR_DM Dedicated Output DRAM data mask.
PS_DDR_ODT Dedicated Output DRAM termination control.
PS_DDR_PARITY Dedicated Output DRAM parity signal
PS_DDR_RAM_RST_N Dedicated Output DRAM reset signal, active low.
PS_DDR_ZQ Dedicated Input/Output ZQ calibration signal.
System Monitor Pins(3)
Multi- System Monitor differential auxiliary analog inputs
AD[0 to 15][P or N] Input
function 0–15.
VREFP Dedicated N/A Voltage reference input.
VREFN Dedicated N/A Voltage reference GND.
System Monitor dedicated differential analog input
VP Dedicated Input
(positive side).
System Monitor dedicated differential analog input
VN Dedicated Input
(negative side).
I2C serial clock. Directly connected to the System
Monitor DRP interface for I2C operation
configuration.
Multi-
I2C_SCLK Bidirectional
function
IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used
for I2C access until after configuration.
I2C serial data line. Directly connected to the System

Monitor DRP interface for I2C operation
configuration.
Multi-
I2C_SDA Bidirectional
function
IMPORTANT: Because the SYSMON I2C interface is
active after power-on, this pin should only be used
for I2C access until after configuration.

30

Optional PMBus alert, interrupt signal. When Low,
indicates a system fault that must be cleared using
PMBus commands. Connect to SMBALERT_TS.
For more information, see the UltraScale
Architecture System Monitor User Guide [Ref 13].
Multi-
SMBALERT Bidirectional
function IMPORTANT: By default, the PMBus is active prior
to configuration. Only use as a multi-functional
I/O pin in designs that can tolerated this pin being
driven prior to configuration.
This pin is present on Kintex UltraScale+ and Virtex

UltraScale+ devices.
Multi-gigabit Serial Transceiver Pins (GTHE4, GTYE4, and PS-GTR)
For more information on the GTH and GTY transceivers, see the UltraScale Architecture GTH Transceivers User
Guide (UG576) [Ref 11] or UltraScale Architecture GTY Transceivers User Guide [Ref 12]. For more information on
the PS-GTR transceivers, see the Zynq UltraScale+ Device Technical Reference Manual [Ref 10].
MGTHRX[P or N][0 to 3] RXP and RXN are the differential input pairs for each
Dedicated Input
_[GT quad number] of the receivers in the GTH Quad.
MGTHTX[P or N][0 to 3] TXP and TXN are the differential output pairs for
Dedicated Output
_[GT quad number] each of the transmitters in the GTH Quad.
MGTYRX[P or N][0 to 3] RXP and RXN are the differential input pairs for each
Dedicated Input
_[GT quad number] of the receivers in the GTY Quad.
MGTYTX[P or N][0 to 3] TXP and TXN are the differential output pairs for
Dedicated Output
_[GT quad number] each of the transmitters in the GTY Quad.
PS_MGTRRX[P or N][0 to 3] RXP and RXN are the differential input pairs for each
Dedicated Input
_[GT quad number] of the receivers in the PS-GTR Quad.
PS_MGTRTX[P or N][0 to 3] TXP and TXN are the differential output pairs for
Dedicated Output
_[GT quad number] each of the transmitters in the PS-GTR Quad.
Analog power-supply pin for the receiver and
MGTAVCC_[L or R]
Dedicated Input transmitter internal circuits for the GTH or GTY
[N or S](4)
transceivers.
Analog power-supply pin for the receiver and
PS_MGTRAVCC Dedicated N/A transmitter internal circuits for the PS-GTR
transceivers.
Analog power-supply pin for the transmitter and
MGTAVTT_[L or R]
Dedicated Input receiver termination circuits for the GTH or GTY
[N or S](4)
transceivers.
MGTVCCAUX_[L or R] Auxiliary analog Quad PLL (QPLL) voltage supply for
Dedicated Input
[N or S](4) the transceivers.

31

Analog power-supply pin for the transmitter and
PS_MGTRAVTT Dedicated N/A receiver termination circuits for the PS-GTR
transceivers.
Configured as either reference clock input pins or as
MGTREFCLK[0 or 1]
Dedicated Input/Output RX recovered clock output pins for the GTH or GTY
[P or N]
transceivers.
PS_MGTREFCLK[0 to 3] Differential reference clock for the PS-GTR
Dedicated Input
[P or N] transceivers.
MGTAVTTRCAL_[L or R] Bias current supply for the termination resistor
Dedicated N/A
[N or S](4) calibration circuit.
MGTRREF_[L or R] Calibration resistor pin for the termination resistor
Dedicated Input
[N or S](4) calibration circuit for the GTH or GTY transceivers.
Calibration resistor pin for the termination resistor
PS_MGTRREF Dedicated Input
calibration circuit for the PS-GTR transceivers.
Zynq UltraScale+ RFSoC Dedicated Pins
VCCSDFEC Dedicated N/A Power supply for the FEC blocks.
VCCINT_AMS Dedicated N/A Digital power supply for the DDC.
ADC_AVCC Dedicated N/A Core ADC and PLL power supply.
ADC_AVCCAUX Dedicated N/A Input buffer and PLL power supply.
ADC_GND Dedicated N/A Analog ground for the ADC.
ADC_SUB_GND Dedicated N/A Digital ground for the ADC.
ADC_CLK_[P or N] External reference clock for PLL or ADC direct
Dedicated Input
sampling clock input.
VCM01/VCM23 Dedicated N/A ADC common mode voltage.
ADC_VIN_[0 to 3]_[P or N] Dedicated Input Analog input signal to the ADC.
ADC_REXT Dedicated N/A ADC external resistor.
DAC_AVCC Dedicated N/A Core DAC and PLL power supply.
DAC_AVCCAUX Dedicated N/A DAC and PLL power supply.
DAC_AVTT Termination voltage for on-die 50 termination
Dedicated N/A
resistors.
DAC_GND Dedicated N/A Analog ground for the DAC.
DAC_SUB_GND Dedicated N/A Digital ground for the DAC.
DAC_CLK_[P or N] External reference clock for PLL or DAC direct
Dedicated Input
sampling clock input.
SYSREF_[P or N] External reference clock/trigger for synchronizing
Dedicated Input
timing of the data converters.
DAC_VOUT[0 to 3]_[P or N] Dedicated Output Analog output signals from the DAC.
DAC_REXT Dedicated Input DAC external resistor.

32

Other Dedicated Pins
DXN Temperature-sensing diode pins (Anode: DXP;
Cathode: DXN). The thermal diode is accessed by
using the DXP and DXN pins. When not used, tie to
GND.
Dedicated N/A
To use the thermal diode an appropriate external
thermal monitoring IC must be added. Consult the
DXP external thermal monitoring IC data sheet for usage
guidelines.
Notes:
1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide (UG571) [Ref 6] for more information on the
VRP pins.
2. V CCO pins in unbonded banks must be connected to the V CCO for that bank (for package migration). Do NOT connect
unbonded V CCO pins to different supplies. Without a package migration requirement, V CCO pins in unbonded banks can be
tied to a common supply (V CCO or GND).
3. See the UltraScale Architecture System Monitor User Guide (UG580) [Ref 13] for the default connections required to support
on-chip monitoring.
4. L (left), R (right), N (north), and S (south) signify the GT transceiver quad power supply groups.

33
Footprint Compatibility between Packages

Zynq UltraScale+ devices are footprint compatible only with other Zynq UltraScale+ devices
with the same number of package pins and the same preceding alphabetic designator. For
example, XCZU9EG-FFVB1156 is compatible with the XCZU15EG-FFVB1156, but not with the
XCZU9EG-FFVC900. Pins that are available in one device but are not available in another
device are labeled as No Connects in the other device's package file.
IMPORTANT: Footprint compatibility does not necessarily imply that all pins will function in the same
manner for different devices in a package. For limitations and guidelines on designing for footprint
compatible packages, refer to the Migration Between the Zynq UltraScale+ Devices and Packages
section of UltraScale Architecture PCB and Pin Planning User Guide (UG583) [Ref 14].
Table 1-5 shows the footprint compatible devices available for each package. See the
Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1] for specific package letter code options.
All packages are available with eutectic BGA balls. For these packages, the device type is XQ
and the Pb-free signifier in the package name is a Q.
Table 1‐5: Footprint Compatibility

Packages Footprint Compatible Devices
SBVA484 XCZU1CG, XCZU1EG
SBVA484 XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG,
SFRA484 XAZU2EG XAZU3EG, XQZU3EG
UBVA494 XCZU1CG, XCZU1EG

UBVA530 XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG,
SFVA625 XCZU1CG, XCZU1EG
SFVA625 XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG,
XAZU2EG XAZU3EG
SFVC784 XCZU1CG, XCZU1EG
SFVC784 XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XCZU4CG, XCZU4EG, XCZU5CG, XCZU5EG,
SFRC784 XAZU2EG XAZU3EG, XQZU3EG XCZU4EV, XAZU4EV XCZU5EV, XAZU5EV,
XQZU5EV
FBVB900 XCZU4CG, XCZU4EG, XCZU5CG, XCZU5EG, XCZU7CG, XCZU7EG,
FFRB900 XCZU4EV XCZU5EV, XQZU5EV XCZU7EV, XAZU7EV,
XQZU7EV
FFVC900 XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG, XCZU15EG, XQZU15EG
FFRC900 XQZU9EG
FFVB1156 XCZU6CG, XCZU6EG XCZU9CG, XCZU9EG, XCZU15EG, XQZU15EG

FFRB1156 XQZU9EG
FFVC1156 XCZU7CG, XCZU7EG, XCZU11EG, XQZU11EG

FFRC1156 XCZU7EV, XQZU7EV

34
Table 1‐5: Footprint Compatibility (Cont’d)

FFVD1156 XCZU21DR, XQZU21DR
FFVE1156 XCZU25DR XCZU27DR, XCZU43DR, XCZU42DR, XCZU65DR, XCZU28DR, XQZU28DR
FSVE1156 XCZU47DR, XCZU67DR(2)
XCZU49DR (1)
FFVB1517 XCZU11EG XCZU17EG XCZU19EG, XQZU19EG

FFVF1517 XCZU7CG, XCZU7EG, XCZU11EG, XAZU11EG
XCZU7EV
FFVG1517 XCZU25DR XCZU27DR, XCZU43DR, XCZU28DR, XQZU28DR XCZU48DR, XQZU48DR
FSVG1517 XCZU47DR,
XCZU49DR(1)
FSRG1517
FFVC1760 XCZU11EG, XQZU11EG XCZU17EG XCZU19EG, XQZU19EG
FFVD1760 XCZU17EG XCZU19EG
FFVF1760 XCZU29DR, XCZU39DR,
FSVF1760 XCZU49DR (1)
FFRF1760 XQZU29DR
FSRF1760 XQZU49DR
FFVH1760 XCZU46DR
FSVH1760 XCZU46DR
FFVE1924 XCZU17EG XCZU19EG
Notes:
1. These footprint compatible devices have a different set of ADC and DAC power sequencing requirements. Refer to Zynq
UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for specific power sequencing differences.
2. The XCZU42DR, XCZU65DR, and XCZU67DR are only partially compatible with other devices in the FFVE1156 and FSVE1156
packages due to key differences in the ADC and DAC architecture. When planning migration between devices, differences
that must be addressed include ADC and DAC bank/pin locations and power rail voltage specifications.
Many Zynq UltraScale+ devices that are footprint compatible in a package have different
I/O bank and transceiver quad numbers connected to the same package pins. Due to these
differences, when migrating between devices in a specific package, the type of bank (HD vs.
HP) or quad (PS-GTR, GTH, or GTY), whether a bank is connected or NC at the package pins,
and where the bank or quad is located on the die must be taken into consideration.
Table 1-6 and Table 1-7 show how the banks and transceiver quads are numbered between
devices in each package.
For all grouped-together footprint-compatible packages, the bank and quad numbers in
the same column (indicated by the letters A through Z) for each device are connected to the
same package pins. For example, in the FFVB1517 packages, bank 88 for the XCZU11 is
connected to the same pins as bank 90 for the XCZU17 and XCZU19.
A limited number of HP I/O banks have fewer than 52 SelectIO pins. For a visual
representation of all of this information, see the Die Level Bank Numbering Overview
section.

35
Table 1‐6: I/O Bank Migration (HD Banks are Shaded)

Package to Device I/O Mapping(1)
Package Device Unbonded I/O Banks
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
XCZU1 44 65 66 64
XCZU2
26 65 66 (2) 25, 24, 44, 64
SBVA484 XAZU2
XCZU3
26 65 66 (2) 25, 24, 44, 64
XAZU3
SFRA484 XQZU3 26 65 66 (2) 25, 24, 44, 64
UBVA494 XCZU1 44 65 66 64
XCZU2 26 65 66 (2) 25, 24, 44, 64

UBVA530
XCZU3 26 65 66 (2) 25, 24, 44, 64
SBVA625 XCZU1 64 65 66 44 25, 24, 44, 64
XCZU2
64 65 66 26 25, 24, 44
XAZU2
SFVA625
XCZU3
64 65 66 26 25, 24, 44
XAZU3
XCZU1 64 65 66 44
XCZU2
64 65 66 25 26 24 44
XAZU2
XCZU3
64 65 66 25 26 24 44
SFVC784 XAZU3
XCZU4
64 65 66 45 46 44 43 63
XAZU4
XCZU5
64 65 66 45 46 44 43 63
XAZU5
Zynq UltraScale+ Packaging and Pinouts 36

Table 1‐6: I/O Bank Migration (HD Banks are Shaded) (Cont’d)

XQZU3 64 65 66 25 26 24 44
SFRC784
XQZU5 64 65 66 45 46 44 43 63
XCZU4 64 65 66 46 45 44, 43, 63

XCZU5 64 65 66 46 45 44, 43, 63
FBVB900
XCZU7 64 65 66 47 48 28, 27, 68, 67, 63, 88, 87
XAZU7 64 65 66 47 48 28, 27, 68, 67, 63, 88, 87
XQZU5 64 65 66 46 45 44, 43, 63
FFRB900
XQZU7 64 65 66 47 48 28, 27, 68, 67, 63, 88, 87
XCZU6 64 65 66 48 47 50, 49, 44, 67

FFVC900 XCZU9 64 65 66 48 47 50, 49, 44, 67
XCZU15 64 65 66 48 47 50, 49, 44, 67
XQZU9 64 65 66 48 47 50, 49, 44, 67
FFRC900
XQZU15 64 65 66 48 47 50, 49, 44, 67
XCZU6 44 64 65 66 67 47 48 49 50
FFVB1156 XCZU9 44 64 65 66 67 47 48 49 50
XCZU15 44 64 65 66 67 47 48 49 50
XQZU9 44 64 65 66 67 47 48 49 50
FFRB1156
XQZU15 44 64 65 66 67 47 48 49 50
XCZU7 64 65 66 87 88 68 67 28 27, 48, 47, 63

FFVC1156
XCZU11 64 65 66 88 89 69 68 67 71, 70, 91, 90
XQZU7 64 65 66 87 88 68 67 28 27, 48, 47, 63
FFRC1156
XQZU11 64 65 66 88 89 69 68 67 71, 70, 91, 90


FFVD1156 XCZU21 65 66 67 68 87 88 89 71, 70, 69, 64, 91, 90, 84
FFRD1156 XQZU21 65 66 67 68 87 88 89 71, 70, 69, 64, 91, 90, 84
XCZU25 65 66 88 89 69, 68, 67, 64, 87, 84

XCZU27 65 66 88 89 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU28 65 66 88 89 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU42 65 66 67(2) 88 68, 64
FFVE1156
XCZU43 65 66 88 89 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
FSVE1156
XCZU47 65 66 88 89 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU48 65 66 88 89 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU65 65 66 67(2) 88 68, 64
XCZU67 65 66 67(2) 88 68, 64
FFRE1156 XQZU28 65 66 88 89 71, 70, 69, 68, 67, 64, 91, 90, 87, 84
XCZU11 65 64 66 88 89 90 71 70 69 68 67 91
FFVB1517 XCZU17 65 64 66 90 91 93 74 73 72 71 70 69 68 67 94
XCZU19 65 64 66 90 91 93 74 73 72 71 70 69 68 67 94
FFRB1517 XQZU19 65 64 66 90 91 93 74 73 72 71 70 69 68 67 94
XCZU7 65 66 64 63 87 88 67 68 28 27 48, 47
FFVF1517 XCZU11 65 66 67 64 88 89 70 71 69 68 91, 90
XAZU11 65 66 67 64 88 89 70 71 69 68 91, 90


XCZU25 84 64 65 66 87 67 68 69 89, 88
XCZU27 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
FFVG1517 XCZU28 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
FSVG1517 XCZU43 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
XCZU47 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
XCZU48 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
FFRG1517 XQZU28 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
FSRG1517 XQZU48 84 64 65 66 87 67 68 69 71, 70, 91, 90, 89, 88
XCZU11 65 64 66 67 88 89 90 91 71 70 69 68
FFVC1760 XCZU17 65 64 66 67 90 91 93 94 71 70 69 68 74, 73, 72
XCZU19 65 64 66 67 90 91 93 94 71 70 69 68 74, 73, 72
XQZU11 65 64 66 67 88 89 90 91 71 70 69 68
FFRC1760
XQZU19 65 64 66 67 90 91 93 94 71 70 69 68 74, 73, 72
XCZU17 65 66 90 91 71 70 69 74, 73, 72, 68, 67, 64, 94, 93

FFVD1760
XCZU19 65 66 90 91 71 70 69 74, 73, 72, 68, 67, 64, 94, 93
XCZU29 84 64 65 66 87 88 89 67 68 69 71, 70, 91, 90

FFVF1760
XCZU39 84 64 65 66 87 88 89 67 68 69 71, 70, 91, 90
FSVF1760
XCZU49 (1) 84 64 65 66 87 88 89 67 68 69 71, 70, 91, 90
FFRF1760 XQZU29 84 64 65 66 87 88 89 67 68 69 71, 70, 91, 90
FSRF1760 XQZU49 84 64 65 66 87 88 89 67 68 69 71, 70, 91, 90
FFVH1760
XCZU46 64 65 66 90 91 69 71 70 67, 68, 84, 87, 88, 89
FSVH1760


XCZU17 65 64 66 67 90 91 93 94 74 73 72 71 70 69 68
FFVE1924
XCZU19 65 64 66 67 90 91 93 94 74 73 72 71 70 69 68
Notes:
1. An alphabetical designator, A through Z, is assigned to every bank in a package. I/Os from banks with the same designator are bonded out to the same pins in that
package. For example, in the FFVF1517 package, the E designator is assigned to bank 67 for the XCZU11 and bank 64 for the XCZU7. These banks are bonded to the same
pins, regardless of where they appear on the XCZU11 and XCZU7 device.
2. Bank 66 is partially bonded out in the SBVA484 package (see Figure 1-8). Bank 67 is partially bonded out in the FFVE1156 and FSVE1156 packages for the XCZU42DR,
XCZU65DR, and XCZU67DR (see Figure 1-49, Figure 1-64, and Figure 1-66.

For each grouped set of footprint compatible packages listed in Table 1-7, there is a row detailing the power supply group for
each Quad. These groups are labeled according to the regions for the transceiver power supply pins, as listed in the ASCII
Pinout Files linked from Chapter 3, Package Files. For a visual representation of all of this information, see the Die Level Bank
Numbering Overview section.
Table 1‐7: Transceiver Quad Migration (GTY Quads are in Shaded)

Package to Die Transceiver Mapping(1)
Package Device Unbonded Quads
A B C D E F G H I J K L M N O P Q R S-Z AA-AF
XCZU1
XCZU2
SBVA484 XAZU2
XCZU3
XAZU3
SFRA484 XQZU3
UBVA494 XCZU1
XCZU2
UBVA530
XCZU3
XCZU1
XCZU2
SFVA625 XAZU2
XCZU3
XAZU3
Power Supply Group R

XCZU1
XCZU2
XAZU2
XCZU3
SFVC784 XAZU3
XCZU4
224 226, 225, 223
XAZU4
XCZU5
224 226, 225, 223
XAZU5

Table 1‐7: Transceiver Quad Migration (GTY Quads are in Shaded) (Cont’d)

SFRC784 XQZU3
XQZU5 224 226, 225, 223

XCZU4 223 224 225 226
XCZU5 223 224 225 226
FBVB900
XCZU7 224 225 226 227 228, 223
XAZU7 224 225 226 227 228, 223
XQZU5 223 224 225 226
FFRB900
XQZU7 224 225 226 227 228, 223
Power Supply Group R L

XCZU6 228 229 230 128 130, 129, 127
FFVC900 XCZU9 228 229 230 128 130, 129, 127
XCZU15 228 229 230 128 130, 129, 127
XQZU9 228 229 230 128 130, 129, 127
FFRC900
XQZU15 228 229 230 128 130, 129, 127
Power Supply Group R L

XCZU6 228 229 230 128 129 130 127
FFVB1156 XCZU9 228 229 230 128 129 130 127
XCZU15 228 229 230 128 129 130 127
XQZU9 228 229 230 128 129 130 127
FFRB1156
XQZU15 228 229 230 128 129 130 127

XCZU7 223 224 225 226 227 228
FFVC1156
XCZU11 224 225 226 227 228 131, 130, 129, 128, 127, 229, 231, 230
XQZU7 223 224 225 226 227 228
FFRC1156
XQZU11 224 225 226 227 228 131, 130, 129, 128, 127, 229, 231, 230


Power Supply Group L
FFVD1156 XCZU21 128 129 130 131 127
FFRD1156 XQZU21 128 129 130 131 127

XCZU25 128 129 127
XCZU27 128 129 131, 130, 127
XCZU28 128 129 131, 130, 127
XCZU42 127 128
FFVE1156 XCZU43 128 129 131, 130, 127
FSVE1156
XCZU47 128 129 131, 130, 127
XCZU48 128 129 131, 130, 127

XCZU65 127 128
XCZU67 127 128

FFRE1156 XCZU28 128 129 131, 130, 127

XCZU11 224 225 226 227 131, 130, 129, 128, 127, 231, 230, 229, 228
134, 133, 132, 131, 130, 129, 128, 127, 234, 233, 232, 231,
XCZU17 224 225 226 227
230, 229, 228
FFVB1517
134, 133, 132, 131, 130, 129, 128, 127, 234, 233, 232, 231,
XCZU19 224 225 226 227
230, 229, 228
XAZU11 224 225 226 227 131, 130, 129, 128, 127, 231, 230, 229, 228
134, 133, 132, 131, 130, 129, 128, 127, 234, 233, 232, 231,
FFRB1517 XQZU19 224 225 226 227
230, 229, 228
Power Supply Group RS RN

XCZU7 223 224 225 226 227 228
FFVF1517
XCZU11 224 225 226 227 228 229 230 231 131, 130, 129, 128, 127


XCZU25 128 129 127
XCZU27 128 129 130 131 127
FFVG1517 XCZU28 128 129 130 131 127

FSVG1517 XCZU43 128 129 130 131 127
XCZU47 128 129 130 131 127
XCZU48 128 129 130 131 127
FFRG1517 XQZU28 128 129 130 131 127

FSRG1517 XQZU48 128 129 130 131 127
Power Supply Group RS RN L

XCZU11 224 225 226 227 228 229 230 231 128 129 130 131 127
FFVC1760 XCZU17 224 225 226 227 228 229 230 231 128 129 130 131 127
XCZU19 224 225 226 227 228 229 230 231 128 129 130 131 134, 133, 132, 127, 234, 233, 232
XQZU11 224 225 226 227 228 229 230 231 128 129 130 131 127
FFRC1760
XQZU19 224 225 226 227 228 229 230 231 128 129 130 131 134, 133, 132, 127, 234, 233, 232
Power Supply Group RS RN L

XCZU17 224 225 226 227 228 229 230 231 232 233 234 128 129 130 131 132 133 134 127
FFVD1760
XCZU19 224 225 226 227 228 229 230 231 232 233 234 128 129 130 131 132 133 134 127

XCZU29 128 129 130 131 127
FFVF1760
XCZU39 128 129 130 131 127
FSVF1760
XCZU49 128 129 130 131 127
FFVH1760
XCZU46 128 129 130 131 127
FSVH1760
FFRF1760 XQZU29 128 129 130 131 127
FSRF1760 XQZU49 128 129 130 131 127


Power Supply Group RS RN
XCZU17 224 225 226 227 228 229 230 231 232 233 234 134, 133, 132, 131, 130, 129, 128, 127
FFVE1924
XCZU19 224 225 226 227 228 229 230 231 232 233 234 134, 133, 132, 131, 130, 129, 128, 127
Notes:
1. An alphabetical designator, A through Z, is assigned to every Quad in a package. Transceivers from Quads with the same designator are bonded out to the same pins in
that package. For example, in the FFVF1517 package, the E designator is assigned to Quad 228 for the XCZU11 and Quad 227 for the XCZU7. These Quads are bonded to
the same pins, regardless of where they appear on the XCZU11 and XCZU7 device.

Die Level Bank Numbering Overview

Banking and Clocking Summary
• For each device, not all banks are bonded out in every package.
GTH/GTY Columns
• One GT Quad = Four transceivers = Four GTHE4 or GTYE4 primitives.
• Not all GT Quads are bonded out in every package.
• Also shown are quads labeled with RCAL. This specifies the location of the RCAL
masters for each device. With respect to the package, the RCAL masters are located on
the same package pin for each package, regardless of the device.
• The XY coordinates shown in each quad correspond to the transceiver channel number
found in the pin names for that quad, as shown in Figure 1-7.
• An alphabetic designator is shown in each quad. Each letter corresponds to the
columns in Table 1-6 and Table 1-7.
• The power supply group is shown in brackets [ ] for each quad.
I/O Banks
• Each user HP I/O bank has a total of 52 I/Os where 48 can be used as differential
(24 differential pairs) or single-ended I/Os. The remaining four function only as
single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
• A limited number of HP I/O banks have fewer than 52 SelectIO pins. These banks are
labeled as partial.
• Each user HD I/O bank has a total of 24 I/Os that can be used as differential (12
differential pairs) or single-ended I/Os.
• Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock
resources.
• Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
• Banks are arranged in columns and separated into rows which are pitch-matched with
adjacent PHY, clock regions, and GT blocks.
• An alphabetic designator is shown in each bank. Each letter corresponds to the
columns in Table 1-6 and Table 1-7.

46
Clocking
• Each bank has four pairs of global clock (GC or HDGC) inputs for four differential or
four single-ended clock inputs. Single-ended clock inputs should be connected to the
P-side of the differential pair.
• Clock signals are distributed through global buffers driving routing and distribution
networks to reach any clock region, I/O, or GT.
• Global clock inputs can connect to an MMCM and two PLLs within the horizontally
adjacent CMT.
Bank Locations of Dedicated and Multi-Function Pins

• All dedicated configuration I/Os and HD I/Os are 3.3V capable.
Processor (PS) Blocks

• MIO pins are shared between banks 500, 501, and 502.
• Configuration pins are in bank 503.
• DDR memory pins are in bank 504.
• Transceiver pins are in the PS-GTR quad 505.
SYSMON, Configuration, PCIe, Interlaken, and 100GE Integrated Blocks

• Configuration: Configuration block.
• SYSMON/Configuration: Block shared between the SYSMONE4 and configuration.
• PCIe: Integrated block for PCIe.
Note: PCIe blocks with an additional (Tandem) label support tandem configuration.
• ILKN: Interlaken block.
• CMAC: 100G Ethernet block.

47
Device Diagrams
Figure 1-1 shows an example diagram with a brief explanation for each component.
X-Ref Target - Figure 1-1
*7<4XDG *7+4XDG ;<ĺ0*7+>7;RU5;@>3RU1@B

3&,( +3,2%DQN +',2%DQN ;<ĺ0*7+>7;RU5;@>3RU1@B
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;< 5 Q ;<ĺ0*7+>7;RU5;@>3RU1@B
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;<;<
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3&,( *7+4XDG ;<ĺ0*7+>7;RU5;@>3RU1@B
+3,2%DQN ;<ĺ0*7+>7;RU5;@>3RU1@B
36&21),* 360,2 X1Y0 X0Y0-X0Y3
D WDQGHP
;<ĺ0*7+>7;RU5;@>3RU1@B
$>56@ ;<ĺ0*7+>7;RU5;@>3RU1@B
,2%DQN7\SH
{+3RU+'` ,QWHJUDWHG%ORFNV Alphabetic Bank/Quad
DQG7UDQVFHLYHU 'HVLJQDWRU&RUUHVSRQGV
;<&RRUGLQDWHV WRFROXPQVLQ7DEOH
DQG7DEOH
;
Figure 1‐1: Example Device Diagram
Figure 1-7 through Figure 1-47 show a die view of each device followed by a view with
respect to each available package. The available resources by device and package are
detailed in the Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1] or Zynq UltraScale+
RFSoC Overview (DS889) [Ref 2].

48
XCZU1CG Bank Diagram Overview

SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66
Configuration
PS DDR 504 PS MIO 501 Configuration HP I/O Bank 65
PS CONFIG 503 PS MIO 500 HD I/O Bank 44 HP I/O Bank 64
X26100-121921
Figure 1‐2: XCZU1CG Banks
Bank Diagram by Package for XCZU1CG

SYSMON HP I/O Bank 66

PS GTR 505 PS MIO 502
Configuration D (Partial)
PS DDR 504 HP I/O Bank 65

PS MIO 501 Configuration
(Partial) C
HD I/O Bank 44
PS CONFIG 503 PS MIO 500 HP I/O Bank 64
E
X26102-121921
Figure 1‐3: XCZU1CG Banks in SBVA484 Package


Configuration D (Partial)

(Partial) C
X26101-121921
Figure 1‐4: XCZU1CG Banks in UBVA494 Package

49

Configuration D

(Partial) C
HD I/O Bank 44 HP I/O Bank 64

PS CONFIG 503 PS MIO 500
E B
X26103-121921
Figure 1‐5: XCZU1CG Banks in SBVA625 Package


Configuration D
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration
C

O B
X26104-121921
Figure 1‐6: XCZU1CG Banks in SFVC784 Package

50
XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Bank Diagram

Overview
SYSMON
PS GTR 505 PS MIO 502 HD I/O Bank 26 HP I/O Bank 66
Configuration
PS DDR 504 PS MIO 501 HD I/O Bank 25 Configuration HP I/O Bank 65
PS CONFIG 503 PS MIO 500 HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64
X15118-060720
Figure 1‐7: XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Banks
Bank Diagram by Package for XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3
HD I/O Bank 26 SYSMON HP I/O Bank 66

B Configuration D (Partial)

PS MIO 501 HD I/O Bank 25 Configuration
(Partial) C
X15119-060720
Figure 1‐8: XCZU2, XAZU2, XCZU3, and XAZU3 Banks in SBVA484 Package
IMPORTANT: For the devices in the SBVA484 package shown in Figure 1-8, the HP I/Os in bank 66 are
powered by VCCO_65.

B Configuration D (Partial)

(Partial) C
X25451-061521
Figure 1‐9: XCZU2 and XCZU3 Banks in UBVA494 Package

51

E Configuration D

(Partial) C
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 HD I/O Bank 24 HD I/O Bank 44
B
X15120-060720
Figure 1‐10: XCZU2, XAZU2, XCZU3, and XAZU3 Banks in SFVA625 Package


F Configuration D

E C
HD I/O Bank 24 HD I/O Bank 44 HP I/O Bank 64

N O B
X15121-060720
Figure 1‐11: XCZU2, XAZU2, XCZU3, XAZU3, and XQZU3 Banks in SFVC784 Package

52
XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5 Bank Diagram

Overview
SYSMON GTH Quad 226

PS GTR 505 PS MIO 502 HD I/O Bank 46 HP I/O Bank 66
Configuration X0Y12-X0Y15
GTH Quad 225

PS DDR 504 PS MIO 501 HD I/O Bank 45 HP I/O Bank 65 Configuration
X0Y8-X0Y11
PCIE4 GTH Quad 224

PS CONFIG 503 PS MIO 500 HD I/O Bank 44 HP I/O Bank 64 X0Y1 X0Y4-X0Y7
(tandem) (RCAL)
PCIE4 GTH Quad 223

X0Y0 X0Y0-X0Y3
X15122-060720
Figure 1‐12: XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5 Banks
Bank Diagram by Package for XCZU4, XAZU4, XCZU5, XAZU5, and XQZU5
HD I/O Bank 46 HP I/O Bank 66 SYSMON GTH Quad 226

F D Configuration X0Y12-X0Y15
HD I/O Bank 45 HP I/O Bank 65 GTH Quad 225

E C X0Y8-X0Y11
PCIE4 GTH Quad 224

PS CONFIG 503 PS MIO 500 X0Y1 X0Y4-X0Y7
N B
(tandem) A [R] (RCAL)
HD I/O Bank 43 PCIE4 GTH Quad 223

HP I/O Bank 63
O X0Y0 X0Y0-X0Y3
X15124-111316
Figure 1‐13: XCZU4, XAZU4, XCZU5, and XAZU5 Banks in SFVC784 Package and
XQZU5 Banks in SFRC784 Package

53
GTH Quad 226

HD I/O Bank 46 HP I/O Bank 66 SYSMON
PS GTR 505 PS MIO 502 X0Y12-X0Y15
N D Configuration
D [R]
GTH Quad 225
PS DDR 504 PS MIO 501 Configuration X0Y8-X0Y11
O C
C [R]
GTH Quad 224
HP I/O Bank 64 PCIE4
PS CONFIG 503 PS MIO 500 HD I/O Bank 44 X0Y4-X0Y7
B X0Y1
B [R] (RCAL)
GTH Quad 223
PCIE4
HD I/O Bank 43 HP I/O Bank 63 X0Y0-X0Y3
X0Y0 A [R]
X15123-112916
Figure 1‐14: XCZU4 and XCZU5 Banks in FBVB900 Package and

XQZU5 Banks in FFRB900 Package

54
XCZU7, XAZU7, and XQZU7 Bank Diagram Overview

GTH Quad 228

HP I/O Bank 28 HD I/O Bank 48 HP I/O Bank 68 HD I/O Bank 88
X0Y20-X0Y23
GTH Quad 227

HP I/O Bank 27 HD I/O Bank 47 HP I/O Bank 67 HD I/O Bank 87
X0Y16-X0Y19
SYSMON GTH Quad 226

Configuration X0Y12-X0Y15
GTH Quad 225

PS DDR 504 PS MIO 501 HP I/O Bank 65 Configuration
X0Y8-X0Y11
PCIE4 GTH Quad 224

PS CONFIG 503 PS MIO 500 HP I/O Bank 64 X0Y1 X0Y4-X0Y7
(tandem) (RCAL)
PCIE4 GTH Quad 223

HP I/O Bank 63
X0Y0 X0Y0-X0Y3
X15125-111316
Figure 1‐15: XCZU7, XAZU7, and XQZU7 Banks
Bank Diagram by Package for XCZU7, XAZU7, and XQZU7

HD I/O Bank 48 GTH Quad 228

HP I/O Bank 28 HP I/O Bank 68 HD I/O Bank 88
O X0Y20-X0Y23
HD I/O Bank 47 GTH Quad 227

HP I/O Bank 27 HP I/O Bank 67 HD I/O Bank 87 X0Y16-X0Y19
N
D [R]
GTH Quad 226
HP I/O Bank 66 SYSMON
D Configuration
C [R]
GTH Quad 225
HP I/O Bank 65
C
B [R]
GTH Quad 224
PS CONFIG 503 PS MIO 500 X0Y4-X0Y7
B X0Y1
A [R] (RCAL)
PCIE4 GTH Quad 223

HP I/O Bank 63
X0Y0 X0Y0-X0Y3
X15126-112916
Figure 1‐16: XCZU7 and XAZU7 Banks in FBVB900 Package and XQZU7 Banks in FFRB900
Package

55
HP I/O Bank 28 HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228

HD I/O Bank 48
R P O X0Y20-X0Y23
GTH Quad 227

HP I/O Bank 67 HD I/O Bank 87
HP I/O Bank 27 HD I/O Bank 47 X0Y16-X0Y19
Q N
E [R]
GTH Quad 226
D Configuration
D [R]
GTH Quad 225
HP I/O Bank 65
C
C [R]
PCIE4 GTH Quad 224
HP I/O Bank 64
B
(tandem) B [R] (RCAL)
GTH Quad 223
PCIE4
HP I/O Bank 63 X0Y0-X0Y3
X0Y0
A [R]
X15127-111316
Figure 1‐17: XCZU7 Banks in FFVC1156 Package and XQZU7 Banks in FFRC1156 Package
GTH Quad 228

HD I/O Bank 48 X0Y20-X0Y23
R Q O
F [RN]
GTH Quad 227
S P N
E [RN]
GTH Quad 226
D Configuration
D [RS]
GTH Quad 225
HP I/O Bank 65
C
C [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
E
(tandem) B [RS] (RCAL)
GTH Quad 223
X0Y0-X0Y3
F X0Y0
A [RS]
X15128-111316
Figure 1‐18: XCZU7 Banks in FFVF1517 Package

56
XCZU6, XCZU9, and XQZU9 Bank Diagram Overview

GTH Quad 130 GTH Quad 230

HD I/O Bank 50
X0Y12-X0Y15 X1Y12-X1Y15

HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11

X0Y4-X0Y7 HD I/O Bank 48 X1Y4-X1Y7
(RCAL) (RCAL)
GTH Quad 127

X0Y0-X0Y3
SYSMON
Configuration
X15129-061420
Figure 1‐19: XCZU6, XCZU9, and XQZU9 Banks

57
Bank Diagram by Package for XCZU6, XCZU9, and XQZU9

GTH Quad 230

GTH Quad 130
X0Y12-X0Y15
C [R]
GTH Quad 229
GTH Quad 129
X0Y8-X0Y11
B [R]
HD I/O Bank 48
X0Y4-X0Y7 X1Y4-X1Y7
N
D [L] (RCAL) A [R] (RCAL)
GTH Quad 127 HD I/O Bank 47

HP I/O Bank 67
X0Y0-X0Y3 O

Configuration D
HP I/O Bank 65
C
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 HD I/O Bank 44
B
X15130-061420
Figure 1‐20: XCZU6 and XCZU9 Banks in FFVC900 Package and XQZU9 in FFRC900 Package

58

HD I/O Bank 50
X0Y12-X0Y15 X1Y12-X1Y15
Q
F [L] C [R]
HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11
P
E [L] B [R]
HD I/O Bank 48
X0Y4-X0Y7 X1Y4-X1Y7
O
GTH Quad 127 HD I/O Bank 47 HP I/O Bank 67

X0Y0-X0Y3 N E

Configuration D
HP I/O Bank 65
C

A B
X15131-061420
Figure 1‐21: XCZU6 and XCZU9 Banks in FFVB1156 Package and XQZU9 in FFRB1156 Package

59
XCZU11, XAZU11, and XQZU11 Bank Diagram Overview

GTY Quad 131 PCIE4 GTH Quad 231

X0Y16-X0Y19 X0Y3 X0Y28-X0Y31
GTY Quad 130 CMAC GTH Quad 230

X0Y12-X0Y15 X0Y1 X0Y24-X0Y27
GTY Quad 129

ILKN GTH Quad 229
X0Y8-X0Y11 HP I/O Bank 69 HD I/O Bank 89
X0Y0 X0Y20-X0Y23
(RCAL)

X0Y4-X0Y7 X0Y2 X0Y16-X0Y19
GTY Quad 127 CMAC PCIE4 GTH Quad 227

HP I/O Bank 67
X0Y0-X0Y3 X0Y0 X1Y1 X0Y12-X0Y15
GTH Quad 226

SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66 X0Y8-X0Y11
Configuration
(RCAL)
GTH Quad 225

X0Y4-X0Y7
PCIE4
GTH Quad 224
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 X1Y0
(tandem) X0Y0-X0Y3
X15132-121517
Figure 1‐22: XCZU11, XAZU11, and XQZU11 Banks

60
Bank Diagram by Package for XCZU11, XAZU11, and XQZU11


X0Y16-X0Y19 X0Y3 X0Y28-X0Y31

X0Y12-X0Y15 X0Y1 X0Y24-X0Y27
GTY Quad 129

ILKN HP I/O Bank 69 HD I/O Bank 89 GTH Quad 229
X0Y8-X0Y11
X0Y0 P O X0Y20-X0Y23
(RCAL)
GTH Quad 228
GTY Quad 128 PCIE4 HP I/O Bank 68 HD I/O Bank 88
X0Y16-X0Y19
X0Y4-X0Y7 X0Y2 Q N
E [R]
GTH Quad 227
GTY Quad 127 CMAC HP I/O Bank 67 PCIE4
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 R X1Y1
D [R]
GTH Quad 226
D Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [R]
PCIE4 GTH Quad 224
HP I/O Bank 64
B (tandem) A [R]
X15133-121517

61
GTY Quad 131 PCIE4 HP I/O Bank 71 GTH Quad 231

HD I/O Bank 91
X0Y16-X0Y19 X0Y3 T X0Y28-X0Y31
GTY Quad 130 CMAC HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y12-X0Y15 X0Y1 U P X0Y24-X0Y27
GTY Quad 129

ILKN HP I/O Bank 69 HD I/O Bank 89 GTH Quad 229
X0Y8-X0Y11
X0Y0 V O X0Y20-X0Y23
(RCAL)
GTY Quad 128 PCIE4 HP I/O Bank 68 HD I/O Bank 88 GTH Quad 228
X0Y4-X0Y7 X0Y2 W N X0Y16-X0Y19
GTH Quad 227

X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 X X1Y1
D [R]
GTH Quad 226
E Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [R]
PCIE4 GTH Quad 224
HP I/O Bank 64
D (tandem) A [R]
X15134-121517
Figure 1‐24: XCZU11 Banks in FFVB1517 Package

62
GTH Quad 231

GTY Quad 131 PCIE4 HP I/O Bank 71
X0Y16-X0Y19 X0Y3 Q
H [RN]
GTH Quad 230
GTY Quad 130 CMAC HP I/O Bank 70
X0Y12-X0Y15 X0Y1 P
G [RN]
GTY Quad 129 GTH Quad 229
ILKN HP I/O Bank 69 HD I/O Bank 89
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 R O
(RCAL) F [RN]
GTH Quad 228
X0Y16-X0Y19
X0Y4-X0Y7 X0Y2 S N
E [RN]
GTH Quad 227
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 E X1Y1
D [RS]
GTH Quad 226
D Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
F (tandem) A [RS]
X15135-121517
Figure 1‐25: XCZU11 and XAZU11 Banks in FFVF1517 Package

63

PCIE4 HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 R Q
M [L] H [RN]
CMAC HP I/O Bank 70 HD I/O Bank 90
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 S P
L [L] G [RN]
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 T O
K [L] (RCAL) F [RN]
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 U N
J [L] E [RN]
GTH Quad 227
X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 F X1Y1
D [RS]
GTH Quad 226
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
D (tandem) A [RS]
X15136-121517

64
XCZU15 and XQZU15 Bank Diagrams


HD I/O Bank 50
X0Y12-X0Y15 X1Y12-X1Y15

HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11

X0Y4-X0Y7 HD I/O Bank 48 X1Y4-X1Y7
(RCAL) (RCAL)
GTH Quad 127

X0Y0-X0Y3
SYSMON
Configuration
X15137-061420
Figure 1‐27: XCZU15 and XQZU15 Banks

65
Bank Diagram by Package for XCZU15 and XQZU15

GTH Quad 230

GTH Quad 130
X0Y12-X0Y15
C [R]
GTH Quad 229
GTH Quad 129
X0Y8-X0Y11
B [R]
HD I/O Bank 48
X0Y4-X0Y7 X1Y4-X1Y7
N
GTH Quad 127 HD I/O Bank 47

HP I/O Bank 67
X0Y0-X0Y3 O

Configuration D
HP I/O Bank 65
C
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 HD I/O Bank 44
B
X15138-061420

66

HD I/O Bank 50
X0Y12-X0Y15 X1Y12-X1Y15
Q
F [L] C [R]
HD I/O Bank 49
X0Y8-X0Y11 X1Y8-X1Y11
P
E [L] B [R]
HD I/O Bank 48
X0Y4-X0Y7 X1Y4-X1Y7
O
GTH Quad 127 HD I/O Bank 47 HP I/O Bank 67

X0Y0-X0Y3 N E

Configuration D
HP I/O Bank 65
C

A B
X15139-061420
Figure 1‐29: XCZU15 Banks in FFVB1156 Package and XQZU15 Banks in FFRB1156 Package

67
XCZU17, XCZU19, and XQZU19 Bank Diagram Overview


X0Y28-X0Y31 X0Y3 X0Y40-X0Y43
GTY Quad 133 ILKN GTH Quad 233

X0Y24-X0Y27 X0Y2 X0Y36-X0Y39
GTY Quad 132 CMAC ILKN GTH Quad 232

HP I/O Bank 72
X0Y20-X0Y23 X0Y2 X1Y1 X0Y32-X0Y35

X0Y16-X0Y19 X0Y3 X0Y28-X0Y31

X0Y12-X0Y15 X0Y1 X0Y24-X0Y27
GTY Quad 129

ILKN ILKN GTH Quad 229
X0Y8-X0Y11 HP I/O Bank 69
X0Y0 X1Y0 X0Y20-X0Y23
(RCAL)
GTY Quad 128 PCIE4 PCIE4 GTH Quad 228

HP I/O Bank 68
X0Y4-X0Y7 X0Y2 X1Y2 X0Y16-X0Y19
GTY Quad 127 CMAC PCIE4 GTH Quad 227

HP I/O Bank 67
X0Y0-X0Y3 X0Y0 X1Y1 X0Y12-X0Y15
GTH Quad 226

SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66 X0Y8-X0Y11
Configuration
(RCAL)
GTH Quad 225

X0Y4-X0Y7
PCIE4
GTH Quad 224
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 X1Y0
(tandem) X0Y0-X0Y3
X15140-071417
Figure 1‐30: XCZU17, XCZU19, and XQZU19 Banks

68
Bank Diagram by Package for XCZU17, XCZU19, and XQZU19

GTY Quad 134 CMAC HP I/O Bank 74 GTH Quad 234

HD I/O Bank 94
X0Y28-X0Y31 X0Y3 Q X0Y40-X0Y43
GTY Quad 133 ILKN HP I/O Bank 73 HD I/O Bank 93 GTH Quad 233
X0Y24-X0Y27 X0Y2 R P X0Y36-X0Y39
GTY Quad 132 CMAC HP I/O Bank 72 ILKN GTH Quad 232
X0Y20-X0Y23 X0Y2 S X1Y1 X0Y32-X0Y35
GTY Quad 131 PCIE4 HP I/O Bank 71 HD I/O Bank 91 GTH Quad 231
X0Y16-X0Y19 X0Y3 T O X0Y28-X0Y31
GTY Quad 130 CMAC HP I/O Bank 70 HD I/O Bank 90 GTH Quad 230
X0Y12-X0Y15 X0Y1 U N X0Y24-X0Y27
GTY Quad 129 HP I/O Bank 69 GTH Quad 229

ILKN ILKN
X0Y8-X0Y11
(RCAL) X0Y0 V X1Y0 X0Y20-X0Y23
GTY Quad 128 PCIE4 HP I/O Bank 68 PCIE4 GTH Quad 228
X0Y4-X0Y7 X0Y2 W X1Y2 X0Y16-X0Y19
GTH Quad 227

X0Y12-X0Y15
D [R]
GTH Quad 226
E Configuration
C [R] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [R]
PCIE4 GTH Quad 224
HP I/O Bank 64
D (tandem) A [R]
X15141-071417
Figure 1‐31: XCZU17 and XCZU19 Banks in FFVB1517 Package and

XQZU19 Banks in FFRB1517 Package

69
GTY Quad 134 CMAC HD I/O Bank 94 GTH Quad 234

HP I/O Bank 74
X0Y28-X0Y31 X0Y3 Q X0Y40-X0Y43
GTY Quad 133 ILKN HD I/O Bank 93 GTH Quad 233

HP I/O Bank 73
X0Y24-X0Y27 X0Y2 P X0Y36-X0Y39
GTY Quad 132 CMAC ILKN GTH Quad 232

HP I/O Bank 72
X0Y20-X0Y23 X0Y2 X1Y1 X0Y32-X0Y35

X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 R O
M [L] H [RN]
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 S N
L [L] G [RN]
ILKN HP I/O Bank 69 ILKN
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 T X1Y0
K [L] (RCAL) F [RN]
PCIE4 HP I/O Bank 68 PCIE4
X0Y4-X0Y7 X0Y16-X0Y19
X0Y2 U X1Y2
J [L] E [RN]
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTH Quad 226
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
D (tandem) A [RS]
X15142-071417
Figure 1‐32: XCZU17 and XCZU19 Banks in FFVC1760 Package and

XQZU19 Banks in FFRC1760 Package

70

CMAC
X0Y28-X0Y31 HP I/O Bank 74 HD I/O Bank 94 X0Y40-X0Y43
X0Y3
R [L] K [RN]
ILKN
X0Y24-X0Y27 HP I/O Bank 73 HD I/O Bank 93 X0Y36-X0Y39
X0Y2
Q [L] J [RN]
CMAC ILKN
X0Y20-X0Y23 HP I/O Bank 72 X0Y32-X0Y35
X0Y2 X1Y1
P [L] I [RN]
X0Y16-X0Y19 X0Y28-X0Y31
X0Y3 P O
O [L] H [RN]
X0Y12-X0Y15 X0Y24-X0Y27
X0Y1 Q N
N [L] G [RN]
X0Y8-X0Y11 X0Y20-X0Y23
X0Y0 R X1Y0
M [L] (RCAL) F [RS]
PCIE4 PCIE4
X0Y4-X0Y7 HP I/O Bank 68 X0Y16-X0Y19
X0Y2 X1Y2
L [L] E [RS]
GTH Quad 227
GTY Quad 127 CMAC PCIE4
HP I/O Bank 67 X0Y12-X0Y15
X0Y0-X0Y3 X0Y0 X1Y1
D [RS]
GTH Quad 226
D Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [RS]
PCIE4 GTH Quad 224
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 X1Y0 X0Y0-X0Y3
(tandem) A [RS]
X15143-071417
Figure 1‐33: XCZU17 and XCZU19 Banks in FFVD1760 Package

71
GTH Quad 234

GTY Quad 134 CMAC HP I/O Bank 74 HD I/O Bank 94
X0Y40-X0Y43
X0Y28-X0Y31 X0Y3 R Q
K [RN]
GTH Quad 233
GTY Quad 133 ILKN HP I/O Bank 73 HD I/O Bank 93
X0Y36-X0Y39
X0Y24-X0Y27 X0Y2 S P
J [RN]
GTH Quad 232
GTY Quad 132 CMAC HP I/O Bank 72 ILKN
X0Y32-X0Y35
X0Y20-X0Y23 X0Y2 T X1Y1
I [RN]
GTH Quad 231
X0Y28-X0Y31
X0Y16-X0Y19 X0Y3 U O
H [RN]
GTH Quad 230
X0Y24-X0Y27
X0Y12-X0Y15 X0Y1 V N
G [RN]
X0Y8-X0Y11 X0Y20-X0Y23
(RCAL) X0Y0 W X1Y0
F [RS]
GTH Quad 228
GTY Quad 128 PCIE4 HP I/O Bank 68 PCIE4
X0Y16-X0Y19
E [RS]
GTH Quad 227
X0Y12-X0Y15
D [RS]
GTH Quad 226
E Configuration
C [RS] (RCAL)
GTH Quad 225
HP I/O Bank 65
C
B [RS]
PCIE4 GTH Quad 224
HP I/O Bank 64
D (tandem) A [RS]
X15144-071417
Figure 1‐34: XCZU17 and XCZU19 Banks in FFVE1924 Package

72
XCZU21DR and XQZU21DR Bank Diagram Overview

GTY Quad 131 PCIE4

SD-FEC HP I/O Bank 71 HD I/O Bank 91
X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y8-X0Y11 SD-FEC HP I/O Bank 69 HD I/O Bank 89
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
PS GTR 505 PS MIO 502 SD-FEC HP I/O Bank 66
Configuration
PS DDR 504 PS MIO 501 SD-FEC HP I/O Bank 65 Configuration
PS CONFIG 503 PS MIO 500 SD-FEC HP I/O Bank 64 HD I/O Bank 84
X19543-101518
Figure 1‐35: XCZU21DR and XQZU21DR Banks

73
Bank Diagram by Package for XCZU21DR and XQZU21DR

GTY Quad 131 PCIE4

X0Y1
D [L]
GTY Quad 130 CMAC
X0Y1
C [L]
GTY Quad 129 ILKN HD I/O Bank 89
X0Y8-X0Y11 SD-FEC HP I/O Bank 69
X0Y0 P
B [L] (RCAL)
X0Y4-X0Y7 SD-FEC
X0Y0 F O
A [L]
SD-FEC
X0Y0-X0Y3 X0Y0 E N

PS GTR 505 PS MIO 502 SD-FEC
D Configuration
HP I/O Bank 65
PS DDR 504 PS MIO 501 SD-FEC Configuration
C
PS CONFIG 503 PS MIO 500 SD-FEC HP I/O Bank 64 HD I/O Bank 84
;
X19545-101518
X19545-081621
Figure 1‐36: XCZU21DR Banks in FFVD1156 Package and XQZU21DR Banks in FFRD1156 Package

74
XCZU25DR Bank Diagram Overview

GTY Quad 129

ILKN
X0Y8-X0Y11 HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229
X0Y0
(RCAL)
GTY Quad 128 PCIE4

HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
X0Y0-X0Y3 X0Y0
SYSMON
PS GTR 505 PS MIO 502 HP I/O Bank 66 ADC Bank 226
Configuration
PS DDR 504 PS MIO 501 HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19546-042720
Figure 1‐37: XCZU25DR Banks
Bank Diagram by Package for XCZU25DR

GTY Quad 129

ILKN HD I/O Bank 89
X0Y8-X0Y11 HP I/O Bank 69 DAC Bank 229
X0Y0 O
B [L] (RCAL)
GTY Quad 128
PCIE4 HD I/O Bank 88
X0Y0 N
A [L]
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0

PS GTR 505 PS MIO 502 ADC Bank 226
D Configuration
HP I/O Bank 65
PS DDR 504 PS MIO 501 Configuration ADC Bank 225
C
X19547-042720
Figure 1‐38: XCZU25DR Banks in FFVE1156 and FSVE1156 Packages

75
GTY Quad 129

ILKN HP I/O Bank 69
X0Y8-X0Y11 HD I/O Bank 89 DAC Bank 229
X0Y0 S
B [L] (RCAL)
GTY Quad 128
PCIE4 HP I/O Bank 68
X0Y0 R
A [L]

ADC Bank 227
X0Y0-X0Y3 X0Y0 Q N

D Configuration
HP I/O Bank 65
C

PS CONFIG 503 PS MIO 500 ADC Bank 224
B (Partial) A
X19548-040720
Figure 1‐39: XCZU25DR Banks in FFVG1517 and FSVG1517 Packages

76

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X19549-040320

77

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN HD I/O Bank 89
X0Y0 O
B [L] (RCAL)
GTY Quad 128
X0Y0 N
A [L]
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0

D Configuration
HP I/O Bank 65
C
X19550-040320

78
GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
ILKN HP I/O Bank 69
X0Y0 S
B [L] (RCAL)
GTY Quad 128
X0Y0 R
A [L]

ADC Bank 227
X0Y0-X0Y3 X0Y0 Q N

D Configuration
HP I/O Bank 65
C

B (Partial) A
X19551-040320

79
XCZU28DR and XQZU28DR Bank Diagram Overview

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129
ILKN
X0Y8-X0Y11 SD-FEC HP I/O Bank 69 HD I/O Bank 89 DAC Bank 229
X0Y0
(RCAL)
GTY Quad 128 PCIE4
SD-FEC HP I/O Bank 68 HD I/O Bank 88 DAC Bank 228
X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

SD-FEC HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
X0Y0-X0Y3 X0Y0
SYSMON
PS GTR 505 PS MIO 502 SD-FEC HP I/O Bank 66 ADC Bank 226
Configuration
PS DDR 504 PS MIO 501 SD-FEC HP I/O Bank 65 Configuration ADC Bank 225
PS CONFIG 503 PS MIO 500 SD-FEC HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X19552-040320
Figure 1‐43: XCZU28DR and XQZU28DR Banks

80
Bank Diagram by Package for XCZU28DR and XQZU28DR

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN HD I/O Bank 89
X0Y8-X0Y11 SD-FEC HP I/O Bank 69 DAC Bank 229
X0Y0 O
B [L] (RCAL)
GTY Quad 128
X0Y4-X0Y7 SD-FEC HP I/O Bank 68 DAC Bank 228
X0Y0 N
A [L]
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0

PS GTR 505 PS MIO 502 SD-FEC ADC Bank 226
D Configuration
HP I/O Bank 65
PS DDR 504 PS MIO 501 SD-FEC Configuration ADC Bank 225
C
X19553-042720
Figure 1‐44: XCZU28DR Banks in FFVE1156 and FSVE1156 Packages and

XQZU28DR in FFRE1156 Package

81
GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
ILKN HP I/O Bank 69
X0Y8-X0Y11 SD-FEC HD I/O Bank 89 DAC Bank 229
X0Y0 S
B [L] (RCAL)
GTY Quad 128
X0Y0 R
A [L]

SD-FEC ADC Bank 227
X0Y0-X0Y3 X0Y0 Q N

D Configuration
HP I/O Bank 65
C

PS CONFIG 503 PS MIO 500 SD-FEC ADC Bank 224
B (Partial) A
X19554-042720
Figure 1‐45: XCZU28DR Banks in FFVG1517 and FSVG1517 Packages and

XQZU28DR in FFRG1517 Package

82
XCZU29DR, XQZU29DR, and XCZU39DR Bank Diagram Overview

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X19555-040620
Figure 1‐46: XCZU29DR, XQZU29DR, and XCZU39DR Banks

83
Bank Diagram by Package for XCZU29DR, XQZU29DR, and XCZU39DR

GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
X0Y8-X0Y11 DAC Bank 229
X0Y0 T P
B [L] (RCAL)
GTY Quad 128
X0Y0 S O
A [L]

ADC Bank 227
X0Y0-X0Y3 X0Y0 R N

D Configuration
HP I/O Bank 65
C

B A
X19556-042620
Figure 1‐47: XCZU29DR and XCZU39DR Banks in FFVF1760 and FSVF1760 Packages and
XQZU29DR Banks in FFRF1760 Package

84

GTY Quad 128

(RCAL)
GTY Quad 127 CMAC

HP I/O Bank 67 DAC Bank 227
X0Y0-X0Y3 X0Y0
SYSMON
Configuration
PS CONFIG 503 PS MIO 500 HP I/O Bank 64 ADC Bank 224
X25704-090221

GTY Quad 128

HD I/O Bank 88
O
B [L] (RCAL)
GTY Quad 127
CMAC HP I/O Bank 67
X0Y0 N (Partial)
A [L]

D Configuration
HP I/O Bank 65
C
X25705-011422

85

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X23814-042620

86

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN HD I/O Bank 89
X0Y0 O
B [L] (RCAL)
GTY Quad 128
X0Y0 N
A [L]
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0

D Configuration
HP I/O Bank 65
C
X23816-122021

87
GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
ILKN HP I/O Bank 69
X0Y0 S
B [L] (RCAL)
GTY Quad 128
X0Y0 R
A [L]

ADC Bank 227
X0Y0-X0Y3 X0Y0 Q N

D Configuration
HP I/O Bank 65
C

B (Partial) A
X23817-042720

88

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X23818-042720

89

GTY Quad 131

X0Y16-X0Y19 SD-FEC DAC Bank 231
X0Y1 S P
D [L]
GTY Quad 130
X0Y12-X0Y15 SD-FEC DAC Bank 230
X0Y1 T O
C [L]
GTY Quad 129 ILKN HP I/O Bank 69

X0Y0 R
B [L] (RCAL)
GTY Quad 128
PCIE4
X0Y0
A [L]
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0

D Configuration
HP I/O Bank 65
C
HP I/O Bank 64
PS CONFIG 503 PS MIO 500 SD-FEC HD I/O Bank 84 ADC Bank 224
B
X23819-081621
Figure 1‐54: XCZU46DR Banks in FFVH1760 and FSVH1760 Packages

90

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X23820-042720

91

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN HD I/O Bank 89
X0Y0 O
B [L] (RCAL)
GTY Quad 128
X0Y0 N
A [L]
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0

D Configuration
HP I/O Bank 65
C
X23821-042720

92
GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
ILKN HP I/O Bank 69
X0Y0 S
B [L] (RCAL)
GTY Quad 128
X0Y0 R
A [L]

ADC Bank 227
X0Y0-X0Y3 X0Y0 Q N

D Configuration
HP I/O Bank 65
C

B (Partial) A
X23822-042720

93

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129 ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4
X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X23823-042720

94

GTY Quad 131 PCIE4

FEC HP I/O Bank 71 HD I/O Bank 91 DAC Bank 231
X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

FEC HP I/O Bank 70 HD I/O Bank 90 DAC Bank 230
X0Y12-X0Y15 X0Y1
GTY Quad 129
ILKN HD I/O Bank 89
X0Y8-X0Y11 FEC HP I/O Bank 69 DAC Bank 229
X0Y0 O
B [L] (RCAL)
GTY Quad 128
X0Y4-X0Y7 FEC HP I/O Bank 68 DAC Bank 228
X0Y0 N
A [L]
GTY Quad 127 CMAC
FEC HP I/O Bank 67 HD I/O Bank 87 ADC Bank 227
X0Y0-X0Y3 X0Y0

PS GTR 505 PS MIO 502 FEC ADC Bank 226
D Configuration
HP I/O Bank 65
PS DDR 504 PS MIO 501 FEC Configuration ADC Bank 225
C
PS CONFIG 503 PS MIO 500 FEC HP I/O Bank 64 HD I/O Bank 84 ADC Bank 224
X23824-042720

GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
ILKN HP I/O Bank 69
X0Y0 S
B [L] (RCAL)
GTY Quad 128
X0Y0 R
A [L]
SD-FEC ADC Bank 227
X0Y0-X0Y3 X0Y0 Q N

D Configuration
HP I/O Bank 65
C

PS CONFIG 503 PS MIO 500 SD-FEC ADC Bank 224
B (Partial) A
X23825-042720
Figure 1‐60: XCZU48DR Banks in FFVG1517 and FSVG1517, and XQZU48DR Banks in FSRG1517 Packages

95

GTY Quad 131 PCIE4

X0Y16-X0Y19 X0Y1
GTY Quad 130 CMAC

X0Y12-X0Y15 X0Y1
GTY Quad 129

ILKN
X0Y0
(RCAL)
GTY Quad 128 PCIE4

X0Y4-X0Y7 X0Y0
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X23826-042720

96

GTY Quad 131

PCIE4
X0Y1
D [L]
GTY Quad 130
CMAC
X0Y1
C [L]
GTY Quad 129
X0Y0 T P
B [L] (RCAL)
GTY Quad 128
X0Y0 S O
A [L]

ADC Bank 227
X0Y0-X0Y3 X0Y0 R N

D Configuration
HP I/O Bank 65
C

B A
X23815-042720
Figure 1‐62: XCZU49DR Banks in FFVF1760 and FSVF1760, and XQZU49DR Banks in FSRF1760 Packages

97

GTY Quad 128

(RCAL)
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X25706-090221

GTY Quad 128

HD I/O Bank 88
O
B [L] (RCAL)
GTY Quad 127
CMAC HP I/O Bank 67
X0Y0 N (Partial)
A [L]

D Configuration
HP I/O Bank 65
C
X25707-011322

98

GTY Quad 128

(RCAL)
GTY Quad 127 CMAC

X0Y0-X0Y3 X0Y0
SYSMON
Configuration
X25708-090221

GTY Quad 128

HD I/O Bank 88
O
B [L] (RCAL)
GTY Quad 127
CMAC HP I/O Bank 67
X0Y0 N (Partial)
A [L]

D Configuration
HP I/O Bank 65
C
X25709-011322

99
Chapter 2
PS Memory Interface Pin Guidelines
Introduction to PS Memory Interface Pins

This chapter shows what is needed to support the broad requirements of various memory
interfaces using the Zynq® UltraScale+™ device DDR subsystem. It covers DDR3/3L, DDR4,
LPDDR4, and LPDDR3.
IMPORTANT: SBVA484 and SFVA625 packages only support 32-bit data buses for the PS DDR
controller. The Zynq UltraScale+ device DDR subsystem can only be configured for 32-bit or 32-bit plus
ECC DDR3/DDR4/LPDDR3 designs when using these packages.
DDR3/3L Guidelines
DDR3/3L Pin Rules
The DDR3/3L pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in a 64-bit interface without
ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins
can be left unconnected.
• Connect the PS_DDR_ZQ pin to GND using a 240 resistor. There should be separate
240 resistors at the MPSoC or RFSoC and at the DRAM.
DDR3/3L Pin Swapping Restrictions

• Address/command/control bits cannot be swapped.
• DQ byte lane swapping is allowed. A byte lane includes any signals associated with the
aligned 8-bits of DQ, such as DM, DQS, DQS_N, and DQ signals.
• DQ bits swapping within a byte lane is allowed.

100
DDR3/3L Pinout Example for Supported Configurations

Table 2-1 shows a pinout example for the DDR3/3L supported configurations. For
termination details, see the UltraScale Architecture PCB Design Guide [Ref 14]. When not
being used for a memory interface, all pins should be left unconnected with the exception
of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.
IMPORTANT: VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq

UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics [Ref 8] and Zynq UltraScale+
RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9], where both VCC_PSINTFP and
VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid
MBIST failure.
Table 2‐1: DDR3/3L Supported Pinout Configurations

DDR3/3L 64-bit DDR3/3L 64-bit DDR3/3L 32-bit DDR3/3L 32-bit
Pin Name
1Rank 2Rank 1Rank 2Rank
VCCO_PSDDR(1) Set to 1.5V (1.35V Set to 1.5V (1.35V Set to 1.5V (1.35V Set to 1.5V (1.35V
for DDR3L) for DDR3L) for DDR3L) for DDR3L)
PS_DDR_A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to
PS_DDR_A15 PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to
PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so
on. on. on. on.
PS_DDR_A16 WE# WE# WE# WE#
PS_DDR_A17 CAS# CAS# CAS# CAS#
PS_DDR_ACT_N RAS# RAS# RAS# RAS#
PS_DDR_ALERT_N Can be left Can be left Can be left Can be left
unconnected. unconnected. unconnected. unconnected.
PS_DDR_BA0 BA[0] BA[0] BA[0] BA[0]
PS_DDR_BA1 BA[1] BA[1] BA[1] BA[1]
PS_DDR_BG0 BA[2] BA[2] BA[2] BA[2]
PS_DDR_BG1 Can be left Can be left Can be left Can be left
PS_DDR_CK_N0 CK# CK#[0] CK# CK#[0]
PS_DDR_CK_N1 Can be left CK#[1] Can be left CK#[1]
unconnected. unconnected.
PS_DDR_CK0 CK. CK[0] CK. CK[0]
PS_DDR_CK1 Can be left CK[1] Can be left CK[1]
PS_DDR_CKE0 CKE CKE[0] CKE CKE[0]
PS_DDR_CKE1 Can be left CKE[1] Can be left CKE[1]
PS_DDR_CS_N0 CS# CS#[0] CS# CS#[0]

101
Table 2‐1: DDR3/3L Supported Pinout Configurations (Cont’d)
Pin Name DDR3/3L 64-bit DDR3/3L 64-bit DDR3/3L 32-bit DDR3/3L 32-bit
PS_DDR_CS_N1 Can be left CS#[1] Can be left CS#[1]
PS_DDR_DM0 to Connect DM0 to Connect DM0 to Connect DM0 to Connect DM0 to
PS_DDR_DM3 PS_DDR_DM0, DM1 PS_DDR_DM0, DM1 PS_DDR_DM0, DM1 PS_DDR_DM0, DM1
to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1,
and so on. and so on. and so on. and so on.
PS_DDR_DM4 to Connect DM4 to Connect DM4 to Can be left Can be left
PS_DDR_DM7 PS_DDR_DM4, DM5 PS_DDR_DM4, DM5 unconnected. unconnected.
to PS_DDR_DM5, to PS_DDR_DM5,
and so on. and so on.
PS_DDR_DM8 DM8, can be left DM8, can be left DM4, can be left DM4, can be left
unconnected unconnected unconnected unconnected
without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to
PS_DDR_DQ31 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1
to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1,
PS_DDR_DQ32 to Connect DQ32 to Connect DQ32 to Can be left Can be left
PS_DDR_DQ63 PS_DDR_DQ32, PS_DDR_DQ32, unconnected. unconnected.
DQ33 to DQ33 to
PS_DDR_DQ33, and PS_DDR_DQ33, and
so on. so on.
PS_DDR_DQ64 ECC_bit[0], can be ECC_bit[0], can be ECC_bit[0], can be ECC_bit[0], can be
left unconnected left unconnected left unconnected left unconnected

102
Table 2‐1: DDR3/3L Supported Pinout Configurations (Cont’d)
Pin Name DDR3/3L 64-bit DDR3/3L 64-bit DDR3/3L 32-bit DDR3/3L 32-bit
PS_DDR_DQS_N0 to Connect DQS#0 to Connect DQS#0 to Connect DQS#0 to Connect DQS#0 to
PS_DDR_DQS_N3 PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0,
DQS#1 to DQS#1 to DQS#1 to DQS#1 to
PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1,
PS_DDR_DQS_N4 to Connect DQS#4 to Connect DQS#4 to Can be left Can be left
PS_DDR_DQS_N7 PS_DDR_DQS_N4, PS_DDR_DQS_N4, unconnected. unconnected.
DQS#5 to DQS#5 to
PS_DDR_DQS_N5, PS_DDR_DQS_N5,
PS_DDR_DQS_N8 DQS#8, can be left DQS#8, can be left DQS#4, can be left DQS#4, can be left
PS_DDR_DQS_P0 to Connect DQS0 to Connect DQS0 to Connect DQS0 to Connect DQS0 to
PS_DDR_DQS_P3 PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0,
DQS1 to DQS1 to DQS1 to DQS1 to
PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1,
PS_DDR_DQS_P4 to Connect DQS4 to Connect DQS4 to Can be left Can be left
PS_DDR_DQS_P7 PS_DDR_DQS_P4, PS_DDR_DQS_P4, unconnected. unconnected.
DQS5 to DQS5 to
PS_DDR_DQS_P5, PS_DDR_DQS_P5,
PS_DDR_DQS_P8 DQS8, can be left DQS8, can be left DQS4, can be left DQS4, can be left
PS_DDR_ODT0 ODT ODT[0] ODT ODT[0]
PS_DDR_ODT1 Can be left ODT[1] Can be left ODT[1]
PS_DDR_PARITY Par_In for RDIMMs. Par_In for RDIMMs. Par_In for RDIMMs. Par_In for RDIMMs.
Can be left Can be left Can be left Can be left
unconnected for unconnected for unconnected for unconnected for
components and components and components and components and
UDIMMs. UDIMMs. UDIMMs. UDIMMs.
PS_DDR_RAM_RST_N RESET# RESET# RESET# RESET#
PS_DDR_ZQ Connect a 240 Connect a 240 Connect a 240 Connect a 240
resistor to GND.(2) resistor to GND. (2) resistor to GND.(2) resistor to GND. (2)
Notes:
1. For VCCO_PSDDR decoupling guidelines, see the UltraScale Architecture PCB Design Guide [Ref 14].
2. There should be separate 240 resistors at the FPGA and at the DRAM.

103
DDR4 Guidelines
DDR4 Pin Rules
The DDR4 pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in a 64-bit interface without
ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and PS_DDR_DM8 pins
can be left unconnected.
• The PS_DDR_ALERT_N can be left floating at the DRAM. For component interfaces,
connect the PS_DDR_ALERT_N pin to the ALERT_N pins of the DDR4 devices in fly-by
routing, and terminate to V DD with a 50 pull-up resistor. For DIMM designs, connect
the PS_DDR_ALERT_N pin to the ALERT_N pin of the connector.
240 resistors at the FPGA and at the DRAM.
• Component interfaces with the same component for all components in the interface.
The x16 components have a different number of bank groups than the x8 components.
For example, create a 72-bit wide component interface by using nine x8 components or
five x16 components, where half of one component is not used. Creating four x16
components and one x8 component is not permissible.
DDR4 Pin Swapping Restrictions

• Address/command/control bits cannot be swapped.
• DQ byte lane swapping is allowed. A byte lane includes any signals associated with the
aligned 8-bits of DQ, such as DM, DQS, DQS_N, and DQ signals.
• DQ bits swapping within a byte lane is allowed.

104
DDR4 Pinout Example for Supported Configurations

Table 2-2 shows a pinout example for the DDR4 supported configurations. For termination details, see the UltraScale
Architecture PCB Design Guide [Ref 14]. When not being used for a memory interface, all pins should be left unconnected with
the exception of VCCO_PSDDR and VCC_PSDDR_PLL, which should be tied to GND.
IMPORTANT: VCC_PSINTFP must be tied to VCC_PSINTFP_DDR. This requirement is in Zynq UltraScale+ MPSoC Data Sheet: DC and AC
Switching Characteristics [Ref 8] and Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics [Ref 9], where both
VCC_PSINTFP and VCC_PSINTFP_DDR must be connected to the same supply and thus both must be powered to avoid MBIST failure.
Table 2‐2: DDR4 Supported Pinout Configurations
Pin Name DDR4 64-bit DDR4 64-bit DDR4 32-bit DDR4 32-bit DDR4 16-bit DDR4 16-bit
1Rank 2Rank 1Rank 2Rank 1Rank 2Rank
VCCO_PSDDR(1) Set to 1.2V. Set to 1.2V. Set to 1.2V. Set to 1.2V. Set to 1.2V. Set to 1.2V.
PS_DDR_A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to Connect A0 to
PS_DDR_A16 PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to PS_DDR_A0, A1 to
PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so PS_DDR_A1, and so
on. on. on. on. on. on.
WE_N can be shared WE_N can be shared WE_N can be shared WE_N can be shared WE_N can be shared WE_N can be shared
with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14, with PS_DDR_A14,
CAS_N can be CAS_N can be CAS_N can be CAS_N can be CAS_N can be CAS_N can be
shared with shared with shared with shared with shared with shared with
PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and PS_DDR_A15, and
RAS_N can be RAS_N can be RAS_N can be RAS_N can be RAS_N can be RAS_N can be
shared with shared with shared with shared with shared with shared with
PS_DDR_A16. PS_DDR_A16. PS_DDR_A16. PS_DDR_A16. PS_DDR_A16. PS_DDR_A16.
PS_DDR_A17 Can be left Can be left Can be left Can be left Can be left Can be left
unconnected unconnected unconnected unconnected unconnected unconnected
PS_DDR_ACT_N ACT_n ACT_n ACT_n ACT_n ACT_n ACT_n
PS_DDR_ALERT_N ALERT_n ALERT_n ALERT_n ALERT_n ALERT_n ALERT_n
PS_DDR_BA0 BA[0] BA[0] BA[0] BA[0] BA[0] BA[0]
PS_DDR_BA1 BA[1] BA[1] BA[1] BA[1] BA[1] BA[1]
PS_DDR_BG0 BG[0] BG[0] BG[0] BG[0] BG[0] BG[0]

Table 2‐2: DDR4 Supported Pinout Configurations (Cont’d)
PS_DDR_BG1 (2) BG[1] BG[1] BG[1] BG[1] BG[1] BG[1]
PS_DDR_CK_N0 CK_c[0] CK_c[0] CK_c[0] CK_c[0] CK_c[0] CK_c[0]
PS_DDR_CK_N1 Can be left CK_c[1] Can be left CK_c[1] Can be left CK_c[1]
unconnected. unconnected. unconnected.
PS_DDR_CK0 CK_t[0] CK_t[0] CK_t[0] CK_t[0] CK_t[0] CK_t[0]
PS_DDR_CK1 Can be left CK_t[1] Can be left CK_t[1] Can be left CK_t[1]
PS_DDR_CKE0 CKE CKE[0] CKE CKE[0] CKE CKE[0]
PS_DDR_CKE1 Can be left CKE[1] Can be left CKE[1] Can be left CKE[1]
PS_DDR_CS_N0 CS_n CS_n[0] CS_n CS_n[0] CS_n CS_n[0]
PS_DDR_CS_N1 Can be left CS_n[1] Can be left CS_n[1] Can be left CS_n[1]
PS_DDR_DM0 to Connect Connect Connect Connect Connect Connect
PS_DDR_DM1 DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0] DM_n[0]/DBI_n[0]
to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0, to PS_DDR_DM0,
DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1] DM_n[1]/DBI_n[1]
to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1, to PS_DDR_DM1,
and so on. and so on. and so on. and so on. and so on. and so on.
PS_DDR_DM2 to Connect Connect Connect Connect Can be left Can be left
PS_DDR_DM3 DM_n[2]/DBI_n[2] DM_n[2]/DBI_n[2] DM_n[2]/DBI_n[2] DM_n[2]/DBI_n[2] unconnected. unconnected.
DM_n[3]/DBI_n[3] DM_n[3]/DBI_n[3] DM_n[3]/DBI_n[3] DM_n[3]/DBI_n[3]

PS_DDR_DM4 to Connect Connect Can be left Can be left Can be left Can be left
PS_DDR_DM7 DM_n[4]/DBI_n[4] DM_n[4]/DBI_n[4] unconnected. unconnected. unconnected. unconnected.
DM_n[5]/DBI_n[5] DM_n[5]/DBI_n[5]
PS_DDR_DM8 DM_n[8]/DBI_n[8], DM_n[8]/DBI_n[8], DM_n[4]/DBI_n[4], DM_n[4]/DBI_n[4], DM_n[2]/DBI_n[2], DM_n[2]/DBI_n[2],
can be left can be left can be left can be left can be left can be left
without ECC. without ECC. without ECC. without ECC. without ECC. without ECC.
PS_DDR_DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to Connect DQ0 to
PS_DDR_DQ15 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1 PS_DDR_DQ0, DQ1
to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1, to PS_DDR_DQ1,
PS_DDR_DQ16 to Connect DQ16 to Connect DQ16 to Connect DQ16 to Connect DQ16 to Can be left Can be left
PS_DDR_DQ31 PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16, unconnected. Do unconnected. Do
DQ17 to DQ17 to DQ17 to DQ17 to not swap with not swap with
PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ0 to PS_DDR_DQ0 to
so on. so on. so on. so on. PS_DDR_DQ15. PS_DDR_DQ15.
PS_DDR_DQ32 to Connect DQ32 to Connect DQ32 to Can be left Can be left Can be left Can be left
PS_DDR_DQ63 PS_DDR_DQ32, PS_DDR_DQ32, unconnected. Do unconnected. Do unconnected. Do unconnected. Do
DQ33 to DQ33 to not swap with not swap with not swap with not swap with
PS_DDR_DQ33, and PS_DDR_DQ33, and PS_DDR_DQ0 to PS_DDR_DQ0 to PS_DDR_DQ0 to PS_DDR_DQ0 to
so on. so on. PS_DDR_DQ31. PS_DDR_DQ31. PS_DDR_DQ31. PS_DDR_DQ31.
PS_DDR_DQ64 ECC_bit[0], can be ECC_bit[0], can be ECC_bit[0], can be ECC_bit[0], can be ECC_bit[0], can be ECC_bit[0], can be
left unconnected left unconnected left unconnected left unconnected left unconnected left unconnected

PS_DDR_DQS_N0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to Connect DQS_c0 to
PS_DDR_DQS_N1 PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0, PS_DDR_DQS_N0,
DQS_c1 to DQS_c1 to DQS_c1 to DQS_c1 to DQS_c1 to DQS_c1 to
PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1, PS_DDR_DQS_N1,
PS_DDR_DQS_N2 to Connect DQS_c2 to Connect DQS_c2 to Connect DQS_c2 to Connect DQS_c2 to Can be left Can be left
PS_DDR_DQS_N3 PS_DDR_DQS_N2, PS_DDR_DQS_N2, PS_DDR_DQS_N2, PS_DDR_DQS_N2, unconnected. unconnected.
DQS_c3 to DQS_c3 to DQS_c3 to DQS_c3 to
PS_DDR_DQS_N3, PS_DDR_DQS_N3, PS_DDR_DQS_N3, PS_DDR_DQS_N3,

PS_DDR_DQS_N4 to Connect DQS_c4 to Connect DQS_c4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_N7 PS_DDR_DQS_N4, PS_DDR_DQS_N4, unconnected. unconnected. unconnected. unconnected.
DQS_c5 to DQS_c5 to
PS_DDR_DQS_N5, PS_DDR_DQS_N5,
PS_DDR_DQS_N8 DQS_c8, can be left DQS_c8, can be left DQS_c4, can be left DQS_c4, can be left DQS_c2, can be left DQS_c2, can be left
PS_DDR_DQS_P0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to Connect DQS_t0 to
PS_DDR_DQS_P1 PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0, PS_DDR_DQS_P0,
DQS_t1 to DQS_t1 to DQS_t1 to DQS_t1 to DQS_t1 to DQS_t1 to
PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1, PS_DDR_DQS_P1,
PS_DDR_DQS_P2 to Connect DQS_t2 to Connect DQS_t2 to Connect DQS_t2 to Connect DQS_t2 to Can be left Can be left
PS_DDR_DQS_P3 PS_DDR_DQS_P2, PS_DDR_DQS_P2, PS_DDR_DQS_P2, PS_DDR_DQS_P2, unconnected. unconnected.
DQS_t3 to DQS_t3 to DQS_t3 to DQS_t3 to
PS_DDR_DQS_P3, PS_DDR_DQS_P3, PS_DDR_DQS_P3, PS_DDR_DQS_P3,
PS_DDR_DQS_P4 to Connect DQS_t4 to Connect DQS_t4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_P7 PS_DDR_DQS_P4, PS_DDR_DQS_P4, unconnected. unconnected. unconnected. unconnected.
DQS_t5 to DQS_t5 to
PS_DDR_DQS_P5, PS_DDR_DQS_P5,
PS_DDR_DQS_P8 DQS_t8, can be left DQS_t8, can be left DQS_t4, can be left DQS_t4, can be left DQS_t2, can be left DQS_t2, can be left
PS_DDR_ODT0 ODT ODT[0] ODT ODT[0] ODT ODT[0]
PS_DDR_ODT1 Can be left ODT[1] Can be left ODT[1] Can be left ODT[1]
PS_DDR_PARITY PAR PAR PAR PAR PAR PAR
PS_DDR_RAM_RST_N RESET_n RESET_n RESET_n RESET_n RESET_n RESET_n

PS_DDR_ZQ Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND Connect to GND
through a 240 through a 240 through a 240 through a 240 through a 240 through a 240
resistor. Connect resistor. Connect resistor. Connect resistor. Connect resistor. Connect resistor. Connect
DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to
VSSQ through a VSSQ through a VSSQ through a VSSQ through a VSSQ through a VSSQ through a
240 resistor. 240 resistor. 240 resistor. 240 resistor. 240 resistor. 240 resistor.
Notes:
2. The PS_DDR_BG1 pin can be left unconnected when targeting x16 component interfaces without a BG1 pin, but it should always be connected for DIMM applications.

LPDDR4 Guidelines
LPDDR4 Pin Rules
The LPDDR4 pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in an 64-bit interface
without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and
PS_DDR_DM8 pins can be left unconnected.
• To achieve maximum performance, address copy mode is suggested.
LPDDR4 Pin Swapping Restrictions

• Command/address bits cannot be swapped.
• To support write DQS to DQ training, DQ byte lane swapping is not allowed.
• To support write DQS to DQ training, DQ bits with bytes 0, 2, and 8 are not allowed to
be swapped.
• Bits within bytes 1 and 3 can be swapped.
LPDDR4 Pinout Example for Supported Configurations

Table 2-3 shows a pinout example for the LPDDR4 supported configurations. For

MBIST failure.
Table 2‐3: LPDDR4 Supported Pinout Configurations
Pin Name LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit LPDDR4 32-bit
1Rank 1Rank ECC 2Rank 2Rank ECC
VCCO_PSDDR(1) Set to 1.1V Set to 1.1V Set to 1.1V Set to 1.1V
PS_DDR_A0 CA0_A CA0_A CA0_A CA0_A

111
Table 2‐3: LPDDR4 Supported Pinout Configurations (Cont’d)
PS_DDR_A6 to Can be left Can be left Can be left Can be left
PS_DDR_A9 unconnected. unconnected. unconnected. unconnected.
PS_DDR_A10 CA0_B CA0_B CA0_B CA0_B
PS_DDR_A16 Can be left Can be left Can be left Can be left
PS_DDR_A17 Can be left Can be left Can be left Can be left
PS_DDR_ACT_N Can be left Can be left Can be left Can be left
PS_DDR_ALERT_N Can be left Can be left Can be left Can be left
PS_DDR_BA0 Can be left Can be left Can be left Can be left
PS_DDR_BA1 Can be left Can be left Can be left Can be left
PS_DDR_CK_N0 CK_c_A CK_c_A CK_c_A CK_c_A
PS_DDR_CK_N1 CK_c_B CK_c_B CK_c_B CK_c_B
PS_DDR_CK0 CK_t_A CK_t_A CK_t_A CK_t_A
PS_DDR_CK1 CK_t_B CK_t_B CK_t_B CK_t_B
PS_DDR_CKE0 CKE_A and CKE_B CKE_A CKE0_A and CKE0_B CKE0_A
PS_DDR_CKE1 Can be left Can be left CKE1_A and CKE1_B CKE1_A
PS_DDR_CS_N0 CS_A and CS_B CS_A CS0_A and CS0_B CS0_A
PS_DDR_CS_N1 Can be left Can be left CS1_A and CS1_B CS1_A
PS_DDR_DM0 DMI0_A DMI0_A DMI0_A DMI0_A

112
PS_DDR_DM1 DMI1_A DMI1_A DMI1_A DMI1_A
PS_DDR_DM2 DMI0_B DMI0_B DMI0_B DMI0_B
PS_DDR_DM3 DMI1_B DMI1_B DMI1_B DMI1_B
PS_DDR_DM4 to Can be left Can be left Can be left Can be left
PS_DDR_DM7 unconnected. unconnected. unconnected. unconnected.
PS_DDR_DM8 Can be left DMI_ECC Can be left DMI_ECC
PS_DDR_DQ0 to Connect DQ0_A to Connect DQ0_A to Connect DQ0_A to Connect DQ0_A to
PS_DDR_DQ15 PS_DDR_DQ0, PS_DDR_DQ0, PS_DDR_DQ0, PS_DDR_DQ0,
DQ1_A to DQ1_A to DQ1_A to DQ1_A to
PS_DDR_DQ1, and PS_DDR_DQ1, and PS_DDR_DQ1, and PS_DDR_DQ1, and
so on. so on. so on. so on.
PS_DDR_DQ16 to Connect DQ0_B to Connect DQ0_B to Connect DQ0_B to Connect DQ0_B to
PS_DDR_DQ31 PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16, PS_DDR_DQ16,
DQ1_B to DQ1_B to DQ1_B to DQ1_B to
PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and PS_DDR_DQ17, and
so on. so on. so on. so on.
PS_DDR_DQ32 to Can be left Can be left Can be left Can be left
PS_DDR_DQ63 unconnected. unconnected. unconnected. unconnected.
PS_DDR_DQ64 Can be left DQ_ECC0 Can be left DQ_ECC0
unconnected. (ECC_bit[0]) unconnected. (ECC_bit[0])
PS_DDR_DQS_N0 DQS0_c_A DQS0_c_A DQS0_c_A DQS0_c_A
PS_DDR_DQS_N1 DQS1_c_A DQS1_c_A DQS1_c_A DQS1_c_A
PS_DDR_DQS_N2 DQS0_c_B DQS0_c_B DQS0_c_B DQS0_c_B
PS_DDR_DQS_N3 DQS1_c_B DQS1_c_B DQS1_c_B DQS1_c_B
PS_DDR_DQS_N4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_N7 unconnected. unconnected. unconnected. unconnected.

113
PS_DDR_DQS_N8 Can be left DQS_c_ECC Can be left DQS_c_ECC
PS_DDR_DQS_P0 DQS0_t_A DQS0_t_A DQS0_t_A DQS0_t_A
PS_DDR_DQS_P1 DQS1_t_A DQS1_t_A DQS1_t_A DQS1_t_A
PS_DDR_DQS_P2 DQS0_t_B DQS0_t_B DQS0_t_B DQS0_t_B
PS_DDR_DQS_P3 DQS1_t_B DQS1_t_B DQS1_t_B DQS1_t_B
PS_DDR_DQS_P4 to Can be left Can be left Can be left Can be left
PS_DDR_DQS_P7 unconnected. unconnected. unconnected. unconnected.
PS_DDR_DQS_P8 Can be left DQS_t_ECC Can be left DQS_t_ECC
PS_DDR_ODT0 Unconnected at Unconnected at Unconnected at Unconnected at
FPGA. FPGA. FPGA. FPGA.
PS_DDR_ODT1 Can be left Can be left Can be left Can be left
PS_DDR_PARITY Can be left Can be left Can be left Can be left
PS_DDR_RAM_RST_N RESET_n RESET_n RESET_n RESET_n
PS_DDR_ZQ Connect to GND Connect to GND Connect to GND Connect to GND
through a 240 through a 240 through a 240 through a 240
resistor. Connect resistor. Connect resistor. Connect resistor. Connect
DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to DRAM ZQ pins to
VDDQ through a VDDQ through a VDDQ through a VDDQ through a
240 resistor. 240 resistor. 240 resistor. 240 resistor.
Notes:

114
LPDDR3 Guidelines
LPDDR3 Pin Rules
The LPDDR3 pin rules are for single and dual-rank memory interfaces.
• All unused DDR pins can be left unconnected. For example, in an 64-bit interface
without ECC, the PS_DDR_DQ64 to PS_DDR_DQ71, PS_DDR_DQS_P8/N8, and
PS_DDR_DM8 pins can be left unconnected.
• To achieve maximum performance, address copy mode is suggested.
LPDDR3 Pin Swapping Restrictions

• Command/address bits cannot be swapped.
• To support command/address training, DQ byte lane swapping is not allowed.
• To support command/address training, DQ bits swapping within a byte lane is not
allowed.
LPDDR3 Pinout Example for Supported Configurations

Table 2-4 shows a pinout example for the LPDDR3 supported configurations. For

MBIST failure.
Table 2‐4: LPDDR3 Supported Pinout Configurations)
Pin Name LPDDR3 64-bit LPDDR3 64-bit LPDDR3 32-bit

(Dual Rank) (Dual Rank)
VCCO_PSDDR(1) Set to 1.2V Set to 1.2V Set to 1.2V
PS_DDR_A0 CA0_A CA0_A CA0

115
Table 2‐4: LPDDR3 Supported Pinout Configurations) (Cont’d)

PS_DDR_A10 CA0_B CA0_B Can be left unconnected.
PS_DDR_A16 Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_A17 Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_ACT_N CA9_B CA9_B Can be left unconnected.
PS_DDR_ALERT_N Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_BA0 CA6_B CA6_B Can be left unconnected.
PS_DDR_BA1 CA7_B CA7_B Can be left unconnected.
PS_DDR_BG0 CA8_B CA8_B Can be left unconnected.
PS_DDR_BG1 Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_CK_N0 CK_c_A CK_c_A CK_c
PS_DDR_CK_N1 CK_c_B CK_c_B Can be left unconnected.
PS_DDR_CK0 CK_t_A CK_t_A CK_t
PS_DDR_CK1 CK_t_B CK_t_B Can be left unconnected.
PS_DDR_CKE0 CKE_A and CKE_B CKE0_A and CKE0_B CKE0
PS_DDR_CKE1 Can be left unconnected. CKE1_A and CKE1_B CKE1
PS_DDR_CS_N0 CS_n_A and CS_n_B CS0_n_A and CS0_n_B CS0_n
PS_DDR_CS_N1 Can be left unconnected. CS1_n_A and CS1_n_B CS1_n
PS_DDR_DM0 DM0_A DM0_A DM0
PS_DDR_DM4 DM0_B DM0_B Can be left unconnected.

116

PS_DDR_DM8 DM_ECC, can be left DM_ECC, can be left DM_ECC, can be left
unconnected without ECC. unconnected without ECC. unconnected without ECC.
PS_DDR_DQ0 DQ0_A DQ0_A DQ0

117

PS_DDR_DQ32 DQ0_B DQ0_B Can be left unconnected.

118

PS_DDR_DQ64 DQ_ECC0 (ECC_bit[0]), can DQ_ECC0 (ECC_bit[0]), can DQ_ECC0 (ECC_bit[0]), can
be left unconnected without be left unconnected without be left unconnected without
ECC. ECC. ECC.
ECC. ECC. ECC.
ECC. ECC. ECC.
ECC. ECC. ECC.
ECC. ECC. ECC.
ECC. ECC. ECC.
ECC. ECC. ECC.
ECC. ECC. ECC.
PS_DDR_DQS_N0 DQS0_c_A DQS0_c_A DQS0_c
PS_DDR_DQS_N4 DQS0_c_B DQS0_c_B Can be left unconnected.
PS_DDR_DQS_N8 DQS_c_ECC, can be left DQS_c_ECC, can be left DQS_c_ECC, can be left
PS_DDR_DQS_P0 DQS0_t_A DQS0_t_A DQS0_t
PS_DDR_DQS_P4 DQS0_t_B DQS0_t_B Can be left unconnected.

119

PS_DDR_DQS_P8 DQS_t_ECC, can be left DQS_t_ECC, can be left DQS_t_ECC, can be left
PS_DDR_ODT0 ODT_A and ODT_B ODT_A and ODT_B ODT
PS_DDR_ODT1 Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_PARITY Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_RAM_RST_N Can be left unconnected. Can be left unconnected. Can be left unconnected.
PS_DDR_ZQ Connect a 240 resistor to Connect a 240 resistor to Connect a 240 resistor to
GND. (2) GND.(2) GND.(2)
Notes:
2. There should be separate 240 resistors at the FPGA and at the DRAM.

120
Chapter 3
Package Files
About ASCII Package Files

The ASCII package files for each Zynq® UltraScale+™ device include a
comma-separated-values (CSV) version and a text version optimized for a browser or text
editor in fixed-width fonts. The information in each of the files includes:
• Device/Package name (family-device-package), with date and time of creation

• Six columns containing data for each pin:
° Pin—Pin location on the package.
° Pin Name—The name of the assigned pin.
° Memory Byte Group—Memory byte group between 0 and 3 split into upper (U) and
lower (L) halves. For more information on the memory byte group, see the
UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150)
[Ref 15].
° Bank—Bank number.
° I/O Type—CONFIG, HD, HP, GTH, GTY, PS-GTR, PSMIO, PSDDR, or PSCONFIG
depends on the I/O type. For more information on the I/O type, see the UltraScale
Architecture SelectIO Resources User Guide (UG571) [Ref 6].
° Super Logic Region—Number corresponding to the super logic region (SLR) in the
devices implemented with stacked silicon interconnect (SSI) technology.
• Total number of pins in the package.

121
Package Specifications Designations

Package specifications are designated as evaluation only, engineering sample, or
production. Each designation is defined as follows.
Evaluation Only
These package specifications are based on initial device specifications, package routability
analysis and mechanical package construction. Package specifications with this designation
are not stable and package pinouts are likely to change and these specifications should
only be used for initial system level design feasibility.
Engineering Sample
These package specifications are based on a released package design and validated with ES
engineering sample (ES) devices. Package specifications with this designation are
considered stable, however some pinout and mechanical specifications might change prior
to the production release of the particular device. Package pinouts with this designation are
to be used for PCB and Vivado® designs using ES devices.
Production
These package specifications are released coincident with production release of a particular
device. Customers receive formal notification of any subsequent changes.

122
ASCII Pinout Files

Links to the ASCII pinout information device/package combinations are listed in Table 3-1.
Download all available package/device/pinout files at:
www.xilinx.com/support/package-pinout-files/zynq-ultrascale-plus-pkgs.html
Note: All package files are ASCII files in TXT and CSV file format. Only the available files listed in
Table 3-1 are linked and consolidated in this ZIP file:
www.xilinx.com/support/packagefiles/zuppackages/zupall.zip
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q.
Table 3‐1: Package/Device Pinout Files for CG, EG, and EV devices

XCZU1CG
SBVA484 XCZU1EG
Production
XCZU2CG XCZU3CG
XCZU2EG XCZU3EG
SBVA484
XAZU2EG XAZU3EG
Production Production
XQZU3EG
SFRA484
Production
XCZU1CG
UBVA494 XCZU1EG
Engineering Sample
XCZU2CG XCZU3CG
UBVA530 XCZU2EG XCZU3EG
XCZU1CG
SFVA625 XCZU1EG
Production
XCZU2CG XCZU3CG
XCZU2EG XCZU3EG
SFVA625
XAZU2EG XAZU3EG

123
Table 3‐1: Package/Device Pinout Files for CG, EG, and EV devices (Cont’d)
XCZU1CG
SFVC784 XCZU1EG
Production
XCZU4CG XCZU5CG
XCZU2CG XCZU3CG
XCZU4EG XCZU5EG
XCZU2EG XCZU3EG
SFVC784 XCZU4EV XCZU5EV
XAZU2EG XAZU3EG
XAZU4EV XAZU5EV
SFRC784 XQZU3EG XQZU5EV
XCZU4CG XCZU5CG XCZU7CG
XCZU4EG XCZU5EG XCZU7EG XAZU7EV
FBVB900
XCZU4EV XCZU5EV XCZU7EV Production
Production Production Production
FFRB900 XQZU5EV XQZU7EV
XCZU6CG XCZU9CG
XCZU15EG
FFVC900 XCZU6EG XCZU9EG
Production
FFRC900 XQZU9EG XQZU15EG
XCZU6CG XCZU9CG
XCZU15EG
FFVB1156 XCZU6EG XCZU9EG
Production
FFRB1156 XQZU9EG XQZU15EG
XCZU7CG
XCZU7EG XCZU11EG
FFVC1156
XCZU7EV Production
Production
FFRC1156 XQZU7EV XQZU11EG
XCZU11EG XCZU17EG XCZU19EG
FFVB1517
FFRB1517 XCZU19EG
Production

124
Table 3‐1: Package/Device Pinout Files for CG, EG, and EV devices (Cont’d)
XCZU7CG
XCZU7EG XCZU11EG XAZU11EG
FFVF1517
XCZU7EV Production Production
Production
FFVC1760
FFRC1760 XQZU11EG XQZU19EG
XCZU17EG XCZU19EG
FFVD1760
XCZU17EG XCZU19EG
FFVE1924

125
Table 3‐2: Package/Device Pinout Files for Zynq UltraScale+ RFSoCs

Package Footprint Compatible Devices
XCZU21DR
FFVD1156
Production
XQZU21DR
FFRD1156
Production
XCZU25DR XCZU27DR XCZU28DR XCZU42DR(2) XCZU43DR XCZU47DR XCZU48DR XCZU65DR(2) XCZU67DR (2)
FFVE1156
Production Production Production Production Production Production Production Production Production
XQZU28DR
FFRE1156
Production
XCZU25DR XCZU27DR XCZU28DR XCZU42DR XCZU43DR XCZU47DR XCZU48DR XCZU65DR(2) XCZU67DR (2)
FSVE1156
Production Production Production Production Production Production Production Production Production
XCZU25DR XCZU27DR XCZU28DR XCZU43DR XCZU47DR XCZU48DR
FFVG1517
Production Production Production Production Production Production
XQZU28DR
FFRG1517
Production
XQZU48DR
FSRG1517
Production
XCZU25DR XCZU27DR XCZU28DR XCZU43DR XCZU47DR XCZU48DR
FSVG1517
Production Production Production Production Production Production
XCZU29DR XCZU39DR XCZU49DR(1)
FFVF1760
XCZU46DR
FFVH1760
Production
XQZU29DR
FFRF1760
Production
XQZU49DR (1)
FSRF1760
Production

Table 3‐2: Package/Device Pinout Files for Zynq UltraScale+ RFSoCs

Package Footprint Compatible Devices
XCZU29DR XCZU39DR XCZU49DR(1)
FSVF1760
XCZU46DR
FSVH1760
Production
Notes:
1. These footprint compatible devices have a different set of ADC and DAC power sequencing requirements. Refer to Zynq UltraScale+ RFSoC Data Sheet: DC and AC
Switching Characteristics (DS926) for specific power sequencing differences.
2. The XCZU42DR, XCZU65DR, and XCZU67DR are only partially compatible with other devices in the FFVE1156 and FSVE1156 packages due to key differences in the ADC
and DAC architecture. When planning migration between devices, differences that must be addressed include ADC and DAC bank/pin locations and power rail voltage
specifications.

Chapter 4
Device Diagrams
Summary
The diagrams in this chapter show top-view perspective of the package pinout of each Zynq® UltraScale+™ device/package
combination. Table 4-1 is a cross reference to the device/package diagrams. The I/O-bank diagram shows the location of each
user I/O, PSMIO, PSDDR, PSCONFIG, and PS-GTR, GTH, and GTY transceiver and the respective bank or GT quad. The
configuration-power diagram shows the location of every power pin and dedicated as well as multi-function configuration pin
in the package. See Package Specifications Designations in Chapter 3 for definitions of Evaluation Only, Engineering Sample,
and Production device diagrams.
IMPORTANT: All packages are available with eutectic BGA balls. To order these packages, the device type starts with an XQ vs. XC or XA, and
the Pb-free signifier in the package name is Q.
Table 4‐1: Cross-Reference to Zynq UltraScale+ Device Diagrams by Package

XCZU1CG
XCZU1EG
SBVA484
Production
page 134

Table 4‐1: Cross-Reference to Zynq UltraScale+ Device Diagrams by Package (Cont’d)

XCZU2CG, XCZU3CG,
XCZU2EG, XCZU3EG,
SBVA484 XAZU2EG XAZU3EG
page 136 page 136
XQZU3EG
SFRA484 Production
page 136
XCZU1CG
XCZU1EG
UBVA494
Production
page 138
XCZU2CG, XCZU3CG,
XCZU2EG XCZU3EG
UBVA530
page 140 page 140
XCZU1CG
XCZU1EG
SFVA625
Production
page 142
XCZU2CG, XCZU3CG,
XCZU2EG, XCZU3EG,
SFVA625 XAZU2EG XAZU3EG
page 144 page 144
XCZU1CG
XCZU1EG
SFVC784
Production
page 146


XCZU4CG, XCZU4EV,
XCZU2CG, XCZU3CG,
XCZU4EG, XCZU5EV,
XCZU2EG, XCZU3EG,
XCZU5CG, XAZU4EV,
SFVC784 XAZU2EG XAZU3EG
XCZU5EG XAZU5EV
page 148 page 148
page 150 page 152
XQZU3EG XQZU5EV
SFRC784 Production Production
page 148 page 152
XCZU4CG,
XCZU4EG, XCZU4EV, XCZU7CG, XCZU7EV
XCZU5CG, XCZU5EV XCZU7EG XAZU7EV
FBVB900 XCZU5EG Production Production Production
Production page 156 page 158 page 160
page 154
XQZU5EV XQZU7EV
FFRB900 Production Production
page 156 page 160
XCZU6CG, XCZU9CG,
XCZU15EG
XCZU6EG XCZU9EG
FFVC900 Production
page 162
page 162 page 162
XQZU9EG XQZU15EG
FFRC900 Production Production
page 162 page 162


XCZU6CG, XCZU9CG,
XCZU15EG
XCZU6EG XCZU9EG
FFVB1156 Production
page 164
page 164 page 164
XQZU9EG XQZU15EG
FFRB1156 Production Production
page 164 page 164
XCZU7CG,
XCZU7EV XCZU11EG
XCZU7EG
FFVC1156 Production Production
Production
page 168 page 170
page 166
XQZU7EV XQZU11EG
page 168 page 170
XCZU21DR
FFVD1156 Production
page 172
XQZU21DR
FFRD1156 Production
page 172
XCZU27DR
XCZU25DR XCZU42DR XCZU43DR XCZU47DR XCZU48DR XCZU65DR XCZU67DR
FFVE1156 XCZU28DR
Production Production Production Production Production Production Production
FSVE1156 Production
page 174 page 178 page 180 page 182 page 184 page 186 page 188
page 176
XQZU28DR
FFRE1156 Production
page 176


FFVB1517 Production Production Production
page 190 page 192 page 192
XQZU19EG
FFRB1517 Production
page 192
XCZU7CG,
XCZU7EV XCZU11EG XAZU11EG
XCZU7EG
FFVF1517 Production Production Production
Production
page 194
FFVG1517 XCZU25DR XCZU27DR XCZU28DR XCZU43DR XCZU47DR XCZU48DR XQZU48DR
FSVG1517 Production Production Production Production Production Production Production
FSRG1517 page 200 page 202 page 202 page 204 page 206 page 208 page 208
XQZU28DR
FFRG1517 Production
page 202
FFVC1760 Production Production Production
XQZU11EG XQZU19EG
page 210 page 212
XCZU17EG XCZU19EG
FFVD1760 Production Production
page 214 page 214


XCZU29DR XCZU39DR XCZU49DR XCZU49DR XQZU49DR
FFVF1760
Production Production Production Production Production
FSVF1760
page 216 page 216 page 218 page 218 page 218
XCZU46DR
FFVH1760
Production
FSVH1760
page 220
XQZU29DR
FFRF1760 Production
page 216
XQZU49DR
FSRF1760 Production
page 218
XCZU17EG XCZU19EG
FFVE1924 Production Production
page 222 page 222

SBVA484 Package–XCZU1CG, XCZU1EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A S 12 12 12 10 10 9 45 48 50 58 69 70 3 3 A
505
VC 65
VC 44
3
B 11 11 11 11 12 9 41 44 47 57 65 68 75 77 B
C
3
O
505
VC 501
VC 502
C 24 22 7 8 8 38 39 46 51 55 62 72 2 2 C
C
O
O
505
VC 502
2
D 21 24 22 7 5 5 6 36 40 42 49 60 66 73 74 D
C
2
O
505
VC 44
3
E 21 20 20 3 3 6 33 35 37 43 56 59 64 E
C
3
O
505
VC 501
F 19 23 23 S 2 4 4 29 31 32 34 53 63 71 76 1 1 F
C
O
505
VC 65
VC 503
2
G 19 17 18 1 1 2 26 30 27 28 52 54 61 67 G
C
2
O
505
VC 503
1
H 17 S 18 16 DI CK RC MD PI MD H
C
1
O
505
1
J 15 13 13 16 MS DO MD MD PO
1 J
505
VC 65
K 15 14 14 PR SR PG IN EO ES 0 0 K
C
O
505
0
L 11 11 12 12 DN
0 L
505
0
M 9 9 10 10 G 0 M
505
N 7 S 8 8 70 71 N
VC 65
VC 504
P 7 2 6 69 P 67 65 P
C
O
O
R 5 2 4 6 68 DM N 66 R
VC 504
T 5 1 1 4 21 23 RS ZQ AL 64 T
C
O
U 3 3 0 3 4 20 DM 22 24 25 29 AC BG BA PA CS CE CE U
VC 500
VC 504
VC 504
V 2 8 7 9 18 N P 19 P N 28 31 BA C CN C CS V
C
O
O
W 1 11 13 14 21 17 16 3 27 26 DM 30 A A BG CN OD OD W
VC 504
VC 504
Y 6 16 15 18 25 5 P 1 9 P 12 14 A A A A A Y
C
O
O
VC 500
AA 5 10 17 19 22 7 4 N 8 10 N 13 A A A A A A AA
C
O
VC 504
AB 12 20 23 24 6 DM 2 0 11 DM 15 A A A A A AB
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Bank 44 PS Bank 504

Bank 65 PS Quad 505
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503
SelectIO Pins Dedicated Pins Transceiver Pins PS Pins

#
# IO_L#P VREF MGT[R, H or Y]RXP# # PS_MIO DN PS_DONE
# IO_L#N MGTAVTTRCAL MGT[R, H or Y]RXN# # PS_DDR_DQ PS_ERROR_OUT
V
EO
#
S IO (single−ended) G MGTRREF # MGT[R, H or Y]TXP# P PS_DDR_DQS_P ES PS_ERROR_STATUS

# IO_L#P_GC # MGT[R, H or Y]TXN# N PS_DDR_DQS_N IN PS_INIT_B
#
# IO_L#N_GC MGTREFCLK#P AL PS_DDR_ALERT_N CK PS_JTAG_TCK
VRP # MGTREFCLK#N AC PS_DDR_ACT_N DI PS_JTAG_TDI
A PS_DDR_A DO PS_JTAG_TDO
BA PS_DDR_BA MS PS_JTAG_TMS
BG PS_DDR_BG MD PS_MODE
CN PS_DDR_CK_N PI PS_PADI
C PS_DDR_CK PO PS_PADO
CE PS_DDR_CKE PR PS_POR_B
CS PS_DDR_CS PG PS_PROG_B
DM PS_DDR_DM RC PS_REF_CLK
OD PS_DDR_ODT SR PS_SRST_B
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐1: SBVA484 Package—XCZU1CG and XCZU1EG I/O Bank Diagram

134
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A V A
B V B
C 35 C
D 34 V D
E E
F 33 E F
G G
H E H
J J
K E K
L 24 21 PL PL AU AU L
M 22 23 PL DP DP AU AU M
N 8 7 LP LP FP BT DD N
P LP LP AD AD DD P
R 38 LP LP FP FP R
T 13 15 FP FP FP FP DD T
U U
V V
W W
Y Y
AA AA
AB AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Power Pins Dedicated Pins Multi−Function I/O Pins PS Pins
GND 7 DXP 33 I2C_SCLK AD VCC_PSADC

VCCAUX_IO 8 DXN 34 I2C_SDA & PERSTN1 AD GND_PSADC
VCCAUX 13 POR_OVERRIDE 35 PERSTN0 AU VCC_PSAUX
VCCINT 15 PUDC_B 38 SMBALERT E PS_MGTRAVCC
VCCINT_IO 21 VP V PS_MGTRAVTT
VCCINT_VCU 22 VN BT VCC_PSBATT
VCCO_[bank number] 23 VREFP DP VCC_PSDDR_PLL
VCCBRAM 24 VREFN PL VCC_PSPLL
VCCADC FP VCC_PSINTFP
GNDADC DD VCC_PSINTFP_DDR
R RSVDGND LP VCC_PSINTLP
n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐2: SBVA484 Package—XCZU1CG and XCZU1EG Power, Dedicated, and Multi-function

Pin Diagram

135
SBVA484 Package–XCZU2CG, XCZU2EG, XCZU3CG,

XCZU3EG, XAZU2EG, and XAZU3EG
IMPORTANT: For the devices in the SBVA484 package, the HP I/Os in bank 66 are powered by
VCCO_65.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A S 12 12 12 10 10 9 45 48 50 58 69 70 3
505
3 A
VC 65
VC 26
3
B 11 11 11 11 12 9 41 44 47 57 65 68 75 77 B
C
3
O
505
VC 501
VC 502
C 24 22 7 8 8 38 39 46 51 55 62 72 2 2 C
C
O
O
505
VC 502
2
D 21 24 22 7 5 5 6 36 40 42 49 60 66 73 74 D
C
2
O
505
V C 26
3
E 21 20 20 3 3 6 33 35 37 43 56 59 64 E
C
3
O
505
VC 501
F 19 23 23 S 2 4 4 29 31 32 34 53 63 71 76 1 1 F
C
O
505
VC 6 5
VC 503
2
G 19 17 18 1 1 2 26 30 27 28 52 54 61 67 G
C
2
O
505
VC 503
1
H 17 S 18 16 DI CK RC MD PI MD H
C
1
O
505
1
J 15 13 13 16 MS DO MD MD PO
505
1 J
V C 65
K 15 14 14 PR SR PG IN EO ES 0 0 K
C
O
505
0
L 11 11 12 12 DN
505
0 L
0
M 9 9 10 10 G 505
0 M
N 7 S 8 8 70 71 N
V C 65
VC 504
P 7 2 6 69 P 67 65 P
C
C
O
O
R 5 2 4 6 68 DM N 66 R
VC 504
T 5 1 1 4 21 23 RS ZQ AL 64 T
C
O
U 3 3 0 3 4 20 DM 22 24 25 29 AC BG BA PA CS CE CE U
VC 500
VC 504
VC 504
V 2 8 7 9 18 N P 19 P N 28 31 BA C CN C CS V
C
C
O
O
W 1 11 13 14 21 17 16 3 27 26 DM 30 A A BG CN OD OD W
VC 504
VC 504
Y 6 16 15 18 25 5 P 1 9 P 12 14 A A A A A Y
C
O
O
VC 500
AA 5 10 17 19 22 7 4 N 8 10 N 13 A A A A A A AA
C
O
VC 504
AB 12 20 23 24 6 DM 2 0 11 DM 15 A A A A A AB
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Bank 26 PS Quad 505

Bank 65
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503
PS Bank 504

#
# IO_L#N MGTAVTTRCAL MGT[R, H or Y]RXN# PS_DDR_DQ PS_ERROR_OUT
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐3: SBVA484 Package—XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and

XAZU3EG I/O Bank Diagram

136
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A V A
B V B
C 35 C
D 34 V D
E E
F 33 E F
G G
H E H
J J
K E K
L 24 21 PL PL AU AU L
M 22 23 PL DP DP AU AU M
N 8 7 LP LP FP BT DD N
P LP LP AD AD DD P
R 38 LP LP FP FP R
T 13 15 FP FP FP FP DD T
U U
V V
W W
Y Y
AA AA
AB AB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐4: SBVA484 Package—XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and

XAZU3EG Power, Dedicated, and Multi-function Pin Diagram

137
UBVA494 Package–XCZU1CG, XCZU1EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A 12 12 64 65 67 68 70 74 75 76 77 MD RC MD DO SR ES MS 3 3 A
505
B 56 55 31 33 48 69 EO DI IN MD PR G B
C 20 11 11 S 59 57 53 38 30 28 49 51 54 72 MD PI PO PG CK DN 2 2 C
505
VC 501
VC 501
VC 502
VC 502
3
D 20 19 23 23 60 44 34 50 58 D
C
3
O
505
E 19 24 62 26 42 39 36 52 61 63 71 73 1 1 E
505
VC 500
VC 500
VC 503
VC 503
2
F 17 22 24 21 27 41 66 F
C
2
O
505
G 17 22 S 21 29 47 45 23 12 8 6 21 10 11 0 0 G
505
VC 65
1
H 18 S 32 46 15 18 H
C
1
O
505
VC 65
3
J 18 16 16 0 3 43 40 35 9 13 4 19 25 16 24 14 7 17 J
C
3
O
505
VC 65
0
K 15 15 9 S 2 12 17 16 22 26 1 20 5 K
C
0
O
505
2
L 13 9 37 11 12 DM 18 27 31 2 L
505
1
M 13 11 11 8 11 22 P 20 24 P 29 DM 30 70 69 DM
1 M
505
0
N 14 12 12 8 8 7 10 10 23 21 N 19 25 N 28 A A P N 71 0 N
505
VC 44
P 14 8 5 7 9 67 P
C
O
VC 504
VC 504
VC 504
R 10 10 5 5 5 6 6 9 9 4 8 13 A A A A AC 68 64 66 65 RS R
C
O
O
VC 44
VC 504
VC 504
T 7 7 6 6 1 3 3 4 4 3 1 10 12 A A A A A BA A CE AL OD ZQ T
C
O
O
U 4 4 1 2 1 7 P 2 P A A DM C A A CS CE CS U
V 3 3 2 2 2 1 DM 6 5 N 0 11 N 15 14 A C CN CN A BA BG PA BG OD V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Bank 44 PS Bank 504

Bank 65 PS Quad 505
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503

#
V
EO
#

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐5: UBVA494 Package—XCZU1CG and XCZU1EG I/O Bank Diagram

138
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A 13 15 A
B 24 21 B
C 22 23 BT C
D 33 8 7 E D
E 34 LP AU AU LP V E
F 35 AU E F
G LP PL PL LP AD V G
H FP FP FP FP AD E H
J V J
K FP FP FP K
L FP FP FP DD L
M M
N N
P AU DP DD DD DD DD P
R R
T T
U 38 U
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐6: UBVA494 Package—XCZU1CG and XCZU1EG Power, Dedicated, and Multi-function

Pin Diagram

139
UBVA530 Package–XCZU2CG, XCZU2EG, XCZU3CG,

and XCZU3EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A 12 12 11 12 12 67 68 69 71 75 73 74 77 76 SR ES MS PR DN 3 3 A
505
B S 11 11 10 66 65 64 62 72 70 MD DO MD RC G B
VC 26
C 23 11 10 8 60 61 59 57 EO PI PO MD MD 2 2 C
C
O
505
VC 501
VC 501
VC 502
VC 502
3
D 23 24 S 9 9 8 55 63 58 D
C
O
O
3
505
VC 503
E 22 24 4 4 7 54 CK 1 1 E
C
O
505
VC 500
VC 500
VC 503
2
F 22 S 21 3 3 6 7 56 52 2 10 DI IN F
C
O
O
2
505
VC 65
VC 26
G 20 20 21 17 2 2 6 5 53 0 PG 0 0 G
C
O
O
505
VC 65 1
H 19 19 C
O
17 15 1 1 5 33 13 9 3 21 19 16 5 17 1 H
505
3
J 16 18 15 42 50 28 31 43 15 25 8 14 22 3 J
505
0
K 16 13 18 9 9 39 51 38 34 30 35 12 1 20 24 7 0 K
505
2
L 13 14 S 27 26 41 40 18 23 4 6 11 2 L
505
VC 65
1
M 14 3 32 29 36 44 49 22 21 P N 26 27 P N 28 M
C
O
1
505
0
N 11 11 2 1 3 37 45 48 47 46 DM 24 29 0 N
505
VC 504
VC 504
VC 504
P 12 12 2 1 DM 8 9 15 23 19 20 17 25 31 DM 30 DM P
C
O
O
VC 504
R 10 10 0 A DM 18 16 64 66 71 R
C
O
VC 504
VC 504
T 10 7 5 4 7 11 2 13 A A A A A A A A BG CS AL CE 65 70 69 T
C
O
O
U 7 5 4 6 P 1 12 A A C CN A AC A OD PA OD 68 P U
V 8 8 6 6 5 N 4 3 P N 14 A A A CN C A A BA BA BG CE CS RS ZQ 67 N V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Bank 26 PS Bank 504

Bank 65 PS Quad 505
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503

#
V
EO
#

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐7: UBVA530 Package—XCZU2CG, XCZU2EG, XCZU3CG, and XCZU3EG I/O Bank Diagram

140
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A 13 15 A
B 24 21 B
C 33 22 23 BT C
D 34 8 7 E D
E 35 AU AU AU V E
F LP LP E F
G PL PL AD LP V G
H LP AD E H
J FP FP FP FP V J
K FP K
L AU FP FP L
M DD M
N FP FP FP DD N
P P
R DD DP DD DD R
T 38 T
U U
V V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐8: UBVA530 Package—XCZU2CG, XCZU2EG, XCZU3CG, and XCZU3EG Power, Dedicated,

and Multi-function Pin Diagram

141
SFVA625 Package–XCZU1CG, XCZU1EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A 8 8 S 19 19 24 22 22 3 2 30 39 41 57 58 60 65 3 3 A
505
3
B 7 10 10 21 23 24 20 4 3 2 29 43 47 55 59 69 3 B
505
C 7 12 12 21 23 20 6 4 5 31 38 46 48 61 62 70 2 2 C
505
VC 66
VC 44
VC 501
VC 502
2
D 9 9 11 11 14 14 S 6 5 1 32 36 51 56 63 66 D
C
2
O
505
VC 66
VC 501
VC 502
3
E 3 3 2 13 13 S 7 8 8 1 34 44 50 53 71 72 E
C
3
O
505
VC 44
F 5 4 2 15 18 16 7 10 12 33 35 42 54 64 75 73 1 1 F
C
O
505
VC 66
VC 501
VC 502
2
G 1 5 4 15 17 18 16 10 11 12 27 40 49 52 68 74 G
C
2
O
505
1
H 1 6 6 17 9 9 11 26 28 37 45 67 77 76 1 H
505
VC 503
1
J 15 17 17 23 24 24 MD MD MD EO J
C
1
O
505
VC 503
K 15 18 23 21 21 22 RC CK PI PO MD G 0 0 K
C
O
505
VC 65
0
L 18 13 S 19 22 DI DO MS IN ES L
C
0
O
505
0
M 16 16 13 20 19 S PG PR
0 M
505
N 3 14 14 20 SR DN 69 N
VC 65
P 3 5 5 11 10 10 70 P DM 67 P
C
O
R 1 1 11 12 12 8 71 N 65 66 R
T 6 9 9 8 68 64 CE CS T
VC 65
U 2 6 4 7 7 S RS ZQ AL A U
C
O
VC 64
VC 500
VC 504
V 2 4 S S 0 2 16 23 AC BG BA BG PA OD A V
C
O
O
VC 500
VC 500
W 23 20 20 22 12 10 10 3 1 10 15 22 19 DM 16 A A BA CS CE W
C
O
VC 504
Y 23 19 22 11 12 8 4 6 7 13 24 23 22 P 17 A A C OD A Y
C
O
VC 64
VC 504
AA 19 24 24 11 8 7 7 5 20 7 DM 21 N 20 18 A CN C CN A AA
C
C
O
O
VC 64
VC 504
AB 21 21 13 14 1 9 9 9 12 18 6 0 9 DM 14 26 29 A A A AB
C
C
O
O
VC 504
AC S 13 14 1 6 6 8 14 5 P 2 8 15 27 P N A A A AC
C
O
VC 504
AD 17 15 16 16 5 5 2 2 4 17 21 4 N 10 P 13 25 DM 31 A A AD
C
O
VC 504
AE 17 15 18 18 3 3 4 11 19 25 3 1 11 N 12 24 28 30 A AE
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Bank 44 PS Bank 503

Bank 64 PS Bank 504
Bank 65 PS Quad 505
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502

#
V
EO
#

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐9: SFVA625 Package—XCZU1CG and XCZU1EG I/O Bank Diagram

142
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A V A
B V B
C C
D V D
E E
F E F
G G
H E H
J 35 34 J
K 33 K
L L
M PL PL PL M
N 24 21 DP DP AU BT N
P 22 23 LP LP AU AU P
R 8 7 LP LP LP AU DD R
T FP LP AD AD DD T
U 38 FP FP FP FP DD U
V 15 13 FP FP V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐10: SFVA625 Package—XCZU1CG and XCZU1EG Power, Dedicated, and Multi-function

Pin Diagram

143
SFVA625 Package–XCZU2CG, XCZU2EG, XCZU3CG,

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A 8 8 S 19 19 24 22 22 3 2 30 39 41 57 58 60 65 3
505
3 A
3
B 7 10 10 21 23 24 20 4 3 2 29 43 47 55 59 69
505
3 B
C 7 12 12 21 23 20 6 4 5 31 38 46 48 61 62 70 2
505
2 C
V C 66
V C 26
VC 501
VC 502
2
D 9 9 11 11 14 14 S 6 5 1 32 36 51 56 63 66 D
C
2
O
505
VC 66
VC 501
VC 502
3
E 3 3 2 13 13 S 7 8 8 1 34 44 50 53 71 72 E
C
3
O
505
VC 26
F 5 4 2 15 18 16 7 10 12 33 35 42 54 64 75 73 1 1 F
C
O
505
VC 66
VC 501
VC 502
2
G 1 5 4 15 17 18 16 10 11 12 27 40 49 52 68 74 G
C
2
O
505
1
H 1 6 6 17 9 9 11 26 28 37 45 67 77 76
505
1 H
VC 503
1
J 15 17 17 23 24 24 MD MD MD EO J
C
1
O
505
VC 503
K 15 18 23 21 21 22 RC CK PI PO MD G 0 0 K
C
O
505
VC 65
0
L 18 13 S 19 22 DI DO MS IN ES L
C
0
O
505
0
M 16 16 13 20 19 S PG PR
505
0 M
N 3 14 14 20 SR DN 69 N
VC 65
P 3 5 5 11 10 10 70 P DM 67 P
C
O
R 1 1 11 12 12 8 71 N 65 66 R
T 6 9 9 8 68 64 CE CS T
VC 6 5
U 2 6 4 7 7 S RS ZQ AL A U
C
O
VC 64
VC 500
VC 504
V 2 4 S S 0 2 16 23 AC BG BA BG PA OD A V
C
O
O
VC 500
VC 500
W 23 20 20 22 12 10 10 3 1 10 15 22 19 DM 16 A A BA CS CE W
C
O
VC 504
Y 23 19 22 11 12 8 4 6 7 13 24 23 22 P 17 A A C OD A Y
C
O
VC 64
VC 504
AA 19 24 24 11 8 7 7 5 20 7 DM 21 N 20 18 A CN C CN A AA
C
C
O
O
VC 64
VC 504
AB 21 21 13 14 1 9 9 9 12 18 6 0 9 DM 14 26 29 A A A AB
C
C
O
O
VC 504
AC S 13 14 1 6 6 8 14 5 P 2 8 15 27 P N A A A AC
C
O
VC 504
AD 17 15 16 16 5 5 2 2 4 17 21 4 N 10 P 13 25 DM 31 A A AD
C
O
VC 504
AE 17 15 18 18 3 3 4 11 19 25 3 1 11 N 12 24 28 30 A AE
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Bank 26 PS Bank 504

Bank 64 PS Quad 505
Bank 65
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502
PS Bank 503

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐11: SFVA625 Package—XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and


144
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
A V A
B V B
C C
D V D
E E
F E F
G G
H E H
J 35 34 J
K 33 K
L L
M PL PL PL M
N 24 21 DP DP AU BT N
P 22 23 LP LP AU AU P
R 8 7 LP LP LP AU DD R
T FP LP AD AD DD T
U 38 FP FP FP FP DD U
V 15 13 FP FP V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐12: SFVA625 Package—XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and


145
SFVC784 Package–XCZU1CG, XCZU1EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 57 62 65 75 3 3 A
505 505
VC 66
2
B 7 9 10 19 20 22 24 55 67 71 76 3 3 B
C
2
O
505 505
2
C 7 12 12 11 20 S 22 24 56 60 68 70 2
2 2 C
505 505
VC 66
VC 502
1
D 2 S 11 14 13 13 18 53 61 69 74 1 1 D
C
1
O
505 505
VC 66
1
E 2 3 5 5 14 S 17 18 59 63 64 0 0 E
C
1
O
505 505
0 0
F 1 3 4 6 15 16 17 30 54 58 77 G 0 0 F
505 505
VC 502
G 1 4 6 15 16 29 52 66 72 73 61 60 G
C
O
VC 65
VC 501
H 8 S 10 10 20 21 24 24 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 28 36 40 43 45 46 N 43 62 57 52 K
VC 65
VC 501
L 7 12 12 14 13 13 18 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
VC 503
VC 504
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
O
O
R 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
O
U 3 2 RS ZQ AL OD OD U
VC 504
V 3 2 BG BA PA CS CE CE V
C
O
W 1 10 BA BG C CN CS A W
VC 504
Y 1 11 10 A AC C CN A A Y
C
O
AA 11 9 9 A A A A A A AA
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 23 24 22 25 A A A A A AB
C
O
O
VC 64
VC 44
AC 18 17 14 14 6 5 3 1 8 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
VC 64
VC 504
AD 16 16 13 13 4 1 7 7 6 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
VC 500
AE 22 21 S 12 4 2 2 4 5 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
VC 44
VC 500
AG 24 20 19 10 10 8 7 1 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 44 PS Bank 503

Bank 64 PS Bank 504
Bank 65 PS Quad 505
Bank 66
PS Bank 500
PS Bank 501
PS Bank 502

#
V
EO
#

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐13: SFVC784 Package—XCZU1CG and XCZU1EG I/O Bank Diagram

146
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A n n n n n n V A
B n n n n n n E B
C n n n n n V C
D n n n n n E V D
E n n n n n n V E
F n n n n n n F
G n n n n n G
H 35 34 n n n n H
J n n n n J
K 33 n n n K
L n n L
M M
N n n n n N
P n n n P
R n n 38 24 21 R
T n n n 22 23 PL PL PL T
U n n n 15 8 7 DP DP AU AU n U
V n n n n n LP LP LP AU n n V
W n n n 13 n n n n LP LP LP AU AD n W
Y n n n n n n n n FP FP BT DD AD n Y
AA n n n FP FP FP FP DD DD AA
AB n n n FP AB
AC n n AC
AD n n n AD
AE n n n AE
AF n AF
AG n n AG
AH n n AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

#
V
EO
#

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐14: SFVC784 Package—XCZU1CG and XCZU1EG Power, Dedicated, and Multi-function

Pin Diagram

147
SFVC784 Package–XCZU2CG, XCZU2EG, XCZU3CG,

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
505
3
505
3 A
VC 66
V C 25
2
B 7 9 10 19 20 22 24 9 10 3 2 1 55 67 71 76 3 3 B
C
2
O
505 505
VC 26
2
C 7 12 12 11 20 S 22 24 9 12 4 4 56 60 68 70 2 2 C
C
2
O
505 505
VC 66
VC 502
1
D 2 S 11 14 13 13 18 7 8 12 5 5 53 61 69 74 1 1 D
C
1
O
505 505
VC 66
V C 25
1
E 2 3 5 5 14 S 17 18 7 8 6 6 8 59 63 64 0 0 E
C
1
O
505 505
V C 26
0 0
F 1 3 4 6 15 16 17 5 6 6 7 8 30 54 58 77 G F
C
0 0
O
505 505
VC 502
G 1 4 6 15 16 3 5 7 9 9 29 52 66 72 73 61 60 G
C
O
VC 65
VC 501
H 8 S 10 10 20 21 24 24 3 4 10 10 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 1 1 4 11 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 2 2 11 28 36 40 43 45 46 N 43 62 57 52 K
V C 65
VC 501
L 7 12 12 14 13 13 18 12 12 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
VC 503
VC 504
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
O
O
R 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
O
U 3 2 RS ZQ AL OD OD U
VC 504
C
O
W 1 10 11 11 9 9 BA BG C CN CS A W
VC 504
Y 1 11 10 12 10 10 A AC C CN A A Y
C
O
VC 24
AA 11 9 9 12 7 A A A A A A AA
C
O
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 7 8 8 23 24 22 25 A A A A A AB
C
O
O
VC 64
VC 44
AC 18 17 14 14 6 5 3 1 8 6 6 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
V C 64
VC 24
VC 504
AD 16 16 13 13 4 1 7 7 6 5 5 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
V C 500
AE 22 21 S 12 4 2 2 4 5 4 1 1 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 4 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
VC 44
VC 500
AG 24 20 19 10 10 8 7 1 2 3 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 24 PS Bank 501

Bank 25 PS Bank 502
Bank 26 PS Bank 503
Bank 44 PS Bank 504
Bank 64 PS Quad 505
Bank 65
Bank 66
PS Bank 500

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐15: SFVC784 Package—XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and


148
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A V A
B E B
C V C
D E V D
E V E
F F
G G
H 35 34 H
J J
K 33 K
L L
M M
N n n n n N
P n n n P
R n n 38 24 21 R
T n n n 22 23 PL PL PL T
U n n n 15 8 7 DP DP AU AU n U
V n n n n n LP LP LP AU n n V
W n n n 13 LP LP LP AU AD n W
Y n n n n n FP FP BT DD AD n Y
AA FP FP FP FP DD DD AA
AB FP AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐16: SFVC784 Package—XCZU2CG, XCZU2EG, XCZU3CG, XCZU3EG, XAZU2EG, and


149
SFVC784 Package–XCZU4CG, XCZU4EG, XCZU5CG,

and XCZU5EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
505
3
505
3 A
V C 66
V C 45
2
B 7 9 10 19 20 22 24 9 10 3 2 1 55 67 71 76 3 3 B
C
2
O
505 505
V C 46
2
C 7 12 12 11 20 S 22 24 9 12 4 4 56 60 68 70 2 2 C
C
2
O
505 505
VC 66
VC 502
1
D 2 S 11 14 13 13 18 7 8 12 5 5 53 61 69 74 1 1 D
C
1
O
505 505
V C 66
VC 45
1
E 2 3 5 5 14 S 17 18 7 8 6 6 8 59 63 64 0 0 E
C
1
O
505 505
V C 46
0 0
F 1 3 4 6 15 16 17 5 6 6 7 8 30 54 58 77 G F
C
0 0
O
505 505
VC 502
G 1 4 6 15 16 3 5 7 9 9 29 52 66 72 73 61 60 G
C
O
V C 65
VC 501
H 8 S 10 10 20 21 24 24 3 4 10 10 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 1 1 4 11 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 2 2 11 28 36 40 43 45 46 N 43 62 57 52 K
VC 65
VC 501
L 7 12 12 14 13 13 18 12 12 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N V G 3
224
3 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
V C 503
VC 504
3
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
3
O
224
R 2
224
2 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
2
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
2
O
224
U 1
224
1 3 2 RS ZQ AL OD OD U
VC 504
1 1
C
1 1
O
224 224
W 0
224
0 1 10 11 11 9 9 BA BG C CN CS A W
VC 504
0 0
Y 1 11 10 12 10 10 A AC C CN A A Y
C
0 0
O
224 224
V C 44
AA 11 9 9 12 7 A A A A A A AA
C
O
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 7 8 8 23 24 22 25 A A A A A AB
C
O
O
VC 64
VC 43
AC 18 17 14 14 6 5 3 1 8 6 6 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
VC 64
VC 44
VC 504
AD 16 16 13 13 4 1 7 7 6 5 5 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
VC 500
AE 22 21 S 12 4 2 2 4 5 4 1 1 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 4 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
VC 43
VC 500
AG 24 20 19 10 10 8 7 1 2 3 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 43 PS Bank 500

Bank 44 PS Bank 501
Bank 45 PS Bank 502
Bank 46 PS Bank 503
Bank 64 PS Bank 504
Bank 65 PS Quad 505
Bank 66
Quad 224

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐17: SFVC784 Package—XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG I/O Bank Diagram

150
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A V A
B E B
C V C
D E V D
E V E
F F
G G
H 35 34 H
J J
K 33 K
L L
M M
N N
P V P
R 38 24 21 R
T V 22 23 PL PL PL T
V
U 15 8 7 DP DP AU AU R U
V E LP LP LP AU R R V
V
W 13 LP LP LP AU AD R W
Y E FP FP BT DD AD R Y
AB FP AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐18: SFVC784 Package—XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG

Power, Dedicated, and Multi-function Pin Diagram

151
SFVC784 Package–XCZU4EV, XCZU5EV, XAZU4EV,

and XAZU5EV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
3 3
A 8 8 9 10 19 21 21 23 23 10 11 11 3 2 1 57 62 65 75
505
3
505
3 A
VC 66
V C 45
2
B 7 9 10 19 20 22 24 9 10 3 2 1 55 67 71 76 3 3 B
C
2
O
505 505
V C 46
2
C 7 12 12 11 20 S 22 24 9 12 4 4 56 60 68 70 2 2 C
C
2
O
505 505
V C 66
VC 502
1
D 2 S 11 14 13 13 18 7 8 12 5 5 53 61 69 74 1 1 D
C
1
O
505 505
V C 66
V C 45
1
E 2 3 5 5 14 S 17 18 7 8 6 6 8 59 63 64 0 0 E
C
1
O
505 505
V C 46
0 0
F 1 3 4 6 15 16 17 5 6 6 7 8 30 54 58 77 G F
C
0 0
O
505 505
VC 502
G 1 4 6 15 16 3 5 7 9 9 29 52 66 72 73 61 60 G
C
O
V C 65
VC 5 0 1
H 8 S 10 10 20 21 24 24 3 4 10 10 31 35 38 39 47 45 DM 40 DM 59 58 H
C
O
O
VC 65
J 8 9 19 19 20 21 23 1 1 4 11 27 32 37 41 44 48 44 41 63 P N 56 J
C
O
K 7 9 11 11 S 22 22 23 2 2 11 28 36 40 43 45 46 N 43 62 57 52 K
VC 65
VC 501
L 7 12 12 14 13 13 18 12 12 26 33 34 42 46 51 47 P 50 51 DM 53 L
C
O
O
VC 503
M 14 18 49 50 ES DN N 42 48 49 54 M
C
O
N V G 3
224
3 15 15 17 17 PI PO SR MS 35 P 39 P N 55 N
VC 503
VC 504
3
P 16 16 S PR EO MD MD IN 34 37 70 68 67 66 P
C
3
O
224
R 2
224
2 6 5 4 RC PG DI CK MD 33 DM 38 69 P 65 R
VC 504
2
T 6 5 4 MD DO 32 36 71 DM N 64 T
C
2
O
224
U 1
224
1 3 2 RS ZQ AL OD OD U
VC 504
1 1
C
1 1
O
224 224
W 0
224
0 1 10 11 11 9 9 BA BG C CN CS A W
VC 504
0 0
Y 1 11 10 12 10 10 A AC C CN A A Y
C
0 0
O
224 224
V C 44
AA 11 9 9 12 7 A A A A A A AA
C
O
VC 500
VC 504
AB 18 17 15 15 S 6 5 3 12 12 8 7 8 8 23 24 22 25 A A A A A AB
C
O
O
V C 64
V C 43
AC 18 17 14 14 6 5 3 1 8 6 6 6 9 12 17 18 21 A A A 16 28 31 AC
C
C
O
O
VC 64
VC 44
VC 504
AD 16 16 13 13 4 1 7 7 6 5 5 5 10 20 2 0 11 19 18 17 29 30 AD
C
C
O
O
VC 500
AE 22 21 S 12 4 2 2 4 5 4 1 1 11 15 19 1 10 DM 14 DM P DM AE
C
O
VC 504
AF 24 22 21 12 11 11 8 4 2 5 4 2 6 8 16 3 P 8 P P N N 26 AF
C
O
VC 64
V C 43
VC 500
AG 24 20 19 10 10 8 7 1 2 3 2 0 1 14 7 DM N N 15 23 20 27 AG
C
C
O
O
AH 23 23 20 19 S 9 9 7 1 3 3 3 2 3 4 7 13 6 5 4 9 12 13 21 22 24 25 AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Bank 43 PS Bank 500

Bank 44 PS Bank 501
Bank 45 PS Bank 502
Bank 46 PS Bank 503
Bank 64 PS Bank 504
Bank 65 PS Quad 505
Bank 66
Quad 224

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐19: SFVC784 Package—XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV I/O Bank Diagram

152
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
A V A
B E B
C V C
D E V D
E V E
F F
G G
H 35 34 H
J J
K 33 K
L L
M M
N N
P V P
R 38 24 21 R
T V 22 23 PL PL PL T
V
U 15 8 7 DP DP AU AU U
V E LP LP LP AU V
V
W 13 LP LP LP AU AD W
Y E FP FP BT DD AD Y
AB FP AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐20: SFVC784 Package—XCZU4EV, XCZU5EV, XAZU4EV, and XAZU5EV


153
FBVB900 Package–XCZU4CG, XCZU4EG, XCZU5CG,

and XCZU5EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
226
3
226
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
226 226 226
1
C 1
226
1
226
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
V C 46
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
226 226 226
VC 45
VC 501
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
225 225
VC 500
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
225 225 225
VC 46
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
225 225 505 505
VC 45
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
225 225 225 505 505
VC 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
224 224 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
224 224 505 505
0 1 0
L 2
224
2
0
224
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
224
1
224
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
224 223
VC 503
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
223 224
0
R 3
223
3 0
223
MD MD ES EO 41 DM N 63 P N 56 R
2
T 2
223
2
223
2 42 44 46 61 60 57 T
1
U 1
223
45 32 34 48 50 P 52 U
0
V 0
223
1
223
1 33 35 49 51 DM N 53 V
W 0
223
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
V C 66
VC 5 0 4
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
AB 23 22 17 14 14 12 5 5 3 1 4 5 16 ZQ AL RS PA CE 64 OD AB
C
O
V C 64
VC 504
AC 23 21 21 17 8 11 11 7 3 1 3 15 17 17 S P 28 29 31 BA BG BG OD CE AC
C
O
O
V C 66
VC 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
V C 65
VC 504
AE 20 19 S 16 15 13 10 10 2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
C
O
O
VC 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
V C 65
VC 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 504
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 45 Quad 226

Bank 46 PS Bank 500
Bank 64 PS Bank 501
Bank 65 PS Bank 502
Bank 66 PS Bank 503
Quad 223 PS Bank 504
Quad 224 PS Quad 505
Quad 225

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐21: FBVB900 Package—XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG I/O Bank Diagram

154
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
T 24 21 PL PL PL AU T
U V 22 23 DP DP BT AU U
V 8 7 LP LP LP AU AU V
W 15 LP LP LP AD AD W
Y 13 FP FP FP FP FP DD Y
AA FP FP DD DD AA
AB R R R R AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐22: FBVB900 Package—XCZU4CG, XCZU4EG, XCZU5CG, and XCZU5EG


155
FBVB900 Package–XCZU4EV and XCZU5EV

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
226
3
226
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
226 226 226
1
C 1
226
1
226
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
V C 46
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
226 226 226
VC 45
VC 5 0 1
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
225 225
VC 500
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
225 225 225
VC 46
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
225 225 505 505
V C 45
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
225 225 225 505 505
V C 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
224 224 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
224 224 505 505
0 1 0
L 2
224
2
0
224
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
224
1
224
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
224 223
VC 503
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
223 224
0
R 3
223
3 0
223
2
T 2
223
2
223
2 42 44 46 61 60 57 T
1
U 1
223
45 32 34 48 50 P 52 U
0
V 0
223
1
223
1 33 35 49 51 DM N 53 V
W 0
223
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
V C 66
VC 504
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
C
O
V C 64
VC 504
C
O
O
VC 66
VC 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
VC 6 5
VC 5 0 4
AE 20 19 S 16 15 13 10 10 C
2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
O
O
V C 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
VC 65
VC 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 504
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 45 Quad 226

Bank 46 PS Bank 500
Bank 64 PS Bank 501
Bank 65 PS Bank 502
Bank 66 PS Bank 503
Quad 225

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐23: FBVB900 Package—XCZU4EV and XCZU5EV I/O Bank Diagram

156
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
AA FP FP DD DD AA
AB AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐24: FBVB900 Package—XCZU4EV and XCZU5EV


157
FBVB900 Package–XCZU7CG and XCZU7EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
227
3
227
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
227 227 227
1
C 1
227
1
227
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
VC 47
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
227 227 227
VC 48
VC 501
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
226 226
VC 500
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
226 226 226
VC 47
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
226 226 505 505
VC 48
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
226 226 226 505 505
VC 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
225 225 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
225 225 505 505
0 1 0
L 2
225
2
0
225
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
225
1
225
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
225 224
VC 503
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
224 225
0
R 3
224
3 0
224
2
T 2
224
2
224
2 42 44 46 61 60 57 T
1
U 1
224
45 32 34 48 50 P 52 U
0
V 0
224
1
224
1 33 35 49 51 DM N 53 V
W 0
224
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
VC 66
VC 504
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
C
O
VC 64
VC 504
C
O
O
VC 66
V C 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
V C 65
VC 504
AE 20 19 S 16 15 13 10 10 2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
C
O
O
VC 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
VC 65
V C 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 504
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 47 Quad 227

Bank 48 PS Bank 500
Bank 64 PS Bank 501
Bank 65 PS Bank 502
Bank 66 PS Bank 503
Quad 226

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐25: FBVB900 Package—XCZU7CG and XCZU7EG I/O Bank Diagram

158
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
AA FP FP DD DD AA
AB R R R R AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐26: FBVB900 Package—XCZU7CG and XCZU7EG


159
FBVB900 Package–XCZU7EV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A 3
227
3
227
3 12 11 11 12 11 11 24 20 1 28 31 54 52 56 57 59 58 63 A
VC 501
VC 502
2 1
B 2 2 12 10 12 10 25 2 26 27 35 34 53 55 62 61 64 B
C
2 1
O
227 227 227
1
C 1
227
1
227
1 9 8 10 9 10 17 5 30 33 38 40 60 66 67 68 C
VC 47
VC 500
VC 501
VC 502
0 0
D 0 0 9 8 8 9 7 3 6 29 36 41 65 70 69 75 71 D
C
0 0
O
227 227 227
VC 48
V C 501
VC 502
3
E 3 3 6 7 7 8 7 14 7 8 39 42 44 77 72 76 74 73 E
C
3
O
226 226
VC 5 0 0
2 1
F 2 2 6 5 6 6 22 10 9 37 43 45 F
C
2 1
O
226 226 226
VC 47
1 3
G 1 1 5 4 5 5 11 13 32 49 3 3 G
C
1 3
O
226 226 505 505
VC 4 8
0 0 3 2
H 0 0 3 3 4 4 0 12 21 51 H
C
0 0 3 2
O
226 226 226 505 505
VC 500
3 1 1
J 2 3 3 4 4 15 50 48 2 2 J
C
3 1 1
O
225 225 505 505
2 2
K G 1 1 2 2 2 K
V
2 3 3 19 16 18 23 46 47 2 1 1
225 225 505 505
0 1 0
L 2
225
2 0
225
1 1 CK DI MS
505
1
505
0 L
1 0
M 1
225
1
225
1 PG DO PI
505
0 G 0
505
0 M
VC 503
0 1
N IN PR PO DN N
C
0 1
O
225 224
VC 5 0 3
3
P 0 0 RC SR MD MD 40 47 P 43 62 DM 59 58 P
C
3
O
224 225
0
R 3
224
3 0
224
2
T 2
224
2
224
2 42 44 46 61 60 57 T
1
U 1
224
45 32 34 48 50 P 52 U
0
V 0
224
1
224
1 33 35 49 51 DM N 53 V
W 0
224
0 9 S P N 71 69 55 54 W
Y S 10 9 6 39 DM 36 70 P 67 66 Y
VC 66
VC 504
AA 24 24 22 18 18 10 12 6 2 2 1 4 5 16 37 38 68 DM N 65 AA
C
C
O
VC 504
C
O
VC 6 4
VC 504
C
O
O
VC 66
V C 66
VC 504
AD 20 19 16 15 8 13 7 4 4 1 3 6 15 14 18 20 N 16 P 30 AC BA CS CS AD
C
C
O
O
VC 65
VC 504
AE 20 19 S 16 15 13 10 10 C
2 2 6 14 24 18 22 17 27 N DM A A A C AE
C
O
O
V C 64
AF S 24 24 18 18 9 9 6 2 2 S 12 13 13 24 21 DM 18 25 26 A A C CN AF
C
O
V C 65
VC 64
VC 504
AG 23 22 22 14 14 11 S 6 3 7 11 12 19 23 S 23 19 24 10 14 A CN A A AG
C
C
O
O
VC 65
AH 23 21 21 S 13 12 11 8 3 1 7 11 19 21 23 7 1 0 8 P 15 A A A A AH
C
O
AJ 20 20 17 16 13 12 8 5 4 1 9 10 20 21 5 DM P 2 N DM 12 A A A AJ
VC 5 0 4
AK 19 19 17 16 15 15 7 7 5 4 8 8 9 10 20 22 22 6 4 N 3 9 11 13 A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 47 Quad 227

Bank 48 PS Bank 500
Bank 64 PS Bank 501
Bank 65 PS Bank 502
Bank 66 PS Bank 503
Quad 226

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐27: FBVB900 Package—XCZU7EV I/O Bank Diagram

160
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A V E A
B V B
C V E C
D V D
V
E V E
F E F
V
G V G
H E V H
J V E J
K V K
L V E V L
M E M
N V N
P E P
R V R
AA FP FP DD DD AA
AB AB
AC AC
AD AD
AE AE
AF 35 34 AF
AG 33 AG
AH AH
AJ 38 AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐28: FBVB900 Package—XCZU7EV


161
FFVC900 Package–XCZU6EG, XCZU9EG, and

XCZU15EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3
A G 3 2 2 3 2 1 A
V
3 3 3 19 17 7 26 44 45 52 66 3 3
230 230 128
2 3
B 3 1 3 2 1 G B
V
2 2 2 20 10 28 37 46 67 3
230 230 128
1
C 1
230
1
230
1 4 1 4 4 18 15 0 27 49 54 68 2
128
2 C
VC 500
VC 502
0 1 2
D 0 0 6 4 5 5 5 21 16 30 34 47 53 D
C
0 1 2
O
230 230 128 128
VC 501
1
E 3 3 6 5 6 6 7 14 2 29 36 56 69 1 1 E
C
1
O
229 230 128
3 0 1
F 3
229
2
229
2 8 7 7 8 7 23 13 3 38 48 55 70
128
0
128
1 F
VC 500
2 0
G 8 10 8 9 9 25 4 11 40 50 71 0 0 G
C
2 0
O
229 230 128
V C 48
VC 47
V C 501
1 3 0
H 1 1 11 10 12 12 22 1 6 39 57 60 75 H
C
1 3 0
O
229 229 505 128
VC 47
VC 502
1
J 0 0 12 12 11 11 10 24 5 31 51 58 64 3 3 J
C
1
O
229 229 505
VC 48
VC 500
0 2 3
K 3 3 24 9 9 11 10 12 8 32 41 63 72 K
C
0 2 3
O
229 228 505 505
VC 501
3 0
L 24 23 23 9 43 59 76 77 2 2 L
C
3 0
O
228 229 505
VC 502
2 1 2
M 2 2 22 21 33 42 61 74 M
C
2 1 2
O
228 228 505 505
1
N 1
228
1
1
228
22 S 21 35 62 65 73 1
505
1 N
1 0 1
P 1
228
0
228
0 20 20 SR RC EO ES
505
0
505
1 P
VC 503
0 0
R 19 MS CK PI PO G 0 0 R
C
0 0
O
228 228 505
VC 503
0
T 6 19 18 DN DO DI PG IN T
C
0
O
505
U 6 5 5 9 9 10 10 13 17 18 15 MD MD MD MD PR 47 46 44 45 U
V C 66
V 4 4 8 11 11 13 17 15 DM P N 62 63 61 V
C
O
VC 66
W 3 3 8 7 12 12 C
O
16 16 42 43 41 40 P 60 W
V C 66
Y 2 2 1 1 7 S 14 14 S 32 33 59 58 N DM Y
C
O
VC 65
AA 24 23 23 15 15 10 10 5 5 34 35 57 56 48 AA
C
O
AB 24 19 18 13 13 12 7 6 6 1 P N DM 51 49 50 AB
VC 65
AC 22 21 19 18 14 11 12 7 4 1 PA RS AC ZQ 39 36 52 P N DM AC
C
O
VC 65
AD 22 21 17 16 14 11 9 8 4 3 20 22 21 23 AL A A A 37 38 BG 53 54 55 AD
C
O
VC 504
VC 504
AE S 20 20 17 16 S S 9 8 3 2 DM P 24 25 27 26 A A A A 64 67 DM 71 AE
C
O
O
V C 64
AF 24 24 23 16 16 7 7 8 1 2 N 19 P N DM A A A BA BG 65 69 AF
C
O
VC 64
VC 504
VC 504
AG 22 23 S 13 13 12 S 8 1 2 16 17 18 28 30 31 A C CN CS BA 66 P 70 AG
C
C
O
O
VC 64
AH 22 20 20 18 14 11 12 9 3 2 7 3 1 29 11 14 A A OD CE N 68 AH
C
O
VC 504
VC 504
AJ S 21 18 17 14 11 9 6 5 3 6 P N 2 10 P N 15 CS CE C CN OD A AJ
C
O
O
VC 504
AK 21 19 19 17 15 15 10 10 6 5 4 4 5 4 DM 0 9 8 DM 12 13 A A A A AK
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Bank 47 Quad 230

Bank 48 PS Bank 500
Bank 64 PS Bank 501
Bank 65 PS Bank 502
Bank 66 PS Bank 503
Quad 229

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐29: FFVC900 Package—XCZU6EG, XCZU9EG, and XCZU15EG I/O Bank Diagram

162
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A E A
B V V V B
V
C V C
D V E V D
V
E V E
F V E V F
G E E G
V
H V H
J V E J
V
K V V K
L E E L
M V E V M
N V E N
P V E V P
R E R
T T
U 24 21 U
V 22 23 PL PL PL AU AU V
W 8 7 LP DP DP AU AU W
Y LP LP LP AD Y
AA 34 33 LP LP FP AD BT AA
AB 35 13 15 FP FP FP FP DD AB
AC 38 FP FP DD DD AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐30: FFVC900 Package—XCZU6EG, XCZU9EG, and XCZU15EG


163
FFVB1156 Package–XCZU6EG, XCZU9EG, and

XCZU15EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A G 9 9 4 3 12 12 12 11 11 G A
V
3 3 3 57 64 65 66 3 3
230 230 130
2 1 3
B 2
230
2
230
2
1
230
10 8 7 4 3 10 10 12 10 55 59 67 68 69 2
130
2
130
3 B
1 0 2
C 1
230
0
230
10 8 7 2 9 11 11 10 9 56 61 70 71
130
2 C
VC 502
0 1
D 1 1 4 4 11 6 5 2 9 7 8 9 7 63 75 1 1 D
C
0 1
O
230 230 130 130
VC 49
V C 47
1 1 0
E 0 0 3 11 12 6 5 8 8 7 8 7 53 60 72 E
C
1 1 0
O
230 229 130 130
VC 49
VC 502
3 3
F 3 3 3 6 6 12 1 1 6 6 6 5 52 54 77 0 0 F
C
3 3
O
229 229 130 129
VC 50
VC 48
VC 502
0 0
G 2 2 2 5 8 9 9 11 5 5 6 5 58 62 74 3 3 G
C
0 0
O
229 229 130 129
V C 47
2 2
H 1 1 2 5 7 8 10 11 2 1 1 3 32 33 73 76 2 2 H
C
2 2
O
229 229 129 129
V C 50
VC 48
1 1 1
J 1 1 7 10 12 12 2 4 4 3 31 41 46 1 1 J
C
1 1 1
O
229 228 129 129
0 1
K 0
229
0
229
0 S 18 23 S 24 19 4 3 2 1 29 36 43 49 0
129
0
129
1 K
VC 501
3 0 0 0
L 15 17 18 23 24 19 4 3 2 1 30 34 38 47 L
C
3 0 0 0
O
228 228 129 129
VC 5 0 1
2 3
M 3 3 15 17 22 20 20 27 40 42 48 3 3 M
C
2 3
O
228 228 128 128
1 2
N 2
228
2 16 16 13 21 22 28 37 39 44 51
128
1
128
2 N
VC 67
1 1
P 1 1 14 14 13 21 26 35 45 50 2 2 P
C
1 1
O
228 228 128 128
0
R 0
228
0 12 11 11 4 2 ES MD MD MS CK
128
0 1
128
1 R
VC 67
V C 503
0 0
T 10 10 12 3 6 4 2 EO MD MD DO 0 0 T
C
0 0
O
228 128 128
VC 67
VC 503
2 3
U 18 18 8 9 9 3 6 PG SR RC DI U
C
C
2 3
O
O
505 505
3
V 23 23 17 17 8 7 7 S 5 5 PI PO PR IN 3
505
3
505
3 V
VC 66
1
W 24 24 15 15 9 9 1 1 DN 2 2 W
C
1
O
505 505
V C 66 2
Y 22 22 13 13 14 11 11 6 6 C
O
5 1
505
1
505
2 Y
VC 66
0 1
AA 21 21 S 14 12 12 S 3 3 5 AA
C
0 1
O
505 505
0
AB S 20 16 10 10 8 4 2 2 G 0
505
0
505
0 AB
AC 19 19 20 16 7 7 8 4 1 1 AC
VC 65
AD 23 23 18 S 9 9 6 2 7 20 23 22 45 44 46 47 60 61 63 62 AD
C
O
VC 500
AE 24 24 17 18 13 12 10 6 1 3 9 12 12 C
O
8 18 25 24 40 P N DM P N DM AE
VC 6 5
VC 44
AF 21 21 17 13 11 12 10 1 4 3 9 11 0 11 21 PA RS AL ZQ A 41 42 43 58 59 AF
C
C
O
O
VC 65
VC 500
VC 504
AG S 20 14 14 11 8 5 5 4 10 10 11 3 23 22 20 24 27 26 AC BA 35 34 33 32 56 57 AG
C
C
O
O
AH 22 19 20 15 7 7 8 S 2 2 7 7 4 10 21 P 25 P N DM BA BG P N DM 51 48 50 AH
VC 64
V C 44
VC 504
VC 504
AJ 22 19 15 16 16 S 9 6 1 8 8 1 12 N 18 29 30 A OD CE 39 36 DM P 49 AJ
C
C
O
O
V C 64
VC 500
AK 23 24 24 18 18 11 11 9 6 1 6 5 5 13 19 DM 17 28 31 A A A BG 37 38 N 53 52 AK
C
C
O
O
VC 64
VC 504
VC 504
AL 23 22 22 13 13 12 12 3 2 6 4 6 14 19 7 16 12 13 15 A C CN A CS 55 54 71 AL
C
C
O
O
AM 21 S 17 14 14 8 8 3 2 4 2 5 16 6 5 4 DM 14 A A A A A OD 68 69 70 AM
VC 504
VC 504
AN 21 19 20 17 16 10 7 5 3 2 1 15 DM P N P N 11 A C CN CS CE 64 P N DM AN
C
C
O
O
AP S 19 20 15 15 16 10 7 5 4 4 3 1 9 17 3 1 2 0 9 8 10 A A A A A 65 66 67 AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 44 Bank 67 PS Bank 501

Bank 47 Quad 128 PS Bank 502
Bank 50 Quad 228 PS Quad 505
Bank 64 Quad 229
Bank 65 Quad 230
Bank 66 PS Bank 500

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐31: FFVB1156 Package—XCZU6EG, XCZU9EG, and XCZU15EG I/O Bank Diagram

164
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A E A
B V E V B
C E V C
D V E V D
E E V E
V
F V E V F
G E E G
V
H V E V H
J V V J
V
K V E V K
L V E L
V
M V V M
N V V N
P V E V P
R E R
T T
U 24 21 U
V 22 23 E V V
W 8 7 PL PL PL E W
Y AU AU DP DP E V Y
AA LP BT AU AU E AA
AB LP LP AD AD V AB
AC LP LP LP FP AD AD AC
AD 33 13 15 FP FP DD FP FP AD
AE 35 34 FP FP DD DD AE
AF 38 n n AF
AG AG
AH AH
AJ AJ
AK AK
AL AL
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐32: FFVB1156 Package—XCZU6EG, XCZU9EG, and XCZU15EG


165
FFVC1156 Package–XCZU7CG and XCZU7EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 3 3 10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30 A
VC 501
B 2 6 7 10 21 20 20 22 24 4 4 2 2 22 22 24 24 S 2 7 11 19 23 31 32 33 34 B
C
O
VC 500
C 2 5 6 7 19 19 8 8 18 6 6 7 8 20 20 15 15 17 1 9 12 21 17 35 36 37 38 C
C
O
VC 88
VC 67
VC 500
D 1 5 8 11 11 S 10 16 16 18 11 11 7 8 7 9 9 17 16 5 8 13 25 39 40 41 42 D
C
O
O
V C 88
VC 67
VC 28
VC 501
E 1 4 4 8 12 7 9 10 14 17 S 12 12 9 9 7 S 11 13 16 3 15 24 20 43 44 45 46 E
C
O
O
VC 68
VC 28
F 9 9 12 7 9 12 14 17 10 14 13 13 17 10 12 11 13 S 10 18 22 47 48 49 50 51 F
C
O
O
VC 68
VC 503
3
G 10 11 12 11 12 13 S 10 14 18 17 15 10 12 14 14 18 18 DO 52 53 54 55 56 G
C
3
O
227
VC 67
VC 28
VC 502
H 3 3 10 11 12 11 13 15 15 18 16 16 15 8 8 6 5 MD MS 57 58 59 60 61 H
C
O
O
227
VC 87
VC 502
2
J 9 9 8 2 4 5 20 20 21 S S 3 3 6 5 MD DI 62 63 64 65 66 J
C
2
O
227
VC 68
K 2 2 7 8 2 4 6 5 22 21 23 23 19 4 4 2 MD MD CK 67 68 69 70 71 72 73 K
C
O
227
1
L 1
227
1
227
1 7 6 3 3 1 6 22 24 24 19 1 1 2 PO 74 75 76 77 L
2 3
M 0
227
0 5 5 6 4 3 1 PR PI
505
2
505
3 M
VC 87
VC 503
0 3
N 3 3 2 2 4 1 3 DN 3 3 N
C
0 3
O
227 226 505 505
3 1
P 3
226
1 IN SR
505
1 2
505
2 P
2 1 2
R 2
226
2
226
2 1
227
RC ES 1
505
1
505
2 R
0 0 1
T 1
226
1 0
227
PG EO
505
0
505
1 T
1 1 0
U 1
226
0
226
0 1
226
0
505
0 G 505
0 U
0 0
V 0
226
0
226
47 V
3 1
W 3
225
3
225
3
1
225
44 46 45 59 P N 61 62 W
0
Y 2
225
2 0
225
P N DM 57 DM 60 63 Y
2 1
AA 2
225
1
225
1 1
224
23 22 22 S 22 24 24 PA 41 42 56 58 48 49 50 AA
1 0
AB 1
225
0
224
24 23 21 21 22 20 AL 43 32 33 53 P N AB
0 1
AC 0
225
0
225
0
1
223
22 24 S 20 20 23 20 ZQ 40 38 34 36 DM 55 54 AC
0
AD G 22 20 19 24 24 23 21 AD
V
3 3 0 RS BG DM P N 35 52
224 223
VC 64
VC 504
VC 504
3
AE 2 2 23 21 20 19 15 19 19 21 S 18 18 AC BA BA 39 37 65 67 51 AE
C
3
O
224 224
V C 66
VC 65
2
AF 18 19 19 23 21 17 17 15 14 S 17 17 16 16 A BG A A A 64 68 DM AF
C
C
2
O
O
224
VC 66
V C 65
VC 504
VC 504
1
AG 1 1 18 16 17 17 15 18 18 14 15 15 14 16 20 17 18 A A A A P N AG
C
C
1
O
O
224 224
VC 64
AH 0 0 S 16 14 13 15 16 S 13 13 S 14 13 13 DM P 25 24 30 A CE 66 69 AH
C
O
224
VC 64
VC 504
VC 504
0
AJ 3 3 12 11 14 13 16 12 12 11 9 11 12 12 22 19 N 26 DM A A OD 70 AJ
C
C
0
O
224 223
VC 66
VC 6 5
3
AK 10 12 11 9 7 10 10 11 9 9 11 10 10 23 21 27 P N A CS A 71 AK
C
C
3
O
O
223
VC 504
2
AL 2 2 10 8 8 9 7 8 8 S 9 7 7 8 8 5 28 29 31 C C CN A A AL
C
2
O
223 223
AM 1
223
1 6 6 5 5 S 4 7 7 3 2 4 6 7 6 3 8 DM 15 12 A A AM
1
AN 1
223
0
223
0 4 4 3 1 2 4 6 6 3 2 4 5 6 DM P N 9 P 14 CN CE A AN
0
AP 0
223
2 2 3 1 2 5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 66 Quad 226
Bank 67 Quad 227
Bank 68 PS Bank 500
Bank 87 PS Bank 501
Bank 88 PS Bank 502

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐33: FFVC1156 Package—XCZU7CG and XCZU7EG I/O Bank Diagram

166
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M V M
N E V N
P V V P
R E E R
T V E 24 21 V T
U E 22 23 DP U
V
V V 8 7 LP PL DP AU V
W E LP LP PL AU AU W
V
Y V LP LP BT PL AU Y
AA E 13 15 34 35 LP FP AD AD AA
AB V E FP FP FP FP DD AB
AC E 33 FP FP DD DD AC
AD V R R R R AD
AE AE
AF V AF
AG AG
AH V AH
AJ AJ
AK V AK
AL AL
AM V 38 AM
AN AN
AP V AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐34: FFVC1156 Package—XCZU7CG and XCZU7EG


167
FFVC1156 Package–XCZU7EV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 3 3 10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30 A
VC 501
B 2 6 7 10 21 20 20 22 24 4 4 2 2 22 22 24 24 S 2 7 11 19 23 31 32 33 34 B
C
O
VC 500
C 2 5 6 7 19 19 8 8 18 6 6 7 8 20 20 15 15 17 1 9 12 21 17 35 36 37 38 C
C
O
VC 88
VC 67
VC 500
D 1 5 8 11 11 S 10 16 16 18 11 11 7 8 7 9 9 17 16 5 8 13 25 39 40 41 42 D
C
O
O
VC 8 8
VC 67
VC 28
VC 501
E 1 4 4 8 12 7 9 10 14 17 S 12 12 9 9 7 S 11 13 16 3 15 24 20 43 44 45 46 E
C
O
O
V C 68
V C 28
F 9 9 12 7 9 12 14 17 10 14 13 13 17 10 12 11 13 S 10 18 22 47 48 49 50 51 F
C
O
O
V C 68
VC 503
3
G 10 11 12 11 12 13 S 10 14 18 17 15 10 12 14 14 18 18 DO 52 53 54 55 56 G
C
3
O
227
VC 6 7
V C 28
VC 502
H 3 3 10 11 12 11 13 15 15 18 16 16 15 8 8 6 5 MD MS 57 58 59 60 61 H
C
O
O
227
VC 87
VC 502
2
J 9 9 8 2 4 5 20 20 21 S S 3 3 6 5 MD DI 62 63 64 65 66 J
C
2
O
227
VC 68
K 2 2 7 8 2 4 6 5 22 21 23 23 19 4 4 2 MD MD CK 67 68 69 70 71 72 73 K
C
O
227
1
L 1
227
1
227
1 7 6 3 3 1 6 22 24 24 19 1 1 2 PO 74 75 76 77 L
2 3
M 0
227
0 5 5 6 4 3 1 PR PI
505
2
505
3 M
V C 87
VC 503
0 3
N 3 3 2 2 4 1 3 DN 3 3 N
C
0 3
O
227 226 505 505
3 1
P 3
226
1 IN SR
505
1 2
505
2 P
2 1 2
R 2
226
2
226
2 1
227
RC ES 1
505
1
505
2 R
0 0 1
T 1
226
1 0
227
PG EO
505
0
505
1 T
1 1 0
U 1
226
0
226
0
1
226
0
505
0 G 505
0 U
0 0
V 0
226
0
226
47 V
3 1
W 3
225
3
225
3
1
225
44 46 45 59 P N 61 62 W
0
Y 2
225
2 0
225
P N DM 57 DM 60 63 Y
2 1
AA 2
225
1
225
1 1
224
23 22 22 S 22 24 24 PA 41 42 56 58 48 49 50 AA
1 0
AB 1
225
0
224
24 23 21 21 22 20 AL 43 32 33 53 P N AB
0 1
AC 0
225
0
225
0
1
223
22 24 S 20 20 23 20 ZQ 40 38 34 36 DM 55 54 AC
0
AD G 22 20 19 24 24 23 21 AD
V
3 3 0 RS BG DM P N 35 52
224 223
VC 64
VC 504
VC 504
3
AE 2 2 23 21 20 19 15 19 19 21 S 18 18 AC BA BA 39 37 65 67 51 AE
C
3
O
224 224
VC 66
VC 65
2
AF 18 19 19 23 21 17 17 15 14 S 17 17 16 16 A BG A A A 64 68 DM AF
C
C
2
O
O
224
VC 66
VC 65
VC 504
VC 504
1
AG 1 1 18 16 17 17 15 18 18 14 15 15 14 16 20 17 18 A A A A P N AG
C
C
1
O
O
224 224
VC 64
AH 0 0 S 16 14 13 15 16 S 13 13 S 14 13 13 DM P 25 24 30 A CE 66 69 AH
C
O
224
VC 64
VC 504
VC 504
0
AJ 3 3 12 11 14 13 16 12 12 11 9 11 12 12 22 19 N 26 DM A A OD 70 AJ
C
C
0
O
224 223
VC 66
V C 65
3
AK 10 12 11 9 7 10 10 11 9 9 11 10 10 23 21 27 P N A CS A 71 AK
C
C
3
O
O
223
VC 504
2
AL 2 2 10 8 8 9 7 8 8 S 9 7 7 8 8 5 28 29 31 C C CN A A AL
C
2
O
223 223
AM 1
223
1 6 6 5 5 S 4 7 7 3 2 4 6 7 6 3 8 DM 15 12 A A AM
1
AN 1
223
0
223
0 4 4 3 1 2 4 6 6 3 2 4 5 6 DM P N 9 P 14 CN CE A AN
0
AP 0
223
2 2 3 1 2 5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 66 Quad 226
Bank 67 Quad 227
Bank 68 PS Bank 500
Bank 87 PS Bank 501
Bank 88 PS Bank 502

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐35: FFVC1156 Package—XCZU7EV I/O Bank Diagram

168
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M V M
N E V N
P V V P
R E E R
T V E 24 21 V T
U E 22 23 DP U
V
V
AA E 13 15 34 35 LP FP AD AD AA
AD V AD
AE AE
AF V AF
AG AG
AH V AH
AJ AJ
AK V AK
AL AL
AM V 38 AM
AN AN
AP V AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐36: FFVC1156 Package—XCZU7EV Power, Dedicated, and Multi-function Pin Diagram

169
FFVC1156 Package–XCZU11EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A 3 3 10 21 23 23 S 22 24 5 5 3 3 1 1 19 19 21 21 23 23 0 4 6 14 16 26 27 28 29 30 A
VC 501
B 2 6 7 10 21 20 20 22 24 4 4 2 2 22 22 24 24 S 2 7 11 19 23 31 32 33 34 B
C
O
VC 500
C 2 5 6 7 19 19 8 8 18 6 6 7 8 20 20 15 15 17 1 9 12 21 17 35 36 37 38 C
C
O
VC 89
VC 68
VC 500
D 1 5 8 11 11 S 10 16 16 18 11 11 7 8 7 9 9 17 16 5 8 13 25 39 40 41 42 D
C
O
O
V C 89
VC 68
V C 67
VC 501
E 1 4 4 8 12 7 9 10 14 17 S 12 12 9 9 7 S 11 13 16 3 15 24 20 43 44 45 46 E
C
O
O
VC 69
VC 67
F 9 9 12 7 9 12 14 17 10 14 13 13 17 10 12 11 13 S 10 18 22 47 48 49 50 51 F
C
O
O
VC 6 9
VC 503
3
G 10 11 12 11 12 13 S 10 14 18 17 15 10 12 14 14 18 18 DO 52 53 54 55 56 G
C
3
O
228
VC 68
VC 67
VC 502
H 3 3 10 11 12 11 13 15 15 18 16 16 15 8 8 6 5 MD MS 57 58 59 60 61 H
C
O
O
228
VC 8 8
VC 502
2
J 9 9 8 2 4 5 20 20 21 S S 3 3 6 5 MD DI 62 63 64 65 66 J
C
2
O
228
VC 6 9
K 2 2 7 8 2 4 6 5 22 21 23 23 19 4 4 2 MD MD CK 67 68 69 70 71 72 73 K
C
O
228
1
L 1
228
1
228
1 7 6 3 3 1 6 22 24 24 19 1 1 2 PO 74 75 76 77 L
2 3
M 0
228
0 5 5 6 4 3 1 PR PI
505
2
505
3 M
VC 88
VC 503
0 3
N 3 3 2 2 4 1 3 DN 3 3 N
C
0 3
O
228 227 505 505
3 1
P 3
227
1 IN SR
505
1 2
505
2 P
2 1 2
R 2
227
2
227
2 1
228
RC ES 1
505
1
505
2 R
0 0 1
T 1
227
1 0
228
PG EO
505
0
505
1 T
1 1 0
U 1
227
0
227
0 1
227
0
505
0 G 505
0 U
0 0
V 0
227
0
227
47 V
3 1
W 3
226
3
226
3 1
226
44 46 45 59 P N 61 62 W
0
Y 2
226
2 0
226
P N DM 57 DM 60 63 Y
2 1
AA 2
226
1
226
1 1
225
23 22 22 S 22 24 24 PA 41 42 56 58 48 49 50 AA
1 0
AB 1
226
0
225
24 23 21 21 22 20 AL 43 32 33 53 P N AB
0 1
AC 0
226
0
226
0
1
224
22 24 S 20 20 23 20 ZQ 40 38 34 36 DM 55 54 AC
0
AD G 22 20 19 24 24 23 21 AD
V
3 3 0 RS BG DM P N 35 52
225 224
VC 64
VC 504
VC 504
3
AE 2 2 23 21 20 19 15 19 19 21 S 18 18 AC BA BA 39 37 65 67 51 AE
C
3
O
225 225
V C 66
V C 65
2
AF 18 19 19 23 21 17 17 15 14 S 17 17 16 16 A BG A A A 64 68 DM AF
C
C
2
O
O
225
VC 66
VC 65
VC 504
VC 504
1
AG 1 1 18 16 17 17 15 18 18 14 15 15 14 16 20 17 18 A A A A P N AG
C
C
1
O
O
225 225
VC 64
AH 0 0 S 16 14 13 15 16 S 13 13 S 14 13 13 DM P 25 24 30 A CE 66 69 AH
C
O
225
V C 64
VC 504
VC 504
0
AJ 3 3 12 11 14 13 16 12 12 11 9 11 12 12 22 19 N 26 DM A A OD 70 AJ
C
0
O
225 224
VC 66
VC 65
3
AK 10 12 11 9 7 10 10 11 9 9 11 10 10 23 21 27 P N A CS A 71 AK
C
C
3
O
O
224
VC 504
2
AL 2 2 10 8 8 9 7 8 8 S 9 7 7 8 8 5 28 29 31 C C CN A A AL
C
2
O
224 224
AM 1
224
1 6 6 5 5 S 4 7 7 3 2 4 6 7 6 3 8 DM 15 12 A A AM
1
AN 1
224
0
224
0 4 4 3 1 2 4 6 6 3 2 4 5 6 DM P N 9 P 14 CN CE A AN
0
AP 0
224
2 2 3 1 2 5 5 1 1 1 1 3 3 5 4 1 2 0 11 10 N 13 OD CS AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 67 Quad 227
Bank 68 Quad 228
Bank 69 PS Bank 500
Bank 88 PS Bank 501
Bank 89 PS Bank 502

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐37: FFVC1156 Package—XCZU11EG I/O Bank Diagram

170
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M V M
N E V N
P V V P
R E E R
T V E 24 21 V T
U E 22 23 DP U
V
V
AA E 13 15 LP FP AD AD AA
AD V 34 n n n n AD
AE 35 AE
AF V AF
AG AG
AH V 38 AH
AJ AJ
AK V AK
AL AL
AM V AM
AN AN
AP V AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐38: FFVC1156 Package—XCZU11EG Power, Dedicated, and Multi-function Pin Diagram

171
FFVD1156 Package–XCZU21DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 12 20 21 21 23 24 24 24 23 29 26 43 52 54 55 59 63 3
131
3
131
3 A
2 1
B 11 11 12 20 22 22 23 24 22 21 23 20 42 45 48 53 61 62 2
131
2
131
2
131
1 B
VC 501
0
C 10 10 19 19 17 17 18 19 22 21 20 27 44 46 56 57 60 64 1 1 C
C
0
O
131 131
VC 68
VC 502
3 2
D 7 9 9 S 16 16 18 19 S 18 18 41 49 51 74 58 67 0 0 D
C
3 2
O
131 130 130
V C 89
V C 68
1
E 6 6 7 15 13 14 14 17 17 16 16 32 34 47 50 76 66 69 3 3 E
C
1
O
130 130
VC 67
VC 501
0
F 5 8 8 15 13 12 S 15 15 14 14 S 33 39 40 75 65 2 2 1 1 F
C
0
O
130 130 130
VC 67
VC 502
1
G 5 3 3 4 11 11 12 9 13 13 12 12 31 37 36 38 73 68 0 0 G
C
1
O
131 130
V C 89
VC 68
0 3
H 2 2 4 7 10 10 9 11 11 8 6 28 30 35 70 72 71 77 PI H
C
0 3
O
131 129
VC 67
J 1 1 S 7 8 8 6 6 7 10 8 6 2 3 3 G J
V
PO 3 3
C
O
129
1 2
K 2 4 4 10 2 4 4 5 9 7 10 5 4 4 2 MD
130
1
129
2 K
V C 88
L 2 6 8 10 2 3 5 9 S 5 1 1 EO MD ES 2 2 L
C
O
129
VC 88
VC 503
0 1
M 1 5 6 8 1 1 3 MD MD M
C
0 1
O
130 129
N 1 5 7 9 11 11 CK DI MS 1
129
1 N
VC 503
1 0
P 3 3 7 9 12 12 RC PG P
C
1 0
O
129 129
R 2 3 3 6 7 10 10 PR DO 0
129
0 R
0 3
T 2 4 5 6 7 11 11 IN SR DN
129
0
128
3 T
U 1 1 4 5 VC 87 8 8 12 12 3 3 U
C
O
128
V C 87
1 2
V 24 24 S S 9 9 V
C
1 2
O
128 128
W 23 23 18 18 15 17 17 2
128
2 W
0 1
Y 21 22 22 14 14 15 16 128
0
128
1 Y
AA 21 19 12 13 13 16 1
128
1 AA
VC 66
0
AB 20 20 19 12 11 11 10 10 AB
C
0
O
128
VC 66
AC 2 2 5 S 9 9 8 0 0 AC
C
O
128
3
AD 3 4 5 6 7 7 8 11 9 7 4 0
505
3 AD
VC 66
VC 500
AE 1 3 4 6 24 24 8 5 3 2 35 40 45 44 3 3 AE
C
C
O
505
V C 65
3 2
AF 1 10 22 23 23 20 15 13 10 6 1 BA 36 32 41 P 46 AF
C
3 2
O
505 505
VC 500
AG 8 8 10 22 21 21 20 19 17 16 14 12 A A PA AL ZQ 37 P N N DM 2 2 AG
C
O
505
2 1
AH 9 9 17 17 S 18 19 18 19 20 DM 23 22 A A BG RS DM 33 43 42 47
505
2
505
1 AH
VC 65
VC 504
VC 504
AJ 12 12 14 14 18 16 16 21 23 21 N P A A AC BA 39 38 34 53 48 1 1 AJ
C
C
O
O
505
VC 65
1 0
AK 7 11 11 13 13 15 15 22 24 25 20 19 18 A C BG A 64 65 54 P 50 AK
C
1 0
O
505 505
VC 504
VC 504
AL 7 S 5 S DM 7 9 8 25 24 17 16 CN A CS A 66 P 55 N 49 G 0 0 AL
C
C
O
O
505
0
AM 4 6 6 5 6 P 4 3 P 15 27 P 31 C A A OD CE 68 N DM 51
505
0 AM
VC 504
VC 504
AN 4 3 2 2 5 N 10 12 N DM N DM 30 CN A A CS OD DM 71 52 57 58 P DM AN
C
C
O
O
AP 3 1 1 1 2 0 11 13 14 26 29 28 A A A A CE 67 70 69 56 59 60 N 61 63 62 AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 66 Quad 130
Bank 67 Quad 131
Bank 68 PS Bank 500
Bank 87 PS Bank 501
Bank 88 PS Bank 502
Bank 89 PS Bank 503

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐39: FFVD1156 Package—XCZU21DR I/O Bank Diagram

172
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A V A
B V B
C V C
D V D
E V E
F E F
G E G
H E H
VCC
J FEC E J
VCC
K FEC E K
VCC
V
L FEC L
VCC
M n FEC V M
VCC
V
N n FEC N
VCC
P n FEC V P
VCC
R FEC E R
VCC
T FEC V T
VCC
U 24 21 FEC AU AU E U
VCC
V n 22 23 FEC AU AD AD V V
VCC
W 8 7 FEC
AU PL E W
VCC
Y FEC BT PL LP V Y
VCC
AA FEC DP PL LP AA
VCC
AB FEC
DD DP LP LP LP V AB
VCC
AC FEC
FP FP FP FP LP AC
VCC
AD 13 FEC
DD DD FP FP FP AD
VCC
AE 35 34 15 FEC AE
VCC
AF 33 FEC V AF
AG E AG
AH V AH
AJ E AJ
AK V AK
AL AL
AM 38 AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
GND FEC VCCSDFEC 7 DXP 33 I2C_SCLK AD VCC_PSADC
n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐40: FFVD1156 Package—XCZU21DR Power, Dedicated, and Multi-function Pin Diagram

173
FFVE1156 and FSVE1156 Packages–XCZU25DR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 2 3 3 3 12 11 11 14 24 40 43 46 50 60 71 73
129
3 A
229 229
2
B 2 3 2 1 12 10 12 20 25 38 45 51 58 62 70 75 3
129
3
129
2 B
VC 500
C 1 229 1 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
VC 88
VC 502
E 0 229 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
V C 89
VC 5 0 1
VC 502
G 3 228 3 8 8 6 4 G G
V
4 11 16 13 31 33 52 56 3 3
C
O
O
128
V C 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 2 228 2 C229C 11 12 3 3 2 0 1 28 EO 2
128
2 J
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
128
1
128
2 K
L 1 228 1 C228C MD MD 1
128
1 L
0 1
M MD RC DI
128
0
128
1 M
VC 503
N 0 228 0 S 228 S PR MS 0 0 N
C
O
128
3 0
P PG CK
505
3
128
0 P
R IN SR ES 3
505
3 R
VC 503
2 3
T 3 227 3 DN DO G T
C
2 3
O
505 505
U 2
505
2 U
1 2
V 1 227 1 C227C 505
1
505
2 V
W 1
505
1 W
0 1
Y 3 226 3 C226C 505
0
505
1 Y
AA 0
505
0 AA
0
AB 1 226 1 C225C 46 44
505
0 AB
AC 19 22 22 23 47 45 P N AC
AD 3 225 3 C224C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
V C 65
VC 504
AF 1 225 1 V 227 V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
O
VC 504
AG V 226 V 21 21 19 19 16 13 S 14 21 22 20 DM N A BA PA P N DM 56 48 AG
C
O
V C 66
AH 3 224 3 V 225 V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
VC 65
AJ V 224 V 22 22 18 S 7 11 11 12 10 P N 16 30 A A BG BG 36 DM P N AJ
C
O
V C 65
VC 504
AK 1 224 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
AM 3 3 10 10 13 12 14 14 1 2 4 5 6 DM 1 10 15 A A CN A CS OD 65 69 AM
VC 504
AN 6 6 4 4 9 9 S 12 8 8 1 2 5 6 5 P 11 P 14 A A C A CS P N 70 AN
C
O
VC 504
AP 5 5 2 2 1 1 11 11 7 7 3 3 6 4 N 2 0 N A A A CN OD CE 64 68 AP
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 66 Bank 227 PS Quad 505
Bank 88 Bank 228
Bank 89 Bank 229
Bank 224 PS Bank 502
SelectIO Pins ADC/DAC Pins Transceiver Pins PS Pins

#
# IO_L#P # ADC_VIN_#_P MGT[R, H or Y]RXP# # PS_MIO DN PS_DONE
# IO_L#N # ADC_VIN_#_N # MGT[R, H or Y]RXN# # PS_DDR_DQ EO PS_ERROR_OUT
S IO (single−ended) C ADC_CLK_P # MGT[R, H or Y]TXP# P PS_DDR_DQS_P ES PS_ERROR_STATUS
# IO_L#P_GC C ADC_CLK_N # MGT[R, H or Y]TXN# N PS_DDR_DQS_N IN PS_INIT_B
#
# IO_L#N_GC R ADC_REXT MGTREFCLK#P AL PS_DDR_ALERT_N CK PS_JTAG_TCK
VRP V VCM01 # MGTREFCLK#N AC PS_DDR_ACT_N DI PS_JTAG_TDI
VREF V VCM23 MGTAVTTRCAL PS_DDR_A PS_JTAG_TDO
V
A DO
# DAC_VOUT_#_P G MGTRREF BA PS_DDR_BA MS PS_JTAG_TMS

# DAC_VOUT_#_N BG PS_DDR_BG MD PS_MODE
C DAC_CLK_P CN PS_DDR_CK_N PI PS_PADI
C DAC_CLK_N C PS_DDR_CK PO PS_PADO
R DAC_REXT CE PS_DDR_CKE PR PS_POR_B
S SYSREF_P CS PS_DDR_CS PG PS_PROG_B
S SYSREF_N DM PS_DDR_DM RC PS_REF_CLK
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐41: FFVE1156 and FSVE1156 Packages—XCZU25DR I/O Bank Diagram

174
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC DAC DAC E A
B DAC DAC DAC DAC DAC B
C DAC DAC DAC DAC DAC E C
DAC DAC DAC
D DAC DAC DAC VTT DAC AUX AUX V D
DAC DAC DAC
E DAC VTT DAC AUX AUX E E
DAC
F DAC DAC DAC VTT DAC DAC V F
DAC DAC DAC
G DAC VTT DAC VCC VCC n G
DAC
H DAC DAC DAC DAC DAC DAC
VCC n n n V H
DAC VCC
V
J DAC DAC VCC DAC FEC n J
DAC VCC VCC
K DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC V K
DAC DAC VCC
V
L DAC DAC
VCC SUB FEC L
DAC VCC VCC
M DAC DAC DAC DAC DAC DAC
VCC
DAC
AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
P DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC P
VCC
R ADC ADC ADC DAC DAC DAC DAC DAC FEC E R
VCC VCC
T ADC ADC ADC DAC DAC DAC AMS 24 21 FEC T
VCC
U ADC ADC ADC ADC ADC ADC DAC DAC 22 23 FEC AU AU AU E U
VCC VCC
V ADC ADC ADC ADC AMS 8 7 FEC BT AU V V
ADC VCC
W ADC ADC ADC ADC ADC ADC
VCC
ADC
FEC
AD AD PL E W
ADC VCC VCC
Y ADC ADC VCC ADC AMS FEC FP DP DP PL PL V Y
ADC VCC
AA ADC ADC ADC ADC ADC ADC VCC ADC FEC FP LP LP LP AA
ADC VCC VCC
AB ADC ADC
VCC
ADC
AMS FEC
FP FP LP LP LP V AB
ADC ADC VCC
AC ADC ADC ADC ADC ADC ADC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD ADC ADC
VCC
ADC
AMS 13 34 FEC
FP DD DD AD
ADC VCC
AE ADC ADC ADC ADC ADC ADC VCC ADC 35 FEC AE
VCC
AF ADC ADC ADC FEC AF
ADC
AG ADC ADC ADC ADC AUX AG
ADC
AH ADC ADC AUX AH
ADC
AJ ADC ADC ADC ADC AUX AJ
ADC
AK ADC ADC ADC ADC AUX AK
AL ADC ADC ADC 38 AL
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
VCCAUX_IO AMS VCCINT_AMS 8 DXN 34 I2C_SDA & PERSTN1 AD GND_PSADC
ADC
VCCAUX VCC ADC_AVCC 13 POR_OVERRIDE 35 PERSTN0 AU VCC_PSAUX
ADC
VCCINT AUX ADC_AVCCAUX 15 PUDC_B 38 SMBALERT E PS_MGTRAVCC
VCCINT_IO ADC ADC_GND 21 VP V PS_MGTRAVTT
ADC
VCCINT_VCU SUB ADC_SUB_GND 22 VN BT VCC_PSBATT
DAC
VCCO_[bank number] VCC DAC_AVCC 23 VREFP DP VCC_PSDDR_PLL
DAC
VCCBRAM AUX DAC_AVCCAUX 24 VREFN PL VCC_PSPLL
DAC
VCCADC VTT DAC_AVTT FP VCC_PSINTFP
GNDADC DAC DAC_GND DD VCC_PSINTFP_DDR
DAC
R RSVDGND SUB DAC_SUB_GND LP VCC_PSINTLP
n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐42: FFVE1156 and FSVE1156 Packages—XCZU25DR Power, Dedicated, and

Multi-function Pin Diagram

175
FFVE1156 and FSVE1156 Packages–XCZU27DR and

XCZU28DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 2 229 3 229 3 3 12 11 11 14 24 40 43 46 50 60 71 73
129
3 A
2
B 2 3 2 1 12 10 12 20 25 38 45 51 58 62 70 75 3
129
3
129
2 B
VC 5 0 0
C 1 229 1 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
V C 88
VC 502
E 0 229 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
VC 89
VC 501
VC 502
G 3 228 3 8 8 6 4 G G
V
4 11 16 13 31 33 52 56 3 3
C
O
O
128
V C 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 2 228 2 C C 11 12 3 3 2 0 1 28 EO 2
128
2 J
229
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
128
1
128
2 K
L 1 228 1 C C MD MD 1
128
1 L
228
0 1
M MD RC DI
128
0
128
1 M
VC 503
N 0 228 0 S 228 S PR MS 0 0 N
C
O
128
3 0
P PG CK
505
3
128
0 P
R IN SR ES 3
505
3 R
VC 503
2 3
T 3 227 3 DN DO G T
C
2 3
O
505 505
U 2
505
2 U
1 2
V 1 227 1 C C 505
1
505
2 V
227
W 1
505
1 W
0 1
Y 3 226 3 C C 505
0
505
1 Y
226
AA 0
505
0 AA
0
AB 1 226 1 C C 46 44
505
0 AB
225
AC 19 22 22 23 47 45 P N AC
AD 3 225 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
224
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
V C 65
VC 504
AF 1 225 1 V 227 V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
V C 504
AG V 226 V 21 21 19 19 16 13 S 14 21 22 20 DM N A BA PA P N DM 56 48 AG
C
O
VC 66
AH 3 224 3 V 225 V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
VC 65
AJ V 224 V 22 22 18 S 7 11 11 12 10 P N 16 30 A A BG BG 36 DM P N AJ
C
O
V C 65
VC 504
AK 1 224 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 88 Bank 228
Bank 89 Bank 229

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐43: FFVE1156 and FSVE1156 Packages—XCZU27DR and XCZU28DR I/O Bank Diagram

176
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
DAC DAC DAC
D DAC DAC DAC VTT DAC AUX AUX V D
DAC DAC DAC
E DAC VTT DAC AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC n G
DAC
VCC n n n V H
DAC VCC
V
J DAC DAC VCC DAC FEC n J
DAC VCC VCC
K DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC V K
DAC DAC VCC
V
L DAC DAC
VCC SUB FEC L
DAC VCC VCC
M DAC DAC DAC DAC DAC DAC VCC DAC AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
VCC
R ADC ADC ADC DAC DAC DAC DAC DAC FEC E R
VCC VCC
T ADC ADC ADC DAC DAC DAC AMS 24 21 FEC T
VCC
U ADC ADC ADC ADC ADC ADC DAC DAC 22 23 FEC AU AU AU E U
VCC VCC
ADC VCC
W ADC ADC ADC ADC ADC ADC VCC ADC FEC AD AD PL E W
ADC VCC VCC
Y ADC ADC VCC ADC AMS FEC FP DP DP PL PL V Y
ADC VCC
AA ADC ADC ADC ADC ADC ADC VCC ADC FEC FP LP LP LP AA
ADC VCC VCC
AB ADC ADC VCC ADC AMS FEC FP FP LP LP LP V AB
ADC ADC VCC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD ADC ADC VCC ADC AMS 13 34 FEC FP DD DD AD
ADC VCC
AE ADC ADC ADC ADC ADC ADC VCC ADC 35 FEC AE
VCC
AF ADC ADC ADC FEC AF
ADC
AG ADC ADC ADC ADC AUX AG
ADC
AH ADC ADC AUX AH
ADC
AJ ADC ADC ADC ADC AUX AJ
ADC
AK ADC ADC ADC ADC AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐44: FFVE1156 and FSVE1156 Packages—XCZU27DR and XCZU28DR Power, Dedicated,


177

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 2 3 3 3 10 9 9 14 24 40 43 46 50 60 71 73 3 A
228 228 128
2
B 2 3 2 1 10 8 12 20 25 38 45 51 58 62 70 75 3 3
2 B
128 128
VC 500
C 1 1 4 2 1 7 8 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
228 128
VC 88
VC 501
1
D 4 5 12 7 11 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
128 128
VC 67
VC 502
E 0 0 6 6 5 12 11 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
228 128
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
128 128
VC 88
VC 501
VC 502
G 3 3 8 8 6 4 4 11 16 13 31 33 52 56 G G
V
3 3
C
O
O
227 127
VC 67
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
128 127
J 2 2 C C 11 12 3 3 2 0 1 28 EO 2 2 J
227 228 127
1 2
K 10 10 12 1 1 3 7 26 S MD PO PI
1 2 K
127 127
L 1 1 C C MD MD 1 1 L
227 227 127
0 1
M MD RC DI
0 1 M
127 127
VC 503
N 0 0 S S PR MS 0 0 N
C
O
227 227 127
3 0
P PG CK
3 0 P
505 127
R IN SR ES 3 3 R
505
VC 503
2 3
T 3 3 DN DO G T
C
2 3
O
225 505 505
U 2 2 U
505
1 2
V 2 2 3 3 1 2 V
225 226 505 505
W 1 1 W
505
0 1
Y 1 1 1 1 0 1 Y
225 226 505 505
AA 0 0 AA
505
0
AB 0 0 C C 46 44 0 AB
225 226 505
AC 19 22 22 23 47 45 P N AC
AD 3 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
224 225
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
VC 65
VC 504
AF 2 2 V V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
O
224 226
VC 504
AG V V 21 21 19 19 16 13 S 14 21 22 20 DM N A BA PA P N DM 56 48 AG
C
O
226
VC 66
AH 1 1 V V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
224 225
VC 65
AJ V V 22 22 18 S 7 11 11 12 10 P N 16 30 A A BG BG 36 DM P N AJ
C
O
224
VC 65
VC 504
AK 0 0 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
224
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 88 Bank 228

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

178
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

DAC DAC DAC
D DAC DAC DAC
VTT
DAC
AUX AUX V D
DAC DAC DAC
E DAC
VTT
DAC
AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC
n G
DAC
VCC
n n n V H
DAC V
J DAC DAC
VCC
DAC n J
DAC VCC
K DAC DAC DAC DAC DAC DAC
VCC
DAC
AMS
V K
DAC DAC V
L DAC DAC
VCC SUB L
DAC VCC
VCC
DAC
AMS
n V M
DAC
N DAC DAC
VCC
DAC n E N
DAC VCC
P DAC DAC DAC DAC DAC DAC
VCC
DAC
AMS n P
R ADC ADC ADC DAC DAC DAC DAC DAC n E R

VCC
T ADC ADC ADC DAC DAC DAC
AMS 24 21 n T
U ADC ADC ADC ADC ADC ADC DAC DAC 22 23 n AU AU AU E U

VCC
V ADC ADC ADC ADC
AMS 8 7 n BT AU V V
ADC
VCC
ADC AD AD PL E W
ADC VCC
Y ADC ADC
VCC
ADC
AMS
FP DP DP PL PL V Y
ADC
AA ADC ADC ADC ADC ADC ADC
VCC
ADC n FP LP LP LP AA
ADC VCC
AB ADC ADC
VCC
ADC
AMS
n FP FP LP LP LP V AB
ADC ADC
VCC SUB 15 33 n FP FP DD AC
ADC VCC
AD ADC ADC
VCC
ADC
AMS 13 34 n FP DD DD AD
ADC
AE ADC ADC ADC ADC ADC ADC
VCC
ADC 35 n AE
AF ADC ADC ADC n AF

ADC
AG ADC ADC ADC ADC
AUX AG
ADC
AH ADC ADC
AUX AH
ADC
AJ ADC ADC ADC ADC
AUX AJ
ADC
AK ADC ADC ADC ADC
AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
r RSVD SUB DAC_SUB_GND LP VCC_PSINTLP
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


179

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 0 3 3 12 11 11 14 24 40 43 46 50 60 71 73 3 A
231 129
2
B 0 2 1 12 10 12 20 25 38 45 51 58 62 70 75 3 3
2 B
129 129
VC 500
C 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
VC 88
VC 502
E 0 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
230 129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
VC 89
VC 501
VC 502
G 8 8 6 4 4 11 16 13 31 33 52 56 G G
V
3 3
C
O
O
128
VC 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 0
229
0 C
230
C 11 12 3 3 2 0 1 28 EO 2
128
2 J
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
128
1
128
2 K
L C C MD MD 1 1 L
228 128
0 1
M MD RC DI
0 1 M
128 128
VC 503
N 0 0 S S PR MS 0 0 N
C
O
228 228 128
3 0
P PG CK
505
3
128
0 P
R IN SR ES 3 3 R
505
VC 503
2 3
T DN DO G T
C
2 3
O
505 505
U 2
505
2 U
1 2
V 1
227
1 C
227
C
505
1
505
2 V
W 1 1 W
505
0 1
Y C C 0 1 Y
226 505 505
AA 0
505
0 AA
0
AB 1
226
1 C
225
C 46 44
505
0 AB
AC 19 22 22 23 47 45 P N AC
AD C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
224
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
VC 65
VC 504
AF 1 1 V R 24 23 23 15 15
C
17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
O
O
225
VC 504
AG V 21 21 19 19 16 13 S 14 21 22 20 DM N A BA PA P N DM 56 48 AG
C
O
VC 66
AH V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
VC 65
AJ V 22 22 18 S 7 11 11 12 10 P N 16 30 A A BG BG 36 DM P N AJ
C
O
VC 65
VC 504
AK 1 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
224
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Bank 65 Quad 128 Bank 226 PS Bank 500 PS Bank 504

Bank 66 Quad 129 Bank 227 PS Bank 501 PS Quad 505
Bank 88 Bank 224 Bank 228 PS Bank 502

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

180
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC DAC n DAC E A
C n n DAC DAC DAC DAC DAC E C
DAC DAC DAC
D DAC DAC DAC
VTT
DAC
AUX AUX V D
DAC DAC DAC
E DAC
VTT
DAC
AUX AUX E E
DAC
F DAC DAC DAC VTT DAC DAC V F
DAC DAC DAC
G n n DAC VTT DAC VCC VCC n G
DAC
VCC n n n V H
DAC VCC V
J DAC DAC
VCC
DAC
FEC n J
DAC VCC VCC
VCC
DAC
AMS FEC V K
DAC DAC VCC V
L n n DAC DAC
VCC SUB FEC L
DAC VCC VCC
VCC
DAC
AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
VCC
R ADC ADC ADC DAC DAC DAC DAC DAC
FEC E R
VCC VCC
T n n ADC ADC ADC DAC DAC DAC
AMS 24 21 FEC T
VCC
U ADC ADC ADC ADC ADC ADC DAC DAC 22 23 FEC
AU AU AU E U
VCC VCC
ADC VCC
W ADC ADC ADC ADC ADC ADC VCC ADC FEC AD AD PL E W
ADC VCC VCC
Y n n ADC ADC
VCC
ADC
AMS FEC
FP DP DP PL PL V Y
ADC VCC
VCC
ADC
FEC
FP LP LP LP AA
ADC VCC VCC
AB ADC ADC VCC ADC AMS FEC FP FP LP LP LP V AB
ADC ADC VCC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD n n ADC ADC
VCC
ADC
AMS 13 34 FEC
FP DD DD AD
ADC VCC
VCC
ADC 35 FEC AE
VCC
AF ADC n ADC ADC FEC AF
ADC
AG ADC ADC ADC n ADC AUX AG
ADC
AH n n ADC n ADC
AUX AH
ADC
AJ ADC ADC ADC n ADC
AUX AJ
ADC
AK ADC ADC ADC ADC
AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


181

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 0 2 3 3 12 11 11 14 24 40 43 46 50 60 71 73 3 A
231 231 129
2
B 0 2 2 1 12 10 12 20 25 38 45 51 58 62 70 75 3 3
2 B
129 129
VC 500
C 2 2 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
230 129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
VC 88
VC 502
E 0 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
230 129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
VC 89
VC 501
VC 502
G 2 2 8 8 6 4 4 11 16 13 31 33 52 56 G G
V
3 3
C
O
O
229 128
VC 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 0 0 C C 11 12 3 3 2 0 1 28 EO 2 2 J
229 230 128
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
1 2 K
128 128
L 2 2 C C MD MD 1 1 L
228 228 128
0 1
M MD RC DI
0 1 M
128 128
VC 503
N 0 0 S S PR MS 0 0 N
C
O
228 228 128
3 0
P PG CK
3 0 P
505 128
R IN SR ES 3 3 R
505
VC 503
2 3
T 3 3 DN DO G T
C
2 3
O
227 505 505
U 2 2 U
505
1 2
V 1 1 C C 1 2 V
227 227 505 505
W 1 1 W
505
0 1
Y 3 3 C C 0 1 Y
226 226 505 505
AA 0 0 AA
505
0
AB 1 1 C C 46 44 0 AB
226 225 505
AC 19 22 22 23 47 45 P N AC
AD 3 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
225 224
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
VC 65
VC 504
AF 1 1 V V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
O
225 227
VC 504
C
O
226
VC 66
AH 3 3 V V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
224 225
VC 65
C
O
224
VC 65
VC 504
AK 1 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
224
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Dual 128 Bank 230
Dual 129 Bank 231

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

182
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
DAC DAC DAC
D DAC DAC DAC
VTT
DAC
AUX AUX V D
DAC DAC DAC
E DAC
VTT
DAC
AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC n G
DAC
VCC n n n V H
DAC VCC V
J DAC DAC
VCC
DAC
FEC J
DAC VCC VCC
VCC
DAC
AMS FEC V K
DAC DAC VCC V
L DAC DAC
VCC SUB FEC L
DAC VCC VCC
VCC
DAC
AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
VCC
DAC
AMS FEC P
VCC
FEC E R
VCC VCC
AMS 24 21 FEC T
VCC
AU AU AU E U
VCC VCC
V ADC ADC ADC ADC
AMS 8 7 FEC
BT AU V V
ADC VCC
VCC
ADC
FEC
AD AD PL E W
ADC VCC VCC
Y ADC ADC
VCC
ADC
AMS FEC
FP DP DP PL PL V Y
ADC VCC
VCC
ADC
FEC
FP LP LP LP AA
ADC VCC VCC
AB ADC ADC
VCC
ADC
AMS FEC
FP FP LP LP LP V AB
ADC ADC VCC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD ADC ADC
VCC
ADC
AMS 13 34 FEC
FP DD DD AD
ADC VCC
VCC
ADC 35 FEC AE
VCC
AF ADC ADC ADC
FEC AF
ADC
AG ADC ADC ADC ADC
AUX AG
ADC
AH ADC ADC
AUX AH
ADC
AJ ADC ADC ADC ADC
AUX AJ
ADC
AK ADC ADC ADC ADC
AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


183

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 0 2 3 3 12 11 11 14 24 40 43 46 50 60 71 73 3 A
231 231 129
2
B 0 2 2 1 12 10 12 20 25 38 45 51 58 62 70 75 3 3
2 B
129 129
VC 500
C 2 2 4 2 1 9 10 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
230 129
VC 89
VC 501
1
D 4 5 8 9 7 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
129 129
VC 88
VC 502
E 0 0 6 6 5 8 7 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
230 129
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
129 129
VC 89
VC 501
VC 502
G 2 2 8 8 6 4 4 11 16 13 31 33 52 56 G G
V
3 3
C
O
O
229 128
VC 88
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
129 128
J 0 0 C C 11 12 3 3 2 0 1 28 EO 2 2 J
229 230 128
1 2
K 10 10 12 1 1 3 7 26 MD PO PI
1 2 K
128 128
L 2 2 C C MD MD 1 1 L
228 228 128
0 1
M MD RC DI
0 1 M
128 128
VC 503
N 0 0 S S PR MS 0 0 N
C
O
228 228 128
3 0
P PG CK
3 0 P
505 128
R IN SR ES 3 3 R
505
VC 503
2 3
T 3 3 DN DO G T
C
2 3
O
227 505 505
U 2 2 U
505
1 2
V 1 1 C C 1 2 V
227 227 505 505
W 1 1 W
505
0 1
Y 3 3 C C 0 1 Y
226 226 505 505
AA 0 0 AA
505
0
AB 1 1 C C 46 44 0 AB
226 225 505
AC 19 22 22 23 47 45 P N AC
AD 3 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
225 224
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
VC 65
VC 504
AF 1 1 V V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
O
225 227
VC 504
C
O
226
VC 66
AH 3 3 V V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
224 225
VC 65
C
O
224
VC 65
VC 504
AK 1 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
224
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Dual 128 Bank 230
Dual 129 Bank 231

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

184
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
DAC DAC DAC
D DAC DAC DAC
VTT
DAC
AUX AUX V D
DAC DAC DAC
E DAC
VTT
DAC
AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC n G
DAC
VCC n n n V H
DAC VCC V
J DAC DAC
VCC
DAC
FEC J
DAC VCC VCC
VCC
DAC
AMS FEC V K
DAC DAC VCC V
L DAC DAC
VCC SUB FEC L
DAC VCC VCC
VCC
DAC
AMS FEC V M
DAC VCC
N DAC DAC
VCC
DAC
FEC E N
DAC VCC VCC
VCC
DAC
AMS FEC P
VCC
FEC E R
VCC VCC
AMS 24 21 FEC T
VCC
AU AU AU E U
VCC VCC
V ADC ADC ADC ADC
AMS 8 7 FEC
BT AU V V
ADC VCC
VCC
ADC
FEC
AD AD PL E W
ADC VCC VCC
Y ADC ADC
VCC
ADC
AMS FEC
FP DP DP PL PL V Y
ADC VCC
VCC
ADC
FEC
FP LP LP LP AA
ADC VCC VCC
AB ADC ADC
VCC
ADC
AMS FEC
FP FP LP LP LP V AB
ADC ADC VCC
VCC SUB 15 33 FEC
FP FP DD AC
ADC VCC VCC
AD ADC ADC
VCC
ADC
AMS 13 34 FEC
FP DD DD AD
ADC VCC
VCC
ADC 35 FEC AE
VCC
AF ADC ADC ADC
FEC AF
ADC
AG ADC ADC ADC ADC
AUX AG
ADC
AH ADC ADC AUX AH
ADC
AJ ADC ADC ADC ADC
AUX AJ
ADC
AK ADC ADC ADC ADC
AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


185

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 3 3 10 9 9 14 24 40 43 46 50 60 71 73 3 A
128
2
B 2 1 10 8 12 20 25 38 45 51 58 62 70 75 3 3
2 B
128 128
VC 500
C 2 2 4 2 1 7 8 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
228 128
VC 88
VC 501
1
D 4 5 12 7 11 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
128 128
VC 67
VC 502
E 0 0 6 6 5 12 11 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
228 128
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
128 128
VC 88
VC 501
VC 502
G 3 3 8 8 6 4 4 11 16 13 31 33 52 56 G G
V
3 3
C
O
O
227 127
VC 67
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
128 127
J 2 2 C C 11 12 3 3 2 0 1 28 EO 2 2 J
227 228 127
1 2
K 10 10 12 1 1 3 7 26 S MD PO PI
1 2 K
127 127
L 1 1 C C MD MD 1 1 L
227 227 127
0 1
M MD RC DI
0 1 M
127 127
VC 503
N 0 0 S S PR MS 0 0 N
C
O
227 227 127
3 0
P PG CK
3 0 P
505 127
R IN SR ES 3 3 R
505
VC 503
2 3
T DN DO G T
C
2 3
O
505 505
U 2 2 U
505
1 2
V 1 2 V
505 505
W 1 1 W
505
0 1
Y 3 3 0 1 Y
226 505 505
AA 0 0 AA
505
0
AB 1 1 C C 46 44 0 AB
226 226 505
AC 19 22 22 23 47 45 P N AC
AD 3 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
225 225
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
VC 65
VC 504
AF 1 1 R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
O
225
VC 504
C
O
226
VC 66
AH 3 3 V V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
224 225
VC 65
C
O
224
VC 65
VC 504
AK 1 1 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
224
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 88 Bank 228

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

186
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
A DAC DAC DAC n DAC n DAC E A
B DAC DAC DAC n DAC n DAC B

DAC DAC DAC
D DAC DAC DAC
VTT
DAC
AUX AUX V D
DAC DAC DAC
E DAC
VTT
DAC
AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC
n G
DAC
VCC
n n n V H
DAC V
J DAC DAC
VCC
DAC n J
DAC VCC
VCC
DAC
AMS
V K
DAC DAC V
L DAC DAC
VCC SUB L
DAC VCC
VCC
DAC
AMS
n V M
DAC
N DAC DAC
VCC
DAC n E N
DAC VCC
VCC
DAC
AMS n P

VCC
T n n ADC ADC ADC DAC DAC DAC
AMS
24 21 n T

VCC
V n n ADC n n ADC ADC ADC
AMS 8 7 n BT AU V V
ADC
VCC
ADC n AD AD PL E W
ADC VCC
Y ADC n n ADC
VCC
ADC
AMS
n FP DP DP PL PL V Y
ADC
VCC
ADC VCC
AB ADC ADC
VCC
ADC
AMS
ADC ADC
ADC VCC
AD ADC ADC
VCC
ADC
ADC
VCC
ADC 35 n AE
AF ADC n n ADC ADC n AF

ADC
AG ADC ADC ADC ADC
AUX AG
ADC
AH ADC ADC
AUX AH
ADC
AJ ADC ADC ADC ADC
AUX AJ
ADC
AK ADC ADC ADC ADC
AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


187

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
3
A 2 3 3 3 10 9 9 14 24 40 43 46 50 60 71 73 3 A
228 228 128
2
B 2 3 2 1 10 8 12 20 25 38 45 51 58 62 70 75 3 3
2 B
128 128
VC 500
C 1 1 4 2 1 7 8 10 19 36 41 44 48 63 65 72 74 2 2 C
C
O
228 128
VC 88
VC 501
1
D 4 5 12 7 11 15 23 34 39 47 55 59 64 77 1 1 D
C
1
O
128 128
VC 67
VC 502
E 0 0 6 6 5 12 11 8 17 22 37 42 49 61 69 68 76 0 0 E
C
O
O
228 128
VC 500
1 0
F R 7 7 6 5 5 9 21 18 32 35 53 57 66 67 F
C
1 0
O
128 128
VC 88
VC 501
VC 502
G 3 3 8 8 6 4 4 11 16 13 31 33 52 56 G G
V
3 3
C
O
O
227 127
VC 67
0 3
H 9 9 11 4 2 2 6 5 27 30 29 54 H
C
0 3
O
128 127
J 2 2 C C 11 12 3 3 2 0 1 28 EO 2 2 J
227 228 127
1 2
K 10 10 12 1 1 3 7 26 S MD PO PI
1 2 K
127 127
L 1 1 C C MD MD 1 1 L
227 227 127
0 1
M MD RC DI
0 1 M
127 127
VC 503
N 0 0 S S PR MS 0 0 N
C
O
227 227 127
3 0
P PG CK
3 0 P
505 127
R IN SR ES 3 3 R
505
VC 503
2 3
T 3 3 DN DO G T
C
2 3
O
225 505 505
U 2 2 U
505
1 2
V 2 2 3 3 1 2 V
225 226 505 505
W 1 1 W
505
0 1
Y 1 1 1 1 0 1 Y
225 226 505 505
AA 0 0 AA
505
0
AB 0 0 C C 46 44 0 AB
225 226 505
AC 19 22 22 23 47 45 P N AC
AD 3 3 C C 19 21 23 S 24 43 42 41 DM 60 63 62 AD
224 225
VC 66
AE 24 20 20 21 17 24 24 27 26 AL 34 32 40 61 DM 59 AE
C
O
VC 65
VC 504
AF 2 2 V V R 24 23 23 15 15 17 18 18 25 P ZQ RS 35 33 57 P N 58 AF
C
C
O
O
224 226
VC 504
C
O
226
VC 66
AH 1 1 V V 20 20 S 7 16 13 14 10 23 DM 29 28 31 A AC 39 37 38 51 49 50 AH
C
O
224 225
VC 65
C
O
224
VC 65
VC 504
AK 0 0 17 17 18 15 8 8 12 9 19 18 17 9 12 A A BA CE 55 54 53 52 AK
C
C
O
O
224
VC 66
VC 504
AL 13 16 16 15 S 4 9 7 3 8 DM 13 A C A A 66 67 DM 71 AL
C
C
O
O
VC 504
C
O
VC 504
C
O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

Bank 88 Bank 228

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

188
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

DAC DAC DAC
D DAC DAC DAC
VTT
DAC
AUX AUX V D
DAC DAC DAC
E DAC
VTT
DAC
AUX AUX E E
DAC
F DAC DAC DAC
VTT
DAC DAC V F
DAC DAC DAC
G DAC
VTT
DAC
VCC VCC
n G
DAC
VCC
n n n V H
DAC V
J DAC DAC
VCC
DAC n J
DAC VCC
VCC
DAC
AMS
V K
DAC DAC V
L DAC DAC
VCC SUB L
DAC VCC
VCC
DAC
AMS
n V M
DAC
N DAC DAC
VCC
DAC n E N
DAC VCC
VCC
DAC
AMS n P

VCC
AMS
24 21 n T

VCC
V ADC ADC ADC ADC
AMS 8 7 n BT AU V V
ADC
VCC
ADC AD AD PL E W
ADC VCC
Y ADC ADC
VCC
ADC
AMS
FP DP DP PL PL V Y
ADC
VCC
ADC VCC
AB ADC ADC
VCC
ADC
AMS
ADC ADC
ADC VCC
AD ADC ADC
VCC
ADC
ADC
VCC
ADC 35 n AE
AF ADC ADC ADC n AF

ADC
AG ADC ADC ADC ADC
AUX AG
ADC
AH ADC ADC
AUX AH
ADC
AJ ADC ADC ADC ADC
AUX AJ
ADC
AK ADC ADC ADC ADC
AUX AK
AM AM
AN AN
AP AP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


189
FFVB1517 Package–XCZU11EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 24 22 23 23 24 22 20 20 18 18 24 24 S 22 22 24 A
B 24 22 21 19 24 22 23 23 16 16 23 20 20 22 24 B
C 20 20 21 19 S 19 21 21 17 17 23 21 22 21 S 20 C
VC 71
D S 18 18 15 18 18 19 S 14 14 15 21 23 23 21 20 D
C
O
VC 70
VC 69
VC 68
E S 17 17 15 16 15 15 13 13 15 19 18 18 17 19 19 E
C
O
O
F 13 13 16 16 16 14 S 13 12 12 S 19 14 14 17 16 F
V C 71
G 10 11 9 14 14 7 17 17 14 13 10 11 11 8 S 13 13 16 15 G
C
O
VC 9 0
VC 70
VC 69
VC 68
H 10 11 9 12 12 7 S 12 12 11 10 9 8 10 10 12 6 6 15 H
C
O
O
J 9 12 S 11 11 8 10 10 11 7 7 9 11 11 12 4 J
VC 71
K 8 8 9 12 10 8 8 8 7 9 9 6 6 5 8 S 9 2 2 4 K
C
O
V C 90
VC 70
VC 69
VC 68
L 7 7 4 2 10 5 5 7 6 5 4 1 5 8 9 5 3 3 L
C
O
O
M 6 6 3 4 2 3 3 6 4 4 6 5 4 1 7 7 5 1 1 M
3 1
N 3
227
3
227
3
1
227
5 5 3 1 1 1 6 2 2 2 2 2 3 3 9 9 7 3 3 N
VC 89
VC 67
2
P 2 2 11 12 12 1 4 4 2 3 3 19 S 15 15 11 11 7 5 1 P
C
2
O
227 227
VC 67
1 0
R 1 1 11 10 10 1 1 23 S 19 17 13 13 12 12 5 6 1 R
C
1 0
O
227 227 227
0
T 0
227
0
227
0 9 9 23 21 21 17 18 18 14 S 8 6 4 T
VC 67
3 1
U 3 3 8 6 5 24 24 16 16 14 10 10 8 4 2 U
C
3 1
O
226 226 226
VC 502
2
V G 8 6 5 20 20 22 22 2 V
V
2 2 72 69 73 70 53 60 62
C
2
O
226 226
VC 89
VC 503
1 0
W 1 1 7 1 MD SR MD 64 65 68 74 58 54 61 63 66 W
C
1 0
O
226 226 226
VC 502
0
Y 0 0 7 3 1 RC PG EO 59 67 55 56 52 57 71 75 77 76 Y
C
0
O
226 226
3 1
AA 3
225
3
225
3 1
225
4 3 MD MD DO ES AA
VC 503
2 1 2 3
AB 2 2 4 2 2 PI PO PR AB
C
2 1 2 3
O
225 225 505 505 505
1 0 3
AC 1
225
1
225
1 0
225
12 10 10 MS DN IN DI 3
505
3
505
3 AC
VC 8 8
0 0 2
AD 0 0 12 9 CK 2 2 AD
C
0 0 2
O
225 225 505 505 505

3 1 1
AE 3
224
3
224
3 1
224
11 11 9 1
505
1
505
1 AE
2 0
AF 2
224
2
224
2 8 8 28 30 27 38 42 47 G 0
505
0
505
0 AF
VC 501
1 0
AG 1 1 7 7 5 5 26 33 39 43 48 AG
C
1 0
O
224 224 224
V C 88
0
AH 0 0 4 6 6 1 32 35 40 44 47 46 44 45 62 P 59 58 AH
C
0
O
224 224
VC 504
AJ 21 21 4 3 1 5 5 2 31 34 37 45 49 P N DM 63 61 N 56 AJ
C
O
VC 501
AK 1 3 8 8 10 15 15 17 17 19 23 3 2 2 1 4 2 29 36 41 46 50 42 43 41 40 60 DM 57 AK
C
O
VC 65
VC 65
VC 504
AL 1 3 5 10 11 13 13 19 22 23 3 3 1 4 0 3 10 12 51 19 27 26 A AL AC ZQ 32 33 48 50 AL
C
C
O
O
VC 65
V C 66
AM 5 S 11 12 S 16 S 22 24 6 6 8 8 2 1 14 20 DM 18 P 31 A BG BG 34 35 P 49 51 AM
C
C
O
VC 504
VC 504
AN 4 4 6 6 12 14 14 16 20 20 24 9 7 7 10 10 4 13 17 22 17 25 N 30 A BA RS DM N DM P N AN
C
O
O
VC 500
AP 2 2 7 7 9 9 18 18 21 9 11 12 12 S 5 16 15 21 P 16 24 28 A A PA 37 38 36 52 54 AP
C
O
VC 66
VC 504
VC 504
AR 2 4 8 8 10 17 17 21 23 23 S 11 14 14 16 6 19 23 23 N 14 DM 29 BA A A OD 39 69 53 55 AR
C
C
O
O
V C 64
VC 64
AT 1 2 4 12 12 10 13 15 S 19 19 15 13 13 16 18 7 20 25 2 0 13 12 15 A A C CE 68 70 71 AT
C
C
O
VC 64
VC 500
VC 504
AU 1 3 6 11 11 13 S 15 24 20 19 15 20 17 17 18 9 22 3 1 P DM P N A CN A CS DM P N AU
C
C
O
O
VC 66
AV 3 5 6 9 14 14 18 24 22 20 19 20 S 22 22 11 18 24 DM N 9 8 11 A A C CN 64 65 66 67 AV
C
O
AW 5 S 9 7 7 18 16 16 22 21 21 23 23 24 24 8 21 6 5 4 7 10 A A A A A CS CE OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 69 Quad 226
Bank 70 Quad 227
Bank 71 PS Bank 500

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐57: FFVB1517 Package—XCZU11EG I/O Bank Diagram

190
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n n n n n n n n n n n n n A
B n n n n n n n n n n n n n n n B
C n n n n n n n n n n n n n n n n n C
D n n n n n n n n n n n n n n n n n D
E n n n n n n n n n n n n n n n n E
F n n n n n n n n n n n n n n n F
G n n n n n n n n n n n n n G
H n n n n n n n n n n n n n n H
J n n n n n n n n n n n n n n n J
K n n n n n n n n n n n K
L n n n n n n n n n n n n n L
M n n n M
N E n n n N
P V E n n P
R E R
T V E T
U V U
V V V
W V W
V
Y V 24 21 Y
AA V 22 23 AA
V
AB V 8 7 E AB
AC V V AC
AD V E PL PL BT E AD
AE E PL DP DP V AE
AF V E LP LP LP AU AU AF
AG E LP AD AD AU AU AG
AH V 15 13 LP LP FP FP AH
AJ FP FP FP DD AJ
AK 33 FP FP DD DD AK
AL 34 AL
AM 38 35 AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐58: FFVB1517 Package—XCZU11EG


191
FFVB1517 Package–XCZU17EG and XCZU19EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 23 23 S 17 17 S 8 10 10 4 2 2 10 10 24 22 23 23 24 22 20 20 18 18 24 24 S 22 22 24 A
B 21 19 19 15 15 11 9 9 8 4 6 6 S 8 8 24 22 21 19 24 22 23 23 16 16 23 20 20 22 24 B
VC 74
C 21 20 20 S 13 13 11 12 7 7 1 1 11 11 7 7 20 20 21 19 S 19 21 21 17 17 23 21 22 21 S 20 C
C
O
V C 74
VC 72
VC 71
D 24 24 18 16 14 14 12 3 3 1 3 3 12 12 9 S 18 18 15 18 18 19 S 14 14 15 21 23 23 21 20 D
C
O
O
VC 74
VC 70
VC 69
VC 68
E 22 22 18 16 5 5 4 1 5 5 14 14 9 S 17 17 15 16 15 15 13 13 15 19 18 18 17 19 19 E
C
O
O
F 23 23 21 19 19 6 6 4 2 2 16 16 13 13 13 13 16 16 16 14 S 13 12 12 S 19 14 14 17 16 F
VC 73
V C 71
G S 21 20 20 11 9 9 5 5 10 11 18 18 S 9 14 14 7 17 17 14 13 10 11 11 8 S 13 13 16 15 G
C
O
O
VC 7 3
VC 93
VC 70
VC 6 9
V C 68
H 24 24 22 22 11 7 7 3 10 11 15 17 17 9 12 12 7 S 12 12 11 10 9 8 10 10 12 6 6 15 H
C
O
O
VC 73
VC 72
J 17 17 13 13 12 12 3 6 2 2 9 12 15 19 24 S 11 11 8 10 10 11 7 7 9 11 11 12 4 J
C
O
VC 71
K 15 15 14 14 10 8 1 6 8 8 9 12 19 20 24 10 8 8 8 7 9 9 6 6 5 8 S 9 2 2 4 K
C
O
VC 93
V C 70
VC 69
V C 68
L S 18 18 16 16 S 10 8 1 4 4 7 7 4 2 21 20 10 5 5 7 6 5 4 1 5 8 9 5 3 3 L
C
O
O
VC 72
M 6 6 3 4 2 21 22 3 3 6 4 4 6 5 4 1 7 7 5 1 1 M
C
O
3 1
N 3
227
3
227
3
1
227
5 5 3 1 23 23 22 1 1 6 2 2 2 2 2 3 3 9 9 7 3 3 N
VC 91
VC 67
2
P 2 2 11 12 12 1 S 4 4 2 3 3 19 S 15 15 11 11 7 5 1 P
C
2
O
227 227
VC 67
1 0
R 1 1 11 10 10 1 1 23 S 19 17 13 13 12 12 5 6 1 R
C
1 0
O
227 227 227
0
T 0
227
0
227
0 9 9 23 21 21 17 18 18 14 S 8 6 4 T
VC 67
3 1
U 3 3 8 6 5 24 24 16 16 14 10 10 8 4 2 U
C
3 1
O
226 226 226
VC 502
2
V G 8 6 5 20 20 22 22 2 V
V
2 2 72 69 73 70 53 60 62
C
2
O
226 226
VC 91
VC 503
1 0
W 1 1 7 1 MD SR MD 64 65 68 74 58 54 61 63 66 W
C
1 0
O
226 226 226
VC 502
0
Y 0 0 7 3 1 RC PG EO 59 67 55 56 52 57 71 75 77 76 Y
C
0
O
226 226
3 1
AA 3
225
3
225
3 1
225
4 3 MD MD DO ES AA
VC 503
2 1 2 3
AB 2 2 4 2 2 PI PO PR AB
C
2 1 2 3
O
225 225 505 505 505
1 0 3
AC 1
225
1
225
1
0
225
12 10 10 MS DN IN DI 3
505
3
505
3 AC
VC 90
0 0 2
AD 0 0 12 9 CK 2 2 AD
C
0 0 2
O
225 225 505 505 505

3 1 1
AE 3
224
3
224
3 1
224
11 11 9 1
505
1
505
1 AE
2 0
AF 2
224
2
224
2 8 8 28 30 27 38 42 47 G 0
505
0
505
0 AF
VC 501
1 0
AG 1 1 7 7 5 5 26 33 39 43 48 AG
C
1 0
O
224 224 224
VC 90
0
AH 0 0 4 6 6 1 32 35 40 44 47 46 44 45 62 P 59 58 AH
C
0
O
224 224
VC 504
AJ 21 21 4 3 1 5 5 2 31 34 37 45 49 P N DM 63 61 N 56 AJ
C
O
VC 501
AK 1 3 8 8 10 15 15 17 17 19 23 3 2 2 1 4 2 29 36 41 46 50 42 43 41 40 60 DM 57 AK
C
O
VC 65
VC 6 5
VC 504
AL 1 3 5 10 11 13 13 19 22 23 3 3 1 4 0 3 10 12 51 19 27 26 A AL AC ZQ 32 33 48 50 AL
C
C
O
O
VC 65
VC 6 6
AM 5 S 11 12 S 16 S 22 24 6 6 8 8 2 1 14 20 DM 18 P 31 A BG BG 34 35 P 49 51 AM
C
C
O
VC 504
VC 504
AN 4 4 6 6 12 14 14 16 20 20 24 9 7 7 10 10 4 13 17 22 17 25 N 30 A BA RS DM N DM P N AN
C
O
O
V C 500
AP 2 2 7 7 9 9 18 18 21 9 11 12 12 S 5 16 15 21 P 16 24 28 A A PA 37 38 36 52 54 AP
C
O
VC 66
VC 504
VC 504
AR 2 4 8 8 10 17 17 21 23 23 S 11 14 14 16 6 19 23 23 N 14 DM 29 BA A A OD 39 69 53 55 AR
C
C
O
O
VC 64
VC 6 4
AT 1 2 4 12 12 10 13 15 S 19 19 15 13 13 16 18 7 20 25 2 0 13 12 15 A A C CE 68 70 71 AT
C
C
O
VC 64
VC 500
VC 504
AU 1 3 6 11 11 13 S 15 24 20 19 15 20 17 17 18 9 22 3 1 P DM P N A CN A CS DM P N AU
C
C
O
O
VC 66
AV 3 5 6 9 14 14 18 24 22 20 19 20 S 22 22 11 18 24 DM N 9 8 11 A A C CN 64 65 66 67 AV
C
O
AW 5 S 9 7 7 18 16 16 22 21 21 23 23 24 24 8 21 6 5 4 7 10 A A A A A CS CE OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 72 Quad 226


#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐59: FFVB1517 Package—XCZU17EG and XCZU19EG I/O Bank Diagram

192
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N E N
P V E P
R E R
T V E T
U V U
V V V
W V W
V
Y V 24 21 Y
AA V 22 23 AA
V
AB V 8 7 E AB
AC V V AC
AD V E PL PL BT E AD
AE E PL DP DP V AE
AF V E LP LP LP AU AU AF
AG E LP AD AD AU AU AG
AH V 15 13 LP LP FP FP AH
AJ FP FP FP DD AJ
AK 33 FP FP DD DD AK
AL 34 AL
AM 38 35 AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐60: FFVB1517 Package—XCZU17EG and XCZU19EG


193
FFVF1517 Package–XCZU7CG and XCZU7EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 11 12 12 11 12 23 22 22 24 3 1 1 4 4 2 2 3 3 18 18 22 22 24 24 A
B 11 10 11 10 12 23 20 20 24 3 6 6 2 2 6 5 5 1 16 16 23 S 21 B
VC 67
VC 68
VC 28
C 10 9 9 10 21 21 19 19 5 5 10 6 4 4 1 17 S 23 19 21 20 20 C
C
O
VC 27
D 8 8 9 9 8 17 17 S S 9 9 10 7 10 10 9 9 S 17 14 13 19 4 D
C
O
V C 87
VC 27
E 6 7 7 7 8 15 16 16 18 S 12 7 8 12 12 8 8 15 15 14 13 6 2 4 E
C
O
O
V C 88
VC 67
VC 68
VC 28
F 6 5 7 5 6 13 13 15 18 11 11 12 8 17 11 11 7 7 10 10 12 12 6 2 F
C
O
V C 27
G 4 5 5 4 6 11 14 14 15 15 13 14 14 17 13 13 15 15 9 9 11 11 5 5 G
C
O
VC 87
H 4 3 3 4 9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S 3 3 1 1 H
C
O
VC 88
VC 67
VC 6 8
VC 28
VC 501
3
J 3 3 1 2 3 3 7 9 8 10 S 17 18 16 20 18 18 21 S 7 41 40 51 45 46 J
C
3
O
228 228
2
K 2
228
2
228
2 1 2 2 2 7 8 S 10 23 S 20 20 20 S 21 19 19 29 44 35 36 26 28 50 K
VC 501
1
L 1 1 1 1 5 4 4 6 23 21 22 22 24 22 23 23 33 47 34 27 43 38 39 42 L
C
1
O
228 228
0
M 0
228
0
228
0 1 5 3 6 21 19 24 22 14 12 67 57 37 30 31 32 48 49 M
3
N 3
227
3
227
3 1 3 2 2 19 24 24 3 18 24 52 76 62 73 63 59 60 58 N
VC 500
VC 502
VC 502
2
P 2 2 20 5 72 74 66 53 69 64 61 54 P
C
2
O
227 227
1
R 1
227
1
227
1 16 1 13 65 77 68 70 56 71 55 75 R
0 1
T 0
227
0
227
0 1
228
25 15 11 T
3 0 3
U 3
226
3
226
3 0
228
23 9 4 G 3
505
3
505
3 U
2 1 3 2
V 2
226
2
226
2 1
227
2 21 22
505
3
505
2 V
VC 500
1 0 1
W 1 1 7 6 8 2 2 W
C
1 0 1
O
226 226 227 505 505
0 1 2
Y 0
226
0
226
0 1
226
10 0 19
505
2 1
505
1 Y
3 0 1 0
AA 3
225
3
225
3 0
226
17
505
1
505
0 AA
2 1 0
AB 2
225
2
225
2 1
225 505
0 0
505
0 AB
1
AC G AC
V
1 1
1
225 225
0 0
AD 0
225
0
225
0 0
225
46 42 45 57 56 P 63 AD
3 1
AE 3
224
3
224
3 1
224
MS DI 40 P DM 58 N 60 61 AE
VC 503
2 0
AF 2 2 PR DO 41 N 44 59 DM 62 AF
C
2 0
O
224 224 224
1 1
AG 1
224
1
224
1 1
223
20 20 23 20 20 RC SR PG CK 43 47 53 48 54 49 AG
0 0
AH 0
224
0
224
0
0
223
23 22 S S 22 23 22 S 23 MD MD MD ES EO 35 38 52 P N 51 AH
VC 503
3
AJ 3 3 21 23 24 22 20 22 21 21 22 23 21 21 MD PO PI DN A 37 DM 55 DM 50 AJ
C
3
O
223 223
VC 65
2
AK 2 2 23 21 19 19 24 20 24 24 19 24 24 19 19 22 21 RS IN A 36 P N 71 64 65 AK
C
2
O
223 223
VC 63
VC 64
VC 504
1
AL 1 1 23 21 S 17 15 18 9 9 19 8 16 16 17 S 23 18 ZQ A BG AC 32 39 70 DM AL
C
C
1
O
O
223 223
0
AM 0
223
0
223
0 21 24 17 15 16 18 7 7 S 8 18 18 17 15 P DM A A PA AL 34 33 P N AM
VC 66
V C 65
AN 24 13 13 16 14 11 12 12 10 14 13 13 15 17 N 20 26 BG A BA BA 69 68 66 AN
C
C
O
VC 63
VC 64
VC 504
VC 504
AP 6 6 18 18 S 17 19 19 22 22 9 11 12 14 11 13 14 10 14 12 11 11 19 16 27 24 25 CS CN A A 67 AP
C
C
O
O
VC 6 6
AR 3 5 16 16 17 S 20 20 9 10 11 12 S 15 13 14 8 10 12 9 4 2 1 DM P N A C A A A AR
C
O
VC 66
VC 65
VC 504
VC 504
AT 4 3 5 14 14 13 13 7 8 8 10 S 17 17 15 18 16 8 10 9 7 S 5 31 30 29 28 CE A A A AT
C
C
O
O
VC 63
VC 64
AU 4 1 9 9 11 15 15 7 1 5 5 1 6 18 16 5 5 7 P N DM 15 P 11 OD A A A AU
C
C
O
VC 504
AV 2 1 10 11 12 12 7 1 6 4 4 5 3 1 6 2 2 6 6 3 3 6 3 8 9 N 14 CE C CN AV
C
O
AW 2 10 S 8 8 7 3 3 6 2 2 5 3 4 4 2 2 4 4 1 1 7 0 12 DM 10 13 CS OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 67 Quad 227
Bank 68 Quad 228

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐61: FFVF1517 Package—XCZU7CG and XCZU7EG I/O Bank Diagram

194
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n V n n A
B n n n n V B
C n n V n n C
D n n n n V D
E n n V n n E
F n n n n V F
G n n V n n G
H n n n n E H
J V J
K E K
L V L
M E n n M
N V E n n N
P V n n E P
R V E n n R
V
T V T
U V E U
V
V V V V
W V E 24 21 E W
V
Y V 22 23 V Y
AA V E 8 7 PL PL PL DP DP E V AA
V
AB V LP LP LP LP AD AU E AB
AC V E LP LP FP BT AD AU AC
V
AD V FP FP FP FP AU AU AD
AE V E FP FP DD DD DD AE
V
AF V R R R R AF
AG V E 13 15 R R AG
AH E 33 AH
AJ V 34 AJ
AK E 35 AK
AL V AL
AM E AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV 38 AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐62: FFVF1517 Package—XCZU7CG and XCZU7EG


195
FFVF1517 Package–XCZU7EV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 11 12 12 11 12 23 22 22 24 3 1 1 4 4 2 2 3 3 18 18 22 22 24 24 A
B 11 10 11 10 12 23 20 20 24 3 6 6 2 2 6 5 5 1 16 16 23 S 21 B
VC 67
VC 68
VC 28
C 10 9 9 10 21 21 19 19 5 5 10 6 4 4 1 17 S 23 19 21 20 20 C
C
O
VC 27
D 8 8 9 9 8 17 17 S S 9 9 10 7 10 10 9 9 S 17 14 13 19 4 D
C
O
V C 87
VC 27
E 6 7 7 7 8 15 16 16 18 S 12 7 8 12 12 8 8 15 15 14 13 6 2 4 E
C
O
O
V C 88
VC 67
VC 68
VC 28
F 6 5 7 5 6 13 13 15 18 11 11 12 8 17 11 11 7 7 10 10 12 12 6 2 F
C
O
V C 27
G 4 5 5 4 6 11 14 14 15 15 13 14 14 17 13 13 15 15 9 9 11 11 5 5 G
C
O
VC 87
H 4 3 3 4 9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S 3 3 1 1 H
C
O
VC 88
VC 67
VC 6 8
VC 28
VC 501
3
J 3 3 1 2 3 3 7 9 8 10 S 17 18 16 20 18 18 21 S 7 41 40 51 45 46 J
C
3
O
228 228
2
K 2
228
2
228
2 1 2 2 2 7 8 S 10 23 S 20 20 20 S 21 19 19 29 44 35 36 26 28 50 K
VC 501
1
L 1 1 1 1 5 4 4 6 23 21 22 22 24 22 23 23 33 47 34 27 43 38 39 42 L
C
1
O
228 228
0
M 0
228
0
228
0 1 5 3 6 21 19 24 22 14 12 67 57 37 30 31 32 48 49 M
3
N 3
227
3
227
3 1 3 2 2 19 24 24 3 18 24 52 76 62 73 63 59 60 58 N
VC 500
VC 502
VC 502
2
P 2 2 20 5 72 74 66 53 69 64 61 54 P
C
2
O
227 227
1
R 1
227
1
227
1 16 1 13 65 77 68 70 56 71 55 75 R
0 1
T 0
227
0
227
0 1
228
25 15 11 T
3 0 3
U 3
226
3
226
3 0
228
23 9 4 G 3
505
3
505
3 U
2 1 3 2
V 2
226
2
226
2 1
227
2 21 22
505
3
505
2 V
VC 500
1 0 1
W 1 1 7 6 8 2 2 W
C
1 0 1
O
226 226 227 505 505
0 1 2
Y 0
226
0
226
0 1
226
10 0 19
505
2 1
505
1 Y
3 0 1 0
AA 3
225
3
225
3 0
226
17
505
1
505
0 AA
2 1 0
AB 2
225
2
225
2 1
225 505
0 0
505
0 AB
1
AC G AC
V
1 1
1
225 225
0 0
AD 0
225
0
225
0 0
225
46 42 45 57 56 P 63 AD
3 1
AE 3
224
3
224
3 1
224
MS DI 40 P DM 58 N 60 61 AE
VC 503
2 0
AF 2 2 PR DO 41 N 44 59 DM 62 AF
C
2 0
O
224 224 224
1 1
AG 1
224
1
224
1 1
223
20 20 23 20 20 RC SR PG CK 43 47 53 48 54 49 AG
0 0
AH 0
224
0
224
0
0
223
VC 503
3
C
3
O
223 223
VC 65
2
AK 2 2 23 21 19 19 24 20 24 24 19 24 24 19 19 22 21 RS IN A 36 P N 71 64 65 AK
C
2
O
223 223
VC 63
VC 64
VC 504
1
C
C
1
O
O
223 223
0
AM 0
223
0
223
0 21 24 17 15 16 18 7 7 S 8 18 18 17 15 P DM A A PA AL 34 33 P N AM
VC 66
V C 65
AN 24 13 13 16 14 11 12 12 10 14 13 13 15 17 N 20 26 BG A BA BA 69 68 66 AN
C
C
O
VC 63
VC 64
VC 504
VC 504
AP 6 6 18 18 S 17 19 19 22 22 9 11 12 14 11 13 14 10 14 12 11 11 19 16 27 24 25 CS CN A A 67 AP
C
C
O
O
VC 6 6
C
O
VC 66
VC 65
VC 504
VC 504
AT 4 3 5 14 14 13 13 7 8 8 10 S 17 17 15 18 16 8 10 9 7 S 5 31 30 29 28 CE A A A AT
C
C
O
O
VC 63
VC 64
AU 4 1 9 9 11 15 15 7 1 5 5 1 6 18 16 5 5 7 P N DM 15 P 11 OD A A A AU
C
C
O
VC 504
AV 2 1 10 11 12 12 7 1 6 4 4 5 3 1 6 2 2 6 6 3 3 6 3 8 9 N 14 CE C CN AV
C
O
AW 2 10 S 8 8 7 3 3 6 2 2 5 3 4 4 2 2 4 4 1 1 7 0 12 DM 10 13 CS OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 67 Quad 227
Bank 68 Quad 228

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐63: FFVF1517 Package—XCZU7EV I/O Bank Diagram

196
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A n n V n n A
B n n n n V B
C n n V n n C
D n n n n V D
E n n V n n E
F n n n n V F
G n n V n n G
H n n n n E H
J V J
K E K
L V L
M E n n M
N V E n n N
P V n n E P
R V E n n R
V
T V T
U V E U
V
V V V V
W V E 24 21 E W
V
Y V 22 23 V Y
V
V
V
AF V AF
AG V E 13 15 AG
AH E 33 AH
AJ V 34 AJ
AK E 35 AK
AL V AL
AM E AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV 38 AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐64: FFVF1517 Package—XCZU7EV Power, Dedicated, and Multi-function Pin Diagram

197
FFVF1517 Package–XCZU11EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
3
A 3
231
3
231
3 11 12 12 11 12 23 22 22 24 3 1 1 4 4 2 2 3 3 18 18 22 22 24 24 A
2
B 2
231
2
231
2 11 10 11 10 12 23 20 20 24 3 6 6 2 2 6 5 5 1 16 16 23 S 21 B
V C 70
VC 71
V C 69
1
C 1 1 10 9 9 10 21 21 19 19 5 5 10 6 4 4 1 17 S 23 19 21 20 20 C
C
1
O
231 231
VC 68
0
D 0 0 8 8 9 9 8 17 17 S S 9 9 10 7 10 10 9 9 S 17 14 13 19 4 D
C
0
O
231 231
VC 8 8
VC 68
3
E 3 3 6 7 7 7 8 15 16 16 18 S 12 7 8 12 12 8 8 15 15 14 13 6 2 4 E
C
3
O
230 230
VC 89
V C 70
VC 71
V C 69
2
F 2 2 6 5 7 5 6 13 13 15 18 11 11 12 8 17 11 11 7 7 10 10 12 12 6 2 F
C
2
O
230 230
VC 68
1
G 1 1 4 5 5 4 6 11 14 14 15 15 13 14 14 17 13 13 15 15 9 9 11 11 5 5 G
C
1
O
230 230
VC 88
0
H 0 0 4 3 3 4 9 11 12 12 17 18 13 16 16 16 14 14 8 8 7 S 3 3 1 1 H
C
0
O
230 230
VC 89
V C 70
V C 71
VC 69
VC 501
3
J 3 3 1 2 3 3 7 9 8 10 S 17 18 16 20 18 18 21 S 7 41 40 51 45 46 J
C
3
O
229 229
2
K 2
229
2
229
2 1 2 2 2 7 8 S 10 23 S 20 20 20 S 21 19 19 29 44 35 36 26 28 50 K
VC 501
1
L 1 1 1 1 5 4 4 6 23 21 22 22 24 22 23 23 33 47 34 27 43 38 39 42 L
C
1
O
229 229
0 1
M 0
229
0
229
0 1
231
1 5 3 6 21 19 24 22 14 12 67 57 37 30 31 32 48 49 M
3 0
N 3
228
3
228
3 0
231
1 3 2 2 19 24 24 3 18 24 52 76 62 73 63 59 60 58 N
VC 500
VC 502
VC 502
2 1
P 2 2 20 5 72 74 66 53 69 64 61 54 P
C
2 1
O
228 228 230
1 0
R 1
228
1
228
1 0
230
16 1 13 65 77 68 70 56 71 55 75 R
0 1
T 0
228
0
228
0 1
229
25 15 11 T
3 0 3
U 3
227
3
227
3 0
229
23 9 4 G 3
505
3
505
3 U
2 1 3 2
V 2
227
2
227
2
1
228
2 21 22
505
3
505
2 V
VC 500
1 0 1
W 1 1 7 6 8 2 2 W
C
1 0 1
O
227 227 228 505 505
0 1 2
Y 0
227
0
227
0 1
227
10 0 19
505
2 1
505
1 Y
3 0 1 0
AA 3
226
3
226
3 0
227
17
505
1
505
0 AA
2 1 0
AB 2
226
2
226
2 1
226 505
0 0
505
0 AB
1
AC G AC
V
1 1
1
226 226
0 0
AD 0
226
0
226
0 0
226
46 42 45 57 56 P 63 AD
3 1
AE 3
225
3
225
3 1
225
MS DI 40 P DM 58 N 60 61 AE
VC 503
2 0
AF 2 2 PR DO 41 N 44 59 DM 62 AF
C
2 0
O
225 225 225
1 1
AG 1
225
1
225
1 1
224
20 20 23 20 20 RC SR PG CK 43 47 53 48 54 49 AG
0 0
AH 0
225
0
225
0
0
224
VC 503
3
C
3
O
224 224
VC 65
2
AK 2 2 23 21 19 19 24 20 24 24 19 24 24 19 19 22 21 RS IN A 36 P N 71 64 65 AK
C
2
O
224 224
VC 64
VC 67
VC 504
1
C
C
1
O
O
224 224
0
AM 0
224
0
224
0 21 24 17 15 16 18 7 7 S 8 18 18 17 15 P DM A A PA AL 34 33 P N AM
VC 66
V C 65
AN 24 13 13 16 14 11 12 12 10 14 13 13 15 17 N 20 26 BG A BA BA 69 68 66 AN
C
C
O
V C 64
V C 67
VC 504
VC 504
AP 6 6 18 18 S 17 19 19 22 22 9 11 12 14 11 13 14 10 14 12 11 11 19 16 27 24 25 CS CN A A 67 AP
C
C
O
O
VC 66
C
O
VC 66
VC 65
VC 504
VC 504
AT 4 3 5 14 14 13 13 7 8 8 10 S 17 17 15 18 16 8 10 9 7 S 5 31 30 29 28 CE A A A AT
C
C
O
O
V C 64
VC 67
AU 4 1 9 9 11 15 15 7 1 5 5 1 6 18 16 5 5 7 P N DM 15 P 11 OD A A A AU
C
C
O
V C 504
AV 2 1 10 11 12 12 7 1 6 4 4 5 3 1 6 2 2 6 6 3 3 6 3 8 9 N 14 CE C CN AV
C
O
AW 2 10 S 8 8 7 3 3 6 2 2 5 3 4 4 2 2 4 4 1 1 7 0 12 DM 10 13 CS OD AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐65: FFVF1517 Package—XCZU11EG I/O Bank Diagram

198
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A V A
B V B
C V C
D V D
E V E
F V F
G V G
H E H
J V J
K E K
L V L
M E M
N V E N
P V E P
R V E R
V
T V T
U V E U
V
V V V V
W V E 24 21 E W
V
Y V 22 23 V Y
V
V
V
AF V n n n n AF
AG V E 13 15 n n AG
AH E 33 35 AH
AJ V 34 AJ
AK E AK
AL V AL
AM E AM
AN AN
AP AP
AR AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐66: FFVF1517 Package—XCZU11EG Power, Dedicated, and Multi-function Pin Diagram

199
FFVG1517 and FSVG1517 Packages–XCZU25DR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 A
VC 87
VC 501
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 B
C
O
O
V C 87
C 3 229 3 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 C
C
O
VC 68
V C 67
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 D
C
O
O
VC 69
VC 501
E 2 229 2 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 E
C
O
O
VC 69
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 F
C
O
VC 68
VC 67
G 1 229 1 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 G
C
O
O
VC 68
VC 502
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 H
C
O
O
V C 69
VC 502
J 0 229 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
O
O
129
VC 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 G K
V
62 64 70 73
C
3
O
129
2
L 3 228 3 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2
129
2
129
2 L
1
M 5 3 1 2 6 S 2 3 54 69 74 76
129
1 M
0
N 2 228 2 C229C 3 1 2 6 2 1 1 52 66 75 12 1
129
1
129
0 N
P 1 11 14 0
129
0 P
3
R 1 228 1 C228C 0 9 13 16 3
128
3
128
3 R
T 7 3 17 2
128
2 T
VC 500
2
U 0 228 0 S 228 S 8 15 23 U
C
2
O
128
1
V 4 10 20 21
129
1 1
128
1 V
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y 3 227 3 C227C 2 18 22 24
128
1 0
128
0 Y
0 0
AA 5 PG CK
128
0
128
0 AA
AB 1 227 1 C226C R IN DN SR PR MD MD AB
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD 3 226 3 C225C MS DI DO 3
505
3 AD
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1 226 1 C224C S 18 18 24 24 EO PO 62 2
505
2 AF
1 1
AG 23 S 16 23 22 63 61
505
1
505
1 AG
VC 65
AH 3 225 3 V 227 V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
505
VC 64
0 0
AJ V 226 V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
505 505
VC 66
AK 1 225 1 V 225 V 21 19 22 14 14 19 S C
O 20 20 23 21 24 27 26 A 57 56 G 0
505
0 AK
AL V 224 V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
VC 65
VC 64
VC 504
AM 3 224 3 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
VC 66
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
VC 84
VC 504
VC 504
AP 1 224 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
VC 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
VC 66
VC 504
VC 504
AT 7 8 8 S 6 4 4 5 5 7 9 S 8 10 P 8 N DM CN A A A P DM 64 N 66 AT
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

Bank 84 Bank 228
Bank 87 Bank 229

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐67: FFVG1517 and FSVG1517 Packages—XCZU25DR I/O Bank Diagram

200
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V r r A
B DAC DAC DAC r r V R R B
C DAC V r r R R C
D DAC DAC DAC r r V R R D
E DAC DAC V r r R R E
F DAC DAC DAC DAC r r V R R F
G DAC DAC V r r R R G
DAC
H DAC DAC DAC
VTT r r V R R H
DAC
J DAC VTT V R R J
DAC
K DAC DAC DAC VTT DAC V K
DAC DAC DAC
L DAC
VTT
DAC
AUX AUX E L
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC r r E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
P DAC DAC DAC DAC DAC DAC AUX DAC VCC SUB FEC r r V P
DAC DAC VCC VCC
V
R DAC DAC AUX DAC VCC DAC AMS FEC V R
DAC DAC VCC
T DAC DAC DAC DAC DAC DAC AUX DAC VCC DAC FEC r r V T
DAC DAC VCC VCC
V
U DAC DAC AUX DAC VCC DAC AMS FEC r r V U
DAC VCC
V DAC DAC DAC DAC DAC DAC DAC DAC
VCC
DAC
FEC E V
DAC VCC VCC
W ADC ADC ADC ADC ADC ADC DAC
VCC
DAC
AMS 24 21 FEC E V W
VCC
Y ADC ADC DAC DAC DAC DAC 22 23 FEC E Y
VCC VCC
AA ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AMS 8 7 FEC V AA
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AC ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS FEC BT AU AU AU V AC
ADC ADC VCC
AD ADC ADC
AUX
ADC
VCC
ADC
FEC
DP DP PL AU E AD
ADC ADC ADC VCC VCC
AE ADC ADC ADC ADC ADC ADC AUX ADC VCC SUB AMS FEC LP PL PL AD V AE
ADC ADC VCC
AF ADC ADC AUX ADC VCC ADC 13 15 FEC FP DP LP AD E AF
ADC ADC VCC VCC
AG ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS 33 FEC FP LP LP DD V AG
ADC ADC VCC
AH ADC ADC AUX ADC VCC ADC 34 FEC FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC ADC AUX ADC VCC ADC AMS 35 FEC FP FP DD DD V AJ
AK ADC AK
AL ADC ADC ADC AL
AM ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐68: FFVG1517 and FSVG1517 Packages—XCZU25DR Power, Dedicated, and


201
FFVG1517 and FSVG1517 Packages–XCZU27DR and

XCZU28DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 3
131
3 A
VC 87
VC 5 0 1
3
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 2 2 B
C
3
O
131 131
VC 87
2
C 3 229 3 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 1 1 C
C
2
O
131 131
V C 68
VC 67
1
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 0 0 D
C
1
O
131 131
VC 69
VC 501
0
E 2 229 2 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 3 3 E
C
0
O
130 131
V C 69
3
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 2 2 F
C
3
O
130 130
V C 68
VC 67
2
G 1 229 1 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 1 1 G
C
2
O
130 130
V C 68
VC 502
1
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 0 0 H
C
1
O
130 130
VC 69
VC 502
0
J 0 229 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
0
O
129 130
V C 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 G K
V
62 64 70 73
C
3
O
129
2
L 3 228 3 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2
129
2
129
2 L
1 1
M 5 3 1 2 6 S 2 3 54 69 74 76
131
1
129
1 M
0
N 2 228 2 C C 3 1 2 6 2 1 1 52 66 75 12 1
129
1
129
0 N
229
0
P 1 11 14
131
0 0
129
0 P
3
R 1 228 1 C C 0 9 13 16 3
128
3
128
3 R
228
1
T 7 3 17
130
1 2
128
2 T
VC 500
0 2
U 0 228 0 S 228 S 8 15 23 U
C
0 2
O
130 128
1
V 4 10 20 21
129
1 1
128
1 V
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y 3 227 3 C C 2 18 22 24
128
1 0
128
0 Y
227
0 0
AA 5 PG CK
128
0
128
0 AA
AB 1 227 1 C C R IN DN SR PR MD MD AB
226
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD 3 226 3 C C MS DI DO 3
505
3 AD
225
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1 226 1 C C S 18 18 24 24 EO PO 62 2
505
2 AF
224
1 1
AG 23 S 16 23 22 63 61
505
1
505
1 AG
VC 65
AH 3 225 3 V 227 V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
505
VC 64
0 0
AJ V 226 V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
505 505
VC 66
AK 1 225 1 V 225 V 21 19 22 14 14 19 S 20 20 23 21 24 27 26 A 57 56 G 0 0 AK
C
O
505
AL V 224 V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
VC 65
VC 64
VC 504
AM 3 224 3 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
VC 6 6
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
V C 84
VC 504
VC 504
AP 1 224 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
V C 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
V C 66
VC 504
VC 504
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Quad 128 Bank 228


#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐69: FFVG1517 and FSVG1517 Packages—XCZU27DR and XCZU28DR I/O Bank Diagram

202
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V A
B DAC DAC DAC V B
C DAC V C
D DAC DAC DAC V D
E DAC DAC V E
F DAC DAC DAC DAC V F
G DAC DAC V G
DAC
H DAC DAC DAC
VTT V H
DAC
J DAC VTT V J
DAC
DAC DAC DAC
L DAC
VTT
DAC
AUX AUX E L
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
P DAC DAC DAC DAC DAC DAC AUX DAC VCC SUB FEC V P
DAC DAC VCC VCC
V
R DAC DAC AUX DAC VCC DAC AMS FEC V R
DAC DAC VCC
T DAC DAC DAC DAC DAC DAC AUX DAC VCC DAC FEC V T
DAC DAC VCC VCC
V
U DAC DAC AUX DAC VCC DAC AMS FEC V U
DAC VCC
VCC
DAC
FEC E V
DAC VCC VCC
VCC
DAC
AMS 24 21 FEC E V W
VCC
VCC VCC
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AC ADC ADC ADC ADC ADC ADC AUX ADC VCC ADC AMS FEC BT AU AU AU V AC
ADC ADC VCC
AD ADC ADC AUX ADC VCC ADC FEC DP DP PL AU E AD
ADC ADC ADC VCC VCC
ADC ADC VCC
AF ADC ADC AUX ADC VCC ADC 13 15 FEC FP DP LP AD E AF
ADC ADC VCC VCC
ADC ADC VCC
AH ADC ADC
AUX
ADC
VCC
ADC 34 FEC
FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC ADC AUX ADC VCC ADC AMS 35 FEC FP FP DD DD V AJ
AK ADC AK
AL ADC ADC ADC AL
AM ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐70: FFVG1517 and FSVG1517 Packages—XCZU27DR and XCZU28DR Power, Dedicated,


203

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 3 3 A
131
VC 87
VC 501
3
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 2 2 B
C
3
O
131 131
VC 87
2
C 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 1 1 C
C
2
O
131 131
VC 68
VC 67
1
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 0 0 D
C
1
O
131 131
VC 69
VC 501
0
E 0 0 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 3 3 E
C
0
O
231 130 131
VC 69
3
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 2 2 F
C
3
O
130 130
VC 68
VC 67
2
G 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 1 1 G
C
2
O
130 130
VC 68
VC 502
1
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 0 0 H
C
1
O
130 130
VC 69
VC 502
0
J 0 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
0
O
230 129 130
VC 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 62 64 70 73 G K
V
C
3
O
129
2
L 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2 2
2 L
129 129
1 1
M 5 3 1 2 6 S 2 3 54 69 74 76 1 1 M
131 129
0
N 0 0 C C 3 1 2 6 2 1 1 52 66 75 12 1 1 0 N
229 230 129 129
0
P 1 11 14 0
0 0 P
131 129
3
R C C 0 9 13 16 3 3 3 R
228 128 128
1
T 7 3 17 1
2 2 T
130 128
VC 500
0 2
U 0 0 S S 8 15 23 U
C
0 2
O
228 228 130 128
1
V 4 10 20 21
129
1
1
128
1 V
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y C C 2 18 22 24 1
0 0 Y
227 128 128
0 0
AA 5 PG CK
128
0
128
0 AA
AB 1
227
1 C
226
C R IN DN SR PR MD MD AB
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD C C MS DI DO 3 3 AD
225 505
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1
226
1 C
224
C S 18 18 24 24 EO PO 62 2
505
2 AF
1 1
AG 23 S 16 23 22 63 61 1 1 AG
505 505
VC 65
AH V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
505
VC 64
0 0
AJ V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
505 505
VC 66
AK 1 1 V 21 19 22 14 14 19 S 20 20 23 21 24 27 26 A 57 56 G 0 0 AK
C
O
225 505
AL V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
VC 65
VC 64
VC 504
AM 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
VC 66
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
VC 84
VC 504
VC 504
AP 1 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
224
VC 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
VC 66
VC 504
VC 504
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Bank 68 Quad 128 Bank 224 Bank 228 PS Bank 502
Bank 65 Bank 69 Quad 129 Bank 225 Bank 230 PS Bank 503
Bank 66 Bank 84 Quad 130 Bank 226 PS Bank 500 PS Bank 504
Bank 67 Bank 87 Quad 131 Bank 227 PS Bank 501 PS Quad 505

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

204
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V A
B DAC DAC DAC V B
C n DAC V C
D DAC DAC DAC V D
E DAC DAC V E
G n n DAC DAC V G
DAC
H DAC DAC DAC
VTT V H
DAC
J DAC
VTT V J
DAC
DAC DAC DAC
L n n DAC VTT DAC AUX AUX E L
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
P DAC DAC DAC DAC DAC DAC AUX DAC VCC SUB FEC V P
DAC DAC VCC VCC V
R n n DAC DAC
AUX
DAC
VCC
DAC
AMS FEC V R
DAC DAC VCC
T DAC DAC DAC DAC DAC DAC
AUX
DAC
VCC
DAC
FEC V T
DAC DAC VCC VCC V
U DAC DAC
AUX
DAC
VCC
DAC
AMS FEC V U
DAC VCC
V DAC DAC DAC DAC DAC DAC DAC DAC VCC DAC FEC E V
DAC VCC VCC
VCC
DAC
AMS 24 21 FEC E V W
VCC
Y n n ADC ADC DAC DAC DAC DAC 22 23 FEC E Y
VCC VCC
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AUX
ADC
VCC
ADC
AMS FEC
BT AU AU AU V AC
ADC ADC VCC
AD n n ADC ADC
AUX
ADC
VCC
ADC
FEC
DP DP PL AU E AD
ADC ADC ADC VCC VCC
ADC ADC VCC
AF ADC ADC
AUX
ADC
VCC
ADC 13 15 FEC
FP DP LP AD E AF
ADC ADC VCC VCC
ADC ADC VCC
AH n n ADC n ADC
AUX
ADC
VCC
ADC 34 FEC
FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC n ADC AUX ADC VCC ADC AMS 35 FEC FP FP DD DD V AJ
AK ADC n AK
AL ADC ADC ADC n AL
AM n n ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


205

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 3 3 A
131
VC 87
VC 501
3
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 2 2 B
C
3
O
131 131
VC 87
2
C 2 2 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 1 1 C
C
2
O
231 131 131
VC 68
VC 67
1
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 0 0 D
C
1
O
131 131
VC 69
VC 501
0
E 0 0 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 3 3 E
C
0
O
231 130 131
VC 69
3
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 2 2 F
C
3
O
130 130
VC 68
VC 67
2
G 2 2 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 1 1 G
C
2
O
230 130 130
VC 68
VC 502
1
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 0 0 H
C
1
O
130 130
VC 69
VC 502
0
J 0 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
0
O
230 129 130
VC 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 62 64 70 73 G K
V
C
3
O
129
2
L 2 2 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2 2
2 L
229 129 129
1 1
M 5 3 1 2 6 S 2 3 54 69 74 76 1 1 M
131 129
0
N 0 0 C C 3 1 2 6 2 1 1 52 66 75 12 1 1
0 N
229 230 129 129
0
P 1 11 14 0
0 0 P
131 129
3
R 2 2 C C 0 9 13 16 3 3
3 R
228 228 128 128
1
T 7 3 17 1
2 2 T
130 128
VC 500
0 2
U 0 0 S S 8 15 23 U
C
0 2
O
228 228 130 128
1
V 4 10 20 21 1
1 1 V
129 128
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y 3 3 C C 2 18 22 24 1
0 0 Y
227 227 128 128
0 0
AA 5 PG CK
0 0 AA
128 128
AB 1 1 C C R IN DN SR PR MD MD AB
227 226
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD 3 3 C C MS DI DO 3 3 AD
226 225 505
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1 1 C C S 18 18 24 24 EO PO 62 2 2 AF
226 224 505
1 1
AG 23 S 16 23 22 63 61 1 1 AG
505 505
VC 65
AH 3 3 V V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
225 227 505

VC 64
0 0
AJ V V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
226 505 505

VC 66
AK 1 1 V V 21 19 22 14 14 19 S 20 20 23 21 24 27 26 A 57 56 G 0 0 AK
C
O
225 225 505
AL V V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
224
VC 65
VC 64
VC 504
AM 3 3 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
224
VC 66
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
VC 84
VC 504
VC 504
AP 1 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
224
VC 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
VC 66
VC 504
VC 504
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Bank 64 Dual 128 Bank 228 PS Bank 504

Bank 65 Dual 129 Bank 229 PS Quad 505
Bank 66 Dual 130 Bank 230

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ

206
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V A
B DAC DAC DAC V B
C DAC V C
D DAC DAC DAC V D
E DAC DAC V E
G DAC DAC V G
DAC
H DAC DAC DAC
VTT V H
DAC
J DAC
VTT V J
DAC
K DAC DAC DAC
VTT
DAC V K
DAC DAC DAC
L DAC
VTT
DAC
AUX AUX E L
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
AUX
DAC
VCC SUB FEC V P
DAC DAC VCC VCC V
R DAC DAC
AUX
DAC
VCC
DAC
AMS FEC V R
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC V T
DAC DAC VCC VCC V
U DAC DAC
AUX
DAC
VCC
DAC
AMS FEC V U
DAC VCC
VCC
DAC
FEC E V
DAC VCC VCC
VCC
DAC
AMS 24 21 FEC E V W
VCC
VCC VCC
AA ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AMS 8 7 FEC V AA
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AUX
ADC
VCC
ADC
AMS FEC
BT AU AU AU V AC
ADC ADC VCC
AD ADC ADC
AUX
ADC
VCC
ADC
FEC
DP DP PL AU E AD
ADC ADC ADC VCC VCC
AUX
ADC
VCC SUB AMS FEC
LP PL AD V AE
ADC ADC VCC
AF ADC ADC
AUX
ADC
VCC
ADC 13 15 FEC
FP DP LP AD E AF
ADC ADC VCC VCC
AG ADC ADC ADC ADC ADC ADC
AUX
ADC
VCC
ADC
AMS 33 FEC
FP LP LP DD V AG
ADC ADC VCC
AH ADC ADC AUX ADC VCC ADC 34 FEC FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC ADC
AUX
ADC
VCC
ADC
AMS 35 FEC
FP FP DD DD V AJ
AK ADC AK
AL ADC ADC ADC AL
AM ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]


207
FFVG1517, FSVG1517 Packages–XCZU48DR

FSRG1517 Package–XQZU48DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A 10 11 11 12 12 23 23 24 24 24 24 20 24 24 22 20 S 32 33 46 3 3 A
131
VC 87
VC 501
3
B 10 7 7 8 8 19 21 21 22 22 22 20 23 22 19 20 29 34 39 49 2 2 B
C
3
O
131 131
VC 87
2
C 2 2 9 9 5 5 4 S 19 20 22 21 21 19 23 21 21 19 27 31 36 41 47 1 1 C
C
2
O
231 131 131
VC 68
VC 67
1
D 3 6 6 4 S 20 18 23 23 19 S S 18 16 16 30 40 43 48 0 0 D
C
1
O
131 131
VC 69
VC 501
0
E 0 0 1 3 2 2 17 16 16 18 17 18 18 S 18 17 17 15 35 38 42 51 3 3 E
C
0
O
231 130 131
VC 69
3
F 1 6 9 9 17 15 15 17 13 16 14 13 13 15 28 37 44 50 2 2 F
C
3
O
130 130
VC 68
VC 67
2
G 2 2 5 5 4 6 S 13 13 15 15 13 14 16 14 11 12 S 26 45 61 63 1 1 G
C
2
O
230 130 130
VC 68
VC 502
1
H 3 3 4 12 12 14 14 7 11 11 14 10 9 11 12 57 58 59 71 68 0 0 H
C
1
O
130 130
VC 69
VC 502
0
J 0 0 1 1 2 11 11 10 10 7 9 12 12 10 9 7 7 55 60 67 72 3 3 J
C
0
O
230 129 130
VC 67
3
K 2 8 8 7 7 9 8 10 10 4 4 8 62 64 70 73 G K
V
C
3
O
129
2
L 2 2 5 4 4 8 6 6 3 5 5 8 53 56 65 77 2 2
2 L
229 129 129
1 1
M 5 3 1 2 6 S 2 3 54 69 74 76 1 1 M
131 129
0
N 0 0 C C 3 1 2 6 2 1 1 52 66 75 12 1 1
0 N
229 230 129 129
0
P 1 11 14 0
0 0 P
131 129
3
R 2 2 C C 0 9 13 16 3 3
3 R
228 228 128 128
1
T 7 3 17 1
2 2 T
130 128
VC 500
0 2
U 0 0 S S 8 15 23 U
C
0 2
O
228 228 130 128
1
V 4 10 20 21 1
1 1 V
129 128
VC 500
0 1
W R 6 19 25 W
C
0 1
O
129 128
1
Y 3 3 C C 2 18 22 24 1
0 0 Y
227 227 128 128
0 0
AA 5 PG CK
0 0 AA
128 128
AB 1 1 C C R IN DN SR PR MD MD AB
227 226
VC 503
3 3
AC RC MD ES AC
C
3 3
O
505 505
AD 3 3 C C MS DI DO 3 3 AD
226 225 505
VC 503
2 2
AE PI MD AE
C
2 2
O
505 505
AF 1 1 C C S 18 18 24 24 EO PO 62 2 2 AF
226 224 505
1 1
AG 23 S 16 23 22 63 61 1 1 AG
505 505
VC 65
AH 3 3 V V 23 24 17 17 16 23 22 60 P N 1 1 AH
C
O
225 227 505

VC 64
0 0
AJ V V 21 24 22 15 15 19 21 21 59 58 DM AJ
C
0 0
O
226 505 505

VC 66
AK 1 1 V V 21 19 22 14 14 19 S 20 20 23 21 24 27 26 A 57 56 G 0 0 AK
C
O
225 225 505
AL V V 18 18 17 9 S 19 20 13 13 12 17 18 18 16 DM 25 P N A AC BG AL 48 AL
224
VC 65
VC 64
VC 504
AM 3 3 15 15 17 9 7 10 20 11 12 15 17 13 16 P N 20 DM 31 A A BA RS 53 52 DM P 49 50 AM
C
C
O
O
224
VC 66
AN 16 16 12 11 7 10 11 10 10 15 13 14 S 22 19 29 28 30 BA PA BG ZQ 55 54 N 51 AN
C
O
VC 84
VC 504
VC 504
AP 1 1 12 12 13 14 12 11 7 9 S 8 11 12 12 14 18 17 16 9 A A A OD 46 47 67 70 69 71 AP
C
C
O
O
224
VC 65
VC 64
AR 11 11 13 14 8 8 7 9 8 7 11 9 8 10 7 6 P 11 A C CS CE 45 44 65 P DM 68 AR
C
C
O
VC 66
VC 504
VC 504
C
C
O
O
VC 84
AU 4 4 6 6 7 10 9 6 2 3 6 6 3 5 6 6 DM N 10 12 A A C A 40 N 35 34 33 32 AU
C
O
VC 504
VC 504
AV 3 3 5 5 10 9 1 3 2 3 2 4 3 5 2 4 5 4 2 13 14 A CN A OD 41 38 DM P 36 AV
C
C
O
AW 2 2 1 1 5 5 1 3 1 1 2 4 1 1 2 4 3 1 0 15 A CS CE A 43 42 39 37 N AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐75: FFVG1517, FSVG1517, FSRG1517 Packages—XCZU48DR, XQZU48DR

I/O Bank Diagram

208
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
A DAC V A
B DAC DAC DAC V B
C DAC V C
D DAC DAC DAC V D
E DAC DAC V E
G DAC DAC V G
DAC
H DAC DAC DAC
VTT V H
DAC
J DAC
VTT V J
DAC
K DAC DAC DAC
VTT
DAC V K
DAC DAC DAC
L DAC
VTT
DAC
AUX AUX E L
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC E M
DAC DAC VCC VCC
N DAC DAC
AUX
DAC
VCC
DAC
AMS FEC E N
DAC DAC DAC VCC
AUX
DAC
VCC SUB FEC V P
DAC DAC VCC VCC V
R DAC DAC
AUX
DAC
VCC
DAC
AMS FEC V R
DAC DAC VCC
AUX
DAC
VCC
DAC
FEC V T
DAC DAC VCC VCC V
U DAC DAC
AUX
DAC
VCC
DAC
AMS FEC V U
DAC VCC
VCC
DAC
FEC E V
DAC VCC VCC
VCC
DAC
AMS 24 21 FEC E V W
VCC
VCC VCC
AA ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AMS 8 7 FEC V AA
ADC ADC VCC
AB ADC ADC
AUX VCC
ADC
FEC AB
ADC ADC VCC VCC
AUX
ADC
VCC
ADC
AMS FEC
BT AU AU AU V AC
ADC ADC VCC
AD ADC ADC
AUX
ADC
VCC
ADC
FEC
DP DP PL AU E AD
ADC ADC ADC VCC VCC
AUX
ADC
VCC SUB AMS FEC
LP PL AD V AE
ADC ADC VCC
AF ADC ADC
AUX
ADC
VCC
ADC 13 15 FEC
FP DP LP AD E AF
ADC ADC VCC VCC
AG ADC ADC ADC ADC ADC ADC
AUX
ADC
VCC
ADC
AMS 33 FEC
FP LP LP DD V AG
ADC ADC VCC
AH ADC ADC
AUX
ADC
VCC
ADC 34 FEC
FP FP FP DD E AH
ADC ADC VCC VCC
AJ ADC ADC ADC ADC
AUX
ADC
VCC
ADC
AMS 35 FEC
FP FP DD DD V AJ
AK ADC AK
AL ADC ADC ADC AL
AM ADC ADC ADC AM
AN ADC ADC ADC AN
AP ADC AP
AR ADC ADC ADC AR
AT 38 AT
AU AU
AV AV
AW AW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐76: FFVG1517, FSVG1517, FSRG1517 Packages—XCZU48DR, XQZU48DR


209
FFVC1760 Package–XCZU11EG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A 10 12 12 10 11 12 12 16 17 17 S 22 24 21 21 23 24 24 24 20 20 9 9 10 18 18 17 21 21 22 22 A
V C 90
V C 69
B 9 9 10 11 11 10 11 10 11 11 16 18 20 22 24 20 22 23 24 22 22 21 19 8 10 14 14 17 20 20 S 23 23 24 B
C
O
O
VC 91
V C 89
VC 68
VC 71
VC 70
C 6 8 8 7 7 8 12 10 9 15 S 18 20 23 19 20 22 S 23 23 21 19 8 12 12 15 16 S 19 19 24 C
C
O
O
VC 91
VC 69
3
D 4 6 5 5 9 7 8 12 9 8 15 14 19 21 23 19 17 18 S S S 17 17 7 11 13 15 16 D
C
3
O
131
2
E 4 3 3 2 2 9 7 4 7 7 8 13 14 19 21 15 16 17 18 18 14 16 16 7 S 11 13 3
131
3
131
2 E
V C 68
VC 71
V C 70
1
F 1 1 1 5 6 4 5 6 6 13 12 11 10 15 16 14 14 18 14 15 15 5 4 3 3 2 2 F
C
1
O
131 131
VC 90
VC 69
3 0
G 1 5 6 5 2 3 4 7 12 11 10 12 13 13 10 12 13 13 5 4 1 1 G
C
3 0
O
231 131 131
V C 89
3
H 3 3 2 3 1 2 3 4 7 8 9 11 11 12 10 12 11 11 6 2 0 0 H
C
3
O
231 131 130
V C 68
VC 71
V C 70
2 1 2
J 2 2 2 3 1 12 12 11 8 S 9 7 9 10 9 9 8 7 6 1 2 3 3 J
C
2 1 2
O
231 231 131 130 130
1
K 1
231
1 10 10 7 11 5 5 6 7 8 9 10 4 S 8 7 1 2
130
2
130
1 K
V C 88
1 0 0
L 0 0 9 7 8 8 4 6 2 3 8 S 6 4 2 26 28 27 30 1 1 L
C
1 0 0
O
231 231 131 130 130
VC 88
0 3
M 3 3 9 6 6 5 4 3 3 2 3 6 6 6 2 29 31 32 0 0 M
C
0 3
O
231 230 130 129
VC 501
3 1 2
N 2 2 1 1 2 5 4 1 2 1 4 4 5 5 3 3 1 33 35 37 3 3 N
C
3 1 2
O
230 230 130 129 129
2 1
P 2
230
1
230
1 2 3 4 1 2 1 5 5 1 34 40 39 41 2
129
2
129
1 P
1 1 0 0
R 1
230
0
230
0 1
231
3 38 44 43
130
0 1
129
1
129
0 R
0 0 3
T G T
V
0 3 3 0 36 47 45 42 0 0 3
230 229 231 129 128
VC 501
3 1 1 2
U 2 2 EO 46 49 3 3 U
C
3 1 1 2
O
229 229 230 129 128 128
2 0 1
V 2
229
1
229
1 0
230
IN ES 50 48 2
128
2
128
1 V
VC 503
1 1 0 0
W 0 0 PR 52 51 1 1 W
C
1 1 0 0
O
229 229 229 129 128 128
0 0
Y 0
229
3
228
3 0
229
PG DN 54 53 0
128
0 Y
3 1 1 3 3
AA 3
228
2
228
2 1
228
MD MD 56
128
1
505
3
505
3 AA
2 0 0
AB 2
228
1
228
1 0
228
SR MD 55 57
128
0 3
505
3 AB
VC 502
1 1 2 2
AC 0 0 CK RC MD 58 59 61 AC
C
1 1 2 2
O
228 228 227 505 505
VC 503
0 0
AD 3 3 DI MS DO 60 63 62 64 66 13 15 2 2 AD
C
0 0
O
228 227 227 505
3 1 1 1
AE G AE
V
3 2 2 1 PO PI 65 67 69 68 18 19 1 1
227 227 226 505 505
VC 500
2 0
AF 1 1 70 71 72 75 21 1 1 AF
C
2 0
O
227 227 226 505
VC 502
1 1 0 0
AG 0 0 73 77 74 25 23 G AG
C
1 1 0 0
O
227 227 225 505 505
0 0
AH 0
227
3
226
3 0
225
76 22 24 20 0
505
0 AH
3 1
AJ 3
226
2
226
2 1
224
24 20 22 19 23 23 24 24 17 16 14 12 46 44 P 60 AJ
2 0
AK 2
226
1
226
1 0
224
24 20 22 19 22 22 24 23 24 10 11 8 9 47 N 42 43 62 63 61 AK
1
AL 1
226
0
226
0 21 19 23 S 20 S 21 21 23 7 6 5 4 45 DM 40 41 P N DM AL
VC 500
0
AM 3 3 18 17 23 21 19 23 20 19 20 20 22 21 S 15 17 1 3 2 0 RS PA AL 57 56 58 59 AM
C
0
O
226 225
VC 504
3
AN 2 2 18 17 16 23 22 24 21 21 19 16 15 22 21 15 16 17 16 31 30 28 ZQ BA BA 39 36 32 33 AN
C
3
O
225 225
VC 67
VC 66
2
AP 1 1 14 S 16 22 S 24 S 18 17 16 15 20 20 S 16 17 18 19 29 A BG BG A 38 P 35 34 AP
C
2
O
225 225
VC 64
VC 65
VC 504
VC 5 0 4
1
AR 0 0 14 13 13 15 15 17 16 18 17 S 19 14 14 13 18 DM P P DM A A AC 37 DM N 48 AR
C
C
1
O
O
225 225
0
AT 0
225
3
224
3 12 12 11 11 14 18 17 16 14 13 13 19 12 12 13 18 N 20 N 26 A A OD CE 51 49 50 AT
VC 67
VC 504
VC 504
3
AU 2 2 S 8 10 12 14 18 15 14 12 11 7 7 11 11 10 23 21 22 25 27 A A CS DM P N AU
C
C
3
O
O
224 224
V C 66
V C 64
V C 65
2
AV 10 10 8 7 10 12 13 13 15 12 11 8 7 7 8 9 10 0 12 14 15 24 C CN 55 54 53 52 AV
C
2
O
224
VC 504
VC 504
1
AW 1 1 3 1 9 9 7 11 11 3 3 9 9 S 8 1 S 8 9 2 1 3 13 A A A A 71 69 70 68 AW
C
1
O
224 224
VC 67
AY 0 0 3 1 7 5 5 1 10 10 4 2 2 1 3 5 5 DM P P N DM A CS CE P N DM AY
C
O
224
V C 66
V C 64
VC 65
0
BA 5 4 4 9 8 7 6 4 2 1 6 4 3 3 1 3 4 6 N 7 9 10 A C CN A 67 65 66 BA
C
0
O
224
BB 6 6 5 2 2 9 8 6 S 4 2 6 5 5 1 2 2 4 6 6 5 4 8 11 A A A OD 64 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 64 Bank 88 Quad 224 PS Bank 500

Bank 68 Quad 128 Quad 228 PS Bank 504
Bank 69 Quad 129 Quad 229 PS Quad 505
Bank 70 Quad 130 Quad 230

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐77: FFVC1760 Package—XCZU11EG I/O Bank Diagram

210
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A A
B B
C C
D D
E E
F V F
G V G
H E V H
J V J
K V E V K
L V V L
M V E V M
N V V N
V
P V V P
R V V R
T V E V T
V
U V V U
V
V V E V V
V
W V E W
Y V E E Y
AA V E 24 21 E E AA
AB V E 22 23 V AB
AC V E 8 7 V AC
AD V E V AD
AE V PL E AE
AF V E FP PL PL DP E AF
V
AG V FP AU AD DP AU AG
AH V E 13 15 LP AU BT AD AU AH
V
AJ V FP FP LP AD AD AJ
AK V E 33 FP DD LP LP AK
AL V 34 FP FP DD DD AL
AM V 35 AM
AN V AN
AP V AP
AR V AR
AT V AT
AU AU
AV V AV
AW 38 AW
AY AY
BA BA
BB BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐78: FFVC1760 Package—XCZU11EG Power, Dedicated, and Multi-function Pin Diagram

211
FFVC1760 Package–XCZU17EG and XCZU19EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A 10 12 12 10 11 12 12 16 17 17 S 22 24 21 21 23 24 24 24 20 20 9 9 10 18 18 17 21 21 22 22 A
VC 93
V C 69
B 9 9 10 11 11 10 11 10 11 11 16 18 20 22 24 20 22 23 24 22 22 21 19 8 10 14 14 17 20 20 S 23 23 24 B
C
O
O
VC 94
VC 91
VC 68
V C 71
VC 70
C 6 8 8 7 7 8 12 10 9 15 S 18 20 23 19 20 22 S 23 23 21 19 8 12 12 15 16 S 19 19 24 C
C
O
O
VC 94
V C 69
3
D 4 6 5 5 9 7 8 12 9 8 15 14 19 21 23 19 17 18 S S S 17 17 7 11 13 15 16 D
C
3
O
131
2
E 4 3 3 2 2 9 7 4 7 7 8 13 14 19 21 15 16 17 18 18 14 16 16 7 S 11 13 3
131
3
131
2 E
V C 68
VC 71
V C 70
1
F 1 1 1 5 6 4 5 6 6 13 12 11 10 15 16 14 14 18 14 15 15 5 4 3 3 2 2 F
C
1
O
131 131
VC 93
VC 69
3 0
G 1 5 6 5 2 3 4 7 12 11 10 12 13 13 10 12 13 13 5 4 1 1 G
C
3 0
O
231 131 131
V C 91
3
H 3 3 2 3 1 2 3 4 7 8 9 11 11 12 10 12 11 11 6 2 0 0 H
C
3
O
231 131 130
VC 68
V C 71
V C 70
2 1 2
J 2 2 2 3 1 12 12 11 8 S 9 7 9 10 9 9 8 7 6 1 2 3 3 J
C
2 1 2
O
231 231 131 130 130
1
K 1
231
1 10 10 7 11 5 5 6 7 8 9 10 4 S 8 7 1 2
130
2
130
1 K
VC 90
1 0 0
L 0 0 9 7 8 8 4 6 2 3 8 S 6 4 2 26 28 27 30 1 1 L
C
1 0 0
O
231 231 131 130 130
VC 90
0 3
M 3 3 9 6 6 5 4 3 3 2 3 6 6 6 2 29 31 32 0 0 M
C
0 3
O
231 230 130 129
VC 501
3 1 2
N 2 2 1 1 2 5 4 1 2 1 4 4 5 5 3 3 1 33 35 37 3 3 N
C
3 1 2
O
230 230 130 129 129
2 1
P 2
230
1
230
1 2 3 4 1 2 1 5 5 1 34 40 39 41 2
129
2
129
1 P
1 1 0 0
R 1
230
0
230
0 1
231
3 38 44 43
130
0 1
129
1
129
0 R
0 0 3
T G T
V
0 3 3 0 36 47 45 42 0 0 3
230 229 231 129 128
VC 501
3 1 1 2
U 2 2 EO 46 49 3 3 U
C
3 1 1 2
O
229 229 230 129 128 128
2 0 1
V 2
229
1
229
1 0
230
IN ES 50 48 2
128
2
128
1 V
VC 503
1 1 0 0
W 0 0 PR 52 51 1 1 W
C
1 1 0 0
O
229 229 229 129 128 128
0 0
Y 0
229
3
228
3 0
229
PG DN 54 53 0
128
0 Y
3 1 1 3 3
AA 3
228
2
228
2 1
228
MD MD 56
128
1
505
3
505
3 AA
2 0 0
AB 2
228
1
228
1 0
228
SR MD 55 57
128
0 3
505
3 AB
VC 502
1 1 2 2
AC 0 0 CK RC MD 58 59 61 AC
C
1 1 2 2
O
228 228 227 505 505
VC 503
0 0
AD 3 3 DI MS DO 60 63 62 64 66 13 15 2 2 AD
C
0 0
O
228 227 227 505
3 1 1 1
AE G AE
V
3 2 2 1 PO PI 65 67 69 68 18 19 1 1
227 227 226 505 505
VC 500
2 0
AF 1 1 70 71 72 75 21 1 1 AF
C
2 0
O
227 227 226 505
VC 502
1 1 0 0
AG 0 0 73 77 74 25 23 G AG
C
1 1 0 0
O
227 227 225 505 505
0 0
AH 0
227
3
226
3
0
225
76 22 24 20 0
505
0 AH
3 1
AJ 3
226
2
226
2 1
224
24 20 22 19 23 23 24 24 17 16 14 12 46 44 P 60 AJ
2 0
AK 2
226
1
226
1 0
224
24 20 22 19 22 22 24 23 24 10 11 8 9 47 N 42 43 62 63 61 AK
1
AL 1
226
0
226
0 21 19 23 S 20 S 21 21 23 7 6 5 4 45 DM 40 41 P N DM AL
VC 500
0
AM 3 3 18 17 23 21 19 23 20 19 20 20 22 21 S 15 17 1 3 2 0 RS PA AL 57 56 58 59 AM
C
0
O
226 225
VC 504
3
AN 2 2 18 17 16 23 22 24 21 21 19 16 15 22 21 15 16 17 16 31 30 28 ZQ BA BA 39 36 32 33 AN
C
3
O
225 225
V C 67
VC 66
2
AP 1 1 14 S 16 22 S 24 S 18 17 16 15 20 20 S 16 17 18 19 29 A BG BG A 38 P 35 34 AP
C
2
O
225 225
V C 64
V C 65
VC 504
VC 504
1
AR 0 0 14 13 13 15 15 17 16 18 17 S 19 14 14 13 18 DM P P DM A A AC 37 DM N 48 AR
C
C
1
O
O
225 225
0
AT 0
225
3
224
3 12 12 11 11 14 18 17 16 14 13 13 19 12 12 13 18 N 20 N 26 A A OD CE 51 49 50 AT
V C 67
VC 504
VC 5 0 4
3
AU 2 2 S 8 10 12 14 18 15 14 12 11 7 7 11 11 10 23 21 22 25 27 A A CS DM P N AU
C
C
3
O
O
224 224
V C 66
VC 64
VC 65
2
AV 10 10 8 7 10 12 13 13 15 12 11 8 7 7 8 9 10 0 12 14 15 24 C CN 55 54 53 52 AV
C
2
O
224
VC 504
VC 504
1
AW 1 1 3 1 9 9 7 11 11 3 3 9 9 S 8 1 S 8 9 2 1 3 13 A A A A 71 69 70 68 AW
C
1
O
224 224
V C 67
AY 0 0 3 1 7 5 5 1 10 10 4 2 2 1 3 5 5 DM P P N DM A CS CE P N DM AY
C
O
224
VC 66
VC 64
VC 65
0
BA 5 4 4 9 8 7 6 4 2 1 6 4 3 3 1 3 4 6 N 7 9 10 A C CN A 67 65 66 BA
C
0
O
224
BB 6 6 5 2 2 9 8 6 S 4 2 6 5 5 1 2 2 4 6 6 5 4 8 11 A A A OD 64 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐79: FFVC1760 Package—XCZU17EG and XCZU19EG I/O Bank Diagram

212
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A A
B B
C C
D D
E E
F V F
G V G
H E V H
J V J
K V E V K
L V V L
M V E V M
N V V N
V
P V V P
R V V R
T V E V T
V
U V V U
V
V V E V V
V
W V E W
Y V E E Y
AA V E 24 21 E E AA
AB V E 22 23 V AB
AC V E 8 7 V AC
AD V E V AD
AE V PL E AE
AF V E FP PL PL DP E AF
V
AG V FP AU AD DP AU AG
AH V E 13 15 LP AU BT AD AU AH
V
AJ V FP FP LP AD AD AJ
AK V E 33 FP DD LP LP AK
AL V 34 FP FP DD DD AL
AM V 35 AM
AN V AN
AP V AP
AR V AR
AT V AT
AU AU
AV V AV
AW 38 AW
AY AY
BA BA
BB BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐80: FFVC1760 Package—XCZU17EG and XCZU19EG


213
FFVD1760 Package–XCZU17EG and XCZU19EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
3 3
A 3
234
3
234
3 12 12 11 10 10 24 23 23 24 24 23 24 24 23 22 52 53 3
134
3
134
3 A
V C 91
1 2 1 2
B 9 9 8 8 11 24 22 22 21 22 23 21 21 23 22 20 54 55 2 2 B
C
1 2 1 2
O
234 234 134 134 134
VC 71
VC 70
VC 69
0 1
C 2 2 7 6 6 20 20 21 22 20 21 21 19 19 20 56 57 1 1 C
C
0 1
O
234 234 134 134
3 0 0
D 3
233
1
234
1 0
234
0 7 5 5 4 19 19 S 20 19 19 S S 18 18 58 59
134
0 0
134
0
134
0 D
VC 91
VC 502
2 3
E 3 3 3 3 4 S 18 18 S S 17 17 17 17 16 16 60 3 3 E
C
2 3
O
233 233 133 133
VC 71
VC 70
VC 69
1 1 2
F 2 2 1 1 2 1 1 17 16 16 18 18 16 16 15 15 14 61 62 2 2 F
C
1 1 2
O
233 233 233 133 133 133
0 1
G 0
233
0
233
0 12 12 2 17 15 15 14 15 15 14 14 13 14 12 63 64 1
133
1
133
1 G
V C 90
3 0 0
H 2 2 3 3 11 10 10 13 13 14 13 13 12 11 13 11 12 65 66 0 0 H
C
3 0 0
O
232 232 232 133 133 133
V C 71
V C 70
VC 69
2 3
J 1 1 11 9 9 7 12 11 11 10 12 11 9 11 10 10 67 68 3 3 J
C
2 3
O
232 232 132 132
VC 502
1 1 1 2
K 0 0 8 8 7 10 10 12 10 8 8 9 9 9 8 8 69 2 2 K
C
1 1 1 2
O
232 232 234 132 132 132
0 1
L 0
232
3
231
3 6 6 5 5 9 8 7 7 7 S 7 7 S 70 71 1
132
1
132
1 L
VC 90
3 0 0 0
M 2 2 4 9 S 8 7 6 6 5 6 6 72 73 0 0 M
C
3 0 0 0
O
231 231 234 132 132 132
2 1 3
N 2
231
1
231
1 1
233
4 3 6 6 5 5 4 4 5 4 5 5 74 75 3
131
3
131
3 N
1 0 1 2
P 1
231
0
231
0 0
233
2 3 3 4 4 2 3 3 1 4 3 2 2 76 77
131
1 2
131
2
131
2 P
0 1 1
R 0
231
3
230
3 1
232
2 1 1 1 3 2 2 2 1 3 1 1 EO 1
131
1
131
1 R
3 0 0 0
T 3
230
2
230
2 0
232
1 PR ES
131
0 0
131
0
131
0 T
VC 503
2 1 3
U 1 1 PG 3 3 U
C
2 1 3
O
230 230 231 130 130
1 0 1 2
V 1
230
0
230
0
0
231
MD IN
130
1
2
130
2
130
2 V
0 1 1
W 0
230
3
229
3 1
230
SR DN 1
130
1
130
1 W
3 0 0 0
Y 3
229
2
229
2 0
230
MD
130
0 0
130
0
130
0 Y
2 1 3
AA 2
229
1
229
1 1
229
RC MD 3
129
3
129
3 AA
VC 503
1 0 1 2
AB 0 0 MD 2 2 AB
C
1 0 1 2
O
229 229 229 129 129 129
0 1 1
AC G AC
V
0 3 3 1 CK MS 1 1 1
229 228 228 129 129
3 0 0 0
AD 3
228
2
228
2 0
228
DI DO PI
129
0 0
129
0
129
0 AD
2 1 3
AE 2
228
1
228
1 1
227
PO 3
128
3
128
3 AE
1 0 1 2
AF 1
228
0
228
0 0
227 128
1 2
128
2
128
2 AF
0 1 1
AG G AG
V
0 3 3 1 1 1 1
228 227 226 128 128
3 0 0 0
AH 3
227
2
227
2 0
226
24 24 24 23 26 27 28 29 0 1
128
0 0
128
0
128
0 AH
2 1
AJ 2
227
1
227
1 1
225
24 23 22 23 21 30 31 10 11 AJ
1 0 3 3
AK 1
227
0
227
0 0
225
22 23 21 22 21 32 33 34 12 13 G 505
3 3
505
3
505
3 AK
V C 501
0 1 2 2
AL 3 3 22 21 20 20 19 35 36 14 15 16 2 2 AL
C
0 1 2 2
O
227 226 224 505 505 505
VC 500
3 0 1 1
AM 2 2 20 20 S S 19 37 38 39 17 18 19 2 20 1 1 AM
C
3 0 1 1
O
226 226 224 505 505 505
V C 500
2 0 0
AN 1 1 S S 19 19 18 17 17 40 41 21 22 23 24 25 3 0 0 AN
C
2 0 0
O
226 226 505 505 505
VC 66
VC 501
1
AP 0 0 3 3 17 18 18 18 16 16 15 42 43 4 5 6 7 8 9 62 AP
C
1
O
226 226 225

VC 65
VC 504
0
AR 2 2 17 16 16 14 14 15 44 45 46 P 19 24 30 PA BA AL ZQ RS 32 33 34 36 47 46 60 61 63 AR
C
C
0
O
O
226 225
3
AT 3
225
1
225
1 0
225
0 15 15 14 14 13 13 12 47 23 DM N 17 26 31 A A AC BG P N DM 45 44 DM P AT
VC 66
VC 504
VC 504
2
AU 3 3 13 13 12 11 11 12 48 49 22 21 18 P N DM A A A A 38 35 P N 56 59 N AU
C
C
2
O
O
225 224
VC 65
1
AV 2 2 11 11 10 12 9 10 9 9 50 51 20 6 16 27 28 CN A A BA BG 39 37 DM 42 57 58 AV
C
1
O
225 224
VC 504
VC 504
0
AW 1 1 8 8 10 7 9 10 8 8 7 6 7 5 4 25 29 12 C A CE A OD 71 40 41 43 50 48 AW
C
C
0
O
O
225 224
VC 66
3 2
AY S 7 6 6 S 7 5 6 DM P 9 DM 13 CN OD A A CS 67 70 69 52 P DM 49 AY
C
3 2
O
224 224
V C 65
VC 504
VC 504
1
BA 0 0 5 2 4 4 1 4 4 3 5 3 2 N 8 P 14 C A A CS CE DM P N 55 N 51 BA
C
C
1
O
O
224 224
0
BB 0
224
5 2 3 3 1 2 2 3 1 1 1 0 10 11 N 15 A A A A 64 65 66 68 54 53 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Bank 65 Quad 129 Quad 226 Quad 234

Quad 128 Quad 225 Quad 233

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐81: FFVD1760 Package—XCZU17EG and XCZU19EG I/O Bank Diagram

214
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A E V A
B E B
C E V C
D V E D
E V E V E
F V E F
G V V E V G
H V V H
J V E E V J
K V V K
L V E E V L
M V V M
N V E E V N
P V E V P
V
R V E V R
T V E V T
V V
U V V U
V
V V V V
V
W V E V W
Y V E V Y
V
AA V E 24 21 V AA
AB V E 22 23 V AB
AC V E 8 7 V AC
AD V E E AD
V
AE V LP PL BT E V AE
V
AF V LP PL AD AD AU E AF
AG V 13 15 LP PL DP DP AU E V AG
AH V E 33 LP FP AU AU E AH
AJ V E 34 FP FP FP AD AD AJ
AK V E FP FP DD V AK
AL V E FP DD DD E AL
AM V 35 E V AM
AN V E E V AN
AP V AP
AR V V AR
AT V AT
AU V AU
AV V AV
AW AW
AY V 38 AY
BA BA
BB BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐82: FFVD1760 Package—XCZU17EG and XCZU19EG


215
FFVF1760 and FSVF1760 Packages–XCZU29DR and

XCZU39DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A C C 12 12 5 5 11 11 22 24 23 23 24 24 23 23 20 22 24 24 23 28 26 3
131
3 A
228 230
VC 87
3
B C C 11 10 4 4 8 8 22 24 21 21 22 22 21 19 20 22 21 21 23 29 27 B
C
3
O
131
2
C C C 9 11 10 3 7 7 10 20 20 S 19 18 20 21 19 S 17 19 19 35 30 2
131
2
131
2 C
229 231
VC 89
V C 69
1
D S 228 S C C 9 8 2 2 3 10 16 18 18 19 16 18 20 17 18 S 17 34 33 31 32 D
C
1
O
131
VC 8 7
V C 68
VC 67
0
E 7 7 8 1 6 9 9 16 S 17 17 16 S S 17 18 15 13 36 37 1 1 E
C
0
O
131 131
VC 501
3
F 3 231 3 2 231 2 6 6 1 12 12 6 12 14 14 15 12 14 14 15 16 16 15 13 40 0 0 F
C
3
O
131 130
VC 89
VC 69
2
G 4 5 5 10 12 12 12 10 13 15 12 10 15 13 14 14 11 43 38 3 3 G
C
2
O
130 130
VC 88
VC 68
VC 67
1
H 1 231 1 0 231 0 3 3 4 10 11 11 8 10 9 13 11 10 11 11 13 12 12 11 42 2 2 H
C
1
O
131 130
VC 88
VC 501
1
J 2 2 9 9 8 8 8 9 11 8 S 9 8 10 10 9 46 39 1 1 J
C
1
O
130 130
V C 69
0
K 3 230 3 2 230 2 1 1 6 6 7 7 S 7 7 8 9 6 8 S 9 44 49 41 0 0 K
C
0
O
131 130
V C 68
VC 67
0
L 5 5 4 6 5 7 7 6 7 7 45 47 3 3 L
C
0
O
129 130
1
M 1 230 1 0 230 0 3 2 1 4 6 5 3 6 6 4 3 5 5 50 51 48
130
1 2
129
2 M
VC 503
3
N 3 2 1 4 3 3 3 5 5 4 3 54 56 53 DN 1 1 N
C
3
O
129 129
0
P 3 229 3 2 229 2 2 4 1 2 4 1 52 55 IN PG
130
0 0
129
0 P
VC 502
2
R 2 1 1 1 2 4 2 2 1 57 58 SR PR 3 3 R
C
2
O
128 129
1
T 1 229 1 0 229 0 61 63 59 CK
129
1 2
128
2 T
1
U R 60 64 DI RC 1
128
1
129
1 U
0
V 3 228 3 2 228 2 62 66 65 DO
129
0 0
128
0 V
VC 502
0
W G W
V
67 69 MS PI
C
0
O
129
1 3
Y 1 228 1 0 228 0 68 74 MD PO
128
1
128
3 Y
0 2
AA 70 73 77 MD
128
0
128
2 AA
3 1
AB 71 76 MD MD
505
3
128
1 AB
VC 503
2 0
AC 3 227 3 2 227 2 72 75 EO ES AC
C
2 0
O
505 128
1
AD 505
1 AD
3
AE 1 227 1 0 227 0 3
505
3
505
3 AE
0
AF R 505
0 2
505
2 AF
2
AG 3 226 3 2 226 2 1
505
1
505
2 AG
1
AH V 227 V V 225 V 22 24 24 23 24 0
505
0 G 505
1 AH
0
AJ 1 226 1 0 226 0 V 226 V V 224 V 24 20 22 23 19 23 24 22 505
0 AJ
V C 66
AK 24 23 23 20 19 21 21 19 23 21 22 38 P 36 33 32 43 AK
C
O
VC 500
AL 3 225 3 2 225 2 20 22 18 18 19 S S 17 20 21 C
O
22 24 39 37 N 34 41 44 DM 42 47 AL
VC 65
AM 20 22 21 S 16 17 17 S 17 20 16 23 25 16 18 BA PA BG DM 35 40 P N 46 AM
C
O
V C 66
AN 1 225 1 0 225 0 18 S 21 19 16 15 13 13 15 18 18 16 21 DM 19 17 A A AC BG BA 62 63 61 45 AN
C
O
VC 64
VC 66
AP 12 12 11 18 S 19 14 14 15 11 13 15 14 12 20 18 P 28 31 30 A A A A DM P 60 AP
C
C
O
O
VC 65
VC 500
VC 504
VC 504
AR 3 224 3 2 224 2 10 11 9 16 17 17 15 12 12 11 13 14 10 12 19 22 N 29 DM OD AL ZQ RS 57 56 N 59 AR
C
C
O
O
VC 84
VC 65
AT 10 9 12 16 14 15 8 10 10 9 11 11 10 15 17 23 21 P N A CS A 53 51 P 58 AT
C
C
O
O
VC 64
VC 504
VC 504
AU 1 224 1 0 224 0 7 8 8 12 14 13 13 8 9 9 9 7 8 13 14 16 20 24 25 26 C A A 54 N 50 48 AU
C
C
O
O
VC 64
VC 500
AV 6 7 5 8 10 11 11 4 6 S 7 6 8 10 12 3 2 0 27 15 CN CE 55 52 DM 49 AV
C
C
O
O
VC 84
VC 504
VC 504
AW C C 6 5 S 8 10 9 9 4 6 7 S 6 9 8 11 4 1 12 14 13 A A CE 70 69 71 AW
C
C
O
O
225 227
AY C C 3 4 4 6 6 7 7 3 5 7 5 4 4 6 7 DM P N DM P CN C A DM P N 67 AY
VC 504
BA C C 3 2 3 3 5 5 2 2 3 5 5 3 3 2 1 4 5 6 8 11 N A
C
O
A CS 64 66 68 BA
224 226
BB C C 2 1 1 1 1 4 4 2 2 1 1 1 1 2 2 0 3 7 5 9 10 A OD A A 65 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Bank 66 Quad 128 Bank 228 PS Bank 504
Bank 67 Quad 129 Bank 229 PS Quad 505

#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐83: FFVF1760 and FSVF1760 Packages—XCZU29DR and XCZU39DR I/O Bank Diagram

216
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A DAC DAC DAC DAC A
B DAC DAC DAC DAC DAC V B
C DAC DAC DAC DAC DAC C
D DAC DAC DAC V D
E DAC DAC DAC DAC DAC DAC DAC E
F DAC DAC DAC V F
G DAC DAC DAC DAC DAC DAC DAC E G
H DAC DAC DAC V H
J DAC DAC DAC DAC DAC DAC DAC E V J
K DAC DAC DAC DAC DAC E K
L DAC DAC DAC DAC DAC DAC DAC DAC DAC E V L
M DAC DAC DAC DAC DAC DAC DAC DAC E M
V
N DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC V N
DAC DAC DAC DAC VCC
P DAC DAC AUX AUX AUX AUX DAC DAC AMS E P
DAC DAC DAC DAC DAC
V
R DAC DAC DAC DAC DAC DAC AUX AUX AUX AUX DAC SUB V R
VCC
T DAC DAC DAC DAC DAC DAC DAC DAC AMS E T
DAC DAC DAC DAC
U DAC DAC DAC DAC DAC DAC VTT VTT VCC VCC DAC E V U
DAC DAC DAC DAC VCC
V DAC DAC VTT VTT DAC VCC VCC DAC AMS V
DAC DAC DAC DAC
W DAC DAC DAC DAC DAC DAC VTT VTT DAC VCC VCC DAC E W
DAC DAC DAC DAC VCC
Y DAC DAC VTT VTT DAC VCC VCC DAC AMS Y
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC 24 21 AA
VCC
AB ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AMS 22 23 AB
ADC ADC ADC ADC
AC ADC ADC AUX AUX ADC VCC VCC ADC 8 7 E AC
ADC ADC ADC ADC VCC
AD ADC ADC ADC ADC ADC ADC
AUX AUX
ADC
VCC VCC
ADC
AMS
AU AU AU AU V AD
ADC ADC ADC ADC
AE ADC ADC AUX AUX ADC VCC VCC ADC BT AD AD PL E V AE
ADC ADC ADC ADC VCC
AF ADC ADC ADC ADC ADC ADC AUX AUX VCC VCC ADC AMS FP DP DP AD PL V AF
ADC
AG ADC ADC ADC ADC ADC ADC ADC SUB FP LP AD PL PL E AG
VCC
AH ADC ADC ADC ADC ADC ADC ADC ADC AMS 13 15 35 34 33 FP LP LP LP AH
AJ ADC ADC ADC ADC FP FP FP LP LP AJ
VCC
AK ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AMS FP DD DD DD DD AK
AL ADC ADC ADC ADC ADC ADC ADC DD DD DD AL
AM ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AM
AN ADC ADC ADC ADC AN
AP ADC ADC ADC ADC ADC ADC ADC ADC AP
AR ADC ADC ADC ADC AR
AT ADC ADC ADC ADC ADC ADC ADC ADC AT
AU ADC ADC ADC AU
AV ADC ADC ADC ADC ADC ADC ADC 38 AV
AW ADC ADC ADC ADC ADC AW
AY ADC ADC ADC ADC ADC AY
BA ADC ADC ADC ADC ADC BA
BB ADC ADC ADC ADC BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐84: FFVF1760 and FSVF1760 Packages—XCZU29DR and XCZU39DR


217
FFVF1760 and FSVF1760 Packages–XCZU49DR

FSRF1760 Package–XQZU49DR
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A C C 12 12 5 5 11 11 22 24 23 23 24 24 23 23 20 22 24 24 23 28 26 3 3 A
228 230 131
VC 87
3
B C C 11 10 4 4 8 8 22 24 21 21 22 22 21 19 20 22 21 21 23 29 27 B
C
3
O
131
2
C C C 9 11 10 3 7 7 10 20 20 S 19 18 20 21 19 S 17 19 19 35 30 2 2
2 C
229 231 131 131
VC 89
VC 69
1
D S S C C 9 8 2 2 3 10 16 18 18 19 16 18 20 17 18 S 17 34 33 31 32 D
C
1
O
228 131
VC 87
VC 68
VC 67
0
E 7 7 8 1 6 9 9 16 S 17 17 16 S S 17 18 15 13 36 37 1 1 E
C
0
O
131 131
VC 501
3
F 3 3 2 2 6 6 1 12 12 6 12 14 14 15 12 14 14 15 16 16 15 13 40 0 0 F
C
3
O
231 231 131 130
VC 89
VC 69
2
G 4 5 5 10 12 12 12 10 13 15 12 10 15 13 14 14 11 43 38 3 3 G
C
2
O
130 130
VC 88
VC 68
VC 67
1
H 1 1 0 0 3 3 4 10 11 11 8 10 9 13 11 10 11 11 13 12 12 11 42 2 2 H
C
1
O
231 231 131 130
VC 88
VC 501
1
J 2 2 9 9 8 8 8 9 11 8 S 9 8 10 10 9 46 39 1 1 J
C
1
O
130 130
VC 69
0
K 3 3 2 2 1 1 6 6 7 7 S 7 7 8 9 6 8 S 9 44 49 41 0 0 K
C
0
O
230 230 131 130
VC 68
VC 67
0
L 5 5 4 6 5 7 7 6 7 7 45 47 3 3 L
C
0
O
129 130
1
M 1 1 0 0 3 2 1 4 6 5 3 6 6 4 3 5 5 50 51 48 1
2 2 M
230 230 130 129
VC 503
3
N 3 2 1 4 3 3 3 5 5 4 3 54 56 53 DN 1 1 N
C
3
O
129 129
0
P 3 3 2 2 2 4 1 2 4 1 52 55 IN PG
0
0 0 P
229 229 130 129
VC 502
2
R 2 1 1 1 2 4 2 2 1 57 58 SR PR 3 3 R
C
2
O
128 129
1
T 1 1 0 0 61 63 59 CK
1
2 2 T
229 229 129 128
1
U R 60 64 DI RC 1 1
1 U
128 129
0
V 3 3 2 2 62 66 65 DO
0
0 0 V
228 228 129 128
VC 502
0
W 67 69 G W
V
MS PI
C
0
O
129
1 3
Y 1 1 0 0 68 74 MD PO
1 3 Y
228 228 128 128
0 2
AA 70 73 77 MD
0 2 AA
128 128
3 1
AB 71 76 MD MD
3 1 AB
505 128
VC 503
2 0
AC 3 3 2 2 72 75 EO ES AC
C
2 0
O
227 227 505 128
1
AD 1 AD
505
3
AE 1 1 0 0 3 3
3 AE
227 227 505 505
0
AF R 0
2 2 AF
505 505
2
AG 3 3 2 2 1 1
2 AG
226 226 505 505
1
AH V V V V 22 24 24 23 24 0 0 G 1 AH
227 225 505 505
0
AJ 1 1 0 0 V V V V 24 20 22 23 19 23 24 22 0 AJ
226 226 226 224 505
VC 66
AK 24 23 23 20 19 21 21 19 23 21 22 38 P 36 33 32 43 AK
C
O
VC 500
AL 3 3 2 2 20 22 18 18 19 S S 17 20 21 22 24 39 37 N 34 41 44 DM 42 47 AL
C
O
225 225
VC 65
AM 20 22 21 S 16 17 17 S 17 20 16 23 25 16 18 BA PA BG DM 35 40 P N 46 AM
C
O
VC 66
AN 1 1 0 0 18 S 21 19 16 15 13 13 15 18 18 16 21 DM 19 17 A A AC BG BA 62 63 61 45 AN
C
O
225 225
VC 64
VC 66
AP 12 12 11 18 S 19 14 14 15 11 13 15 14 12 20 18 P 28 31 30 A A A A DM P 60 AP
C
C
O
O
VC 65
VC 500
VC 504
VC 504
AR 3 3 2 2 10 11 9 16 17 17 15 12 12 11 13 14 10 12 19 22 N 29 DM OD AL ZQ RS 57 56 N 59 AR
C
C
O
O
224 224
VC 84
VC 65
AT 10 9 12 16 14 15 8 10 10 9 11 11 10 15 17 23 21 P N A CS A 53 51 P 58 AT
C
C
O
O
VC 64
VC 504
VC 504
AU 1 1 0 0 7 8 8 12 14 13 13 8 9 9 9 7 8 13 14 16 20 24 25 26 C A A 54 N 50 48 AU
C
C
O
O
224 224
VC 64
VC 500
AV 6 7 5 8 10 11 11 4 6 S 7 6 8 10 12 3 2 0 27 15 CN CE 55 52 DM 49 AV
C
C
O
O
VC 84
VC 504
VC 504
AW C C 6 5 S 8 10 9 9 4 6 7 S 6 9 8 11 4 1 12 14 13 A A CE 70 69 71 AW
C
C
O
O
225 227
AY C C 3 4 4 6 6 7 7 3 5 7 5 4 4 6 7 DM P N DM P CN C A DM P N 67 AY
VC 504
BA C C 3 2 3 3 5 5 2 2 3 5 5 3 3 2 1 4 5 6 8 11 N A A CS 64 66 68 BA
C
O
224 226
BB C C 2 1 1 1 1 4 4 2 2 1 1 1 1 2 2 0 3 7 5 9 10 A OD A A 65 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐85: FFVF1760, FSVF1760, FSRF1760 Packages—XCZU49DR, XQZU49DR

I/O Bank Diagram

218
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A DAC DAC DAC DAC A
B DAC DAC DAC DAC DAC V B
C DAC DAC DAC DAC DAC C
D DAC DAC DAC V D
E DAC DAC DAC DAC DAC DAC DAC E
F DAC DAC DAC V F
G DAC DAC DAC DAC DAC DAC DAC E G
H DAC DAC DAC V H
J DAC DAC DAC DAC DAC DAC DAC E V J
K DAC DAC DAC DAC DAC E K
L DAC DAC DAC DAC DAC DAC DAC DAC DAC E V L
M DAC DAC DAC DAC DAC DAC DAC DAC E M
V
N DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC V N
DAC DAC DAC DAC VCC
P DAC DAC
AUX AUX AUX AUX
DAC DAC
AMS E P
DAC DAC DAC DAC DAC V
R DAC DAC DAC DAC DAC DAC
AUX AUX AUX AUX
DAC
SUB V R
VCC
T DAC DAC DAC DAC DAC DAC DAC DAC
AMS E T
DAC DAC DAC DAC
U DAC DAC DAC DAC DAC DAC
VTT VTT VCC VCC
DAC E V U
DAC DAC DAC DAC VCC
V DAC DAC
VTT VTT
DAC
VCC VCC
DAC
AMS V
DAC DAC DAC DAC
W DAC DAC DAC DAC DAC DAC
VTT VTT
DAC
VCC VCC
DAC E W
DAC DAC DAC DAC VCC
Y DAC DAC
VTT VTT
DAC
VCC VCC
DAC
AMS Y
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC 24 21 AA
VCC
AMS 22 23 AB
ADC ADC ADC ADC
AC ADC ADC
AUX AUX
ADC
VCC VCC
ADC 8 7 E AC
ADC ADC ADC ADC VCC
AD ADC ADC ADC ADC ADC ADC
AUX AUX
ADC
VCC VCC
ADC
AMS
AU AU AU AU V AD
ADC ADC ADC ADC
AE ADC ADC
AUX AUX
ADC
VCC VCC
ADC BT AD AD PL E V AE
ADC ADC ADC ADC VCC
AF ADC ADC ADC ADC ADC ADC
AUX AUX VCC VCC
ADC
AMS
FP DP DP AD PL V AF
ADC
AG ADC ADC ADC ADC ADC ADC ADC
SUB
FP LP AD PL E AG
VCC
AH ADC ADC ADC ADC ADC ADC ADC ADC AMS 13 15 35 34 33 FP LP LP LP AH
AJ ADC ADC ADC ADC FP FP FP LP LP AJ
VCC
AK ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC
AMS
FP DD DD DD DD AK
AL ADC ADC ADC ADC ADC ADC ADC DD DD DD AL
AM ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC AM
AN ADC ADC ADC ADC AN
AP ADC ADC ADC ADC ADC ADC ADC ADC AP
AR ADC ADC ADC ADC AR
AT ADC ADC ADC ADC ADC ADC ADC ADC AT
AU ADC ADC ADC AU
AV ADC ADC ADC ADC ADC ADC ADC 38 AV
AW ADC ADC ADC ADC ADC AW
AY ADC ADC ADC ADC ADC AY
BA ADC ADC ADC ADC ADC BA
BB ADC ADC ADC ADC BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐86: FFVF1760, FSVF1760, FSRF1760 Packages—XCZU49DR, XQZU49DR


219
FFVH1760 and FSVH1760 Packages–XCZU46DR

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A 12 12 11 11 9 9 22 24 23 23 24 24 23 23 20 22 24 24 23 28 26 3 3 A
131
VC 91
3
B 8 10 10 5 7 7 22 24 21 19 22 22 21 19 20 22 21 21 23 29 B
C
3
O
131
2
C 6 6 8 5 3 3 1 S 17 21 19 18 20 21 19 S 17 19 19 27 30 2 2
2 C
131 131
VC 91
VC 70
1
D 4 4 2 2 1 20 20 17 16 S 18 20 18 18 S 17 34 33 31 32 D
C
1
O
131
VC 71
VC 69
0
E 10 12 12 18 18 15 15 16 S 17 17 14 16 15 13 35 36 1 1 E
C
0
O
131 131
VC 501
1
F 2 2 10 11 11 8 16 16 S 13 14 15 15 14 16 12 15 13 37 0 0 F
C
1
O
231 131 131
VC 90
VC 70
3
G S S 9 9 8 12 14 14 13 12 14 13 8 10 10 12 9 40 38 3 3 G
C
3
O
228 130 130
VC 71
VC 69
0
H 0 0 6 7 7 12 9 11 11 12 13 11 8 S 11 9 42 43 2 2 H
C
0
O
231 131 130
VC 501
2
J 6 5 10 10 9 7 10 10 11 9 6 11 7 46 39 1 1 J
C
2
O
130 130
VC 90
VC 70
1 1
K 0 0 2 2 4 5 8 8 S 7 8 S 9 4 6 3 7 44 49 41 K
C
1 1
O
230 230 130 130
VC 71
VC 69
0
L 4 3 6 5 8 7 5 5 4 3 5 5 45 47 0 0 L
C
0
O
130 130
0 3
M 3 3 2 3 4 6 5 6 7 4 2 1 1 50 51 48 0 3 M
229 130 129
VC 502
2
N 2 2 2 1 4 3 3 6 3 4 2 77 75 73 72 3 3 N
C
2
O
229 129 129
1
P 1 1 1 2 1 3 2 76 74 71 70 1
2 2 P
229 129 129
1
R 2 1 1 1 2 66 67 68 69 1 1
1 R
129 129
0
T 3 3 0 0 65 64 63 0
0 0 T
228 229 129 129
0
U R 60 61 62 3 3
0 U
128 129
VC 502
1 3
V 2 2 59 58 57 V
C
1 3
O
228 128 128
2
W 1 1 54 55 56 2 2
2 W
228 128 128
0 1
Y 0 0 53 52 ES EO
0 1 Y
228 128 128
0
AA PG SR DN 1 1
0 AA
128 128
VC 503
AB G AB
V
IN CK DI 0 0
C
O
128
VC 503
3
AC 3 3 MD RC DO AC
C
3
O
227 505
3
AD 1 1 MD MS PI PO
3
3 3 AD
227 505 505
2 2
AE 3 3 MD MD
2 2 AE
226 505 505
1
AF R PR
1
2 2 AF
505 505
1
AG 1 1 3 3 1 1
1 AG
226 225 505 505
0
AH V V 24 24 0 G 0 0 AH
227 505 505
0
AJ 1 1 V V 24 22 20 23 0 AJ
225 226 505
AK 2 2 V V 24 23 23 22 20 23 21 24 P 36 33 32 43 44 AK
225 225
VC 65
AL 0 0 V V 21 21 18 S S 21 23 24 22 22 39 37 N 34 41 42 DM 47 46 AL
C
O
225 224
VC 64
AM 22 19 18 16 19 19 23 21 20 22 24 25 16 PA 38 DM BG 35 40 P N 45 AM
C
O
VC 66
AN 3 3 2 2 22 19 17 16 14 17 17 21 18 20 23 21 19 18 BA A A AC BG BA 62 63 61 AN
C
O
224 224
VC 65
AP 20 17 12 12 14 15 19 19 18 20 18 19 DM 17 31 30 A A A A 56 P 60 AP
C
O
VC 64
VC 500
VC 504
VC 504
AR 1 1 18 18 20 15 15 10 13 15 S S 16 16 17 16 P N 29 28 OD AL ZQ RS 57 DM N 59 AR
C
C
O
O
224
VC 66
AT S 16 S 13 13 10 11 13 13 17 17 14 14 15 14 23 22 P N A CS A 53 51 P 58 AT
C
O
VC 65
VC 66
VC 504
VC 504
AU 0 0 12 16 14 11 11 8 11 13 15 15 12 10 13 12 11 21 25 DM 26 C A A 54 N 50 48 AU
C
C
O
O
224
VC 64
VC 500
AV 12 14 9 9 8 9 9 11 11 12 8 10 10 9 3 20 24 27 15 CN CE 55 52 DM 49 AV
C
C
O
VC 504
VC 504
AW 8 10 10 7 7 6 S 7 7 9 9 8 8 7 6 2 0 12 14 DM C A A 70 69 71 AW
C
O
O
AY 8 6 S 3 4 6 5 7 5 7 S 6 6 5 4 P N 1 13 P CN CE A DM P N 67 AY
VC 504
BA 4 6 5 5 3 4 5 3 3 5 4 4 2 3 2 DM 6 8 11 N A A CS 64 66 68 BA
C
O
BB 4 2 2 1 1 2 2 1 1 3 3 1 1 2 1 0 4 7 5 9 10 A OD A A 65 BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42


#
#
V
A DO

PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐87: FFVH1760 and FSVH1760 Packages—XCZU49DR I/O Bank Diagram

220
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
A DAC DAC DAC DAC DAC DAC A
B DAC DAC DAC DAC DAC DAC DAC B
C DAC DAC DAC DAC DAC DAC DAC C
D DAC DAC DAC DAC DAC DAC DAC E D
E DAC DAC DAC DAC DAC DAC DAC DAC E
F DAC DAC DAC DAC DAC DAC DAC DAC E F
G DAC DAC DAC DAC DAC DAC DAC DAC E V G
H DAC DAC DAC DAC DAC DAC DAC DAC V H
J DAC DAC DAC DAC DAC DAC DAC DAC DAC E J
K DAC DAC DAC DAC DAC DAC DAC V K
DAC
L DAC DAC DAC DAC DAC DAC DAC
AUX
DAC E L
DAC
M DAC DAC DAC DAC DAC DAC DAC
AUX
DAC DAC V M
DAC DAC VCC VCC V
N DAC DAC DAC DAC DAC
AUX AUX
DAC
AMS FEC N
DAC DAC VCC VCC
P DAC DAC DAC DAC DAC DAC DAC
AUX AUX
DAC
AMS FEC V P
DAC DAC DAC VCC V
R DAC DAC DAC DAC DAC DAC DAC
AUX AUX SUB FEC V R
VCC VCC
T DAC DAC DAC DAC DAC DAC DAC DAC
AMS FEC V T
DAC DAC DAC DAC VCC VCC
U DAC DAC DAC DAC DAC DAC
VTT VTT VCC VCC
DAC
AMS FEC E U
DAC DAC DAC DAC VCC
V DAC DAC DAC DAC
VTT VTT
DAC
VCC VCC
DAC
FEC V V
W DAC DAC DAC DAC
VTT VTT
DAC
VCC VCC
DAC
AMS FEC E W
Y DAC DAC DAC DAC
VTT VTT
DAC
VCC VCC
DAC
AMS FEC V Y
VCC
AA DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC DAC 24 21 FEC AA
VCC VCC
AMS 22 23 FEC AB
ADC ADC ADC ADC VCC VCC
AC ADC ADC ADC ADC
AUX AUX
ADC
VCC VCC
ADC
AMS 8 7 FEC AC
ADC ADC ADC ADC VCC
AD ADC ADC ADC ADC
AUX AUX
ADC
VCC VCC
ADC
FEC E AD
AE ADC ADC ADC ADC
AUX AUX
ADC
VCC VCC
ADC
AMS FEC
DP DP E V AE
AF ADC ADC ADC ADC ADC ADC
AUX AUX VCC VCC
ADC
AMS FEC
PL AD AD V AF
ADC VCC
AG ADC ADC ADC ADC ADC ADC ADC
SUB FEC
BT PL PL AD AD AU E V AG
VCC VCC
AH ADC ADC ADC ADC ADC ADC ADC ADC
AMS 13 15 FEC
LP LP FP AU AH
VCC VCC
AJ ADC ADC ADC ADC ADC ADC ADC ADC
AMS 34 FEC
LP LP LP FP AU AU AJ
VCC
AK ADC ADC ADC ADC ADC ADC 35 33 FEC LP FP FP FP DD AK
AL ADC ADC ADC ADC ADC ADC ADC ADC FP FP FP DD DD AL
AM ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC DD AM
AN ADC ADC ADC ADC ADC ADC ADC ADC AN
AP ADC ADC ADC ADC ADC ADC ADC AP
AR ADC ADC ADC ADC ADC ADC ADC AR
AT ADC ADC ADC ADC ADC ADC ADC AT
AU ADC ADC ADC ADC ADC ADC ADC AU
AV ADC ADC ADC ADC ADC ADC ADC ADC AV
AW ADC ADC ADC ADC ADC ADC ADC AW
AY ADC ADC ADC ADC ADC ADC ADC AY
BA ADC ADC ADC ADC ADC ADC ADC 38 BA
BB ADC ADC ADC ADC ADC ADC BB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

VCC
VCC
ADC
ADC
ADC
DAC
DAC
DAC
DAC
R RSVDGND n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐88: FFVH1760 and FSVH1760 Packages—XCZU49DR


221
FFVE1924 Package–XCZU17EG and XCZU19EG

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A 3 3 4 4 6 12 12 12 12 10 10 22 22 24 23 23 24 24 24 23 23 17 17 18 24 23 23 22 17 S A
VC 94
V C 93
3
B 2 5 6 8 11 11 11 9 9 21 21 23 24 21 24 22 22 21 21 19 15 18 24 21 21 22 17 24 S B
C
3
O
234
VC 94
1 2
C 2 5 8 11 8 8 7 7 20 20 19 23 19 21 22 22 20 20 19 15 16 16 19 19 20 16 24 23 23 C
C
1 2
O
234 234
VC 72
0
D 1 1 7 7 6 6 5 5 17 S S 19 19 S 20 20 S S 18 18 14 14 S S 20 16 15 22 21 21 D
C
0
O
234
VC 93
VC 73
VC 74
VC 71
3
E 3 3 9 9 10 4 2 2 1 17 16 18 18 S 18 18 17 17 16 16 13 13 11 12 12 14 15 22 20 20 E
C
3
O
233 234
2
F 2
233
2
234
2 10 4 3 3 1 15 15 16 14 17 17 15 15 15 14 14 10 10 9 11 12 14 13 13 19 18 18 F
V C 72
VC 70
1 1
G 1 1 12 12 11 11 11 13 13 14 14 15 16 13 11 12 12 7 9 8 8 12 11 11 10 19 24 G
C
1 1
O
233 234 234
V C 91
V C 73
V C 74
VC 71
0 0
H 0 0 9 10 10 10 11 12 12 14 13 16 13 11 9 10 7 S 8 8 9 9 10 23 23 24 H
C
0 0
O
233 234 234
VC 71
3 1
J 3 3 9 8 8 10 9 9 8 11 13 12 12 7 9 8 10 6 6 6 6 S 7 7 20 22 22 J
C
3 1
O
232 233 233
VC 72
VC 70
2 0
K 2 2 5 7 7 6 6 7 8 9 11 10 10 S 7 8 4 4 3 4 5 5 19 20 21 21 K
C
2 0
O
232 233 233
VC 73
VC 74
VC 70
1 1
L 1 1 5 3 4 4 S 7 9 8 8 7 5 6 6 3 5 5 4 3 12 12 19 S 18 18 L
C
1 1
O
232 233 232
VC 91
0 0
M 0 0 1 3 2 2 3 6 6 5 7 S 5 4 4 2 2 1 2 2 3 11 14 14 S 17 M
C
0 0
O
232 233 232
VC 90
3
N 2 2 3 3 1 12 12 11 3 5 5 5 3 6 3 3 1 1 1 9 9 11 13 15 16 16 17 N
C
3
O
231 232 232
VC 69
2 1
P 1 1 9 10 10 11 1 4 4 1 3 2 6 2 2 1 5 8 8 10 13 15 9 5 5 P
C
2 1
O
231 232 231
VC 69
1
R 0 0 3 3 9 8 8 7 7 1 2 2 1 2 4 4 1 3 3 5 S 7 7 10 12 9 S 4 R
C
1
O
231 232 231
VC 9 0
V C 69
0 0
T 2 2 6 6 5 5 1 4 4 6 6 15 13 13 12 4 2 T
C
0 0
O
231 231 231
VC 68
3
U 0 0 1 1 4 4 3 3 1 2 2 19 18 18 15 11 8 8 6 2 U
C
3
O
230 231 231
VC 68
2 1
V 3 3 1 2 2 22 22 19 17 17 14 11 7 6 3 1 V
C
2 1
O
230 230 230
VC 68
1
W 1 1 2 2 1 24 23 21 21 16 16 14 10 10 7 3 1 W
C
1
O
230 230 230
VC 67
0 0
Y 0 0 24 23 20 20 S S 13 13 9 S 6 Y
C
0 0
O
230 230 230
VC 67
3
AA 2 2 3 3 22 22 S S 14 12 12 9 5 6 4 AA
C
3
O
229 229 229
VC 67
2 1
AB 1 1 23 23 20 18 18 14 11 8 8 5 4 AB
C
2 1
O
229 229 229
1
AC 1
229
3
228
3 0
229
0 24 21 21 20 16 16 15 11 7 3 3 2 AC
0 0
AD 0
229
2
228
2 0
229
CK MD EO ES 28 24 19 19 17 17 15 10 10 7 1 2 AD
VC 503
VC 501
3
AE 0 0 1 1 PR MD MD 30 29 31 26 33 32 52 53 55 58 60 1 AE
C
3
O
228 228 228
VC 501
VC 502
2 1
AF 3 3 PG MD MS DI 27 40 39 37 34 54 56 57 61 66 67 69 AF
C
2 1
O
228 227 228
VC 503
VC 501
VC 502
VC 502
1
AG 1 1 2 2 SR RC PI 47 46 50 35 38 36 59 63 62 64 65 68 AG
C
1
O
228 227 227
0 0
AH 0
228
0
227
0 0
228
DN IN DO PO 48 51 45 44 42 41 70 71 72 75 73 77 74 76 AH
3
AJ 3
227
2
226
2 3
226
3 43 49 AJ
2 1 3 3
AK 2
227
1
226
1 1
227
24 24 24 19
505
3 G 3
505
3
505
3 AK
1 0 2 2
AL G 24 24 21 23 23 24 23 23 AL
V
1 0 0 0 21 13 2 2 2 2
227 226 227 505 505 505
0 1 1 1
AM 0
227
3
225
3 1
226
23 23 22 21 22 22 22 22 18 15
505
1 1
505
1
505
1 AM
3 0 0 0
AN 3
226
2
225
2 0
226
21 22 19 19 20 20 21 21 23
505
0 0
505
0
505
0 AN
VC 65
2 1
AP 1 1 21 20 19 18 20 S 20 19 19 14 AP
C
2 1
O
226 225 225

VC 66
VC 5 0 0
1 0
AR 0 0 20 19 17 18 S 18 18 S 16 20 22 20 29 30 31 ZQ 38 36 32 33 47 46 62 63 AR
C
1 0
O
226 225 225

VC 64
0 1
AT 3 3 S S 17 15 15 16 15 S 17 17 23 21 P 28 DM RS AL 37 P 34 45 44 60 61 P AT
C
0 1
O
226 224 224

VC 65
3 0
AU 2 2 18 16 16 13 14 16 16 15 17 25 22 DM N P N 26 BG 39 DM N P N DM DM N AU
C
3 0
O
225 224 224

VC 66
VC 500
VC 504
2
AV 1 1 17 17 18 15 13 12 14 16 14 14 13 24 19 17 16 25 27 A BA PA BA 35 43 42 57 56 59 AV
C
C
2
O
O
225 224
VC 66
VC 64
VC 504
VC 504
1
AW 0 0 12 12 14 13 13 15 12 11 12 12 11 13 1 12 18 0 14 24 A BG A A 40 41 53 52 48 58 AW
C
C
1
O
O
225 224
VC 65
VC 504
3
AY 9 10 11 11 14 9 9 10 11 10 10 9 11 4 10 3 2 13 15 A A AC A CE OD 54 DM P 50 AY
C
C
3
O
O
224
VC 500
0 2
BA 9 8 10 7 7 7 7 10 8 8 8 9 7 7 3 11 1 P 12 DM A A C A CS 67 55 N 51 49 BA
C
0 2
O
225 224
VC 64
VC 504
1
BB 8 6 6 S 5 5 S S 8 5 5 1 2 7 8 N P N 11 A A CN OD 66 DM 70 71 BB
C
1
O
224
VC 504
VC 504
BC 1 3 3 2 5 3 3 6 6 2 6 3 3 1 6 9 DM 7 8 10 A A C A CE 65 68 69 BC
C
C
O
O
0
BD 0
224
1 2 4 4 5 1 1 4 4 2 2 2 6 4 4 0 5 6 5 4 9 A A A CN CS 64 P N BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Bank 64 Bank 72 Quad 225 Quad 233

Bank 65 Bank 73 Quad 226 Quad 234

#
V
# # EO

#
PA PS_DDR_PARITY
RS PS_DDR_RAM_RST_N
ZQ PS_DDR_ZQ
Figure 4‐89: FFVE1924 Package—XCZU17EG and XCZU19EG I/O Bank Diagram

222
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A A
B B
C C
D D
E E
F V F
G V G
H V E H
J V E J
K V E K
L V E L
M V E M
N V E N
P V V P
R V E R
T V V T
U V E U
V V V V
V
W V W
Y V V Y
V
AA V AA
AB V V 24 21 AB
V
AC V 22 23 AC
AD V V 8 7 AD
V
AE V AE
AF V V AF
AG V E AG
AH V V AH
AJ V E PL PL DP AU AU AJ
AK V E 13 15 FP PL DP AD AU AK
AL V 34 33 FP BT AD AU AD E V AL
AM V E FP FP LP AD LP E AM
AN V E FP LP FP LP LP V AN
AP V E 35 FP DD DD DD LP AP
AR V E AR
AT V E AT
AU V AU
AV V AV
AW AW
AY AY
BA BA
BB 38 BB
BC BC
BD BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

n NC
E MGTAVCC_[R or L]
V MGTAVTT_[R or L]
V
MGTVCCAUX_[R or L]
Figure 4‐90: FFVE1924 Package—XCZU17EG and XCZU19EG


223
Chapter 5
Mechanical Drawings
Summary
This chapter provides mechanical drawings (package specifications) of the Zynq®
UltraScale+™ devices. Table 5-1 and Table 5-2 cross-reference to the mechanical drawings
by device and package combination. See Package Specifications Designations in Chapter 3
for definitions of Evaluation Only, Engineering Sample, and Production mechanical
drawings.
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q. For the
mechanical drawings, refer to the Pb-free version of these packages.
TIP: For information on materials composition and weight of a device, refer to the material declaration
data sheet (MDDS). MDDS files: Click on this link to find the Zynq UltraScale+ devices Packaging
Specifications. In step 2 select the product category: SoCs, MPSoCs & RFSoCs. In step 3, select the
product type. In step 4, click on the package specifications selection to find the available MDDS files. All
published MDDS files are also available on the See All Package Specifications page.

224
Table 5‐1: Cross-Reference to Zynq UltraScale+ MPSoC Mechanical Drawings by Package

Device
XCZU5CG XCZU7CG
XCZU3CG XCZU4CG
Package XCZU1CG
XCZU2CG
XCZU3EG XCZU4EG
XCZU5EG
XCZU6CG
XCZU7EG XCZU9CG XCZU11EG XCZU15EG
XCZU1EG
XCZU2EG
XAZU3EG XCZU4EV XCZU5EV XCZU6EG XCZU7EV XCZU9EG XAZU11EG XQZU15EG XCZU17EG XCZU19EG
XQZU19EG
XAZU2EG XQZU3EG XAZU4EV XAZU5EV XAZU7EV XQZU9EG XQZU11EG XQZU15EG
XQZU5EV XQZU7EV
Figure 5-2 Figure 5-2
SBVA484
Figure 5-3
SFRA484
Production
Figure 5-4
UBVA494 Engineering
Sample

UBVA530
SFVA625

SFRC784
Figure 5-9
SFVC784
Production
FBVB900

FFRB900

FFRC900
Figure 5-14 Figure 5-14 Figure 5-14
FFVC900

FFRB1156

Table 5‐1: Cross-Reference to Zynq UltraScale+ MPSoC Mechanical Drawings by Package (Cont’d)

Device
XCZU5CG XCZU7CG
XCZU3CG XCZU4CG
Package XCZU1CG
XCZU2CG
XCZU3EG XCZU4EG
XCZU5EG
XCZU6CG
XCZU7EG XCZU9CG XCZU11EG XCZU15EG XCZU19EG
XCZU1EG XCZU2EG XAZU3EG
XCZU5EV XCZU7EV XCZU9EG XAZU11EG XQZU15EG XCZU17EG
XAZU2EG XCZU4EV XAZU5EV
XCZU6EG
XAZU7EV XQZU9EG XQZU11EG XQZU15EG XQZU19EG
XQZU3EG XAZU4EV XQZU5EV XQZU7EV
FFVB1156

FFRC1156
FFVC1156
Figure 5-24
FFRB1517
Production
FFVB1517

FFVF1517

FFRC1760
FFVC1760
Figure 5-30
FFVD1760
Production
Figure 5-36
FFVE1924
Production

Table 5‐2: Cross-Reference to Zynq UltraScale+ RFSoC Mechanical Drawings by Package

Device
Package XCZU21DR XCZU25DR XCZU28DR XCZU29DR XCZU39DR XCZU42DR XCZU43DR XCZU46DR XCZU47DR
XCZU48DR XCZU49DR XCZU65DR XCZU67DR
XQZU21DR XCZU27DR XQZU28DR XQZU29DR XQZU49DR
XQZU48DR
Figure 5-19
FFRD1156
Production
Figure 5-21
FFVD1156
Production
Figure 5-20
FFRE1156
Production
Figure 5-21 Figure 5-21 Figure 5-21 Figure 5-21 Figure 5-21 Figure 5-21 Figure 5-21
FFVE1156
Figure 5-22 Figure 5-22 Figure 5-22 Figure 5-22 Figure 5-22 Figure 5-22 Figure 5-22
FSVE1156
Figure 5-26
FFRG1517
Production
Figure 5-27 Figure 5-27 Figure 5-27 Figure 5-27
FFVG1517
Production Production Production Production
Figure 5-28
FSRG1517
Production
Figure 5-29 Figure 5-29 Figure 5-29 Figure 5-29
FSVG1517
Production Production Production Production
Figure 5-33
FFRF1760
Production
FFVF1760
Figure 5-35
FSRF1760
Production

Table 5‐2: Cross-Reference to Zynq UltraScale+ RFSoC Mechanical Drawings by Package (Cont’d)

Device
Package XCZU21DR XCZU25DR XCZU28DR XCZU29DR
XCZU47DR
XCZU49DR
XQZU21DR XCZU27DR XQZU28DR XQZU29DR XCZU39DR XCZU42DR XCZU43DR XCZU46DR XCZU48DR XQZU49DR XCZU65DR XCZU67DR
XQZU48DR
FSVF1760
Figure 5-32
FFVH1760
Production
Figure 5-34
FSVH1760
Production

Table 5‐3: Mechanical Drawing Dimension Definitions

Dimension Definition
⌓ Bilateral tolerance of package sides with respect to datums A and B
⏥ Flatness tolerance of silicon die or package lid top surface
Bilateral tolerance for parallelism of silicon die or package lid top surface with respect to
//
the seating plane datum C
A Thickness of package with respect to the seating plane datum C
A1 Thickness of BGA balls with respect to the seating plane datum C
A2 Thickness of package body, including stiffener ring or lid and excluding BGA balls, with
respect to the seating plane datum C
A3 Distance from top of silicon die to top of stiffener ring or lid with respect to the seating
plane datum C
D/E Length/width of package with respect to datums A and B
D1/E1 Length/width of BGA matrix with respect to datums A and B
e BGA ball pitch measured at the center of each ball
øb BGA ball diameter
⌓aaa Unidirectional upward tolerance with respect to the seating plane datum C
/ / bbb Bilateral tolerance for parallelism of package surface with respect to the seating plane
datum C
øddd BGA ball position tolerance of diameter ddd with respect to datums A and B perpendicular
to the seating plane datum C in which the center of each ball must lie
øeee BGA ball position tolerance of diameter eee measured with respect to other balls within
the BGA matrix in which the center of each ball must lie
M BGA ball matrix size

229
SBVA484 Flip-Chip, Fine-Pitch BGA (XCZU1CG and

XCZU1EG)
Figure 5‐1: Package Dimensions for SBVA484 (XCZU1CG and XCZU1EG)

230
SBVA484 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3,

XAZU2EG, and XAZU3EG)
ug1075_c5_112918
Figure 5‐2: Package Dimensions for SBVA484 (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)

231
SFRA484 Flip-Chip, Fine-Pitch BGA (XQZU3EG)

ug1085_c5_061419
Figure 5‐3: Package Dimensions for SFRA484 (XQZU3EG)

232
UBVA494 Flip-Chip, Fine-Pitch BGA (XCZU1)

Figure 5‐4: Package Dimensions for UBVA494 (XCZU1)

233
UBVA530 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3)

Figure 5‐5: Package Dimensions for UBVA530 (XCZU2, XCZU3)
IMPORTANT: The weight for the UBVA530 is 0.2 grams.

234
SFVA625 Flip-Chip, Fine-Pitch BGA (XCZU1CG and

XCZU1EG)
Figure 5‐6: Package Dimensions for SFVA625 (XCZU1CG, and XCZU1EG)

235
SFVA625 Flip-Chip, Fine-Pitch BGA (XCZU2, XCZU3,

XAZU2EG, and XAZU3EG)
ug1075_c5_073116
Figure 5‐7: Package Dimensions for SFVA625 (XCZU2, XCZU3, XAZU2EG, and XAZU3EG)

236
SFRC784 Ruggedized Flip-Chip BGA (XQZU3EG and

XQZU5EV)
ug1075_c5_121918
Figure 5‐8: Package Dimensions for SFRC784 (XQZU3EG and XQZU5EV)

237
SFVC784 Flip-Chip, Fine-Pitch BGA (XCZU1, XCZU2,

XAZU2EG, XCZU3, XAZU3EG, XCZU4, XAZU4EV,
XCZU5, and XAZU5EV)
ug1075_c5_073117
Figure 5‐9: Package Dimensions for SFVC784 (XCZU1, XCZU2, XAZU2EG, XCZU3, XAZU3EG, XCZU4,
XAZU4EV, XCZU5, and XAZU5EV)

238
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU4CG,

XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, and
XCZU5EV)
ug1075_c5_120717
Figure 5‐10: Package Dimensions for FBVB900

(XCZU4CG, XCZU4EG, XCZU4EV, XCZU5CG, XCZU5EG, and XCZU5EV)

239
FBVB900 Flip-Chip, Fine-Pitch BGA (XCZU7CG,

XCZU7EG, XCZU7EV, and XAZU7EV)
ug1075_c5_073117
Figure 5‐11: Package Dimensions for FBVB900 (XCZU7CG, XCZU7EG, XCZU7EV, and XAZU7EV)

240

FFRB900 (XQZU7EV) Ruggedized Flip-Chip BGA
ug1075_c5_080818
Figure 5‐12: Package Dimensions for FFRB900 (XQZU7EV)

241
FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and

XQZU15EG) Ruggedized Flip-Chip BGA
ug1075_c5_100318
Figure 5‐13: Package Dimensions for FFRB900 (XQZU5EV) and FFRC900 (XQZU9EG and XQZU15EG)

242
FFVC900 Flip-Chip, Fine-Pitch BGA (XCZU6CG,

XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG)
ug1075_c5_073116
Figure 5‐14: Package Dimensions for FFVC900 (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and
XCZU15EG)

243
FFRB1156 Ruggedized Flip-Chip BGA (XQZU9EG and

XQZU15EG)
ug1075_c5_100318
Figure 5‐15: Package Dimensions for FFRB1156 (XQZU9EG and XQZU15EG)

244
FFVB1156 Flip-Chip, Fine-Pitch BGA (XCZU6CG,

XCZU6EG, XCZU9CG, XCZU9EG, and XCZU15EG)
ug1075_c5_073116
Figure 5‐16: Package Dimensions for FFVB1156 (XCZU6CG, XCZU6EG, XCZU9CG, XCZU9EG, and
XCZU15EG)

245
FFRC1156 Ruggedized Flip-Chip BGA (XQZU7EV and

XQZU11EG)
ug1075_c5_100318
Figure 5‐17: Package Dimensions for FFRC1156 (XQZU7EV and XQZU11EG)

246
FFVC1156 Flip-Chip, Fine-Pitch BGA

(XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG)
ug1075_c5_073116
Figure 5‐18: Package Dimensions for FFVC1156 (XCZU7CG, XCZU7EG, XCZU7EV, and XCZU11EG)

247
FFRD1156 (XQZU21DR) Ruggedized Flip-Chip BGA

ug1085_c5_061419
Figure 5‐19: Package Dimensions for FFRD1156 (XQZU21DR)

248
FFRE1156 (XQZU28DR) Ruggedized Flip-Chip BGA

ug1085_c5_061419
Figure 5‐20: Package Dimensions for FFRE1156 (XQZU28DR)

249
FFVD1156 (XCZU21DR) and FFVE1156

(XCZU25DR–XCZU27DR, XCZU42DR–XCZU48DR,
XCZU65DR–XCZU67DR) Flip-Chip, Fine-Pitch BGA
Figure 5‐21: Package Dimensions for FFVE1156 (XCZU21DR) and FFVE1156 (XCZU25DR, XCZU27DR,
XCZU28DR, XCZU42DR, XCZU43DR, XCZU47DR, XCZU48DR, XCZU65DR, XCZU67DR)

250
FSVE1156 (XCZU25DR, XCZU27DR, XCZU28DR,

XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip,
Fine-Pitch, Lidless w/Stiffener Ring BGA
ug1075_c5_032821
Figure 5‐22: Package Dimensions for FSVE1156 (XCZU25DR, XCZU27DR, XCZU28DR, XCZU43DR,

XCZU47DR, XCZU48DR)

251
FSVE1156 (XCZU42DR, XCZU65DR, XCZU67DR)

Flip-Chip, Fine-Pitch, Lidless w/Stiffener Ring BGA
Figure 5‐23: Package Dimensions for FSVE1156 (XCZU42DR, XCZU65DR, XCZU67DR)

252
FFRB1517 (XQZU19EG) Ruggedized Flip-Chip BGA

ug1085_c5_061419
Figure 5‐24: Package Dimensions for FFRB1517 (XQZU19EG)

253
FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and

FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV, XCZU11EG,
and XAZU11EG) Flip-Chip, Fine-Pitch BGA
ug1075_c5_073117
Figure 5‐25: Package Dimensions for FFVB1517 (XCZU11EG, XCZU17EG, and XCZU19EG) and
FFVF1517 (XCZU7CG, XCZU7EG, XCZU7EV, XCZU11EG, and XAZU11EG)

254
FFRG1517 (XQZU28DR) Ruggedized Flip-Chip BGA

ug1085_c5_061419
Figure 5‐26: Package Dimensions for FFRG1517 (XQZU28DR)

255
FFVG1517 (XCZU25DR, XCZU27DR, XCZU28DR,

XCZU43DR, XCZU47DR, XCZU48DR)
Flip-Chip, Fine-Pitch BGA
ug1075_ffvg1517_040120
Figure 5‐27: Package Dimensions for FFVG1517 (XCZU25DR, XCZU27DR, XCZU28DR,


256
FSRG1517 (XQZU48DR) Ruggedized Flip Chip,

Lidless with Stiffener Ring BGA
Figure 5‐28: Package Dimensions for FSRG1517 (XQZU48DR)

257
FSVG1517 (XCZU25DR, XCZU27DR, XCZU28DR,

XCZU43DR, XCZU47DR, XCZU48DR) Flip-Chip,
Fine-Pitch, Lidless with Stiffener Ring BGA
ug1075_c5_032821
Figure 5‐29: Package Dimensions for FSVG1517 (XCZU25DR, XCZU27DR, XCZU28DR,


258
FFVC1760 and FFVD1760 Flip-Chip, Fine-Pitch BGA

(XCZU11EG, XCZU17EG, and XCZU19EG)
ug1075_c5_073116
Figure 5‐30: Package Dimensions for FFVC1760 and FFVD1760 (XCZU11EG, XCZU17EG, and XCZU19EG)

259
FFRC1760 Ruggedized Flip-Chip BGA

(XQZU11EG and XQZU19EG)
ug1085_c5_061419
Figure 5‐31: Package Dimensions for FFRC1760 (XQZU11EG and XQZU19EG)

260
FFVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and

FFVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch BGA
ug1075_c5_040120
Figure 5‐32: Package Dimensions for FFVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and

FFVH1760 (XCZU46DR)

261
FFRF1760 (XQZU29DR) Ruggedized Flip-Chip BGA

ug1085_c5_061419
Figure 5‐33: Package Dimensions for FFRF1760 (XQZU29DR)

262
FSVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and

FSVH1760 (XCZU46DR) Flip-Chip, Fine-Pitch, Lidless
with Stiffener Ring BGA
ug1075_c5_010421
Figure 5‐34: Package Dimensions for FSVF1760 (XCZU29DR, XCZU39DR, XCZU49DR) and

FSVH1760 (XCZU46DR)

263
FSRF1760 (XQZU49DR) Ruggedized Flip Chip, Lidless

with Stiffener Ring BGA
Figure 5‐35: Package Dimensions for FSRF1760 (XQZU49DR)

264
FFVE1924 Flip-Chip, Fine-Pitch BGA (XCZU17EG,

and XCZU19EG)
ug1075_c5_073117
Figure 5‐36: Package Dimensions for FFVE1924 (XCZU17EG and XCZU19EG)

265
Chapter 6
Package Marking
Introduction
The package top-markings for the XC and XA Zynq® UltraScale+™ devices are similar to the
examples shown in Figure 6-1 and Figure 6-2. In addition to the markings explained in
Table 6-1, refer to the FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+
Products (XTP424) [Ref 17] and (XTP544) [Ref 18].
The package top-markings for the XQ Zynq UltraScale+ devices are as shown in Figure 6-3.
On XQ products only the Xilinx logo and the 2D bar code are marked.
ug1075_c6_032920
Figure 6‐1: XC and XA Zynq UltraScale+ Devices Package Marking

266
Device Type
Package Mask Code
2D Bar Code
XILINX ®
ZYNQ ®
UltraScale+ TM
TM
Device Type XCZU9EG
Package FFVB1156xxxXXXX Date Code
DxxxxxxA Lot Code

Speed Grade 1E ES9839 Engineering Sample
Operating Range
Country of Origin
ug1075_ch6_01_121517
Figure 6‐2: XC and XA Zynq UltraScale+ Devices Package Marking

267
ug1075_c6_121918
Figure 6‐3: XQ Zynq UltraScale+ Devices Package Marking
Table 6‐1: XC and XA Device Marking Definition—Example

Item Definition
Xilinx Logo Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Family Device family name with trademark and trademark-registered status. This line is optional and could
Brand Logo appear blank.
1st Line Device name. This line is not marked on some devices. Refer to the bar code for more information.
2nd Line This line is not marked on some devices. Refer to the bar code for more information.
• Package code: FF
1st digit: F for flip-chip BGA, S for flip-chip BGA with 0.8 mm ball pitch.
2nd digit: F for lidded, B for bare-die.
• 3rd digit: Pb-free code: V for RoHS 6/6, R or Q for packages with eutectic BGA balls.
All Zynq UltraScale+ devices are available with Pb-free RoHS compliant packaging. For more
details on Xilinx Pb-free and RoHS compliant products, see: www.xilinx.com/pbfree.
• 4th digit: This is the pin out (net list) identifier.
• 5th–8th digits: These are the physical pin count identifiers: B1156 is shown in the Figure 6-2
example marking drawing. Example: A package code of FFVB1517 and FFVF1517 means they
have a different pinout (net list) but the same physical ball count and physical dimensions.
• Three letter circuit design revision, the location code for the wafer fab, and the geometry code
(xxx).
• When marked, the date code: YYWW. This code is not marked on some devices. Refer to the bar
code for more information.

268
Table 6‐1: XC and XA Device Marking Definition—Example (Cont’d)

Item Definition
3rd Line When marked, this line describes ten alphanumeric characters for assembly location, 7-digit lot
number, and step information. The last digit is usually an A or an M if a stepping version does not
exist.
This line is not marked on some devices. Refer to the bar code for more information.
4th Line When marked, this line describes the device speed grade (1) and temperature operating range (E).
When not marked on the package, the product is considered to operate at the extended (E)
temperature range. If a bar code is present on the device, the 4th line might be blank or unmarked.
In this case, refer to the bar code for speed grade and temperature range information. For more
information on the ordering codes, see the Zynq UltraScale+ MPSoC Overview (DS891) [Ref 1].
Other variations for the 4th line:
L1I The L1I indicates a -1LI device. The -1LI speed grade offers reduced maximum power
consumption. For more information, see the Zynq UltraScale+ MPSoC data sheet
[Ref 8].
1E xxxx The xxxx indicates a 4-digit SCD device option. An SCD is a special ordering code
that is not always marked in the device top mark.
1E ES The addition of an ES after the operating temperature range code indicates an
2I ES engineering sample.
L1I ES
Bar Code A device-specific bar code is marked on each device. Refer to the FAQ: Top Marking Change for 7
Series, UltraScale, and UltraScale+ Products (XTP424) [Ref 17].

269
Chapter 7
Packing and Shipping
Introduction
Zynq® UltraScale+™ devices are packed in trays. Trays are used to pack most of Xilinx
surface-mount devices since they provide excellent protection from mechanical damage. In
addition, they are manufactured using antistatic material to provide limited protection
against ESD damage and can withstand a bake temperature of 125°C.
Table 7‐1: Standard Device Counts per Tray and Box
Package Maximum Number of Maximum Number of

Devices Per Tray Units In One Internal Box
SBVA484, SFRA484 84 420
UBVA494
UBVA530 126 630
SFVA625 60 300
SFVC784, SFRC784 60 300
FBVB900, FFVC900, FFRB900, FFRC900 27 135
FFVB1156, FFRB1156, FFVC1156, FFRC1156
24 120
FFVD1156, FFRD1156, FFVE1156, FFRE1156
FSVE1156 24 72
FFVB1517, FFRB1517, FFVF1517 21 105
FFVG1517, FFRG1517 21 63
FSVG1517, FSRG1517 21 63
FFVC1760, FFRC1760
12 60
FFVD1760, FFVF1760, FFVH1760, FFRF1760
FSVF1760, FSVH1760, FSRF1760 12 36
FFVE1924 12 36
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example:
FFQE1156).

270
Chapter 8
Soldering Guidelines
Soldering Guidelines
To implement and control the production of surface-mount assemblies, the dynamics of the
solder reflow process and how each element of the process is related to the end result must
be thoroughly understood.
RECOMMENDED: Xilinx recommends that customers qualify their custom PCB assembly processes
using package samples.
The primary phases of the reflow process are:
• Melting the particles in the solder paste

• Wetting the surfaces to be joined
• Solidifying the solder into a strong metallurgical bond
The peak reflow temperature of a surface-mount component body should not be more than
250°C maximum (260°C for dry rework only) for Pb-free packages and 220°C for eutectic
packages, and is package size dependent. For multiple BGAs in a single board and because
of surrounding component differences, Xilinx recommends checking all BGA sites for
varying temperatures.
The infrared reflow (IR) process is strongly dependent on equipment and loading.
Components might overheat due to lack of thermal constraints. Unbalanced loading can
lead to significant temperature variation on the board. These guidelines are intended to
assist users in avoiding damage to the components; the actual profile should be
determined by those using these guidelines. For complete information on package
moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC
Standard J-STD-020C.
IMPORTANT: Following the initial placement and reflow process, devices should not be reflowed more
than two additional times and should not be removed from the board. Any additional rework beyond
that is likely to cause irreparable damage to the device.

271
Sn/Pb Reflow Soldering

Figure 8-1 shows typical conditions for solder reflow processing of Sn/Pb soldering using
IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture
sensitivity of surface-mount components must be verified prior to surface-mount flow.
TMAX (body) = 220°C

TMAX (leads) = 235°C
Temperature (°C) 2–3°C/s Ramp down

1–3°C/s
T = 183°C
t183
60s < t183< 120s

Preheat & drying dwell
applies to lead area
120–180 s between
95–180°C (Note 2)
<1°C/s
Time (s)
ug1075_c7_02_111218
Figure 8‐1: Typical Conditions for IR Reflow Soldering of Sn/Pb Solder

Notes for Figure 8-1:
1. Maximum temperature range = 220°C (body). Minimum temperature range before

205°C (leads/balls).
2. Preheat dwell 95–180°C for 120–180 seconds.
3. IR reflow must be performed on dry packages.

272
Pb-Free Reflow Soldering

Xilinx uses SnAgCu solder balls for commercial-grade (XC) and automotive-grade (XA) BGA
packages. In addition, suitable package materials are qualified for the higher reflow
temperatures (250°C maximum, 260°C for dry rework only) required by Pb-free soldering
processes.
Xilinx does not support soldering SnAgCu BGA packages with SnPb solder paste using a
Sn/Pb soldering process. Traditional Sn/Pb soldering processes have a peak reflow
temperature of 220°C. At this temperature range, the SnAgCu BGA solder balls do not
properly melt and wet to the soldering surfaces. As a result, reliability and assembly yields
can be compromised.
The optimal profile must take into account the solder paste/flux used, the size of the board,
the density of the components on the board, and the mix between large components and
smaller, lighter components. Profiles should be established for all new board designs using
thermocouples at multiple locations on the component. In addition, if there is a mixture of
devices on the board, then the profile should be checked at various locations on the board.
Ensure that the minimum reflow temperature is reached to reflow the larger components
and at the same time, the temperature does not exceed the threshold temperature that
might damage the smaller, heat sensitive components.
Table 8-1 and Figure 8-2 provide guidelines for profiling Pb-free solder reflow of 0.8 mm
and 1.0 mm pitch packages. InFo package guidelines are listed in a separate Table 8-2. In
general, a gradual, linear ramp into a spike has been shown by various sources to be the
optimal reflow profile for Pb-free solders (Figure 8-2). This profile has been shown to yield
better wetting and less thermal shock than conventional ramp-soak-spike profile for the
Sn/Pb system. SnAgCu alloy reaches full liquidus temperature at 235°C. When profiling,
identify the possible locations of the coldest solder joints and ensure that those solder
joints reach a minimum peak temperature of 235°C for at least 10 seconds. Reflowing at
high peak temperatures of 260°C and above can damage the heat sensitive components
and cause the board to warp. Users should reference the latest IPC/JEDEC J-STD-020
standard for the allowable peak temperature on the component body. The allowable peak
temperature on the component body is dependent on the size of the component. Refer to
Table 8-3 for peak package reflow body temperature information. In any case, use a reflow
profile with the lowest peak temperature possible.
Table 8‐1: Pb-Free Reflow Soldering Guidelines

Profile Feature Convection, IR/Convection
Ramp-up rate 2°C/s maximum. 1°C/s maximum for lidless packages with
stiffener ring.
Preheat temperature 150°–200°C 60–120 seconds.
Temperature maintained above 217°C 60–150 seconds (60–90 seconds typical).
Time within 5°C of actual peak temperature 30 seconds maximum.

273
Table 8‐1: Pb-Free Reflow Soldering Guidelines (Cont’d)

Peak temperature (lead/ball) 230°C—245°C typical (depends on solder paste, board
size, component mixture).
Peak temperature (body) 240°C—250°C, package body size dependent.
Ramp-down rate 2°C/s maximum.
Time 25°C to peak temperature 3.5 minutes minimum, 5.0 minutes typical, 8 minutes
maximum.
Tbody (MAX) = 240–250°C (package type dependent)

See data sheet for maximum value by package type
Tlead (MIN) = 230–245°C (10s minimum)
217°C Ramp down 2°C/s max

Temperature (°C)
t 217
Wetting time = 60–150 s
150–200°C
Ramp up 2°C/s maximum
1°C/s maximum for lidless packages
with stiffener ring
Preheating
60–120s
Time (s)
ug1075_c7_01_022818
Figure 8‐2: Typical Conditions for Pb-Free Reflow Soldering
Table 8‐2: InFO Package Reflow Soldering Guidelines

Ramp-up rate 4°C/s maximum
Preheat temperature 150°–190°C 60–100 seconds
Temperature maintained above 217°C 45–75 seconds
Time within 5°C of actual peak temperature 30 seconds maximum
Peak temperature (lead/ball) 230°C—235°C typical (depends on solder paste, board
size, component mixture)
Peak temperature (body) 240°C—245°C
Ramp-down rate 2°C/s maximum.
Time 25°C to peak temperature 3.5 minutes minimum, 5.0 minutes typical, 8 minutes
maximum.

274
Peak Package Reflow Temperatures

Table 8‐3: Peak Package Reflow Body Temperature (Based on J-STD-020 Standard)
Product Peak Package Reflow JEDEC Moisture Sensitivity
Package Category Body Temperature Level (MSL)
SBVA484 XC 4
Mass reflow: 250°C
SFVA625
XA Dry rework: 260°C 3
SFVC784
UBVA494
UBVA530
FBVB900, FFVC900
FFVB1156, FFVC1156
Mass reflow: 245°C
FFVD1156, FFVE1156 All 4
Dry rework: 260°C
FFVB1517, FFVF1517, FFVG1517
FFVC1760, FFVD1760, FFVF1760,
FFVH1760
FFVE1924
FSVE1156
Mass reflow: 240°C
FSVG1517 All 4
Dry rework: 260°C
FSVF1760, FSVH1760
SFRA484, SFRC784
FFRB900, FFRC900
FFRB1156, FFRC1156 Mass reflow: 220°C
XQ (1) 4
FFRD1156, FFRE1156 Dry rework: 235°C
FFRB1517, FFRG1517, FSRG1517
FFRC1760, FFRF1760, FSRF1760
Notes:
1. For devices with the Pb-free signifier in the package name (labeled as Q vs. V) use the temperatures and MSL
listed for the XQ product category.
For sophisticated boards with a substantial mix of large and small components, it is critical
to minimize the T across the board (<10°C) to minimize board warpage and thus, attain
higher assembly yields. Minimizing the T is accomplished by using a slower rate in the
warm-up and preheating stages. Xilinx recommends a heating rate of less than 1°C/s during
the preheating and soaking stages, in combination with a heating rate of not more than
3°C/s throughout the rest of the profile.
It is also important to minimize the temperature gradient on the component, between top
surface and bottom side, especially during the cooling down phase. The key is to optimize
cooling while maintaining a minimal temperature differential between the top surface of
the package and the solder joint area. The temperature differential between the top surface
of the component and the solder balls should be maintained at less than 7°C during the
critical region of the cooling phase of the reflow process. This critical region is in the part of
the cooling phase where the balls are not completely solidified to the board yet, usually

275
between the 200°C–217°C range. To efficiently cool the parts, divide the cooling section
into multiple zones, with each zone operating at different temperatures.
The optimal profile must take into account the solder paste/flux used, the size of the board,
the density of the components on the board, and the mix between large components and
smaller, lighter components. Profiles should be established for all new board designs using
thermocouples at multiple locations on the component. In addition, if there is a mixture of
devices on the board, then the profile should be checked at various locations on the board,
as shown in Figure 8-3 and Figure 8-4. Ensure that the minimum reflow temperature is
reached to reflow the larger components and at the same time, the temperature does not
exceed the threshold temperature that might damage the smaller, heat sensitive
components.
Figure 8‐3: Thermocouple Top

276
Figure 8‐4: Thermocouple Bottom
Post Reflow/Cleaning/Washing
Many PCB assembly subcontractors use a no-clean process in which no post-assembly
washing is required. Although a no-clean process is recommended, if cleaning is required,
Xilinx recommends a water-soluble paste and a washer using a deionized-water. Baking
after the water wash is recommended to prevent fluid accumulation.
Cleaning solutions or solvents are not recommended because some solutions contain
chemicals that can compromise the lid adhesive, thermal compound, or components inside
the package.
Conformal Coating
Xilinx does not have information regarding the reliability of flip-chip BGA packages on a
board after exposure to any specific conformal coating process. Therefore, any process
using conformal coating should be qualified for the specific use case to cover the materials
and process steps.
Ruggedized XQ packages are designed to support conformal coating, with vented lids that
ensure proper cleaning can occur after the etching process and prior to conformal coating.
RECOMMENDED: When a conformal coating is required, Parylene-based material should be used to

avoid potential risk of weakening the lid or stiffener ring adhesive used in Xilinx packages.

277
Strain Gauge Measurement

Strain gauge measurements are recommended to be done at each process step that has the
potential to cause excessive board flexing leading to solder joint cracking. Assembly
processes where strain gauge measurements are recommended include:
• PCB Router (during PCB loading/unloading into fixture and during the routing process)
• PTH solder assembly during top-catch loading/unloading
• Press fit assembly during press base and tooling loading/unloading and during
machine pressing process
• DIMM memory (during PCB loading/unloading and during insertion/removal of DIMM)
• Heat-sink assembly process (during PCB loading/unloading and during entire screw
assembly process)
• X-ray fixture (during PCBA loading/unloading)
Strain gauge measurements should be in the range of ±500 µstrain. Dye and pry analysis is
required to confirm if the measured strain causes solder joint cracking. It is recommended
to conduct dye and pry analysis for any strain reading greater than 500 µstrain.
To reduce the affects of strain on a device, edge bonding can be used and is recommended
for larger packages. See Edge Bonding Guidelines for implementation details.

278
Solder Paste
Solder paste consists of solder alloy and a flux system. A typical solder paste composition
by volume is split between about 50% alloy and 50% flux. The metal load mass (solder alloy
powder) is around 90%, with the remaining 10% mass a flux system. The primary purpose of
the flux system is to remove the contaminations from the solder joints during the soldering
process. The capability of removing contaminations is determined by the activation level of
the type of solder paste. The preferred solder paste metal alloy has a lead-free composition
(SnAgCu where Ag is 3–4% and Cu is 0.5–1%). A no-clean solder paste is preferred to
eliminate any risk of improper cleaning that could leave active residue beneath the device
and other BTC components. The paste must be suitable for printing the solder stencil
aperture dimensions. Type 4 paste is recommended for better paste release performance.
When using a solder paste, you must adhere to the handling recommendations of the paste
manufacturer.
Component Placement
IMPORTANT: The following component placement guidelines apply to all package types included in
this guide (lidded, lidless, bare-die, etc.).
Xilinx device packages must be placed accurately according to their geometry outline.
Positioning packages manually via hand mounting is not recommended.
Typical component placement accuracies of ±50  m can be achieved using standard pick
and placement machine equipment with vision system. The PCB and the components are
optically checked and measured and the components are placed on the PCB in specific
programmed positions based on the PCB CAD information. The pick and placement
machine vision system detects the fiducials on the PCB immediately prior to mounting the
FPGA. Recognition of the packages is performed by the vision system, to ensure correct
centering of the FPGA placement on the PCB pad array.
BGA packages with solder balls can self-align during the reflow process because of the
solder high surface tension that enables the pulling and centering of the device, and where
a slight offset of the placement is still allowed. For guidance, the maximum tolerable offset
of device placement is around 30% of the pad diameter on the PCB for typical non-solder
mask defined pads. This means that for device packages the solder ball to PCB pad
misalignment must be better than 150  m to assure a robust mounting process. Generally,
this is achievable using a wide range of modern pick and placement systems. The following
setup conditions are important for the pick and placement systems:

279
• The pick and placement nozzle type should be sized to the dimensions of the Xilinx
device. The nozzle needs to firmly hold the device package during the pick and
placement stage. The appropriate nozzle type for the device package can be chosen
from the manual provided by the pick and placement equipment company.
• The ball recognition capabilities of the placement system should be used and package
outline centering should be avoided. This eliminates the solder ball to package edge
tolerances of the package. Refer to the specific package outline drawing for details.
• To ensure the proper identification of the device package by the vision system, a
suitable lighting system and the correct choice of the features of the measuring
method are essential. The most suitable settings can be chosen from the manual
provided by the pick and placement equipments company.
• To avoid solder bridging or solder smear, ensure the proper placement force of the
device package during placement on the PCB. Excessive placement force can lead to
excess solder paste and cause solder bridging. However, a slight placement force can
lead to insufficient solder paste contact between the device package solder balls and
the solder paste, causing solder defects including open solder joints, badly centered
packages, or even head-in-pillow (HIP) defects.

280
Chapter 9
Recommended PCB Design Rules for BGA

Packages
BGA Packages
Xilinx provides the diameter of a land pad on the package side. This information is required
prior to the start of the board layout so the board pads can be designed to match the
component-side land geometry. The typical values of these land pads are described in
Figure 9-1 and summarized in Table 9-1 for 1.0 mm pitch packages. For Xilinx BGA
packages, non-solder mask defined (NSMD) pads on the board are suggested to allow a
clearance between the land metal (diameter L) and the solder mask opening (diameter M)
as shown in Figure 9-1. An example of an NSMD PCB pad solder joint is shown in Figure 9-2.
It is recommended to have the board land pad diameter with a 1:1 ratio to the package
solder mask defined (SMD) pad for improved board level reliability. The space between the
NSMD pad and the solder mask as well as the actual signal trace widths depend on the
capability of the PCB vendor. The cost of the PCB is higher when the line width and spaces
are smaller.
M
L
Opening in
Solder Mask (M)
Solder Mask
Solder Land (L)
e
UG1075_c8_01_101315
Figure 9‐1: Suggested Board Layout of Soldered Pads for BGA Packages

281
BGA Package
SMD
BGA Solder Ball
Land Pad
Solder Mask
L
PCB M
UG1075_c8_02_101315
Figure 9‐2: Example of an NSMD PCB Pad Solder Joint
Table 9‐1: BGA Package Design Rules

Flip-Chip BGA Packages 1.0 mm Pitch 0.8 mm Pitch 0.5 mm Pitch
Design Rule Dimensions in mm (mils)
Package land pad opening (SMD) 0.53 mm (20.9 mils) 0.40 mm (15.7 mils) 0.28 mm (11.0 mils)
Maximum PCB solder land (L) diameter 0.53 mm (20.9 mils) 0.40 mm (15.7 mils) 0.26 mm (10.2 mils)
Opening in PCB solder mask (M) diameter 0.63 mm (24.8 mils) 0.50 mm (19.7 mils) 0.36 mm (14.2 mils)
Solder ball land pitch (e) 1.00 mm (39.4 mils) 0.80 mm (31.5 mils) 0.50 mm (19.7 mils)
Notes:
1. Controlling dimension in mm.

282
Stencil
Solder paste is applied to PCB metal pads by screen printing. The volume of the printed
solder paste is determined by the stencil aperture and the stencil thickness. In most cases,
the thickness of a stencil must be matched to the needs of all components on the PCB.
Stencil apertures should be a circular shape. To ensure a uniform and high-solder paste
transfer to the PCB, laser-cut stencil, made from mostly stainless steel, is typically used.
Nickel blank stencils, referring to stencils where the entire foil is laser-cut from a sheet of
pure nickel material, can also be used. However, high-quality nano-coated stencils (laser cut
from stainless steel) can perform as well as or better than nickel blanks.
Uniform Stencil Aperture Design

• For packages with 1 mm or 0.8 mm ball pitch, a uniform stencil aperture opening of
19.7 mils to 20.0 mils round is recommended.
• For InFO packages with 0.5 mm ball pitch, a uniform stencil with squared aperture
openings (rounded corners) of 12 mils and pitch of 19.8 mils, as show in Figure 9-3 is
recommended. A stencil thickness of 4 mils is also recommended.

283
19.7 mils
19.7 mils
12 mils
12 mils
X25233-032921
Figure 9‐3: Recommended Stencil Design for InFO Packages

284
Chapter 10
Edge Bonding Guidelines
Summary
The edge bonding technique uses high-adhesion adhesives dispensed along the periphery
of a component, as shown in Figure 10-1. Xilinx recommends edge bonding for increased
mechanical reliability in cases where the device is exposed to extensive temperature cycling
or extreme shock and vibration, such as space, defense, and telecommunications
applications. Designers are expected to evaluate the need for edge bonding based on the
requirements of the specific application implementation.
Figure 10‐1: Edge Bonded BGA Packages

Various edge-bonding adhesive patterns were evaluated using an in-line dispensing
machine. Based on the evaluation, the dispensing pattern shown in Table 10-1 is
recommended. A dot pattern, shown in Figure 10-2, was also successfully evaluated
following the same parameters (dot locations at L1 and L2) as the recommended dispensing
pattern.
Table 10‐1: Edge Bonding Pattern and Parameters

Dimension UBVA494 UBVA530
Length (L1) 5.3 mm 5.6 mm
Length (L2) 3.2 mm 3.2 mm

285
Table 10‐1: Edge Bonding Pattern and Parameters (Cont’d)

Dimension UBVA494 UBVA530
Width (W)/Dot (Size) 1 mm 1 mm
Height (% of body height) 50–90% 50–90%
Figure 10‐2: Dot Pattern
Edge Bonding Implementation

Edge bonding is the dispensing of an epoxy material around the periphery of the package
after board mount. Xilinx requires the use of the Zymet UA-2605-B edge-bonding material.
Edge bonding is not intended to under fill the package. This technique allows for
component rework and improves the robustness of the mounted component by controlling
the expansion and warpage of the board during normal operating conditions.
IMPORTANT: Following the initial placement and reflow process, devices should not be reflowed more
than two additional times and should not be removed from the board. Any additional rework beyond
that is likely to cause irreparable damage to the device.
To place the adhesive while using an in-line soldering robot, Xilinx recommends the
parameters shown in Table 10-2.
Table 10‐2: Process Parameters for Edge Bonding

Process Parameter Range Specification
Needle size 25—20 gauge
Needle height Above the device edge midpoint, or 0 to 1.5 mm below the device top surface

286
Table 10‐2: Process Parameters for Edge Bonding (Cont’d)

Process Parameter Range Specification
Needle edge spacing Half to three quarters of the needle outer diameter (D)
D
D/2 to 3/4D
X23147-090519
Dispense needle speed 0.1 to 200 mm/second (typical 15 mm/sec)

Valve pressure 20 to 60 psi (typical 25 psi)
The adhesive is dispensed along the perimeter of the assembled component at a width of
3 mm and a height of 50% to 90% the substrate height, leaving a small section at the center
of each edge unbonded, as illustrated in Figure 10-3. This is to ensure that there is an outlet
for any expansion of the air during processing. Xilinx recommends centering the opening
on each side with a width of 25–30% the length of the package substrate. The exact
locations and size of the openings can be varied depending on the design and rework.

287
W No test points under adhesive

Adhesive Width (W) placement keep-out locations.
Extends ~1 mm from
the device
Adhesive bead must be
continuous and maintain
Opening ~30–50% uniform contact to both the
of substrate length length of the substrate and the
PCB solder mask surface.
L2
Adhesive Length (L)

Typically 25%–35% L1
of substrate length
from the corner
Adhesive Height
Too Little Correct Too Much
50% to 90% of
BGA substrate
height
Minimize the amount of

adhesive under the substrate
X25244-040821
Figure 10‐3: Edge Bonding Adhesive Placement Parameters
RECOMMENDED: Curing conditions are 155°C for 10 minutes.
Component Clearance Surrounding Edge Bond

An adjacent component clearance surrounding the Xilinx device is necessary to have the
30° to 45° angle required by the for the edge bond dispenser to dispense the edge bond
adhesive material. The surrounding component height and distance from the device is
validated based on each unique product design layout.

288
Edge Bond Removal

Edge bond material can be removed by heating to 170–180°C, and scraping using a stiff
probe made of stable organic material such as a non-resinous wood or Teflon. Use a hot air
blower on the edge bond area and slowly remove the edge bond adhesive from side to side.
Do not use force to remove the edge bond adhesive. Excess adhesive on the PCB can be
removed using a chisel-tip soldering iron, with sufficient precautions to limit damage to the
PCB surface.

289
Chapter 11
Thermal Specifications
Introduction
Zynq® UltraScale+™ devices are offered exclusively in thermally efficient flip-chip BGA
packages. These flip-chip packages range in pin-count from the smaller 19 x 19 mm
SBVA484 to the 45 x 45 mm FFVE1924. This suite of packages is used to address the various
power requirements of the Zynq UltraScale+ devices. Zynq UltraScale+ devices are
implemented in the 16 nm process technology.
Unlike features in an ASIC, the combination of Zynq UltraScale+ device features used in a
user application is not known to the component supplier. Therefore, it remains a challenge
for Xilinx to predict the power requirements of a given Zynq UltraScale+ device when it
leaves the factory. Accurate estimates are obtained when the board design takes shape. For
this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to
help users quickly and accurately estimate their design power requirements. Zynq
UltraScale+ devices are supported similarly to previous products. The uncertainty of design
power requirements makes it difficult to apply canned thermal solutions to fit all users.
Therefore, Xilinx devices do not come with preset thermal solutions. Your design’s
operating conditions dictate the appropriate solution.

290
Thermal Resistance Data

Table 11-1 shows the thermal resistance data for Zynq UltraScale+ devices (grouped in the
packages offered). The data includes junction-to-ambient in still air, junction-to-case, and
junction-to-board data based on standard JEDEC four-layer measurements.
IMPORTANT: The data in Table 11-1 is for device/package comparison purposes only. Attempts to
recreate this data are only valid using the transient 2-phase measurement techniques outlined in
JESD51-14. Do not use these values for thermal simulations. Use the Package Thermal Models [Ref 23].
TIP: The thermal data query for all available devices by package is available on the Xilinx website:
www.xilinx.com/cgi-bin/thermal/thermal.pl.
type starts with an XQ vs. XC or XA, and the Pb-free signifier in the package name is Q (for example:
FFQE1156). Refer to the Pb-free version of these packages for their thermal resistance data and thermal
models.
Table 11‐1: Thermal Resistance Data
Package  JB(1)  JC(1)  JA(1)  JA-Effective (°C/W)(2)

Package Devices
Body Size (°C/W) (°C/W) (°C/W) @250 LFM @500 LFM @750 LFM
XCZU1 3.35 0.09 16.9 12.5 10.5 9.7
XCZU2 2.46 0.06 14.9 11.5 9.6 8.9
SBVA484 19 x 19 XCZU3 2.46 0.06 14.9 11.5 9.6 8.9
XAZU2EG 2.46 0.06 14.9 11.5 9.6 8.9
XAZU3EG 2.46 0.06 14.9 11.5 9.6 8.9
SFRA484 19 x 19 XQZU3EG 2.70 0.43 15.3 11.7 9.8 9.1
UBVA494 15 x 9.5 XCZU1 2.28 0.03 22.4 19.7 16.5 15.0
XCZU2 2.28 0.03 22.4 19.7 16.5 15.0
UBVA530 16 x 9.5
XCZU3 2.28 0.03 22.4 19.7 16.5 15.0
XCZU1 2.58 0.52 13.8 10.2 8.6 8.0
XCZU2 2.22 0.38 13.2 9.9 8.3 7.8
SFVA625 21 x 21 XCZU3 2.22 0.38 13.2 9.9 8.3 7.8
XAZU2EG 2.22 0.38 13.2 9.9 8.3 7.8
XAZU3EG 2.22 0.38 13.2 9.9 8.3 7.8

291
Table 11‐1: Thermal Resistance Data (Cont’d)

Package Devices
XCZU1 2.50 0.49 12.5 9.1 7.6 7.1
XCZU2 2.67 0.50 12.8 9.2 7.8 7.2
XCZU3 2.67 0.50 12.8 9.2 7.8 7.2
XCZU4 2.28 0.27 12.2 8.9 7.4 7.0
SFVC784 23 x 23 XCZU5 2.28 0.27 12.2 8.9 7.4 7.0
XAZU2EG 2.67 0.50 12.8 9.2 7.8 7.2
XAZU3EG 2.67 0.50 12.8 9.2 7.8 7.2
XAZU4EV 2.28 0.27 12.2 8.9 7.4 7.0
XAZU5EV 2.28 0.27 12.2 8.9 7.4 7.0
XQZU3EG 2.44 0.42 12.4 9.0 7.6 7.1
SFRC784 23 x 23
XQZU5EV 2.26 0.27 12.1 8.9 7.4 7.0
XCZU4 2.62 0.04 9.6 6.3 5.3 5.0
XCZU5 2.62 0.04 9.6 6.3 5.3 5.0
FBVB900 31 x 31
XCZU7 2.32 0.03 9.2 6.1 5.1 4.8
XAZU7 2.32 0.03 9.2 6.1 5.1 4.8
XQZU5EV 2.26 0.27 9.1 6.1 5.1 4.8
FFRB900 31 x 31
XQZU7EV 2.14 0.19 8.9 6.0 5.0 4.8
XCZU6 2.33 0.25 9.2 6.1 5.1 4.9
FFVC900 31 x 31 XCZU9 2.33 0.25 9.2 6.1 5.1 4.9
XCZU15 2.25 0.18 9.1 6.1 5.1 4.8
XQZU9EG 2.10 0.18 8.9 6.0 5.0 4.7
FFRC900 31 x 31
XQZU15EG 2.07 0.17 8.9 6.0 5.0 4.7
XCZU6 2.40 0.20 8.3 5.3 4.5 4.2
FFVB1156 35 x 35 XCZU9 2.40 0.20 8.3 5.3 4.5 4.2
XCZU15 2.09 0.23 7.9 5.1 4.3 4.1
XQZU9EG 2.09 0.18 7.9 5.1 4.3 4.1
FFRB1156 35 x 35
XQZU15EG 2.06 0.17 7.9 5.1 4.3 4.1
XCZU7 2.39 0.21 8.3 5.3 4.5 4.2
FFVC1156 35 x 35
XCZU11 2.20 0.16 8.0 5.2 4.3 4.1
XQZU7EV 2.12 0.19 7.9 5.2 4.3 4.1
FFRC1156 35 x 35
XQZU11EG 2.01 0.15 7.8 5.1 4.3 4.1
FFVD1156 35 x 35 XCZU21DR 1.94 0.16 7.8 5.1 4.2 4.0
FFRD1156 35 x 35 XQZU21DR 1.94 0.16 7.8 5.1 4.2 4.0

292

Package Devices
XCZU25DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU27DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU28DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU42DR 1.94 0.16 7.8 5.1 4.2 4.0
FFVE1156 35 x 35 XCZU43DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU47DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU48DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU65DR 1.94 0.16 7.8 5.1 4.2 4.0
XCZU67DR 1.94 0.16 7.8 5.1 4.2 4.0
FFRE1156 35 x 35 XQZU28DR 1.93 0.11 7.7 5.1 4.2 4.0
XCZU25DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU27DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU28DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU42DR 2.40 0.02 8.3 5.3 4.4 4.2
FSVE1156 35 x 35 XCZU43DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU47DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU48DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU65DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU67DR 2.40 0.02 8.3 5.3 4.4 4.2
XCZU11 2.22 0.16 7.1 4.4 3.7 3.5
FFVB1517 40 x 40 XCZU17 2.17 0.11 7.0 4.4 3.7 3.5
XCZU19 2.17 0.11 7.0 4.4 3.7 3.5
FFRB1517 40 x 40 XQZU19EG 1.90 0.11 6.8 4.3 3.5 3.4
XCZU7 2.38 0.21 7.3 4.5 3.8 3.6
FFVF1517 40 x 40 XCZU11 2.22 0.16 7.1 4.4 3.7 3.5
XAZU11 2.22 0.16 7.1 4.4 3.7 3.5
XCZU25DR 1.93 0.16 6.8 4.3 3.6 3.4
XCZU27DR 1.93 0.16 6.8 4.3 3.6 3.4
XCZU28DR 1.93 0.16 6.8 4.3 3.6 3.4
FFVG1517 40 x 40
XCZU43DR 1.93 0.16 6.8 4.3 3.6 3.4
XCZU47DR 1.93 0.16 6.8 4.3 3.6 3.4
XCZU48DR 1.93 0.16 6.8 4.3 3.6 3.4
FFRG1517 40 x 40 XQZU28DR 1.93 0.16 6.8 4.3 3.6 3.4
FSRG1517 40 x 40 XQZU48DR 2.43 0.02 7.3 4.5 3.8 3.6

293

Package Devices
XCZU25DR 2.43 0.02 7.3 4.5 3.8 3.6
XCZU27DR 2.43 0.02 7.3 4.5 3.8 3.6
XCZU28DR 2.43 0.02 7.3 4.5 3.8 3.6
FSVG1517 40 x 40
XCZU43DR 2.43 0.02 7.3 4.5 3.8 3.6
XCZU47DR 2.43 0.02 7.3 4.5 3.8 3.6
XCZU48DR 2.43 0.02 7.3 4.5 3.8 3.6
XCZU11 1.96 0.14 6.4 4.0 3.3 3.2
FFVC1760 42.5 x 42.5 XCZU17 1.77 0.10 6.3 3.9 3.2 3.1
XCZU19 1.77 0.10 6.3 3.9 3.2 3.1
XQZU11EG 1.96 0.14 6.4 4.0 3.3 3.2
FFRC1760 42.5 x 42.5
XQZU19EG 1.77 0.10 6.3 3.9 3.2 3.1
XCZU17 1.77 0.10 6.3 3.9 3.2 3.1
FFVD1760 42.5 x 42.5
XCZU19 1.77 0.10 6.3 3.9 3.2 3.1
XCZU29DR 2.04 0.17 6.5 4.0 3.3 3.2
FFVF1760 42.5 x 42.5 XCZU39DR 2.04 0.17 6.5 4.0 3.3 3.2
XCZU49DR 2.04 0.17 6.5 4.0 3.3 3.2
FFVH1760 42.5 x 42.5 XCZU46DR 2.04 0.17 6.5 4.0 3.3 3.2
FFRF1760 42.5 x 42.5 XQZU29DR 2.04 0.17 6.5 4.0 3.3 3.2
FSRF1760 42.5 x 42.5 XQZU49DR 2.47 0.02 7.0 4.3 3.5 3.6
XCZU29DR 2.47 0.02 7.0 4.3 3.5 3.6
FSVF1760 42.5 x 42.5 XCZU39DR 2.47 0.02 7.0 4.3 3.5 3.6
XCZU49DR 2.47 0.02 7.0 4.3 3.5 3.6
FSVH1760 42.5 x 42.5 XCZU46DR 2.47 0.02 7.0 4.3 3.5 3.6
XCZU17 1.77 0.10 5.9 3.6 3.0 2.9
FFVE1924 45 x 45
XCZU19 1.77 0.10 5.9 3.6 3.0 2.9
Notes:
1. This data is for device/package comparison purposes only. Attempts to recreate this data are only valid using the
transient 2-phase measurement techniques outlined in JESD51-14. Do not use these values for thermal
simulations. Use the Package Thermal Models [Ref 23].
2. All  JA-Effective values assume no heat sink and include thermal dissipation through a standard JEDEC four-layer
board. The Xilinx power estimation tools (Vivado® Power Analysis, and Xilinx Power Estimator), which require
detailed board dimensions and layer counts, are useful for deriving more precise  JA-Effective values.

294
Support for Thermal Models

Table 11-1 provides the traditional thermal resistance data for Zynq UltraScale+ devices.
These resistances are measured using a prescribed JEDEC standard that might not
necessarily reflect your actual board conditions and environment. The quoted  JA and  JC
numbers are environmentally dependent, and JEDEC has traditionally recommended that
these be used with that awareness. For more accurate junction temperature prediction,
these might not be enough, and a system-level thermal simulation might be required.
Though Xilinx continues to support these figures of merit data, for Zynq UltraScale+
devices, boundary conditions independent thermal resistor network (Delphi) models are
offered for all Zynq UltraScale+ devices. These compact models seek to capture the thermal
behavior of the packages more accurately at predetermined critical points (junction, case,
top, leads, and so on) with the reduced set of nodes as illustrated in Figure 11-1.
Unlike a full 3D model, these are computationally efficient and work well in an integrated
system simulation environment. Delphi models are available for download on the Xilinx
website (under the Device Model tab).
DELPHI BCI-CTM Topology for Two Resistor Model

Flip-Chip BGA
TI TO
Rjc
Junction
SIDE Junction
Rjb
BI BO UG1075_c9_01_101415
Figure 11‐1: Thermal Model Topologies
RECOMMENDED: Xilinx recommends the use of the Delphi thermal model. Xilinx also recommends a
best practice review of manufacturing variations on the thermal performance of the device from both
the thermal interface material parameters and thermal solution variations. Examples of manufacture
variations include the tolerance in airflow from a fan, the tolerance on performance of the heat pipe
and vapor chamber, and manufacturing variations of the attachment of fins to the heat-sink base and
the flatness of the surface.

295
Chapter 12
Thermal Management Strategy
Introduction
As described in this section, Xilinx relies on a multi-pronged approach to consuming less
power and dissipating heat for systems using Zynq® UltraScale+™ devices.
Flip-Chip Packages
Zynq UltraScale+ devices are offered in flip-chip BGA packages, which present a low
thermal path. With the exception of the bare-die packages, the flip-chip BGA packages
incorporate a heat spreader with an additional thermal interface material (TIM), as shown in
Figure 12-1.
Thermal Interface Material (TIM)
Lid-Heat Spreader
Die
Substrate
UG1075_c10_01_101415
Figure 12‐1: Heat Spreader with Thermal Interface Material

Materials with better thermal conductivity and consistent process deliver low thermal
resistance to the heat spreader.
A parallel effort to ensure optimized package electrical return paths produces the added
benefit of enhanced power and ground plane arrangement in the packages. A boost in
copper density on the planes improves the overall thermal conductivity through the
laminate. In addition, the extra dense and distributed via fields in the package increase the
vertical thermal conductivity.

296
System Level Heat Sink Solutions

To complete a comprehensive thermal management strategy, an overall thermal budget
that includes custom or OEM heat sink solutions depends on the physical and mechanical
constraints of the system. A heat-sink solution, managed by the system-level designer,
should be tailored to the design and specific system constraints. This includes
understanding the inherent device capabilities for delivering heat to the surface.
By considering the system's physical, mechanical, and environmental constraints, the

overall thermal budget is maintained and does not exceed the device’s maximum operating
temperature. The heat sink is an integral part of the thermal management solution to
maintain a safe operating temperature. As a result, the system-level designer must be aware
of the following:
• For lidless packages, the nominal stiffener height can be different from the height of
the die. Therefore, the heat sink must have an island to contact the die.
• Especially for lidless packages, Xilinx advises against direct use of the  JC parameters
(see Table 11-1) to determine the thermal performance of the device in your
application. The calculation of these parameters are done in accordance with the JEDEC
standard JESD51 where system parameters differ greatly from most applications.
Instead, run thermal simulations of the system in worst-case environmental conditions
using Delphi thermal models, which more accurately represent the device thermal
performance under all boundary conditions.
• Consider the mechanical specifications of the package as well as the selection of the
thermal interface between the die and the thermal management solution to ensure the
lowest thermal contact resistance.
• The total thermal contact of the thermal interface material is determined based on
parameters from the thermal interface supplier’s data sheet.
• See the applied pressure recommendation on page 300. Lower pressure runs the risk of
poor thermal contact and higher pressure runs the risk of damaging the device;
therefore, strict control of pressure is required.
• Consider all uncertainties in thermal modeling, including manufacturing variations
from the thermal solutions (for example, fan airflow tolerance, heat pipe or vapor
chamber performance tolerance, variation of the attachment of fins to heat sink base,
and surface flatness).

297
Thermal Interface Material

When installing heat sinks for Zynq UltraScale+ devices, a suitable thermal interface
material (TIM) must be used. This thermal material significantly aids the transfer of heat
from the component to the heat sink.
For bare-die flip-chip BGAs, the surface of the silicon contacts the heat sink. For lidded
flip-chip BGAs, the lid contacts the heat sink. The surface size of the bare-die flip-chip BGA
and lidded flip-chip BGAs are different. Xilinx recommends a different type of thermal
material for long-term use with each type of flip-chip BGAs package.
Thermal interface material is needed because even the largest heat sink and fan cannot
effectively cool an Zynq UltraScale+ device unless there is good physical contact between
the base of the heat sink and the top of the Zynq UltraScale+ device. The surfaces of both
the heat sink and the Zynq UltraScale+ device silicon are not absolutely smooth. This
surface roughness is observed when examined at a microscopic level. Because surface
roughness reduces the effective contact area, attaching a heat sink without a thermal
interface material is not sufficient due to inadequate surface contact.
A thermal interface material such as phase-change material, thermal grease, or thermal

pads fills these gaps and allows effective transference of heat between the Zynq
UltraScale+ device die and the heat sink.
The selection of the thermal interface (TIM) between the package and the thermal
management solution is critical to ensure the lowest thermal contact resistance. Therefore,
the following parameters must be considered.
1. The flatness of the lid and the flatness of the contact surface of the thermal solution.
2. The applied pressure of the thermal solution on the package, which must be within the
allowable maximum pressure that can be applied on the package.
3. The total thermal contact of the thermal interface material. This value is determined
based on the parameters in step 1 and step 2, which are published in the data sheet of
the thermal interface supplier.

298
Types of TIM
There are many type of TIM available for sale. The most commonly used thermal interface
materials are listed.
• Thermal grease
• Thermal pads
• Phase change material
• Thermal paste
• Thermal adhesives
• Thermal tape
Guidelines for Thermal Interface Materials

Five factors affect the choice, use, and performance of the interface material used between
the processor and the heat sink:
• Thermal Conductivity of the Material

• Electrical Conductivity of the Material
• Spreading Characteristics of the Material
• Long-Term Stability and Reliability of the Material
• Ease of Application
• Applied Pressure from Heat Sink to the Package via Thermal Interface Materials
Thermal Conductivity of the Material

Thermal conductivity is the quantified ability of any material to transfer heat. The thermal
conductivity of the interface material has a significant impact on its thermal performance.
The higher the thermal conductivity, the more efficient the material is at transferring heat.
Materials that have a lower thermal conductivity are less efficient at transferring heat,
causing a higher temperature differential to exist across the interface. To overcome this less
efficient heat transfer, a better cooling solution (typically, a more costly solution) must be
used to achieve the desired heat dissipation.
Electrical Conductivity of the Material

Some metal-based TIM compounds are electrically conductive. Ceramic-based compounds
are typically not electrically conductive. Manufacturers produce metal-based compounds
with low-electrical conductivity, but some of these materials are not completely electrically
inert. Metal-based thermal compounds are not hazardous to the Zynq UltraScale+ device
die itself, but other elements on the Zynq UltraScale+ device or motherboard can be at risk

299
if they become contaminated by the compound. For this reason, Xilinx does not
recommend the use of electrically conductive thermal interface material.
Spreading Characteristics of the Material

The spreading characteristics of the thermal interface material determines its ability, under
the pressure of the mounted heat sink, to spread and fill in or eliminate the air gaps
between the Zynq UltraScale+ device and the heat sink. Because air is a very poor thermal
conductor, the more completely the interface material fills the gaps, the greater the heat
transference.
Long-Term Stability and Reliability of the Material

The long-term stability and reliability of the thermal interface material is described as the
ability to provide a sufficient thermal conductance even after an extended time or
extensive. Low-quality compounds can harden or leak out over time (the pump-out effect),
leading to overheating or premature failure of the Zynq UltraScale+ device. High-quality
compounds provide a stable and reliable thermal interface material throughout the lifetime
of the device. Thermal greases with higher viscosities are typically more resistant to pump
out effects on bare-die devices.
Ease of Application
A spreadable thermal grease requires the surface mount supplier to carefully use the
appropriate amount of material. Too much or too little material can cause problems. The
thermal pad is a fixed size and is therefore easier to apply in a consistent manner.
Applied Pressure from Heat Sink to the Package via Thermal Interface
Materials
IMPORTANT: The following table shows the required applied pressure on the thermal interface
material (TIM) between the package and the heat sink. Thermocouples should not be present between
the package and the heat sink, as their presence will degrade the thermal contact and result in
incorrect thermal measurements. The best practice is to select the appropriate pressure for the
optimum thermal contact performance between the package and the thermal system solution, and the
mechanical integrity of the package (with the thermal solution to pass all mechanical stress and
vibration qualification tests).
Table 12‐1: Required Applied Pressure by Package Type

Package Type Supported Pressure Range (PSI)
0.8 mm and 1.0 mm pitch 20 to 50 PSI
InFO packages (e.g., UBVA530) 3 to 5 PSI

300
RECOMMENDED: Xilinx recommends using dynamic mounting around the four corners of the device
package. On the PCB, use a bracket clip as part of the heat sink attachment to provide mechanical
package support. See Figure 12-2.
HS Base Heat Sink
PKG
X15431-111316
Figure 12‐2: Dynamic Mounting and Bracket Clips on Heat Sink Attachment
Heat Sink Removal

When removing or reworking heat sinks, the phase-change material residue must be
removed from the surface of the die. Laird Technologies, Inc. provides the following
guidance for complete removal of the phase-change material from the component.
Instructions for Removal of Phase-change Material

1. Separate the Components
2. Scrape Away Thick Residue
3. Clean Remaining Residue with Solvent
4. Working with Laird Material
Separate the Components

At room temperature, if possible, use a back and forth twisting motion to break the bond
between the phase-change thermal interface material and mated components (i.e., heat
sink and Zynq UltraScale+ device). See Figure 12-3.

301
Phase Change
Thermal Interface Heat Sink
Material
Zynq
UltraScale+
Device
X20431-022818
Figure 12‐3: Breaking the Bond between Thermal Interface Material and Mated Components
For smaller components (typically 15 mm x 15 mm or less), the bond usually breaks free
easily at room temperature. For larger components, in situations where minimal movement
is available, or if using fragile components, heat the component (preferred) or heat sink to
about 40°C–60°C before removal.
The guideline is 40°C–60°C, however, you might find that for your application, heating to
35°C is adequate. You might prefer to heat to 70°C which makes the phase-change thermal
interface material very soft and the components can be easily separated.
Scrape Away Thick Residue

For a faster clean-up once components are separated, scrape away any large residual
material amounts with a plastic spatula or a wooden tongue depressor. A clean dry rag can
be used to wipe away excess material.
Clean Remaining Residue with Solvent

Using a clean cloth/wipe, wet it with your choice of solvent (see the following list) and wipe
away any remaining residue.
• Toluene (easiest)
• Acetone (very good)
• Isoparaffinic hydrocarbon: Isopar, Soltrol (trade names) (very good)
• Isopropyl alcohol (OK)

302
Working with Laird Material

Safe handling, disposal, and first-aid measures for working with phase-change material are
included in the Laird Technologies material safety data sheet (MSDS). Read the MSDS
before using or handling. See the Laird Technologies, Inc. website, www.lairdtech.com.
Measurement Debug
When performing in-system thermal testing, to ensure accurate data and not incur damage
to the device, do not place a thermocouple in between the device and the heat sink. On the
extreme side, it might cause additional mechanical and/or thermal stress to the device,
leading to damage. Even if damage does not occur, it often leads to a thicker and or uneven
thermal interface material thickness, leading to a thermal performance difference from a
system without a thermocouple. To obtain the device temperature, use the System Monitor
as a non-invasive means to get accurate device measurements while debugging the system.

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Chapter 13
Heat Sink Guidelines for Bare-die

Flip-Chip Packages
Heat Sink Attachments for Bare-die FB Packages

Heat sinks can be attached to the package in multiple ways. For heat to dissipate effectively,
the advantages and disadvantages of each heat sink attachment method must be
considered. Factors influencing the selection of the heat sink attachment method include
the package type, contact area of the heat source, and the heat sink type.
Silicon and Decoupling Capacitors Height Consideration

When designing heat sink attachments for bare-die flip-chip BGA packages, the height of
the die above the substrate and also the height of decoupling capacitors must be
considered (Figure 13-1). This is to prevent electrical shorting between the heat sink (metal)
and the decoupling capacitors.
Decoupling
Capacitor Silicon Underfill Substrate
UG1075_c11_01_101415
Figure 13‐1: Cross Section of Bare-die Flip-chip BGA

304
Types of Heat Sink Attachments

There are six main methods for heat sink attachment. Table 13-1 lists their advantages and
disadvantages.
• Thermal tape
• Thermally conductive adhesive or glue
• Wire form Z-clips
• Plastic clip-ons
• Threaded stand-offs (PEMs) and compression springs
• Push-pins and compression springs
Table 13‐1: Heat Sink Attachment Methods

Attachment
Advantages Disadvantages
Method
Thermal tape • Generally easy to attach and is inexpensive. • The surfaces of the heat sink and the chip
• Lowest cost approach for aluminum heat must be very clean to allow the tape to
sink attachment. bond correctly.
• No additional space required on the PCB. • Because of the small contact area, the tape
might not provide sufficient bond strength.
• Tape is a moderate to low thermal
conductor that could affect the thermal
performance.
Thermally • Outstanding mechanical adhesion. • Adhesive application process is
conductive • Fairly inexpensive, costs a little more than challenging and it is difficult to control the
adhesive or glue tape. amount of adhesive to use.
• No additional space required on the PCB. • Difficult to rework.

• Because of the small contact area, the
adhesive might not provide sufficient bond
strength.
Wire form Z-clips • It provides a strong and secure mechanical • Requires additional space on the PCB for
attachment. In environments that require anchor locations.
shock and vibration testing, this type of
strong mechanical attachment is necessary.
• Easy to apply and remove. Does not cause
the semiconductors to be destroyed (epoxy
and occasionally tape can destroy the
device).
• It applies a preload onto the thermal
interface material (TIM). Pre-loads actually
improve thermal performance.

305
Table 13‐1: Heat Sink Attachment Methods (Cont’d)

Attachment Advantages Disadvantages
Method
Plastic clip-ons • Suitable for designs where space on the • Needs a keep out area around the silicon
PCB is limited. devices to use the clip.
• Easy to rework by allowing heat sinks to be • Caution is required when installing or
easily removed and reapplied without removing clip-ons because localized stress
damaging the PCB board. can damage the solder balls or chip
• Can provide a strong enough mechanical substrate.
attachment to pass shock and vibration
test.
Threaded • Provides stable attachments to heat source • Holes are required in the PCB taking
stand-offs and transfers load to the PCB, backing valuable space that can be used for trace
(PEMs) and plate, or chassis. lines.
compression • Suitable for high mass heat sinks. • Tends to be expensive, especially since
springs holes need to be drilled or predrilled onto
• Allows for tight control over mounting
force and load placed on chip and solder the PCB board to use stand-offs.
balls.
Push-pins and • Provides a stable attachment to a heat • Requires additional space on the PCB for
compression source and transfers load to the PCB. push-pin locations.
springs • Allows for tight control over mounting
force and load placed on chip and solder
balls.
Heat Sink Attachment

Component Pick-up Tool Consideration
For pick-and-place machines to place bare-die flip-chip BGAs onto PCBs, Xilinx
recommends using soft tips or suction cups for the nozzles. This prevents chipping,
scratching, or even cracking of the bare die (Figure 13-2).
Preferred Incorrect Pickup Method
Metal Metal
Decoupling Tip Decoupling Tip
Capacitor Nozzle Silicon Substrate Capacitor Nozzle Silicon Substrate
Soft Tips
Metal Pick Up Tip Nozzle with Soft Tips or Metal Pick Up Tip Nozzle Can Damage
Suction Cups is Preferred the Exposed Silicon
UG1075_c11_02_101415
Figure 13‐2: Recommended Method For Using Pick-up Tools

306
Heat Sink Attachment Process Considerations

After the component is placed onto the PCBs, when attaching a heat sink to the bare-die
package, the factors in Table 13-2 must be carefully considered (see Figure 13-3).
Table 13‐2: Heat Sink Attachment Considerations

Consideration(s) Effect(s) Recommendation(s)
In heat sink attach process, • Uneven heat sink placement • Even heat sink placement
what factors can cause • Uneven TIM thickness • Even TIM thickness
damage to the exposed die
and passive capacitors? • Uneven force applied when • Even force applied when placing heat sink
placing heat sink placement placement
Does the heat sink tilt or tip Uneven heat sink placement will • Careful handling not to contact the heat
the post attachment? damage the silicon and can sink with the post attachment.
cause field failures. • Use a fixture to hold the heat sink in place
with post attachment until it is glued to
the silicon.
Preferred Incorrect Alignment

Even Force Even Force
Decoupling Decoupling
Capacitor Capacitor
Silicon Silicon
Substrate Substrate
Preferred Incorrect Force

Even Force Even Force
Decoupling
Heat Sink
Capacitor
Silicon
Substrate Silicon
Substrate
Mother Board
Preferred application of heat sink Improper application of heat sink can cause damage
1. Heat sink is aligned parallel to silicon to heat sink
2. Even bond line thickness of TIM 1. Heat sink is not aligned parallel to silicon
3. Even compressive force is applied on all sides 2. Uneven bond line thickness of TIM
3. Uneven force is applied
UG1075_c11_03_101415
Figure 13‐3: Recommended Application of Heat Sink

307
Standard Heat Sink Attach Process with Thermal Conductive Adhesive
Prior to attaching the heat sink, the Zynq UltraScale+ device needs be surface mounted on
the motherboard.
1. Place the motherboard into a jig or a fixture to hold the motherboard steady to prevent
any movement during the heat sink attachment process.
2. Thermoset material (electrically non-conductive) is applied over the backside surface of
silicon in a pattern using automated dispensing equipment. Automated dispensers are
often used to provide a stable process speed at a relatively low cost. The optimum
dispensing pattern needs to be determined by the SMT supplier.
Note: Minimal volume coverage of the backside of the silicon can result in non-optimum heat
transfer.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the adhesive spreads to cover the backside silicon. A force transducer is
normally used to measure and limit the placement force.
4. The epoxy is cured with heat at a defined time.
Note: The epoxy curing temperature and time is based on manufacturer’s specifications.
Standard Heat Sink Attach Process with Thermal Adhesive Tape
the motherboard.
2. Thermal adhesive tape cut to the size of the heat sink is applied on the underside of the
heat sink at a modest angle with the use of a squeegee rubber roller. Apply pressure to
help reduce the possibility of air entrapment under the tape during application.
3. The heat sink is placed on the backside of the silicon with a pick and place machine. A
uniform pressure is applied over the heat sink to the backside of the silicon. As the heat
sink is placed, the thermal adhesive tape is glued to the backside of the silicon. A force
transducer is normally used to measure and limit the placement force.
4. A uniform and constant pressure is applied uniformly over the heat sink and held for a
defined time.
Note: The thermal adhesive tape hold time is based on manufacturer’s specifications.

308
Push-Pin and Shoulder Screw Heat Sink Attachment Process with Phase Change Material (PCM)
Application
the motherboard.
Note: The jig or fixture needs to account for the push pin depth of the heat sink.
2. PCM tape, cut to the size of the heat sink, is applied on the underside of the heat sink
at a modest angle with the use of a squeegee rubber roller. Apply pressure to help
reduce the possibility of air entrapment under the tape during application.
3. Using the push-pin tool, heat sinks are applied over the packages ensuring a pin locking
action with the PCB holes. The compression load from springs applies the appropriate
mounting pressure required for proper thermal interface material performance.
Note: Heat sinks must not tilt during installation. This process cannot be automated due to the
mechanical locking action which requires manual handling. The PCB drill hole tolerances need to
be close enough to eliminate any issues concerning the heat sink attachment.

309
Appendix A
Additional Resources and Legal Notices
Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.
Solution Centers
See the Xilinx Solution Centers for support on devices, software tools, and intellectual
property at all stages of the design cycle. Topics include design assistance, advisories, and
troubleshooting tips.
Documentation Navigator and Design Hubs

Xilinx® Documentation Navigator provides access to Xilinx documents, videos, and support
resources, which you can filter and search to find information. To open the Xilinx
Documentation Navigator (DocNav):
• From the Vivado® IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.
Xilinx Design Hubs provide links to documentation organized by design tasks and other
topics, which you can use to learn key concepts and address frequently asked questions. To
access the Design Hubs:
• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.
Note: For more information on Documentation Navigator, see the Documentation Navigator page
on the Xilinx website.

310
References
1. Zynq UltraScale+ MPSoC Overview (DS891)
2. Zynq UltraScale+ RFSoC Overview (DS889)
3. XQ UltraScale Architecture Data Sheet: Overview (DS895)
4. XA Zynq UltraScale+ MPSoC Data Sheet: Overview (DS894)
5. Zynq UltraScale+ device Packaging Specifications
6. UltraScale Architecture SelectIO Resources User Guide (UG571)
7. UltraScale Architecture Clocking Resources User Guide (UG572)
8. Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
9. Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
10. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
11. UltraScale Architecture GTH Transceiver User Guide (UG576)
12. UltraScale Architecture GTY Transceiver User Guide (UG578)
13. UltraScale Architecture System Monitor User Guide (UG580)
14. UltraScale Architecture PCB Design Guide (UG583)
15. UltraScale Architecture-Based Memory Interface Solutions Product Guide (PG150)
16. UltraScale Architecture Configuration User Guide (UG570)
17. FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP424)
18. FAQ: Top Marking Change for 7 Series, UltraScale, and UltraScale+ Products (XTP544)
19. MDDS files: Click on this link to find the Zynq UltraScale+ devices Packaging
Specifications. In step 2 select the product category: SoCs, MPSoCs & RFSoCs. In step 3,
select the product type. In step 4, click on the package specifications selection to find
the available MDDS files. All published MDDS files are also available on the See All
Package Specifications page.
20. The following websites contain additional information on heat management and contact
information.
° Wakefield: www.wakefield-vette.com
° Aavid: www.aavid.com
° Advanced Thermal Solutions: www.qats.com
° Radian Thermal Products: www.radianheatsinks.com
° Thermo Cool: www.thermocoolcorp.com
° CTS: www.ctscorp.com

311
21. Refer to the following websites for interface material sources:
° Henkel: www.henkel.com
° Bergquist Company: www.bergquistcompany.com
° AOS Thermal Compound: www.aosco.com
° Chomerics: www.chomerics.com
° Kester: www.kester.com
22. Refer to the following websites for CFD tools Xilinx supports with thermal models.
° Mentor Flotherm: www.mentor.com/products/mechanical/flotherm/flotherm/
° ANSYS Icepak: www.ansys.com

23. Refer to the Package Thermal Models on xilinx.com.
24. The following papers are referenced for more information on thermal modeling.
° Lemczyk, T.F., Mack, B., Culham, J.R. and Yovanovich, M.M., 1992, “Printed Circuit
Board Trace Thermal Analysis and Effective Conductivity”, ASME J. Electronic
Packaging, Vol. 114, pp. 413 - 419.50.
° Refai-Ahmed, G. and Karimanal, K., 2003, “Validation of Compact Conduction Models

of BGA Under Realistic Boundary,” J. of Components and Packaging Technology, Vol.
26, No. 3, pp. 610-615.
° Sansoucy, E, Refai-Ahmed, G., and Karimanal, K., 2002, “Thermal Characterization of

TBGA Package for an integration in Board Level Analysis,” Eighth Intersociety on
Thermal Conference Phenomena in Electronic Systems, San Diego., USA.
° Karimanal,K and Refai-Ahmed, G., and., 2002, “Validation of Compact Conduction

Models of BGA Under Realistic Boundary Conditions,” Eighth Intersociety on
Thermal Conference Phenomena in Electronic Systems, San Diego, USA.
° Karminal, K. and Refai-Ahmed, G., 2001, “Compact conduction Model (CCM) of

Microelectronic Packages- A BGA Validation Study,” APACK Conference on Advance
in Packaging, Singapore.

312
Please Read: Important Legal Notices

The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the
maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS
ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related
to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,
incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a
result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised
of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of
updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials
without prior written consent. Certain products are subject to the terms and conditions of Xilinx’s limited warranty, please refer to
Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms
contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any
application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in such critical applications,
please refer to Xilinx’s Terms of Sale which can be viewed at www.xilinx.com/legal.htm#tos.
AUTOMOTIVE APPLICATIONS DISCLAIMER
AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF
AIRBAGS OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A
SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD (“SAFETY
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TEST SUCH SYSTEMS FOR SAFETY PURPOSES. USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY
AT THE RISK OF CUSTOMER, SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT
LIABILITY.
© Copyright 2015–2022 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other
designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm,
ARM1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. PCI,
PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective
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Zynq UltraScale+ Device

Packaging and Pinouts

Product Specification User Guide

UG1075 (v1.11) January 18, 2022

Xilinx is creating an environment where employees, customers,

Date Version Revision

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Chapter 1: Packaging Overview

Chapter 2: PS Memory Interface Pin Guidelines

Chapter 3: Package Files

Chapter 4: Device Diagrams

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Chapter 6: Package Marking

Chapter 7: Packing and Shipping

Chapter 8: Soldering Guidelines

Chapter 9: Recommended PCB Design Rules for BGA Packages

Chapter 10: Edge Bonding Guidelines

Chapter 11: Thermal Specifications

Chapter 12: Thermal Management Strategy

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Chapter 13: Heat Sink Guidelines for Bare-die Flip-Chip Packages

Appendix A: Additional Resources and Legal Notices

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Introduction to the UltraScale Architecture

Kintex® UltraScale+ devices provide the best price/performance/watt balance in a FinFET

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Device Packaging and Pinouts

Differences from Previous Generations

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐1: Package Specifications

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐1: Package Specifications (Cont’d)

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Gigabit Transceiver Channels by Device/Package

Table 1‐2: Serial Transceiver Channels (PS-GTR, GTH, and GTY) by Device/Package

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Zynq UltraScale+ Packaging and Pinouts Send Feedback

User I/O Pins by Device/Package

Table 1‐3: Available I/O Pins by Device/Package

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐3: Available I/O Pins by Device/Package (Cont’d)

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐3: Available I/O Pins by Device/Package (Cont’d)

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐3: Available I/O Pins by Device/Package (Cont’d)

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐3: Available I/O Pins by Device/Package (Cont’d)

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐4: Pin Definitions

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐4: Pin Definitions (Cont’d)

PS DONE signal. Requires an external pull-up

Zynq UltraScale+ Packaging and Pinouts Send Feedback

Table 1‐4: Pin Definitions (Cont’d)