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COMPAL CONFIDENTIAL
MODEL NAME : PAL51/53
1 1

PCB NO : LA-6592P (DAA00001V10)


BOM P/N : 43192931L01
GPIO MAP: E3 Master GPIO Map10102010.xlsx

2
E3 MACALLAN 14" SG 2

rPGA Sandy Bridge +


FCBGA PCH Cougar Point-M
2011-1-13
REV : 1.0(A00)
@ : Nopop Component
3 3

CONN@ : ME controll and stuff by default


MB Type BOM P/N

TPM EN/ TCM DIS 43192931L01 1@ 3@

TPM DIS/ TCM EN 43192931L02 2@ 4@

TPM DIS/ TCM DIS 43192931L03 2@ 3@

ATG TPM EN/ TCM DIS 43192931L11 1@ 3@

ATG TPM DIS/ TCM EN 43192931L12 2@ 4@

4
ATG TPM DIS/ TCM DIS 43192931L13 2@ 3@ 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
MB PCB TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Part Number Description
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
DAA00001V10 PCB 0FE LA-6592P REV0 M/B DIS LA-6592P
Date: Thursday, January 13, 2011 Sheet 1 of 75
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Block Diagram Compal confidential Model: PAL51/53

Memory BUS (DDR3) DDRIII-DIMM X2


1066/1333MHz BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
iLVDS Sandy Bridge PAGE 12,13
LVDS Switch
LVDS CONN PI3LVD400ZFEX 4MB (Socket 988B)
PAGE 24 PAGE 23
1
dLVDS rPGA CPU 1

Touch Screen
HDMI Repeater 988 pins PAGE 24
HDMI CONN DPE PEG
PAGE 26 PS121 PAGE 26
N12M-NS BT PAGE 43
PAGE 6-11

DPC PAGE 46-51 FDI DMI2 Camera


DPD Trough eDP Cable
DOCKING PORT Lane x 8 Lane x 4
VGA dVGA
PAGE 40
iVGA SATA Repeater
DAI Video Switch INTEL USB SATA
MAX14885E
MAX4951BE E-SATA
USB[8,9] VGA PAGE 39
CRT CONN PAGE 25 2560
SATA5
COUGAR POINT-M USB Port PAGE 39
DOCK LAN On IO board
iLVDS BGA USB Port PAGE 38
2560
2 2

PAGE 14-21 USB Port PAGE 38


2062

SDXC/MMC/MS Card reader on IO board


PAGE 35 OZ600FJ0LN PCIE x1 USB Port
PAGE 35
PCI Express BUS 100MHz Intel Lewisville
HD Audio I/F
PCI Express BUS 100MHz DOCK LAN 82579LM
Option
SPI S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
PCIE3 PCIE5 PCIE2 PCIE1 PAGE 32

EXPRESS 1/2 Mini Card 1/2 Mini Card Full Mini Card China TPM1.2 LPC BUS SATA
33MHz INT.Speaker LAN SWITCH
Card Flash WLAN WWAN/UWB SSX44B SATA Repeater HDA Codec PI3L720 PAGE 32
W25X64ZE MAX4951BE 92HD90B2 PAGE 30
PAGE 37 PAGE 36 PAGE 36 PAGE 36 PAGE 34
PAGE 14
PAGE 28
USB10 USB6 USB4 USB5 64M 4K sector PAGE 30

USH TPM1.2 HeadPhone & RJ45


3
Smart Card TDA8034HN W25Q16BVSSIG MIC Jack 3

PAGE 33 PAGE 33 BCM5882 HDD MDC


PAGE 14 on IO board
PAGE 33,34 16M 4K sector
CPU XDP Port RFID PAGE 28
Fingerprint DAI
PAGE 7 PAGE 33 FP_USB USB7 To Docking side
CONN PAGE 23 RJ11
PCH XDP Port
PCIE4 E-Module on IO board Dig.
PAGE 14
SMSC SIO
BC BUS PAGE 29
MIC
Thermal PWM FAN ECE5028
GUARDIAN III PAGE 41 Trough eDP Cable
PAGE 22
EMC4022
PAGE 22
SMSC KBC
MEC5055
WiFi ON/OFF &
PAGE 42
Power ON/OFF SW
4 PAGE 31 4

DC/DC Interface DELL CONFIDENTIAL/PROPRIETARY


PAGE 44
TP CONN KB CONN
PAGE 43 PAGE 43
LED Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
PAGE 45 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DIS Block Diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 2 of 75
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POWER STATES
USB PORT# DESTINATION
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
State S3# S4# S5# A# PLANE PLANE PLANE PLANE
0 JUSB2 (Right side 1)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JUSB3 (Right side 2)
D D
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF
2 JESA1 (Right Side ESATA)
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF
3 JESA1 (Ext Left Side )
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF
PCH
6 JMINI3(Flash)
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH->BIO

8 DOCKING
PM TABLE
9 DOCKING
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
C
SATA DESTINATION C
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M
10 Express card
+3.3V_ALW_PCH +1.8V_RUN (M-OFF)
power SATA 0 HDD
+3.3V_RTC_LDO +1.5V_RUN
plane 11 Bluetooth
+0.75V_DDR_VTT
SATA 1 ODD/ E3 Module Bay
+VCC_CORE
12 Camera
+1.05V_RUN_VTT
SATA 2 NA
+1.05V_RUN
State 13 LCD Touch
SATA 3 NA

S0 ON ON ON ON ON SATA 4 ESATA 0 BIO


USH
S3 ON ON OFF ON OFF SATA 5 Dock 1 NA

S5 S4/AC ON OFF OFF ON OFF


need to update Power Status and PM Table
B
S5 S4/AC don't exist OFF OFF OFF OFF OFF PCI EXPRESS DESTINATION B

Lane 1 MINI CARD-1 WWAN

Lane 2 MINI CARD-2 WLAN

Lane 3 Express card

Lane 4 E3 Module Bay (USB3)

DSC DP/HDMI Port Connetion Lane 5 1/2vMINI CARD-3 PCIE

Port C Dock DP port 2 Lane 6 MMI

Port D Dock DP port 1 Lane 7 10/100/1G LOM

A
Port E MB HDMI Conn Lane 8 None A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 3 of 75
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MODC_EN
HDDC_EN
EN_INVPWR FDC654P
+BL_PWR_SRC
Q21

ADAPTER
PGPU_PWR_EN ISL95870A
D +GPU_CORE SI3456BDV SI3456BDV D
(PU15)
(Q27) (Q30)

1.05V_VTTPWRGD
ISL95870AH
+VCC_SA
+PWR_SRC (PU13)
BATTERY +5V_HDD +5V_MOD

1.05V_0.8V_PWROK
MAX17411
+VCC_GFXCORE
(PU9)

ALWON

CHARGER
+15V_ALW
SN0608098
C +5V_ALW RUN_ON C
(PU2)

SI4164DY
+3.3V_ALW (Q50)

AUX_EN_WOWL

PCH_ALW_ON
+5V_RUN

AUX_ON
SUS_ON

RUN_ON

M_ON
SN1003055 SN1003055
MAX17411 RT8209BGQW RT9026GFP TPS51311
(PU9) (PU3) (PU5) (PU4) (PU7) (PU6)
1.05V_0.8V_PWROK

SI3456 SI3456 S13456 SI3456 NTMS4920 SI3456


CPU_VTT_ON
0.75V_VR_EN

M_ON

(Q38) (Q49) (Q54) (Q34) (Q55) (Q58)


DDR_ON

RUN_ON

B B

+VCC_CORE +1.5V_MEM +0.75V_DDR_VTT +1.8V_RUN +1.05V_RUN_VTT +1.05V_M +3.3V_WLAN +3.3V_ALW_PCH +3.3V_SUS +3.3V_LAN +3.3V_RUN +3.3V_M
RUN_ON

CPU1.5V_S3_GATE RUN_ON
Pop option

+1.0V_LAN Pop option

+3.3V_M
AO4728 NTGS4141N SI4164
(QC3) (Q59) (Q63)
+0.8V_VCCSA
A A

+1.05V_RUN DELL CONFIDENTIAL/PROPRIETARY


+1.5V_CPU_VDDQ +1.5V_RUN
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 4 of 75
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5 4 3 2 1

@ 2.2K
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SMBUS Address [0x9a]

@ 2.2K
+3.3V_ALW_PCH
H14 MEM_SMBCLK 202
2N7002
C9 MEM_SMBDATA 200 DIMMA SMBUS Address [A0]
2N7002
2.2K
202
PCH
D
2.2K
+3.3V_LAN 200 DIMMB
SMBUS Address [A4] D

C8 LAN_SMBCLK 28

G12 LAN_SMBDATA 31 LOM SMBUS Address [C8]


M16 E14 53
XDP1 SMBUS Address [TBD]
2.2K 51
SML1_SMBDATA

SML1_SMBCLK
+3.3V_ALW_PCH
2.2K 53
51 XDP2
A5 B6 2.2K SMBUS Address [TBD]

3A 3A
2.2K +3.3V_ALW SMBUS Address
2.2K
APR_EC: 0x48
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70
129 MSLICE_EC: 0x72 2.2K
+3.3V_RUN
1A A3 DOCK_SMB_DAT DOCKING
USB: 0x59
AUDIO: 0x34 14
SLICE_BATTERY: 0x17 13 G Sensor
2.2K SMBUS Address [0x3B]
SLICE_CHARGER: 0x13
C
+3.3V_ALW C

2.2K
30
B5 LCD_SMBCLK
1B WWAN
32 SMBUS Address [TBD]
1B A4 LCD_SMDATA

2.2K

KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT 100 ohm
CONN
2.2K

+3.3V_ALW
2.2K
USH_SMBCLK M9
1E A50
B53 USH_SMBDAT L9 USH SMBUS Address [0xa4]
1E
B B
2.2K

+3.3V_SUS
2.2K
MEC 5055 7
2B A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
2B B52 CARD_SMBDAT

2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK 10
1G
CHARGER_SMBDAT 9 Charger
1G A47 SMBUS Address [0x12]

2.2K
+3.3V_ALW
2.2K
B7 BAY_SMBDAT 29
2D
30 E3 Module Bay
A A7 BAY_SMBCLK SMBUS Address [0xd2] A
2D

2.2K
+3.3V_RUN
2.2K
2A B49 GPU_SMBCLK 8 Compal Electronics, Inc.
GPU SMBUS Address [0xXX] Title
B48 GPU_SMBDAT 9
2A
SMBUS TOPOLOGY
Size Document Number Rev

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1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 5 of 75
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(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2. JCPU1I

(2)PEG_ICOMPO use 12mil connect to RC2


JCPU1A T35 F22
PEG_COMP VSS161 VSS234
PEG_ICOMPI J22 T34 VSS162 VSS235 F19
PEG_ICOMPO J21 T33 VSS163 VSS236 E30
DMI_CRX_PTX_N0 B27 H22 T32 E27
16 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_RX#[0] PEG_RCOMPO VSS164 VSS237
16 DMI_CRX_PTX_N1 B25 T31 E24
DMI_CRX_PTX_N2 DMI_RX#[1] VSS165 VSS238
16 DMI_CRX_PTX_N2 A25 PEG_CRX_GTX_N[0..15] 46 T30 E21
D DMI_CRX_PTX_N3 DMI_RX#[2] PEG_CRX_GTX_N0 VSS166 VSS239 D
16 DMI_CRX_PTX_N3 B24 K33 T29 E18
DMI_RX#[3] PEG_RX#[0] PEG_CRX_GTX_N1 VSS167 VSS240
M35 T28 E15
DMI_CRX_PTX_P0 PEG_RX#[1] PEG_CRX_GTX_N2 VSS168 VSS241
16 DMI_CRX_PTX_P0 B28 L34 T27 E13
DMI_CRX_PTX_P1 DMI_RX[0] PEG_RX#[2] PEG_CRX_GTX_N3 VSS169 VSS242
16 DMI_CRX_PTX_P1 B26 J35 T26 E10
DMI_RX[1] PEG_RX#[3] VSS170 VSS243

DMI
DMI_CRX_PTX_P2 A24 J32 PEG_CRX_GTX_N4 P9 E9
16 DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] VSS171 VSS244
DMI_CRX_PTX_P3 B23 H34 PEG_CRX_GTX_N5 P8 E8
16 DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5] PEG_CRX_GTX_N6 VSS172 VSS245
H31 P6 E7
DMI_CTX_PRX_N0 PEG_RX#[6] PEG_CRX_GTX_N7 VSS173 VSS246
16 DMI_CTX_PRX_N0 G21 G33 P5 E6
DMI_CTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] PEG_CRX_GTX_N8 VSS174 VSS247
16 DMI_CTX_PRX_N1 E22 G30 P3 E5
DMI_CTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_CRX_GTX_N9 VSS175 VSS248
16 DMI_CTX_PRX_N2 F21 F35 P2 E4
DMI_CTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] PEG_CRX_GTX_N10 VSS176 VSS249
16 DMI_CTX_PRX_N3 D21 E34 N35 E3
DMI_TX#[3] PEG_RX#[10] PEG_CRX_GTX_N11 VSS177 VSS250
PEG_RX#[11] E32 N34 VSS178 VSS251 E2
16 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 G22 D33 PEG_CRX_GTX_N12 N33 E1
DMI_CTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PEG_CRX_GTX_N13 VSS179 VSS252
16 DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31 N32 VSS180 VSS253 D35

PCI EXPRESS* - GRAPHICS


16 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 F20 B33 PEG_CRX_GTX_N14 N31 D32
DMI_CTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_CRX_GTX_N15 VSS181 VSS254
16 DMI_CTX_PRX_P3 C21 DMI_TX[3] PEG_RX#[15] C32 PEG_CRX_GTX_P[0..15] 46 N30 VSS182 VSS255 D29
PEG_CTX_GRX_P[0..15] N29 D26
PEG_CRX_GTX_P0 PEG_CTX_GRX_P[0..15] 46 VSS183 VSS256
PEG_RX[0] J33 N28 VSS184 VSS257 D20
L35 PEG_CRX_GTX_P1 PEG_CTX_GRX_N[0..15] N27 D17
PEG_RX[1] PEG_CRX_GTX_P2 PEG_CTX_GRX_N[0..15] 46 VSS185 VSS258
PEG_RX[2] K34 N26 VSS186 VSS259 C34
16 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 A21 H35 PEG_CRX_GTX_P3 M34 C31
FDI_CTX_PRX_N1 FDI0_TX#[0] PEG_RX[3] PEG_CRX_GTX_P4 VSS187 VSS260
16 FDI_CTX_PRX_N1 H19 FDI0_TX#[1] PEG_RX[4] H32 L33 VSS188 VSS261 C28
16 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 E19 G34 PEG_CRX_GTX_P5 L30 C27
FDI_CTX_PRX_N3 FDI0_TX#[2] PEG_RX[5] PEG_CRX_GTX_P6 VSS189 VSS262
F18 G31 L27 C25
16 FDI_CTX_PRX_N3
Intel(R) FDI
FDI_CTX_PRX_N4 FDI0_TX#[3] PEG_RX[6] PEG_CRX_GTX_P7 VSS190 VSS263
16 FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33 L9 VSS191 VSS264 C23
16 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 C20 F30 PEG_CRX_GTX_P8 L8 C10
FDI_CTX_PRX_N6 FDI1_TX#[1] PEG_RX[8] PEG_CRX_GTX_P9 VSS192 VSS265
16 FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35 L6 VSS193 VSS266 C1
16 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 E17 E33 PEG_CRX_GTX_P10 L5 B22
FDI1_TX#[3] PEG_RX[10] PEG_CRX_GTX_P11 VSS194 VSS267
F32 L4 B19

16 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 A22 FDI0_TX[0]


PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
D34
E31
PEG_CRX_GTX_P12
PEG_CRX_GTX_P13
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
16 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 G19 C33 PEG_CRX_GTX_P14 L1 B13
C FDI_CTX_PRX_P2 FDI0_TX[1] PEG_RX[14] PEG_CRX_GTX_P15 VSS198 VSS271 C
16 FDI_CTX_PRX_P2 E20 FDI0_TX[2] PEG_RX[15] B32 K35 VSS199 VSS272 B11
16 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 G18 K32 B9
FDI_CTX_PRX_P4 FDI0_TX[3] PEG_CTX_GRX_C_N0 VSS200 VSS273
16 FDI_CTX_PRX_P4 B20 FDI1_TX[0] PEG_TX#[0] M29 K29 VSS201 VSS274 B8
16 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 C19 M32 PEG_CTX_GRX_C_N1 K26 B7
FDI_CTX_PRX_P6 FDI1_TX[1] PEG_TX#[1] PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_P0 CC49 2 PEG_CTX_GRX_P0 VSS202 VSS275
16 FDI_CTX_PRX_P6 D19 M31 1 0.22U_0402_16V7K~D J34 B5
FDI_CTX_PRX_P7 FDI1_TX[2] PEG_TX#[2] PEG_CTX_GRX_C_N3 PEG_CTX_GRX_C_N0 CC33 2 PEG_CTX_GRX_N0 VSS203 VSS276
16 FDI_CTX_PRX_P7 F17 FDI1_TX[3] PEG_TX#[3] L32 1 0.22U_0402_16V7K~D J31 VSS204 VSS277 B3
L29 PEG_CTX_GRX_C_N4 H33 B2
FDI_FSYNC0 PEG_TX#[4] PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_P1 CC50 2 PEG_CTX_GRX_P1 VSS205 VSS278
16 FDI_FSYNC0 J18 K31 1 0.22U_0402_16V7K~D H30 A35
FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PEG_CTX_GRX_C_N6 PEG_CTX_GRX_C_N1 CC34 2 PEG_CTX_GRX_N1 VSS206 VSS279
16 FDI_FSYNC1 J17 K28 1 0.22U_0402_16V7K~D H27 A32
FDI1_FSYNC PEG_TX#[6] PEG_CTX_GRX_C_N7 VSS207 VSS280
J30 H24 A29
FDI_INT PEG_TX#[7] PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_P2 CC51 2 PEG_CTX_GRX_P2 VSS208 VSS281
16 FDI_INT H20 J28 1 0.22U_0402_16V7K~D H21 A26
FDI_INT PEG_TX#[8] PEG_CTX_GRX_C_N9 PEG_CTX_GRX_C_N2 CC35 2 PEG_CTX_GRX_N2 VSS209 VSS282
H29 1 0.22U_0402_16V7K~D H18 A23
FDI_LSYNC0 PEG_TX#[9] PEG_CTX_GRX_C_N10 VSS210 VSS283
16 FDI_LSYNC0 J19 G27 H15 A20
FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_P3 CC52 2 PEG_CTX_GRX_P3 VSS211 VSS284
16 FDI_LSYNC1 H17 E29 1 0.22U_0402_16V7K~D H13 A3
FDI1_LSYNC PEG_TX#[11] PEG_CTX_GRX_C_N12 PEG_CTX_GRX_C_N3 CC36 2 PEG_CTX_GRX_N3 VSS212 VSS285
PEG_TX#[12]
F27 1 0.22U_0402_16V7K~D H10
VSS213
(1) EDP_COMPIO use 4mil trace to RC1 D28 PEG_CTX_GRX_C_N13 H9
PEG_TX#[13] PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_P4 CC53 2 PEG_CTX_GRX_P4 VSS214
F26 1 0.22U_0402_16V7K~D H8
(2) EDP_ICOMPO use 12mil to RC1 PEG_TX#[14] PEG_CTX_GRX_C_N15 PEG_CTX_GRX_C_N4 CC37 2 PEG_CTX_GRX_N4 VSS215
E25 1 0.22U_0402_16V7K~D H7
EDP_COMP PEG_TX#[15] VSS216
A18 H6
eDP_COMPIO PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P5 CC54 2 PEG_CTX_GRX_P5 VSS217
A17 M28 1 0.22U_0402_16V7K~D H5
eDP_ICOMPO PEG_TX[0] PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N5 CC38 2 PEG_CTX_GRX_N5 VSS218
B16
eDP_HPD PEG_TX[1]
M33 1 0.22U_0402_16V7K~D H4
VSS219
M30 PEG_CTX_GRX_C_P2 H3
PEG_TX[2] PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P6 CC55 2 PEG_CTX_GRX_P6 VSS220
L31 1 0.22U_0402_16V7K~D H2
PEG_TX[3] PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N6 CC39 2 PEG_CTX_GRX_N6 VSS221
C15 L28 1 0.22U_0402_16V7K~D H1
eDP_AUX PEG_TX[4] PEG_CTX_GRX_C_P5 VSS222
D15 K30 G35
eDP_AUX# PEG_TX[5] VSS223
eDP

K27 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P7 CC56 2 1 0.22U_0402_16V7K~D PEG_CTX_GRX_P7 G32


PEG_TX[6] PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N7 CC40 2 PEG_CTX_GRX_N7 VSS224
J29 1 0.22U_0402_16V7K~D G29
PEG_TX[7] PEG_CTX_GRX_C_P8 VSS225
C17 J27 G26
eDP_TX[0] PEG_TX[8] PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P8 CC57 1 PEG_CTX_GRX_P8 VSS226
F16
eDP_TX[1] PEG_TX[9]
H28 2 0.22U_0402_16V7K~D G23
VSS227
C16 G28 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N8 CC41 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N8 G20
eDP_TX[2] PEG_TX[10] PEG_CTX_GRX_C_P11 VSS228
G15 E28 G17
eDP_TX[3] PEG_TX[11] PEG_CTX_GRX_C_P12 PEG_CTX_GRX_C_P9 CC58 1 PEG_CTX_GRX_P9 VSS229
F28 2 0.22U_0402_16V7K~D G11
B PEG_TX[12] PEG_CTX_GRX_C_P13 PEG_CTX_GRX_C_N9 CC42 1 PEG_CTX_GRX_N9 VSS230 B
C18
eDP_TX#[0] PEG_TX[13]
D27 2 0.22U_0402_16V7K~D F34
VSS231
E16 E26 PEG_CTX_GRX_C_P14 F31
eDP_TX#[1] PEG_TX[14] PEG_CTX_GRX_C_P15 PEG_CTX_GRX_C_P10 CC59 1 PEG_CTX_GRX_P10 VSS232
D16
eDP_TX#[2] PEG_TX[15]
D25 2 0.22U_0402_16V7K~D F29
VSS233
F15 PEG_CTX_GRX_C_N10 CC43 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N10
eDP_TX#[3]
PEG_CTX_GRX_C_P11 CC60 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P11
Sandy Bridge_rPGA_Rev1p0 PEG_CTX_GRX_C_N11 CC44 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N11

PEG_CTX_GRX_C_P12 CC61 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P12


PEG_CTX_GRX_C_N12 CC45 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N12

PEG_CTX_GRX_C_P13 CC62 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P13


PEG_CTX_GRX_C_N13 CC46 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N13 Sandy Bridge_rPGA_Rev1p0

PEG Compensation PEG_CTX_GRX_C_P14 CC63 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P14


DP Compensation PEG_CTX_GRX_C_N14 CC47 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N14

+1.05V_RUN_VTT PEG_CTX_GRX_C_P15 CC64 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_P15


+1.05V_RUN_VTT PEG_CTX_GRX_C_N15 CC48 1 2 0.22U_0402_16V7K~D PEG_CTX_GRX_N15
1
1

RC2
RC1 24.9_0402_1%~D
24.9_0402_1%~D
2
2

PEG_COMP
EDP_COMP

eDP_COMPIO and ICOMPO signals should be shorted near PEG_ICOMPI and RCOMPO signals should be shorted and routed
A A
balls and routed with typical impedance <25 mohms with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (1/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 6 of 75
5 4 3 2 1
5 4 3 2 1

Follow DG Rev0.71 SM_DRAMPWROK topology


WWW.AliSaler.Com +3.3V_ALW_PCH
+1.5V_CPU_VDDQ
+3.3V_ALW_PCH
+1.05V_RUN_VTT

1
+1.05V_RUN_VTT +1.05V_RUN_VTT

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
CC1561 2 1 1

1
RC12

CC65

CC66
UC2 200_0402_5%~D @ RC124 @JXDP1
@ JXDP1
1 B 1K_0402_5%~D 1 2

P
41,42 RUNPWROK

2
RUNPWROK_AND 2 2 GND0 GND1
4 1 2 PM_DRAM_PWRGD_CPU XDP_PREQ# 3 4 CFG16 CFG16 9
O RC28 130_0402_5%~D XDP_PRDY# OBSFN_A0 OBSFN_C0 CFG17
+3.3V_ALW_PCH 1 2 2 5 6 CFG17 9

2
A OBSFN_A1 OBSFN_C1

2
RC18 200_0402_5%~D 7 8
74AHC1G09GW_TSSOP5~D RC64 SYS_PWROK_XDP XDP_OBS0 GND2 GND3 CFG0
16 PM_DRAM_PWRGD 9 10 CFG0 9

3
39_0402_5%~D XDP_OBS1 OBSDATA_A0 OBSDATA_C0 CFG1
Place near JXDP1 11
OBSDATA_A1 OBSDATA_C1
12 CFG1 9
13 14
D XDP_OBS2 GND4 GND5 CFG2 D
15 16 CFG2 9

1 1
XDP_OBS3 OBSDATA_A2 OBSDATA_C2 CFG3
17 18 CFG3 9
D OBSDATA_A3 OBSDATA_C3
19 20
QC1 CFG10 GND6 GND7 CFG8
11,44 RUN_ON_CPU1.5VS3# 2 9 CFG10 21 22 CFG8 9
G SSM3K7002FU_SC70-3~D CFG11 OBSFN_B0 OBSFN_D0 CFG9
9 CFG11 23 24 CFG9 9
OBSFN_B1 OBSFN_D1
S 25 26

3
XDP_OBS4 GND8 GND9 CFG4
27 28 CFG4 9
XDP_OBS5 OBSDATA_B0 OBSDATA_D0 CFG5
29 30 CFG5 9
OBSDATA_B1 OBSDATA_D1
The resistor for HOOK2 should beplaced 31 32
XDP_OBS6 GND10 GND11 CFG6
such that the stub is very small on CFG0 net 33
OBSDATA_B2 OBSDATA_D2
34 CFG6 9
XDP_OBS7 35 36 CFG7 CFG7 9
OBSDATA_B3 OBSDATA_D3
37 GND12 GND13 38
H_CPUPWRGD 1 2 H_CPUPWRGD_XDP 39 40 CLK_XDP
RC51 CFD_PWRBTN#_XDP PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_XDP#
14,16 SIO_PWRBTN#_R 2 1K_0402_5%~D 41 42
@ RC6 0_0402_5%~D HOOK1 ITPCLK#/HOOK5
43 VCC_OBS_AB VCC_OBS_CD 44
CFG0 1 2 XDP_HOOK2 45 46 XDP_RST#_R
+1.05V_RUN_VTT RC71 SYS_PWROK_XDP HOOK2 RESET#/HOOK6 XDP_DBRESET#
16,41 SYS_PWROK 2 1K_0402_5%~D 47 HOOK3 DBR#/HOOK7 48
@ RC9 0_0402_5%~D 49 50
DDR_XDP_WAN_SMBDAT_R1 GND14 GND15 XDP_TDO
12,13,14,15,28,36 DDR_XDP_WAN_SMBDAT 1 2 51 SDA TD0 52
1 2 H_THERMTRIP# RC1251 2 0_0402_5%~D DDR_XDP_WAN_SMBCLK_R1 53 54 XDP_TRST#
12,13,14,15,28,36 DDR_XDP_WAN_SMBCLK SCL TRST# XDP_TDI
@ RC126 56_0402_5%~D RC127 0_0402_5%~D 55 56
H_CATERR# XDP_TCLK TCK1 TDI XDP_TMS
1 2 57 TCK0 TMS 58
@ RC128 49.9_0402_1%~D 59 60
H_PROCHOT# GND16 GND17
1 2
RC44 62_0402_5%~D JCPU1B Keep R1132, R1133, R1136-R119 SAMTE_BSH-030-01-L-D-A
for slew rate control.

BCLK A28 CPU_DMI @ RC13 1 2 0_0402_5%~D CLK_CPU_DMI 15

MISC

CLOCKS
C26 A27 CPU_DMI# @ RC15 1 2 0_0402_5%~D
PROC_SELECT# BCLK# CLK_CPU_DMI# 15
XDP_RST#_R 2 1 PLTRST_XDP# 17
RC8 1K_0402_5%~D
C C
41 CPU_DETECT# AN34 SKTOCC#
DPLL_REF_CLK A16 CPU_DPLL @ RC16 1 2 0_0402_5%~D CLK_CPU_DPLL 15
A15 CPU_DPLL# @RC17 1 2 0_0402_5%~D
DPLL_REF_CLK# CLK_CPU_DPLL# 15
1 2 CLK_XDP 1 2
H_CATERR# @ CLK_CPU_ITP 15
AL33 @ RC48
@RC48 0_0402_5%~D RH107 0_0402_5%~D
CATERR# CLK_XDP# 1 2 CLK_CPU_ITP# 15
@ RH106 0_0402_5%~D
THERMAL

D
AN33 R8 DDR3_DRAMRST#_CPU 3 1
18 H_PECI PECI SM_DRAMRST# DDR3_DRAMRST# 12
DDR3
MISC
QC2
Max 500mils BSS138W-7-F_SOT323-3~D

G
9 CLK_XDP_ITP 1 2

2
1
42,58,60 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 @ RH109 0_0402_5%~D
RC57 56_0402_5%~D PROCHOT# SM_RCOMP[0] SM_RCOMP1 RC50
A5 9 CLK_XDP_ITP# 1 2
Close to JCBU1 SM_RCOMP[1] SM_RCOMP2 4.99K_0402_1%~D DDR_HVREF_RST @ RH108 0_0402_5%~D
A4
SM_RCOMP[2]

22 H_THERMTRIP# 1 2 H_THERMTRIP#_R AN32 SM_RCOMP2 --> 15mil 1

2
@ RC129 0_0402_5%~D THERMTRIP#
SM_RCOMP1/0 --> 20mil CC177
place RC129 near CPU 0.047U_0402_16V4Z~D
2
AP29 XDP_PRDY#
PRDY# XDP_PREQ#
AP27
PREQ#
AR26 XDP_TCLK 1 2
TCK 15 DDR_HVREF_RST_PCH
PWR MANAGEMENT

AR27 XDP_TMS @ RC46 0_0402_5%~D


JTAG & BPM

H_PM_SYNC TMS XDP_TRST#


16 H_PM_SYNC AM34
PM_SYNC TRST#
AP30 42 DDR_HVREF_RST_GATE 1 2 PU/PD for JTAG signals
@RC47
@ RC47 0_0402_5%~D
AR28 XDP_TDI_R +3.3V_RUN
TDI XDP_TDO_R
AP26
VCCPWRGOOD_0_R TDO
18 H_CPUPWRGD 1 2 AP33
B @ RC25 UNCOREPWRGOOD XDP_DBRESET# B
0_0402_5%~D 2 1
RC19 1K_0402_5%~D
AL35 XDP_DBRESET#_R 2 1 XDP_DBRESET# XDP_DBRESET# 14,16
PM_DRAM_PWRGD_CPU DBR# @ RC26 0_0402_5%~D +1.05V_RUN_VTT
V8
SM_DRAMPWROK
AT28 XDP_OBS0_R 1 2 XDP_OBS0 XDP_TMS RC27 2 1 51_0402_1%~D
BPM#[0] XDP_OBS1_R @ RC30 0_0402_5%~D XDP_OBS1 XDP_TDI_R XDP_TDI
AR29 1 2 1 2
BPM#[1] XDP_OBS2_R @ RC31 0_0402_5%~D XDP_OBS2 @ RC23 0_0402_5%~D XDP_TDI_R RC29 2
BPM#[2]
AR30 1 2 1 51_0402_1%~D
PCH_PLTRST#_R AR33 AT30 XDP_OBS3_R @ RC33 1 2 0_0402_5%~D XDP_OBS3
RESET# BPM#[3] XDP_OBS4_R @ RC34 0_0402_5%~D XDP_OBS4 XDP_PREQ# @ RC32 2
BPM#[4]
AP32 1 2 1 51_0402_1%~D
AR31 XDP_OBS5_R @ RC36 1 2 0_0402_5%~D XDP_OBS5 XDP_TDO_R 1 2 XDP_TDO
BPM#[5] XDP_OBS6_R @ RC37 0_0402_5%~D XDP_OBS6 0_0402_5%~D XDP_TDO RC35 2
AT31 1 2 @ RC24 1 51_0402_1%~D
BPM#[6] XDP_OBS7_R @ RC38 0_0402_5%~D XDP_OBS7
AR32 1 2
BPM#[7] @ RC39 0_0402_5%~D
For ESD concern, please put near CPU XDP_TCLK RC40 2 1
51_0402_1%~D
Sandy Bridge_rPGA_Rev1p0 XDP_TRST# RC41 2 1
51_0402_1%~D

Buffered reset to CPU VCCPWRGOOD_0_R


+3.3V_RUN +1.05V_RUN_VTT SM_RCOMP2
SM_RCOMP1
1
0.1U_0402_16V4Z~D

SM_RCOMP0
1 RC130
1
75_0402_1%~D
RC4

10K_0402_5%~D

1
CC140

140_0402_1%~D

25.5_0402_1%~D

200_0402_1%~D
RC42

RC43

RC45
2

2
2
5

UC1

2
A A
1
P

NC PCH_PLTRST#_BUF
Y 4 1 2 PCH_PLTRST#_R
14,17 PCH_PLTRST# 2 RC10 43_0402_5%~D Avoid stub in the PWRGD path
A
G

while placing resistors RC25 & RC130


DELL CONFIDENTIAL/PROPRIETARY
1
3

SN74LVC1G07DCKR_SC70-5~D @ RC11
Open drain buffer 0_0402_5%~D
Compal Electronics, Inc.
2

Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Sandy Bridge (2/6)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD

WWW.AliSaler.Com
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6592P
Date: Thursday, January 13, 2011 Sheet 7 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
JCPU1D
JCPU1C

AE2 M_CLK_DDR2
D M_CLK_DDR0 13 DDR_B_D[0..63] SB_CLK[0] M_CLK_DDR#2 M_CLK_DDR2 13 D
12 DDR_A_D[0..63] AB6 M_CLK_DDR0 12 AD2 M_CLK_DDR#2 13
SA_CLK[0] M_CLK_DDR#0 DDR_B_D0 SB_CLK#[0] DDR_CKE2_DIMMB
AA6 M_CLK_DDR#0 12 C9 R9 DDR_CKE2_DIMMB 13
DDR_A_D0 SA_CLK#[0] DDR_CKE0_DIMMA DDR_B_D1 SB_DQ[0] SB_CKE[0]
C5 V9 DDR_CKE0_DIMMA 12 A7
DDR_A_D1 SA_DQ[0] SA_CKE[0] DDR_B_D2 SB_DQ[1]
D5 D10
DDR_A_D2 SA_DQ[1] DDR_B_D3 SB_DQ[2]
D3 C8
DDR_A_D3 SA_DQ[2] DDR_B_D4 SB_DQ[3] M_CLK_DDR3
D2 A9 AE1 M_CLK_DDR3 13
DDR_A_D4 SA_DQ[3] M_CLK_DDR1 DDR_B_D5 SB_DQ[4] SB_CLK[1] M_CLK_DDR#3
D6 AA5 M_CLK_DDR1 12 A8 AD1 M_CLK_DDR#3 13
DDR_A_D5 SA_DQ[4] SA_CLK[1] M_CLK_DDR#1 DDR_B_D6 SB_DQ[5] SB_CLK#[1] DDR_CKE3_DIMMB
C6 AB5 M_CLK_DDR#1 12 D9 R10 DDR_CKE3_DIMMB 13
DDR_A_D6 SA_DQ[5] SA_CLK#[1] DDR_CKE1_DIMMA DDR_B_D7 SB_DQ[6] SB_CKE[1]
C2 V10 DDR_CKE1_DIMMA 12 D8
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_B_D8 SB_DQ[7]
C3 G4
DDR_A_D8 SA_DQ[7] DDR_B_D9 SB_DQ[8]
F10 F4
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F8 SA_DQ[9] F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D10 G10 AB4 DDR_B_D11 G1 AA2
DDR_A_D11 SA_DQ[10] RSVD_TP[1] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G9 SA_DQ[11] RSVD_TP[2] AA4 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D12 F9 W9 DDR_B_D13 F5
DDR_A_D13 SA_DQ[12] RSVD_TP[3] DDR_B_D14 SB_DQ[13]
F7 SA_DQ[13] F2 SB_DQ[14]
DDR_A_D14 G8 DDR_B_D15 G2
DDR_A_D15 SA_DQ[14] DDR_B_D16 SB_DQ[15]
G7 SA_DQ[15] J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D16 K4 AB3 DDR_B_D17 J8 AB1
DDR_A_D17 SA_DQ[16] RSVD_TP[4] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
K5 SA_DQ[17] RSVD_TP[5] AA3 K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D18 K1 W10 DDR_B_D19 K9
DDR_A_D19 SA_DQ[18] RSVD_TP[6] DDR_B_D20 SB_DQ[19]
J1 SA_DQ[19] J9 SB_DQ[20]
DDR_A_D20 J5 DDR_B_D21 J10
DDR_A_D21 SA_DQ[20] DDR_B_D22 SB_DQ[21] DDR_CS2_DIMMB#
J4 SA_DQ[21] K8 SB_DQ[22] SB_CS#[0] AD3 DDR_CS2_DIMMB# 13
DDR_A_D22 J2 AK3 DDR_CS0_DIMMA# DDR_B_D23 K7 AE3 DDR_CS3_DIMMB#
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# 12 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# 13
DDR_A_D23 K2 AL3 DDR_CS1_DIMMA# DDR_B_D24 M5 AD6
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# 12 DDR_B_D25 SB_DQ[24] RSVD_TP[17]
M8 SA_DQ[24] RSVD_TP[7] AG1 N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D25 N10 AH1 DDR_B_D26 N2
DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D27 SB_DQ[26]
N8 SA_DQ[26] N1 SB_DQ[27]
DDR_A_D27 N7 DDR_B_D28 M4
DDR_A_D28 SA_DQ[27] DDR_B_D29 SB_DQ[28] M_ODT2
M10 SA_DQ[28] N5 SB_DQ[29] SB_ODT[0] AE4 M_ODT2 13

DDR SYSTEM MEMORY B


DDR_A_D29 M9 AH3 M_ODT0 DDR_B_D30 M2 AD4 M_ODT3
C DDR_A_D30 SA_DQ[29] SA_ODT[0] M_ODT1 M_ODT0 12 DDR_B_D31 SB_DQ[30] SB_ODT[1] M_ODT3 13 C
N9 AG3 M1 AD5
DDR SYSTEM MEMORY A
DDR_A_D31 SA_DQ[30] SA_ODT[1] M_ODT1 12 DDR_B_D32 SB_DQ[31] RSVD_TP[19]
M7 SA_DQ[31] RSVD_TP[9] AG2 AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D32 AG6 AH2 DDR_B_D33 AM6
DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D34 SB_DQ[33]
AG5 SA_DQ[33] AR3 SB_DQ[34]
DDR_A_D34 AK6 DDR_B_D35 AP3
DDR_A_D35 SA_DQ[34] DDR_B_D36 SB_DQ[35]
AK5 SA_DQ[35] AN3 SB_DQ[36] DDR_B_DQS#[0..7] 13
DDR_A_D36 AH5 DDR_B_D37 AN2 D7 DDR_B_DQS#0
SA_DQ[36] DDR_A_DQS#[0..7] 12 SB_DQ[37] SB_DQS#[0]
DDR_A_D37 AH6 C4 DDR_A_DQS#0 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D38 SA_DQ[37] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ5 G6 AP2 K6
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ6 J3 AP5 N3
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D41 SB_DQ[40] SB_DQS#[3] DDR_B_DQS#4
AJ8 M6 AN9 AN5
DDR_A_D41 SA_DQ[40] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AK8 AL6 AT5 AP9
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AJ9 AM8 AT6 AK12
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AK9 AR12 AP6 AP15
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH8 AM15 AN8
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D46 SB_DQ[45]
AH9 AR6
DDR_A_D46 SA_DQ[45] DDR_B_D47 SB_DQ[46]
AL9 AR5
DDR_A_D47 SA_DQ[46] DDR_B_D48 SB_DQ[47]
AL8 AR9 DDR_B_DQS[0..7] 13
DDR_A_D48 SA_DQ[47] DDR_B_D49 SB_DQ[48] DDR_B_DQS0
AP11 DDR_A_DQS[0..7] 12 AJ11 C7
DDR_A_D49 SA_DQ[48] DDR_A_DQS0 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AN11 D4 AT8 G3
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AL12 F6 AT9 J6
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM12 K3 AH11 M3
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AM11 N6 AR8 AN6
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AL11 AL5 AJ12 AP8
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AP12 AM9 AH12 AK11
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AN12 AR11 AT11 AP14
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D57 SB_DQ[56] SB_DQS[7]
AJ14 AM14 AN14
DDR_A_D57 SA_DQ[56] SA_DQS[7] DDR_B_D58 SB_DQ[57]
AH14 AR14
DDR_A_D58 SA_DQ[57] DDR_B_D59 SB_DQ[58]
AL15 AT14 DDR_B_MA[0..15] 13
DDR_A_D59 SA_DQ[58] DDR_B_D60 SB_DQ[59]
AK15 DDR_A_MA[0..15] 12 AT12
DDR_A_D60 SA_DQ[59] DDR_B_D61 SB_DQ[60] DDR_B_MA0
AL14 AN15 AA8
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AK14 AD10 AR15 T7
B DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2 B
AJ15 W1 AT15 R7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 SB_DQ[63] SB_MA[2] DDR_B_MA3
AH15 W2 T6
SA_DQ[63] SA_MA[2] DDR_A_MA3 SB_MA[3] DDR_B_MA4
W7 T2
SA_MA[3] DDR_A_MA4 SB_MA[4] DDR_B_MA5
V3 T4
SA_MA[4] DDR_A_MA5 SB_MA[5] DDR_B_MA6
V2 T3
SA_MA[5] DDR_A_MA6 DDR_B_BS0 SB_MA[6] DDR_B_MA7
W3 13 DDR_B_BS0 AA9 R2
DDR_A_BS0 SA_MA[6] DDR_A_MA7 DDR_B_BS1 SB_BS[0] SB_MA[7] DDR_B_MA8
12 DDR_A_BS0 AE10 W6 13 DDR_B_BS1 AA7 T5
DDR_A_BS1 SA_BS[0] SA_MA[7] DDR_A_MA8 DDR_B_BS2 SB_BS[1] SB_MA[8] DDR_B_MA9
12 DDR_A_BS1 AF10 V1 13 DDR_B_BS2 R6 R3
DDR_A_BS2 SA_BS[1] SA_MA[8] DDR_A_MA9 SB_BS[2] SB_MA[9] DDR_B_MA10
12 DDR_A_BS2 V6 W5 AB7
SA_BS[2] SA_MA[9] DDR_A_MA10 SB_MA[10] DDR_B_MA11
AD8 R1
SA_MA[10] DDR_A_MA11 SB_MA[11] DDR_B_MA12
V4 T1
SA_MA[11] DDR_A_MA12 DDR_B_CAS# SB_MA[12] DDR_B_MA13
W4 13 DDR_B_CAS# AA10 AB10
DDR_A_CAS# SA_MA[12] DDR_A_MA13 DDR_B_RAS# SB_CAS# SB_MA[13] DDR_B_MA14
12 DDR_A_CAS# AE8 AF8 13 DDR_B_RAS# AB8 R5
DDR_A_RAS# SA_CAS# SA_MA[13] DDR_A_MA14 DDR_B_WE# SB_RAS# SB_MA[14] DDR_B_MA15
12 DDR_A_RAS# AD9 V5 13 DDR_B_WE# AB9 R4
DDR_A_WE# SA_RAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[15]
12 DDR_A_WE# AF9 V7
SA_WE# SA_MA[15]

Sandy Bridge_rPGA_Rev1p0
Sandy Bridge_rPGA_Rev1p0

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (3/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 8 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com CFG Straps for Processor

CFG2

1
@RC51
@ RC51
1K_0402_5%~D

2
D JCPU1E D

L7 @ T1 PAD~D
RSVD28 @ T2 PAD~D
AG7
CFG0 RSVD29 @ T3 PAD~D
7 CFG0 AK28 AE7
CFG1 CFG[0] RSVD30 @ T4 PAD~D
7 CFG1 AK29
CFG[1] RSVD31
AK2 PEG Static Lane Reversal - CFG2 is for the 16x
CFG2 AL26 W8 @ T5 PAD~D
7 CFG2 CFG3 CFG[2] RSVD32
7 CFG3 AL27
CFG4 CFG[3]
7 CFG4 AK26
CFG[4] 1:(Default) Normal Operation; Lane #
CFG5 AL29 AT26 @ T6 PAD~D CFG2
7 CFG5 CFG6 AL30
CFG[5] RSVD33
AM33 @ T7 PAD~D
definition matches socket pin map definition
7 CFG6 CFG7 CFG[6] RSVD34
7 CFG7 AM31 CFG[7] RSVD35 AJ27 @ T8 PAD~D 0:Lane Reversed
CFG8 AM32
7 CFG8 CFG9 CFG[8]
7 CFG9 AM30 CFG[9]
CFG10 AM28
7 CFG10 CFG11 CFG[10] CFG4
7 CFG11 AM26 CFG[11]
@ T9 PAD~D CFG12 AN28 CFG[12]

1
@ T10 PAD~D CFG13 AN31 T8 @ T11 PAD~D
@ T12 PAD~D CFG14 CFG[13] RSVD37 @ T13 PAD~D @ RC52
AN26 CFG[14] RSVD38 J16
@ T14 PAD~D CFG15 AM27 H16 @ T15 PAD~D 1K_0402_5%~D
+VCC_GFXCORE CFG16 CFG[15] RSVD39 @ T16 PAD~D
7 CFG16 AK31 CFG[16] RSVD40 G16
CFG17 AN29
7 CFG17

2
RSVD1 CFG[17]
1 2 follow DG0.9 change to 1Kohm 5%
@RC122
@ RC122 49.9_0402_1%~D

AR35 @ T17 PAD~D


+VCC_CORE RSVD1 RSVD41 @ T18 PAD~D
AJ31 VAXG_VAL_SENSE RSVD42 AT34
RSVD2 AH31 AT33 @ T19 PAD~D
RSVD3 RSVD3 VSSAXG_VAL_SENSE RSVD43 @ T20 PAD~D
1 2 AJ33 VCC_VAL_SENSE RSVD44 AP35 Display Port Presence Strap
@RC120
@ RC120 49.9_0402_1%~D RSVD4 AH33 AR34 @ T21 PAD~D
VSS_VAL_SENSE RSVD45
C C
1 : Disabled; No Physical Display Port
1 2 RSVD2 @ T22 PAD~D AJ26 CFG4
RSVD5 attached to Embedded Display Port

RESERVED
@RC123
@ RC123 49.9_0402_1%~D
1 2 RSVD4
@RC121
@ RC121 49.9_0402_1%~D
RSVD46 B34 @ T23 PAD~D 0 : Enabled; An external Display Port device is
1 2 +DIMM0_1_VREF_CPU +DIMM0_1_VREF_CPU B4 A33 @ T24 PAD~D
@RC96
@ RC96 1K_0402_5%~D
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU D1 RSVD6 RSVD47
A34 @ T25 PAD~D
connected to the Embedded Display Port
+DIMM0_1_CA_CPU RSVD7 RSVD48
1 2 +DIMM0_1_CA_CPU B35 @ T26 PAD~D
@RC97
@ RC97 1K_0402_5%~D RSVD49 @ T27 PAD~D
C35
RSVD50
@ T28 PAD~D F25 CFG6
@ T29 PAD~D RSVD8
F24
@ T30 PAD~D RSVD9 CFG5
F23
@ T31 PAD~D RSVD10 @ T32 PAD~D
D24 AJ32
RSVD11 RSVD51

1
@ T33 PAD~D G25 AK32 @ T34 PAD~D
@ T35 PAD~D RSVD12 RSVD52 @ RC54 @ RC53
G24
@ T36 PAD~D RSVD13 1K_0402_5%~D 1K_0402_5%~D
E23
@ T37 PAD~D RSVD14
D23
@ T38 PAD~D RSVD15 @ T39 PAD~D
C30 AH27

2
@ T40 PAD~D RSVD16 VCC_DIE_SENSE
A31
@ T41 PAD~D RSVD17
B30
@ T42 PAD~D RSVD18
B29
@ T43 PAD~D RSVD19
D30 AN35 CLK_XDP_ITP 7
@ T44 PAD~D RSVD20 RSVD54
B31 AM35 CLK_XDP_ITP# 7
@ T45 PAD~D RSVD21 RSVD55
A30
@ T46 PAD~D RSVD22
C29
RSVD23
PCIE Port Bifurcation Straps
@ T47 PAD~D J20
@ T48 PAD~D RSVD24 @ T49 PAD~D
B18 AT2
RSVD25 RSVD56
@ T155 PAD~D A19
VCCIO_SEL RSVD57
AT1 @ T50 PAD~D 11: (Default) x16 - Device 1 functions 1 and 2 disabled
AR1 @ T51 PAD~D
B RSVD58 B
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
@ T52 PAD~D J15
RSVD27 disabled
01: Reserved - (Device 1 function 1 disabled ; function
B1 @ T53 PAD~D
KEY 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Sandy Bridge_rPGA_Rev1p0 CFG7

1
@ RC56
1K_0402_5%~D

2
PEG DEFER TRAINING

1: (Default) PEG Train immediately


CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (4/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 9 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com JCPU1F POWER


+1.05V_RUN_VTT
+VCC_CORE +VCC_CORE

53AAG35 8.5A
VCC1
AG34 VCC2 VCCIO1 AH13

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D
1 1 1 1 1 AG33 AH10
VCC3 VCCIO2
AG32 AG10
CC67 CC75 CC76 CC77 VCC4 VCCIO3
CC68 AG31 AC10 1 1 1 1 1 1 1 1 1 1 1
D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D VCC5 VCCIO4 D
AG30 Y10
2 2 2 2 2 VCC6 VCCIO5

CC78

CC69

CC79

CC80

CC81

CC82

CC83

CC84

CC85

CC70

CC86
AG29 U10
VCC7 VCCIO6
AG28 P10
VCC8 VCCIO7 2 2 2 2 2 2 2 2 2 2 2
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 J13
VCC11 VCCIO10
AF34 J12
VCC12 VCCIO11
1 1 1 1 1 AF33 J11
VCC13 VCCIO12
AF32 H14
CC87 CC71 CC72 CC88 CC73 VCC14 VCCIO13
AF31 H12
VCC15 VCCIO14

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D
10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D AF30 H11
2 2 2 2 2 VCC16 VCCIO15
AF29 VCC17 VCCIO16 G14 1 1 1
AF28 VCC18 VCCIO17 G13 1 1 1 1 1

PEG AND DDR

@ CC90

@ CC91

@ CC92

@ CC93

CC107

CC108

CC109
AF27 G12 + + + @
VCC19 VCCIO18

CC89
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 F12 2 2 2 2 2 2 2 2
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
+VCC_CORE AC34 C14
VCC32 VCCIO30
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
1 1 1 1 1 AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
C CC110 CC111 CC112 CC113 CC114 C
AC28 VCC38 VCCIO36 A14
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D AC27 A13
2 2 2 2 2 VCC39 VCCIO37
AC26 VCC40 VCCIO38 A12
+1.05V_RUN_VTT
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23

1
AA32 VCC44
AA31 Note: Place the PU resistors close to CPU RC60
VCC45 75_0402_1%~D
1 1 1 1 1 AA30
VCC46 R1555 close to CPU 300 - 1500mils
AA29
CC115 CC116 CC117 CC118 VCC47
CC119 AA28

2
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D VCC48
AA27
2 2 2 2 2 VCC49 H_CPU_SVIDALRT#
AA26 1 2 VIDALERT_N 58
VCC50

CORE SUPPLY
Y35 RC61 43_0402_5%~D
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55 +1.05V_RUN_VTT
1 1 1 1 1 Y30
VCC56
Y29
CC120 CC121 CC122 CC123 CC124 VCC57 CAD Note: Place the PU
Y28
VCC58

1
22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D Y27 resistors close to CPU
2 2 2 2 2 VCC59 RC63
Y26 R1558 close to CPU 300 - 1500mils
VCC60 130_0402_1%~D
V35
VCC61

SVID
V34 AJ29 H_CPU_SVIDALRT#
VCC62 VIDALERT# VIDSCLK
V33 AJ30 VIDSCLK 58

2
VCC63 VIDSCLK VIDSOUT Iccmax current changed for PDDG Rev0.7
V32 AJ28 VIDSOUT 58
VCC64 VIDSOUT
V31
VCC65
1 V30
V29
VCC66 CPU Power Rail Table
VCC67 SVID note: VIDALERT# trace
CC125 V28
VCC68
S0 Iccmax
22U_0805_6.3VAM~D V27
VCC69 routing need to be routed between Voltage Rail Voltage Current (A)
B 2 V26 B
VCC70 VIDSCLK and VIDSOUT signals
U35
VCC71
U34
VCC72
VCC 0.65-1.3 53
U33
VCC73
U32
VCC74
U31
VCC75
VCCIO 1.05 8.5
U30
VCC76
U29
+VCC_CORE VCC77
U28
VCC78
VAXG 0.0-1.1 26
U27
VCC79
U26
VCC80 +VCC_CORE
R35
VCC81
VCCPLL 1.8 3
R34
VCC82
1 1 1 1 R33
VCC83

1
R32
VCC84
VDDQ 1.5 5
+ CC129 + @CC130 + CC131 + CC132 RC66
470U_D2_2V-M~D 470U_D2_2V-M~D 470U_D2_2V-M~D 470U_D2_2V-M~D
R31
VCC85 Place RC66, RC70near CPU
R30 100_0402_1%~D
VCC86
R29
VCC87
VCCSA 0.65-0.9 6
2 3 2 3 2 3 2 3
SENSE LINES

R28

2
VCC88 VCCSENSE_R
R27 AJ35 1 2 VCCSENSE 58
VCC89 VCC_SENSE VSSSENSE_R @ RC67 1
R26
VCC90 VSS_SENSE
AJ34 2 0_0402_5%~D VSSSENSE 58 +1.5V_MEM 1.5 12-16 *
P35 @ RC68 0_0402_5%~D
VCC91
P34
VCC92

1
P33
VCC93 VTT_SENSE_R RC70
P32 B10 1 2 VTT_SENSE 57
VCC94 VCCIO_SENSE VSSIO_SENSE_R @ RC1321
P31
VCC95 VSSIO_SENSE
A10 2 0_0402_5%~D VTT_GND 57 100_0402_1%~D * Description
1 1 P30 @ RC133 0_0402_5%~D
VCC96
P29 5A to Mem controller(+1.5V_CPU_VDDQ)

2
+ @CC133 + CC134 VCC97
P28 5-6A to 2 DIMMs/channel
470U_D2_2V-M~D 470U_D2_2V-M~D VCC98
P27
VCC99 2-5A to +1.5V_RUN & +0.75V_DDR_VTT
P26
2 3 2 3 VCC100
A A

DELL CONFIDENTIAL/PROPRIETARY
Sandy Bridge_rPGA_Rev1p0
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Sandy Bridge (5/6)
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev

WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6592P
Date: Thursday, January 13, 2011 Sheet 10 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +1.5V_CPU_VDDQ Source


+1.5V_MEM QC3 +1.5V_CPU_VDDQ
+3.3V_ALW2 +15V_ALW AO4728L_SO8~D
8 1
7 2

1
10U_0805_6.3V6M~D

20K_0402_5%~D
@ RC73
6 3 1

CC135
RC72 5

1
100K_0402_5%~D JCPU1H
RC74

4
100K_0402_5%~D 2 AT35 AJ22

2
VSS1 VSS81
AT32 AJ19
D RUN_ON_CPU1.5VS3 VSS2 VSS82 D
AT29 AJ16

2
VSS3 VSS83

3
AT27 AJ13
VSS4 VSS84
AT25 AJ10
QC4B VSS5 VSS85
1 AT22 AJ7
RUN_ON_CPU1.5VS3# DMN66D0LDW-7_SOT363-6~D VSS6 VSS86
5 AT19 AJ4
CC136 VSS7 VSS87
AT16 AJ3
4700P_0402_25V7K~D +V_DDR_REF QC5 +V_SM_VREF_CNT VSS8 VSS88
AT13 AJ2

4
2 NTR4503NT1G_SOT23-3~D VSS9 VSS89
AT10 AJ1
VSS10 VSS90

6
AT7 AH35
VSS11 VSS91
1 3 AT4 AH34
QC4A VSS12 VSS92
AT3 AH32
DMN66D0LDW-7_SOT363-6~D VSS13 VSS93
37,41,44,55,63 RUN_ON 1 2 2 AR25 VSS14 VSS94 AH30

1
@ RC77 0_0402_5%~D AR22 AH29
RC78 VSS15 VSS95
AR19 AH28

1
2 100K_0402_5%~D VSS16 VSS96
42 CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# 7,44 AR16 VSS17 VSS97 AH26
@ RC79 0_0402_5%~D AR13 AH25
VSS18 VSS98
1 2 AR10 AH22

2
@ RC134 0_0402_5%~D VSS19 VSS99
AR7 VSS20 VSS100 AH19
AR4 VSS21 VSS101 AH16
AR2 VSS22 VSS102 AH7
RUN_ON_CPU1.5VS3 AP34 AH4
+VCC_GFXCORE

JCPU1G
POWER AP31
AP28
AP25
VSS23
VSS24
VSS25
VSS103
VSS104
VSS105
AG9
AG8
AG4
VSS26 VSS106
AP22 VSS27 VSS107 AF6
26A AP19 VSS28 VSS108 AF5

SENSE
LINES
AT24 VAXG1 VAXG_SENSE AK35 VCC_AXG_SENSE 58 AP16 VSS29 VSS109 AF3
AT23 VAXG2 VSSAXG_SENSE AK34 VSS_AXG_SENSE 58 AP13 VSS30 VSS110 AF2
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1 1 1 1 1 1 1 1 AT21 VAXG3 AP10 VSS31 VSS111 AE35


CC137

CC138

CC144

CC145

CC146

CC147

CC139

CC148

AT20 VAXG4 AP7 VSS32 VSS112 AE34


AT18 VAXG5 AP4 VSS33 VSS113 AE33
AT17 VAXG6 AP1 VSS34 VSS114 AE32
C 2 2 2 2 2 2 2 2 AR24 AN30 AE31 C
VAXG7 CC1782 VSS35 VSS115
AR23 VAXG8 1 0.1U_0402_10V7K~D AN27 VSS36 VSS116 AE30
AR21 AN25 AE29
AR20
VAXG9
VAXG10
+V_SM_VREF_CNT AN22
VSS37
VSS38 VSS VSS117
VSS118 AE28

VREF
AR18 CC1792 1 0.1U_0402_10V7K~D AN19 AE27
VAXG11 VSS39 VSS119
AR17 VAXG12 AN16 VSS40 VSS120 AE26
AP24 VAXG13 SM_VREF AL1 AN13 VSS41 VSS121 AE9
AP23 CC1492 1 0.1U_0402_10V7K~D AN10 AD7
VAXG14 VSS42 VSS122
AP21 AN7 AC9
VAXG15 VSS43 VSS123
22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1 1 1 1 AP20
VAXG16
+V_SM_VREF should AN4
VSS44 VSS124
AC8
CC151

CC141

CC152

CC153

AP18 have 10 mil trace width CC1502 1 0.1U_0402_10V7K~D AM29 AC6


VAXG17 VSS45 VSS125
AP17 AM25 AC5
VAXG18 VSS46 VSS126
AN24 AM22 AC3
2 2 2 2 VAXG19 +1.5V_CPU_VDDQ VSS47 VSS127
AN23 AM19 AC2
VAXG20 @ PJP1 VSS48 VSS128
AN21 AM16 AB35
VAXG21 VSS49 VSS129
AN20 1 2 AM13 AB34
VAXG22 DDR3 -1.5V RAILS VSS50 VSS130
AN18 AM10 AB33
VAXG23 PAD-OPEN 4x4m VSS51 VSS131
AN17
VAXG24 5A AM7
VSS52 VSS132
AB32
GRAPHICS

AM24 AF7 +1.5V_MEM AM4 AB31


VAXG25 VDDQ1 @ PJP2 VSS53 VSS133
AM23 AF4 AM3 AB30
VAXG26 VDDQ2 VSS54 VSS134
AM21 AF1 1 2 AM2 AB29
VAXG27 VDDQ3 VSS55 VSS135

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

330U_D2_2VM_R6M~D
AM20 AC7 1 1 1 1 1 1 1 AM1 AB28
VAXG28 VDDQ4 PAD-OPEN 4x4m VSS56 VSS136
AM18 AC4 AL34 AB27
VAXG29 VDDQ5 VSS57 VSS137

CC161

CC162

CC163

CC164

CC165

CC166

CC167
AM17 AC1 + AL31 AB26
VAXG30 VDDQ6 VSS58 VSS138
AL24 Y7 AL28 Y9
VAXG31 VDDQ7 2 2 2 2 2 2 VSS59 VSS139
AL23 Y4 AL25 Y8
VAXG32 VDDQ8 2 VSS60 VSS140
AL21 Y1 AL22 Y6
VAXG33 VDDQ9 VSS61 VSS141
AL20 U7 AL19 Y5
VAXG34 VDDQ10 VSS62 VSS142
AL18 U4 AL16 Y3
VAXG35 VDDQ11 VSS63 VSS143
AL17 U1 AL13 Y2
VAXG36 VDDQ12 VSS64 VSS144
AK24 P7 AL10 W35
VAXG37 VDDQ13 VSS65 VSS145
AK23 P4 AL7 W34
B VAXG38 VDDQ14 VSS66 VSS146 B
AK21 P1 AL4 W33
VAXG39 VDDQ15 VSS67 VSS147
AK20 AL2 W32
VAXG40 VSS68 VSS148
AK18 AK33 W31
VAXG41 VSS69 VSS149
AK17 AK30 W30
VAXG42 VSS70 VSS150
AJ24 AK27 W29
VAXG43 VSS71 VSS151
AJ23 AK25 W28
VAXG44 VSS72 VSS152
AJ21 AK22 W27
VAXG45 VSS73 VSS153
AJ20 AK19 W26
VAXG46 VSS74 VSS154
AJ18 AK16 U9
VAXG47 VSS75 VSS155
AJ17 AK13 U8
VAXG48 VSS76 VSS156
AH24
6A AK10 U6
SA RAIL

VAXG49 VSS77 VSS157


AH23 AK7 U5
VAXG50 VSS78 VSS158
AH21 M27 +VCC_SA AK4 U3
VAXG51 VCCSA1 VSS79 VSS159
10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D
AH20 M26 AJ25 U2
VAXG52 VCCSA2 VSS80 VSS160
AH18 L26
VAXG53 VCCSA3
AH17 J26 1 1 1 1 1
VAXG54 VCCSA4

@ CC171
J25
VCCSA5
CC168

CC169

CC170
J24 + CC172
VCCSA6 330U_D2_2VM_R6M~D Sandy Bridge_rPGA_Rev1p0
H26
VCCSA7 2 2 2 2
H25
VCCSA8 2
1.8V RAIL

3A 1
@ RC137
2
0_0402_5%~D
+GND_VCC_SA 61

+1.8V_RUN B6 H23 +VCCSA_SENSE 61


VCCPLL1 VCCSA_SENSE
MISC

A6
VCCPLL2
10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

330U_D2_2.5VM_R6M~D

1 1 1 1 A2
VCCPLL3
CC173

CC174

CC175

CC176

+ C22 H_FC_C22
FC_C22
C24 1 2 VCCSA_VID_1 61
2 2 2 VCCSA_VID1
10K_0402_5%~D

@ RC138 0_0402_5%~D
1

A 2 A
RC83

Sandy Bridge_rPGA_Rev1p0

DELL CONFIDENTIAL/PROPRIETARY
2

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Sandy Bridge (6/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 11 of 75
5 4 3 2 1
5 4 3 2 1

1 2 +DIMM0_1_VREF_DQ +1.5V_MEM +1.5V_MEM 2-3A to 1 DIMMs/channel


WWW.AliSaler.Com
+V_DDR_REF
Note: @ RD1 0_0402_5%~D JDIMM1
1 2 1 2
Check voltage tolerance of +DIMM0_1_VREF_CPU VREF_DQ VSS
JDIMMA H=5.2

2.2U_0603_6.3V6K~D
@ RD7 0_0402_5%~D 3 4 DDR_A_D4
VSS DQ4
VREF_DQ at the DIMM socket DDR_A_D0 5 DQ0 DQ5 6 DDR_A_D5

0.1U_0402_16V4Z~D
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
1 1 9 VSS DQS0# 10
11 12 DDR_A_DQS0
DM0 DQS0

CD1

CD2
13 VSS VSS 14
DDR_A_D2 15 16 DDR_A_D6 +1.5V_MEM
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
8 DDR_A_DQS#[0..7]
All VREF traces should 19 VSS VSS 20
have 10 mil trace width DDR_A_D8 21 22 DDR_A_D12
DQ8 DQ12

1
DDR_A_D9 23 24 DDR_A_D13
8 DDR_A_D[0..63] DQ9 DQ13
25 26 RD27
D DDR_A_DQS#1 VSS VSS 1K_0402_1%~D D
8 DDR_A_DQS[0..7] 27 28
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30
DQS1 RESET#
8 DDR_A_MA[0..15] Populate RD1 for Intel DDR3 31 32

2
DDR_A_D10 VSS VSS DDR_A_D14
VREFDQ multiple methods M1 33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15 DDR3_DRAMRST#_R 1
35 36 13 DDR3_DRAMRST#_R 2 DDR3_DRAMRST# 7
DQ11 DQ15 RD28 1K_0402_1%~D
37 38
DDR_A_D16 VSS VSS DDR_A_D20
39 40
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 42
DQ17 DQ21
43 44
DDR_A_DQS#2 VSS VSS
Layout Note: 45
DQS2# DM2
46
DDR_A_DQS2 47 48
Place near JDIMMA 49
DQS2 VSS
50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60
+1.5V_MEM 61 62 DDR_A_DQS#3
VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DQ26 DQ30
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D27 69 70 DDR_A_D31
DQ27 DQ31
1 1 1 1 71 VSS VSS 72
CD3

CD4

CD5

CD6

DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
2 2 2 2 8 DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA 8
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
8 DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
C C
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
+1.5V_MEM 93 94
DDR_A_MA3 VDD VDD DDR_A_MA2
95 A3 A2 96
DDR_A_MA1 97 98 DDR_A_MA0
A1 A0
99 VDD VDD 100
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

M_CLK_DDR0 101 102 M_CLK_DDR1


8 M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 M_CLK_DDR1 8
8 M_CLK_DDR#0 103 104 M_CLK_DDR#1 8
CK0# CK1#
330U_SX_2VY~D

1 105 106
VDD VDD
@ CD13

1 1 1 1 1 1 1 DDR_A_MA10 107 108 DDR_A_BS1


A10/AP BA1 DDR_A_BS1 8
CD7

CD8

CD9

CD10

CD11

CD12

CD14

+ DDR_A_BS0 109 110 DDR_A_RAS#


8 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 8
111 112
DDR_A_WE# VDD VDD DDR_CS0_DIMMA#
8 DDR_A_WE# 113 114 DDR_CS0_DIMMA# 8
2 2 2 2 2 2 2 2 DDR_A_CAS# WE# S0# M_ODT0
8 DDR_A_CAS# 115 116 M_ODT0 8
CAS# ODT0
117 118
DDR_A_MA13 VDD VDD M_ODT1 +DIMM0_1_VREF_CA
119 120 M_ODT1 8
DDR_CS1_DIMMA# A13 ODT1
8 DDR_CS1_DIMMA# 121 122
S1# NC
123 124
VDD VDD
125 126 1 2 +V_DDR_REF
TEST VREF_CA @ RD29 0_0402_5%~D
127 128
VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_A_D32 129 130 DDR_A_D36
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132 1 2 +DIMM0_1_CA_CPU
DQ33 DQ37 @ RD31 0_0402_5%~D
133 134 1 1
VSS VSS

CD15

CD16
Layout Note: DDR_A_DQS#4 135 136
DDR_A_DQS4 DQS4# DM4
137 138
Place near JDIMMA.203,204 139
DQS4 VSS
140 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 142
DDR_A_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_A_D44
145 146
DDR_A_D40 VSS DQ44 DDR_A_D45
147 148
DDR_A_D41 DQ40 DQ45
149 150
B DQ41 VSS DDR_A_DQS#5 B
151 152
VSS DQS5# DDR_A_DQS5
153 154
+0.75V_DDR_VTT DM5 DQS5
155 156
DDR_A_D42 VSS VSS DDR_A_D46
157 158
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
161 162
DDR_A_D48 VSS VSS DDR_A_D52
163 164
DQ48 DQ52
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D49 165 166 DDR_A_D53


DQ49 DQ53
1 1 1 1 167 168
DDR_A_DQS#6 VSS VSS
169 170
DQS6# DM6
CD17

CD18

CD19

CD20

DDR_A_DQS6 171 172


DQS6 VSS DDR_A_D54
173 174
2 2 2 2 DDR_A_D50 VSS DQ54 DDR_A_D55
175 176
DDR_A_D51 DQ50 DQ55
177 178
DQ51 VSS DDR_A_D60
179 180
DDR_A_D56 VSS DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS DDR_A_DQS#7
185 186
VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS VSS DDR_A_D62
191 192
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 194
DQ59 DQ63
195 196
RD21 VSS VSS
2 10K_0402_5%~D 197
SA0 EVENT#
198
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT 7,13,14,15,28,36
VDDSPD SDA
1 2 201 202 DDR_XDP_WAN_SMBCLK 7,13,14,15,28,36
RD3 10K_0402_5%~D SA1 SCL
1 1 203 204 +0.75V_DDR_VTT
VTT VTT
0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

+0.75V_DDR_VTT
CD21

CD22

205 206
2 2 GND1 GND2
FOX_AS0A626-U4SN-7F
A CONN@ A

change footprint.

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 12 of 75
5 4 3 2 1
5 4 3 2 1

2-3A to 1 DIMMs/channel
WWW.AliSaler.Com All VREF traces should
have 10 mil trace width
+DIMM0_1_VREF_DQ +1.5V_MEM

1
JDIMM2
VREF_DQ VSS 2
+1.5V_MEM

3 4 DDR_B_D4
VSS DQ4
JDIMMB H=9.2

2.2U_0603_6.3V6K~D
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5

0.1U_0402_16V4Z~D
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
8 DDR_B_DQS#[0..7] 1 1 9 VSS DQS0# 10
11 12 DDR_B_DQS0
DM0 DQS0

CD23

CD24
8 DDR_B_D[0..63] Populate RD4 for Intel DDR3 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
VREFDQ multiple methods M1 2 2 DDR_B_D3 17
DQ2 DQ6
18 DDR_B_D7
8 DDR_B_DQS[0..7] DQ3 DQ7
19 20
DDR_B_D8 VSS VSS DDR_B_D12
8 DDR_B_MA[0..15] 21 22
D DDR_B_D9 DQ8 DQ12 DDR_B_D13 D
23 24
DQ9 DQ13
25 26
DDR_B_DQS#1 VSS VSS
27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#_R
29 30 DDR3_DRAMRST#_R 12
DQS1 RESET#
Note: 31
VSS VSS
32
DDR_B_D10 33 34 DDR_B_D14
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37
VSS VSS
38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 42
DQ17 DQ21
43 44
DDR_B_DQS#2 VSS VSS
45 DQS2# DM2 46
DDR_B_DQS2 47 48
DQS2 VSS DDR_B_D22
49 VSS DQ22 50
DDR_B_D18 51 52 DDR_B_D23
DDR_B_D19 DQ18 DQ23
53 DQ19 VSS 54
Layout Note: 55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 58
Place near JDIMMB DDR_B_D25 59
DQ24 DQ29
60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
+1.5V_MEM
DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB
8 DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB 8
75 VDD VDD 76
77 78 DDR_B_MA15
NC A15
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_B_BS2 79 80 DDR_B_MA14
8 DDR_B_BS2 BA2 A14
1 1 1 1 81 VDD VDD 82
C DDR_B_MA12 DDR_B_MA11 C
83 A12/BC# A11 84
CD25

CD26

CD27

CD28

DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 VDD VDD 88
2 2 2 2 DDR_B_MA8 DDR_B_MA6
89 A8 A6 90
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 98
A1 A0
99 100
M_CLK_DDR2 VDD VDD M_CLK_DDR3
8 M_CLK_DDR2 101 102 M_CLK_DDR3 8
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
8 M_CLK_DDR#2 103 104 M_CLK_DDR#3 8
+1.5V_MEM CK0# CK1#
105 106
DDR_B_MA10 VDD VDD DDR_B_BS1
107 108 DDR_B_BS1 8
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
8 DDR_B_BS0 109 110
BA0 RAS# DDR_B_RAS# 8
111 112
VDD VDD
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

330U_SX_2VY~D

DDR_B_WE# 113 114 DDR_CS2_DIMMB#


8 DDR_B_WE# DDR_B_CAS# WE# S0# M_ODT2 DDR_CS2_DIMMB# 8
8 DDR_B_CAS# 115 116 M_ODT2 8
CAS# ODT0
1 117 118
VDD VDD +DIMM0_1_VREF_CA
@ CD35

1 1 1 1 1 1 1 DDR_B_MA13 119 120 M_ODT3


A13 ODT1 M_ODT3 8
CD29

CD30

CD31

CD32

CD33

CD34

CD36

+ DDR_CS3_DIMMB# 121 122


8 DDR_CS3_DIMMB# S1# NC
123 124
VDD VDD
125 126
2 2 2 2 2 2 2 2 TEST VREF_CA
127 128
VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
DQ33 DQ37
133 134 1 1
DDR_B_DQS#4 VSS VSS
135 136
DQS4# DM4

CD37

CD38
DDR_B_DQS4 137 138
DQS4 VSS DDR_B_D38
139 140
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 142
DDR_B_D35 DQ34 DQ39
143 144
DQ35 VSS DDR_B_D44
145 146
B DDR_B_D40 VSS DQ44 DDR_B_D45 B
147 148
DDR_B_D41 DQ40 DQ45
Layout Note: 149
DQ41 VSS
150
151 152 DDR_B_DQS#5
Place near JDIMMB.203,204 153
VSS DQS5#
154 DDR_B_DQS5
DM5 DQS5
155 156
DDR_B_D42 VSS VSS DDR_B_D46
157 158
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS VSS DDR_B_D52
163 164
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 166
DQ49 DQ53
167 168
+0.75V_DDR_VTT DDR_B_DQS#6 VSS VSS
169 170
DDR_B_DQS6 DQS6# DM6
171 172
DQS6 VSS DDR_B_D54
173 174
DDR_B_D50 VSS DQ54 DDR_B_D55
175 176
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

179 180 DDR_B_D60


DDR_B_D56 VSS DQ60 DDR_B_D61
1 1 1 1 181 182
DDR_B_D57 DQ56 DQ61
183 184
DQ57 VSS
CD39

CD40

CD41

CD42

185 186 DDR_B_DQS#7


VSS DQS7# DDR_B_DQS7
187 188
2 2 2 2 DM7 DQS7
189 190
DDR_B_D58 VSS VSS DDR_B_D62
191 192
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 194
DQ59 DQ63
195 196
+3.3V_RUN VSS VSS
197 198
SA0 EVENT#
+3.3V_RUN 199 200 DDR_XDP_WAN_SMBDAT 7,12,14,15,28,36
VDDSPD SDA
2 1 201 202 DDR_XDP_WAN_SMBCLK 7,12,14,15,28,36
RD5 10K_0402_5%~D SA1 SCL
+0.75V_DDR_VTT 203 204 +0.75V_DDR_VTT
VTT VTT
1
10K_0402_5%~D
RD6

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

1 1 205 GND1 GND2 206


A A
CD43

CD44

FOX_AS0A626-U8SN-7F
2

CONN@
2 2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-SODIMM SLOT2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 13 of 75
5 4 3 2 1
5 4 3 2 1

PCH_AZ_SYNC is sampled
CMOS_CLR1 CMOS setting Can be place in 0 height area.
WWW.AliSaler.Com
Shunt
Open
Clear CMOS
Keep CMOS
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.

+3.3V_ALW_PCH
17 USB_OC0#_R
17 USB_OC1#_R
17 USB_OC2#
@ RH1
@ RH3
@ RH4
1
1
1
2
2
2
33_0402_5%~D
33_0402_5%~D
33_0402_5%~D
XDP_FN0
XDP_FN1
XDP_FN2
+3.3V_ALW_PCH
+3.3V_ALW_PCH
1
3
5
GND0
OBSFN_A0
OBSFN_A1
@ JXDP2
GND1
OBSFN_C0
OBSFN_C1
2
4
6
XDP_FN16
XDP_FN17
@ RH5 1 2 33_0402_5%~D XDP_FN3 1 7 8
17 USB_OC3# @ RH6 33_0402_5%~D XDP_FN4 XDP_FN0 GND2 GND3 XDP_FN8
1 2 9 OBSDATA_A0 OBSDATA_C0 10
17 USB_OC4# @ RH7 33_0402_5%~D XDP_FN5 @CH1
@CH1 XDP_FN1 XDP_FN9
ME_CLR1 TPM setting 17 USB_OC5#
1 2 11 OBSDATA_A1 OBSDATA_C1 12

1
@ RH8 1 2 33_0402_5%~D XDP_FN6 0.1U_0402_16V4Z~D 13 14
RH66 17 USB_OC6# @ RH9 33_0402_5%~D XDP_FN7 2 XDP_FN2 GND4 GND5 XDP_FN10
Shunt Clear ME RTC Registers 17,42 SIO_EXT_SMI#
1 2
XDP_FN8 XDP_FN3
15 OBSDATA_A2 OBSDATA_C2 16
XDP_FN11
1K_0402_5%~D @ RH10 1 2 33_0402_5%~D 17 18
18,41 SLP_ME_CSW_DEV# @ RH12 33_0402_5%~D XDP_FN9 OBSDATA_A3 OBSDATA_C3
Open Keep ME RTC Registers 18,36 USB_MCARD1_DET# HDD_DET#_R @ RH13
1 2
33_0402_5%~D XDP_FN10
19 GND6 GND7 20
1 2 21 22

2
BBS_BIT0_R @ RH14 33_0402_5%~D XDP_FN11 OBSFN_B0 OBSFN_D0
1 2 23 24
@ RH15 33_0402_5%~D XDP_FN12 OBSFN_B1 OBSFN_D1
1 2 25
GND8 GND9
26
D +RTC_CELL PCH_AZ_SYNC 18 GPIO36 @ RH16 33_0402_5%~D XDP_FN13 XDP_FN4 XDP_FN12 D
18 GPIO37 1 2 27
OBSDATA_B0 OBSDATA_D0
28
@ RH17 1 2 33_0402_5%~D XDP_FN14 XDP_FN5 29 30 XDP_FN13
18 EN_ESATA_RPTR# OBSDATA_B1 OBSDATA_D1

1
@ RH18 1 2 33_0402_5%~D XDP_FN15 31 32
18,41 TEMP_ALERT# GND10 GND11
1

@ RH282 @ RH19 1 2 33_0402_5%~D XDP_FN16 XDP_FN6 33 34 XDP_FN14


RH38 100K_0402_5%~D 18 PCH_GPIO15 @ RH20 33_0402_5%~D XDP_FN17 XDP_FN7 OBSDATA_B2 OBSDATA_D2 XDP_FN15
1 2 35 36
330K_0402_5%~D 18 SIO_EXT_SCI#_R @ RH283 1K_0402_5%~D OBSDATA_B3 OBSDATA_D3
37 38
GND12 GND13 +3.3V_ALW_PCH
16,42 PCH_RSMRST#_Q 2 1 RSMRST#_XDP 42,58 1.05V_0.8V_PWROK 1 2 1.05V_0.8V_PWROK_R 39 40

2
PWRGOOD/HOOK0 ITPCLK/HOOK4
@ RH24 1K_0402_5%~D
7,16 SIO_PWRBTN#_R 1 2 PCH_PWRBTN#_XDP 41 42
2

PCH_INTVRMEN @ RH21 0_0402_5%~D HOOK1 ITPCLK#/HOOK5


43 44
VCC_OBS_AB VCC_OBS_CD RSMRST#_XDP
45 46
HOOK2 RESET#/HOOK6
1

47 48 XDP_DBRESET#
HOOK3 DBR#/HOOK7 XDP_DBRESET# 7,16
@ RH39
@RH39 On Die PLL VR is supplied by CH2 @ RH284 0_0402_5%~D 49 GND14 GND15 50
330K_0402_5%~D 18P_0402_50V8J~D 1 2 DDR_XDP_WAN_SMBDAT_R2 51 52 PCH_JTAG_TDO
1.5V when sampled high, 1.8 V 2 1 PCH_RTCX1 7,12,13,15,28,36 DDR_XDP_WAN_SMBDAT
1 2 DDR_XDP_WAN_SMBCLK_R2 53
SDA TD0
54
7,12,13,15,28,36 DDR_XDP_WAN_SMBCLK SCL TRST#
when sampled low @ RH285 0_0402_5%~D 55 56 PCH_JTAG_TDI
2

YH1 PCH_JTAG_TCK TCK1 TDI PCH_JTAG_TMS


57 TCK0 TMS 58

1
1 G 2 59 GND16 GND17 60
RH2
INTVRMEN- Integrated SUS 10M_0402_5%~D
UH4A
SAMTE_BSH-030-01-L-D-A
4 3
1.1V VRM Enable G

2
* High - Enable Internal VRs CH3 32.768KHZ_12.5PF_Q13MC1461000~D A20 RTCX1 FWH0 / LAD0 C38 LPC_LAD0 33,34,41,42
18P_0402_50V8J~D A38

LPC
Low - Enable External VRs 2 1 1 2 PCH_RTCX2 C20
FWH1 / LAD1
B37
LPC_LAD1 33,34,41,42 +3.3V_RUN
RTCX2 FWH2 / LAD2 LPC_LAD2 33,34,41,42
RH286 0_0402_5%~D C37
FWH3 / LAD3 LPC_LAD3 33,34,41,42
+RTC_CELL 1 2 PCH_RTCRST# D20
RH22 20K_0402_5%~D RTCRST# IRQ_SERIRQ
FWH4 / LFRAME# D36 LPC_LFRAME# 33,34,41,42 2 1
1 2 SRTCRST# G22 RH28 8.2K_0402_5%~D
RH23 20K_0402_5%~D SRTCRST# PCH_AZ_SYNC_Q 2
E36 1

RTC
INTRUDER# LDRQ0# LPC_LDRQ0# 41
1 2 K22 K36 RH37 10K_0402_5%~D
INTRUDER# LDRQ1# / GPIO23 LPC_LDRQ1# 41
RH11 1M_0402_5%~D PCH_GPIO33 2 1
2 1 PCH_INTVRMEN C17 V5 IRQ_SERIRQ RH355 100K_0402_5%~D
C INTVRMEN SERIRQ IRQ_SERIRQ 33,34,41,42 BBS_BIT0_R C
@ CH100 2 1
27P_0402_50V8J~D RH51 4.7K_0402_5%~D
1 1 2 2 1 1 2 2 SATA0RXN AM3 PSATA_PRX_DTX_N0_C 28
1 2 PCH_AZ_BITCLK N34 AM1
31 PCH_AZ_MDC_BITCLK HDA_BCLK SATA0RXP PSATA_PRX_DTX_P0_C 28

SATA 6G
RH32 33_0402_5%~D
SATA0TXN AP7
PSATA_PTX_DRX_N0_C 28 HDD
PCH_AZ_SYNC L34 AP5
@ @ HDA_SYNC SATA0TXP PSATA_PTX_DRX_P0_C 28
ME1 SHORT PADS~D CMOS1 SHORT PADS~D T10 AM10
30 SPKR SPKR SATA1RXN SATA_ODD_PRX_DTX_N1_C 29
1 2 1 2 AM8 SATA_ODD_PRX_DTX_P1_C 29
1U_0402_6.3V6K~D PCH_AZ_RST# SATA1RXP
CH5 1U_0402_6.3V6K~D CH4
31 PCH_AZ_MDC_RST# 1 2 K34
HDA_RST# SATA1TXN
AP11
SATA_ODD_PTX_DRX_N1_C 29 ODD/ E Module Bay
CMOS place near DIMM RH34 33_0402_5%~D AP10
SATA1TXP SATA_ODD_PTX_DRX_P1_C 29
PCH_AZ_CODEC_SDIN0 E34 AD7 +3.3V_RUN
30 PCH_AZ_CODEC_SDIN0 HDA_SDIN0 SATA2RXN
AD5
SATA2RXP
30 PCH_AZ_CODEC_SDOUT 1 2 PCH_AZ_SDOUT 31 PCH_AZ_MDC_SDIN1
PCH_AZ_MDC_SDIN1 G34
HDA_SDIN1 SATA2TXN
AH5
RH29 33_0402_5%~D AH4 SPKR 2 1
SATA2TXP
30 PCH_AZ_CODEC_SYNC 1 2 PCH_AZ_SYNC_Q C34 @RH35
@ RH35 10K_0402_5%~D

IHDA
RH26 33_0402_5%~D +3.3V_ALW_PCH HDA_SDIN2
AB8
SATA3RXN
30 PCH_AZ_CODEC_RST# 1 2 PCH_AZ_RST# 1 2 A34
HDA_SDIN3 SATA3RXP
AB10 No Reboot Strap
RH27 33_0402_5%~D @RH287
@ RH287 1K_0402_5%~D AF3
SATA3TXN
30 PCH_AZ_CODEC_BITCLK 1 2 PCH_AZ_BITCLK SATA3TXP
AF1 Low = Default
1 RH25 33_0402_5%~D 1 2 PCH_AZ_SDOUT A36 SPKR
31 PCH_AZ_MDC_SDOUT

SATA
HDA_SDO
41 ME_FWP RH36 1 2 33_0402_5%~D Y7 ESATA_PRX_DTX_N4_C 39
High = No Reboot
@ CH101 +3.3V_ALW_PCH RH50 1K_0402_5%~D SATA4RXN
Y5 ESATA_PRX_DTX_P4_C 39
PCH_GPIO33 SATA4RXP
27P_0402_50V8J~D
2
C36
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD3
ESATA_PTX_DRX_N4_C 39 E-SATA
AD1
SATA4TXP ESATA_PTX_DRX_P4_C 39
1

USB30_SMI# N32
29 USB30_SMI# HDA_DOCK_RST# / GPIO13
@RH288
@ RH288 Y3
+3.3V_RUN SATA5RXN SATA_PRX_DKTX_N5_C 40
0_0603_5%~D Y1
SATA5RXP SATA_PRX_DKTX_P5_C 40
SATA5TXN
AB3
SATA_PTX_DKRX_N5_C 40 DOCK
RH59 2 1 51_0402_1%~D PCH_JTAG_TCK J3 AB1
2

JTAG_TCK SATA5TXP SATA_PTX_DKRX_P5_C 40


1

B RH44 2 1 200_0402_1%~D PCH_JTAG_TMS H7 Y11 +1.05V_RUN B

JTAG
@ RH295 JTAG_TMS SATAICOMPO
8.2K_0402_5%~D RH45 2 1 200_0402_1%~D PCH_JTAG_TDI K5 Y10 +SATA_COMP 1 2
JTAG_TDI SATAICOMPI RH40 37.4_0402_1%~D
+3.3V_ALW_PCH_JTAG RH43 2 1 200_0402_1%~D PCH_JTAG_TDO H1
2

JTAG_TDO +1.05V_RUN
100_0402_1%~D

100_0402_1%~D

100_0402_1%~D

AB12
SATA3RCOMPO
1

PCH_SPI_DO
@ RH48

@ RH49

@ RH47

AB13 +SATA3_COMP 1 2
SATA3COMPI
SPI_MOSI RH42 49.9_0402_1%~D

High: Enable Intel 


Anti-Theft Technology PCH_SPI_CLK T3 AH1 RBIAS_SATA3 1 2
+3.3V_RUN
2

SPI_CLK SATA3RBIAS RH46 750_0402_1%~D


Left floating: Disable Intel Anti-Theft Technology

1
PCH_SPI_CS0# Y14
SPI_CS0# RH30
PCH_SPI_CS1# T1 10K_0402_5%~D

SPI
+3.3V_SPI +3.3V_M 17,34,36,37,41,42 PCH_PLTRST#_EC SPI_CS1#
P3 SATA_ACT#
SATALED# SATA_ACT# 45

2
2
G

PCH_SPI_DO V4 V14 HDD_DET#_R @RH290


@ RH290 1 2 0_0402_5%~D
SPI_MOSI SATA0GP / GPIO21 HDD_DET# 28
1 2
RH350 0_0402_5%~D 1 2 PCH_AZ_SYNC_Q 3 1 PCH_AZ_SYNC PCH_SPI_DIN U3 P1 BBS_BIT0_R 1 3

S
31 PCH_AZ_MDC_SYNC SPI_MISO SATA1GP / GPIO19 PCH_SATA_MOD_EN# 42
CONN@ RH33 33_0402_5%~D
S

JSPI1
1 SPI_PCH_CS1# 1 2 2 1 SSM3K7002FU_SC70-3~D CougarPoint_Rev_1p0 QH1 BSS138W-7-F_SOT323-3~D

G
2
1 PCH_SPI_CS1# RH345 0_0402_5%~D RH31 1M_0402_5%~D
2 QH7 7,17 PCH_PLTRST#
2 SPI_PCH_DO
3 1 2
3 PCH_SPI_DO RH346 0_0402_5%~D
4
4 SPI_PCH_DIN
5 1 2 +3.3V_SPI C745 BBS_BIT0 - BIOS BOOT STRAP BIT 0
5 PCH_SPI_DIN RH347 0_0402_5%~D +3.3V_SPI C746 0.1U_0402_16V4Z~D
6
6 SPI_PCH_CLK 0.1U_0402_16V4Z~D
7 1 2 1 2
7 PCH_SPI_CLK RH348 0_0402_5%~D
8 1 2
8
1

SPI_PCH_CS0#
9
9 1 2
200 MIL SO8
1

PCH_SPI_CS0# RH349 0_0402_5%~D R888


10 10
200 MIL SO8
1

1
A R890 3.3K_0402_5%~D A
11
11 +3.3V_SPI
3.3K_0402_5%~D R891 16Mb Flash ROM R892
12 12
13
+3.3V_M 64Mb Flash ROM 3.3K_0402_5%~D U53 X76@ 3.3K_0402_5%~D
2

13 SPI_PCH_CS1#1
14 U52 X76@ 2 SPI_CS1# 1 8
2

14 SPI_PCH_CS0# /CS VCC


15 1 2 SPI_CS0# 1 8 R935 47_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2

15 /CS VCC 2
16 R933 47_0402_5%~D SPI_PCH_DIN 1 2 SPI_DIN32 2 7
16 SPI_PCH_DIN DO(IO1) /HOLD(IO3)
1 2 SPI_DIN64 2 DO /HOLD 7 R895 33_0402_5%~D
SPI_WP#_SEL SPI_CLK32 1 2 SPI_PCH_CLK
17 SPI_WP#_SEL
R894
1
33_0402_5%~D
2 3 6 SPI_CLK64 1 2 SPI_PCH_CLK @R896
@
1
R896
2
0_0402_5%~D
3 /WP(IO2) CLK 6
R897 33_0402_5%~D Compal Electronics, Inc.
G1 41 SPI_WP#_SEL /WP CLK SPI_DO32 1 Title
G2 18 @ R898 0_0402_5%~D R899 33_0402_5%~D 4 GND DI(IO0) 5 2 SPI_PCH_DO
SPI_DO64 1 SPI_PCH_DO
4 GND DIO 5
R901
2
33_0402_5%~D
R900 33_0402_5%~D
PCH (1/8)
W25Q16BVSSIG_SO8~D Size Document Number Rev

WWW.AliSaler.Com
W25Q64BVSSIG_SO8~D 1.0
HRS_FH12-16S-0P5SH(55)~D LA-6592P
Date: Thursday, January 13, 2011 Sheet 14 of 75
5 4 3 2 1
5 4 3 2 1

+3.3V_RUN

WWW.AliSaler.Com QH5A

2
DMN66D0LDW-7_SOT363-6~D

MEM_SMBCLK 6 1 DDR_XDP_WAN_SMBCLK 7,12,13,14,28,36

5
MEM_SMBDATA 3 4 DDR_XDP_WAN_SMBDAT 7,12,13,14,28,36
QH5B
D Follow DG0.9 Device down & Express/Mini UH4B DMN66D0LDW-7_SOT363-6~D D

card topology 1 2
BG34 @ RH296 0_0402_5%~D
36 PCIE_PRX_WANTX_N1 PERN1 PCH_SMB_ALERT#
36 PCIE_PRX_WANTX_P1 BJ34 E12
PERP1 SMBALERT# / GPIO11
MiniWWAN (Mini Card 1)---> 36 PCIE_PTX_WANRX_N1
AV32
PETN1 1 2
AU32 H14 MEM_SMBCLK @ RH297 0_0402_5%~D
36 PCIE_PTX_WANRX_P1 PETP1 SMBCLK +3.3V_ALW_PCH
BE34 C9 MEM_SMBDATA
36 PCIE_PRX_WLANTX_N2 PERN2 SMBDATA
36 PCIE_PRX_WLANTX_P2 BF34
PERP2 SML1_SMBCLK
MiniWLAN (Mini Card 2)---> 36 PCIE_PTX_WLANRX_N2
BB32
PETN2 1 2
AY32 RH298 2.2K_0402_5%~D

SMBUS
36 PCIE_PTX_WLANRX_P2 PETP2 DDR_HVREF_RST_PCH SML1_SMBDATA
SML0ALERT# / GPIO60 A12 1 2
DDR_HVREF_RST_PCH 7 RH299 2.2K_0402_5%~D
37 PCIE_PRX_EXPTX_N3 BG36 PERN3
BJ36 C8 LAN_SMBCLK DDR_HVREF_RST_PCH 2 1
37 PCIE_PRX_EXPTX_P3 PERP3 SML0CLK LAN_SMBCLK 32
EXPRESS Card---> 37 PCIE_PTX_EXPRX_N3 AV34 PETN3
RH300 1K_0402_5%~D
AU34 G12 LAN_SMBDATA GPIO74 2 1
37 PCIE_PTX_EXPRX_P3 PETP3 SML0DATA LAN_SMBDATA 32
RH301 10K_0402_5%~D
BF36 MEM_SMBCLK 2 1
29 PCIE_PRX_EMBTX_N4 PERN4
BE36 RH302 2.2K_0402_5%~D
29 PCIE_PRX_EMBTX_P4 PERP4 GPIO74 MEM_SMBDATA
E3 Module Bay---> 29 PCIE_PTX_EMBRX_N4 AY34 PETN4 SML1ALERT# / PCHHOT# / GPIO74 C13 2 1
BB34 RH303 2.2K_0402_5%~D
29 PCIE_PTX_EMBRX_P4 PETP4 SML1_SMBCLK PCH_SMB_ALERT#
E14 2 1

PCI-E*
SML1CLK / GPIO58 SML1_SMBCLK 42 RH304 10K_0402_5%~D
36 PCIE_PRX_WPANTX_N5 BG37 PERN5
1/2vMINI CARD-3 PCIE BH37 M16 SML1_SMBDATA
36 PCIE_PRX_WPANTX_P5 PERP5 SML1DATA / GPIO75 SML1_SMBDATA 42
AY36
(Mini Card 3)---> 36 PCIE_PTX_WPANRX_N5
BB36
PETN5
36 PCIE_PTX_WPANRX_P5 PETP5
BJ38 +3.3V_LAN
35 PCIE_PRX_MMITX_N6 PERN6
35 PCIE_PRX_MMITX_P6 BG38

Controller
PERP6 PCH_CL_CLK1
MMI ---> 35 PCIE_PTX_MMIRX_N6 AU36 PETN6 CL_CLK1 M7 PCH_CL_CLK1 36
AV36 LAN_SMBCLK 2 1
C 35 PCIE_PTX_MMIRX_P6 PETP6 RH305 2.2K_0402_5%~D C

Link
BG40 T11 PCH_CL_DATA1 LAN_SMBDATA 2 1
32 PCIE_PRX_GLANTX_N7 PERN7 CL_DATA1 PCH_CL_DATA1 36
BJ40 RH306 2.2K_0402_5%~D
32 PCIE_PRX_GLANTX_P7 PERP7
10/100/1G LAN ---> 32 PCIE_PTX_GLANRX_N7 AY40 PETN7
BB40 P10 PCH_CL_RST1# RH80
32 PCIE_PTX_GLANRX_P7 PETP7 CL_RST1# PCH_CL_RST1# 36 GFX_CLK_REQ#
+3.3V_ALW_PCH 2 1
BE38 PERN8
BC38 10K_0402_5%~D
PERP8
AW38
PETN8

1
D
AY38
PETP8 QH2
41,49 3.3V_RUN_GFX_ON 2
M10 GFX_CLK_REQ# G SSM3K7002FU_SC70-3~D
PCIE_MINI1# PEG_A_CLKRQ# / GPIO47
2 1 Y40 S

3
36 CLK_PCIE_MINI1# @ RH3072 PCIE_MINI1 CLKOUT_PCIE0N
1 0_0402_5%~D Y39
36 CLK_PCIE_MINI1 CLKOUT_PCIE0P CLK_PCIE_VGA#
MiniWWAN (Mini Card 1)---> +3.3V_ALW_PCH @ RH3082 1 0_0402_5%~D CLKOUT_PEG_A_N
AB37
CLK_PCIE_VGA# 46

CLOCKS
RH81 10K_0402_5%~D MINI1CLK_REQ# J2 AB38 CLK_PCIE_VGA
36 MINI1CLK_REQ# PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA 46

2 1 PCIE_LAN# AB49 AV22 CLK_CPU_DMI#


32 CLK_PCIE_LAN# @ RH82 2 PCIE_LAN CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# 7
1 0_0402_5%~D AB47 AU22
32 CLK_PCIE_LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 7
10/100/1G LAN ---> @ RH83 0_0402_5%~D
LANCLK_REQ# M1 CLK_BUF_DMI# 1 2
32 LANCLK_REQ# PCIECLKRQ1# / GPIO18
AM12 CLK_CPU_DPLL# CLK_BUF_DMI RH74 1 2 10K_0402_5%~D
CLKOUT_DP_N CLK_CPU_DPLL CLK_CPU_DPLL# 7 RH75 10K_0402_5%~D
AM13
PCIE_MMI# CLKOUT_DP_P CLK_CPU_DPLL 7
2 1 AA48
35 CLK_PCIE_MMI# PCIE_MMI CLKOUT_PCIE2N CLK_BUF_BCLK
MMI Card---> 35 CLK_PCIE_MMI
@ RH85 2 1 0_0402_5%~D AA47
CLKOUT_PCIE2P
1 2
@ RH86 1 2 0_0402_5%~D BF18 CLK_BUF_DMI# RH91 10K_0402_5%~D
+3.3V_RUN CLKIN_DMI_N
RH87 10K_0402_5%~D MMICLK_REQ# V10 BE18 CLK_BUF_DMI
35 MMICLK_REQ# PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
CLK_BUF_DOT96# 1 2
2 1 PCIE_MINI3# Y37 BJ30 CLK_BUF_BCLK CLK_BUF_DOT96 RH76 1 2 10K_0402_5%~D
36 CLK_PCIE_MINI3# CLKOUT_PCIE3N CLKIN_GND1_N
MiniWPAN (Mini Card 3)---> @ RH88 2 1 0_0402_5%~D PCIE_MINI3 Y36 BG30 RH77 10K_0402_5%~D
B 36 CLK_PCIE_MINI3 CLKOUT_PCIE3P CLKIN_GND1_P B
+3.3V_ALW_PCH @ RH90 2 1 0_0402_5%~D
RH152 10K_0402_5%~D MINI3CLK_REQ# A8 CLK_BUF_CKSSCD# 1 2
36 MINI3CLK_REQ# PCIECLKRQ3# / GPIO25 CLK_BUF_DOT96# CLK_BUF_CKSSCD
G24 RH78 1 2 10K_0402_5%~D
CLKIN_DOT_96N CLK_BUF_DOT96 RH79 10K_0402_5%~D
E24
PCIE_EXP# CLKIN_DOT_96P
37 CLK_PCIE_EXP# 2 1 Y43
PCIE_EXP CLKOUT_PCIE4N CLK_PCH_14M
Express card---> 37 CLK_PCIE_EXP
@ RH92 2 1 0_0402_5%~D Y45
CLKOUT_PCIE4P 1 2
@ RH93 2 1 0_0402_5%~D AK7 CLK_BUF_CKSSCD# RH183 10K_0402_5%~D
+3.3V_ALW_PCH CLKIN_SATA_N
RH94 10K_0402_5%~D EXPCLK_REQ# L12 AK5 CLK_BUF_CKSSCD
37 EXPCLK_REQ# PCIECLKRQ4# / GPIO26 CLKIN_SATA_P

2 1 PCIE_MINI2# V45 K45 CLK_PCH_14M


36 CLK_PCIE_MINI2# CLKOUT_PCIE5N REFCLK14IN
@ RH95 2 1 0_0402_5%~D PCIE_MINI2 V46 CLOCK TERMINATION for FCIM and need close to PCH
36 CLK_PCIE_MINI2 CLKOUT_PCIE5P
MiniWLAN (Mini Card 2)---> +3.3V_ALW_PCH @ RH96 2 1 0_0402_5%~D
RH97 10K_0402_5%~D MINI2CLK_REQ# L14 H45
36 MINI2CLK_REQ# PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LOOPBACK 17
@ RH309
AB42 V47 XTAL25_IN 2 1 0_0402_5%~D
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 V49
CLKOUT_PEG_B_P XTAL25_OUT

1
+3.3V_ALW_PCH 1 2 PEG_B_CLKRQ# E6 RH99
RH98 10K_0402_5%~D PEG_B_CLKRQ# / GPIO56 1M_0402_5%~D
Y47 XCLK_RCOMP 1 2 YH2
XCLK_RCOMP +1.05V_RUN
V40 RH100 90.9_0402_1%~D 25MHZ_18PF_7A25000110~D

2
CLKOUT_PCIE6N
V42 2 1
CLKOUT_PCIE6P

18P_0402_50V8J~D

18P_0402_50V8J~D
T13
PCIECLKRQ6# / GPIO45
2 2
2 1 PCIE_EMB# V38 K43 PCI_TCM 4@ RH311 2 1 22_0402_5%~D
29 CLK_PCIE_EMB# CLK_PCI_TPM_CHA 34
FLEX CLOCKS

CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64

CH18

CH19
eModule Bay---> @ RH3102 1 0_0402_5%~D PCIE_EMB V37
29 CLK_PCIE_EMB CLKOUT_PCIE7P
+3.3V_ALW_PCH @ RH3122 1 0_0402_5%~D F47 SIO_14M RH313 2 1 22_0402_5%~D
CLKOUTFLEX1 / GPIO65 CLK_SIO_14M 41 1 1
RH104 10K_0402_5%~D EMBCLK_REQ# K12
29 EMBCLK_REQ# PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 H47 PCI_TPM RH314 2 1 22_0402_5%~D CLK_PCI_TPM 33
A CLK_BCLK_ITP# AK14 A
7 CLK_CPU_ITP# 2 1
@ RH2802 CLK_BCLK_ITP AK13 CLKOUT_ITPXDP_N JETWAY_14M
7 CLK_CPU_ITP 1 0_0402_5%~D CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 K49 @ RH315 2 1 22_0402_5%~D JETWAY_CLK14M 34
@ RH281 0_0402_5%~D

CougarPoint_Rev_1p0
DELL CONFIDENTIAL/PROPRIETARY
PCIE REQ power rail:
Compal Electronics, Inc.
suspend: 0 3 4 5 6 7 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
core: 1 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (2/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Tuesday, January 18, 2011 Sheet 15 of 75
5 4 3 2 1
5 4 3 2 1

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+3.3V_ALW_PCH

2.2K_0402_5%~D

2.2K_0402_5%~D
1

1
RH316

RH317
1 2 SUS_STAT#/LPCPD#

2
@ RH318 10K_0402_5%~D
PCH_DPWROK 1 2PCH_RSMRST#_R
1 2 ME_SUS_PWR_ACK @ RH113 0_0402_5%~D G_CLK_DDC2 1 6 PCH_CRT_DDC_CLK
D PCH_CRT_DDC_CLK 25 D
RH144 10K_0402_5%~D
QH6A
1 2 PCH_PCIE_WAKE# DMN66D0LDW-7_SOT363-6~D

2
RH142 10K_0402_5%~D RESET_OUT# 1 2 SYS_PWROK +3.3V_RUN
@ RH321 0_0402_5%~D

5
1 2 SIO_SLP_LAN# DSWODVREN - On Die DSW VR Enable QH6B
@ RH319 10K_0402_5%~D DMN66D0LDW-7_SOT363-6~D
Enabled (DEFAULT) G_DAT_DDC2 4 3 PCH_CRT_DDC_DAT
PCH_RI# PCH_CRT_DDC_DAT 25
1 2
RH140 10K_0402_5%~D ME_SUS_PWR_ACK_R 1 2 SUSACK#_R HIGH: R221 STUFFED,
@ RH323 0_0402_5%~D R222 UNSTUFFED
+3.3V_RUN
PCH_RSMRST#_Q 1 2 Disabled
RH322 10K_0402_5%~D
1 2 CLKRUN# LOW: R221 STUFFED,
RH137 8.2K_0402_5%~D ME_SUS_PWR_ACK 1 2 R222 UNSTUFFED
@ RH145 10K_0402_5%~D L_DDC_DATA - LVDS Detected
1 LVDS is detected
0 LVDS is not detected Intel request DDPB can not support eDP
UH4C
UH4D

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 PANEL_BKEN_PCH J47 AP43


6 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N0 6 24 PANEL_BKEN_PCH ENVDD_PCH L_BKLTEN SDVO_TVCLKINN
6 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 6 24,41 ENVDD_PCH M45 L_VDD_EN SDVO_TVCLKINP AP45
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
6 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N2 6 BIA_PWM_PCH
6 DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 6 24 BIA_PWM_PCH P45 L_BKLTCTL SDVO_STALLN AM42
BC12 FDI_CTX_PRX_N4 AM40
FDI_RXN4 FDI_CTX_PRX_N4 6 SDVO_STALLP
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 LDDC_CLK_PCH T40
6 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N5 6 23 LDDC_CLK_PCH LDDC_DATA_PCH L_DDC_CLK
6 DMI_CTX_PRX_P1 BC20 DMI1RXP FDI_RXN6 BG10 FDI_CTX_PRX_N6 6 23 LDDC_DATA_PCH K47 L_DDC_DATA SDVO_INTN AP39
C DMI_CTX_PRX_P2 FDI_CTX_PRX_N7 C
6 DMI_CTX_PRX_P2 BJ18 DMI2RXP FDI_RXN7 BG9 FDI_CTX_PRX_N7 6 SDVO_INTP AP40
DMI_CTX_PRX_P3 BJ20 T45
6 DMI_CTX_PRX_P3 DMI3RXP L_CTRL_CLK
BG14 FDI_CTX_PRX_P0 P39
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P0 6 L_CTRL_DATA
6 DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 6
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 1 2 L_IBG AF37 P38
6 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P2 6 LVD_IBG SDVO_CTRLCLK
BB18 BG13 RH344 2.37K_0402_1%~D AF36 M39
6 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P3 6 LVD_VBG SDVO_CTRLDATA
AV18 BE12
DMI
FDI
6 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 6
BG12 FDI_CTX_PRX_P5 AE48
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P5 6 LVD_VREFH
6 DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 6 AE47 AT49
DMI_CRX_PTX_P1 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P7 LVD_VREFL DDPB_AUXN
6 DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 6 AT47
DMI_CRX_PTX_P2 DMI1TXP FDI_RXP7 DDPB_AUXP
6 DMI_CRX_PTX_P2 AY18 AT40
DMI_CRX_PTX_P3 DMI2TXP DDPB_HPD
AU18 AK39

LVDS
6 DMI_CRX_PTX_P3 DMI3TXP 23 LCD_ACLK-_PCH LVDSA_CLK#
AW16 FDI_INT AK40 AV42
+1.05V_RUN FDI_INT FDI_INT 6 23 LCD_ACLK+_PCH LVDSA_CLK DDPB_0N
AV40
FDI_FSYNC0 DDPB_0P
BJ24 AV12 FDI_FSYNC0 6 23 LCD_A0-_PCH AN48 AV45
DMI_ZCOMP FDI_FSYNC0 LVDSA_DATA#0 DDPB_1N
AM47 AV46

Digital Display Interface


DMI_COMP_R FDI_FSYNC1 23 LCD_A1-_PCH LVDSA_DATA#1 DDPB_1P
1 2 BG25 BC10 FDI_FSYNC1 6 23 LCD_A2-_PCH AK47 AU48
RH111 49.9_0402_1%~D DMI_IRCOMP FDI_FSYNC1 LVDSA_DATA#2 DDPB_2N
AJ48 AU47
RBIAS_CPY FDI_LSYNC0 LVDSA_DATA#3 DDPB_2P
1 2 BH21
DMI2RBIAS FDI_LSYNC0
AV14 FDI_LSYNC0 6 DDPB_3N
AV47
RH112 750_0402_1%~D AN47 AV49
FDI_LSYNC1 23 LCD_A0+_PCH LVDSA_DATA0 DDPB_3P
BB10 FDI_LSYNC1 6 23 LCD_A1+_PCH AM49
FDI_LSYNC1 LVDSA_DATA1
23 LCD_A2+_PCH AK49
+RTC_CELL LVDSA_DATA2
AJ47 P46
LVDSA_DATA3 DDPC_CTRLCLK
P42
DSWODVREN RH1271 DDPC_CTRLDATA
A18 2 330K_0402_1%~D
DSWVRMEN
23 LCD_BCLK-_PCH AF40
LVDSB_CLK#
System Power Management

@RH129
@ RH1291 2 330K_0402_1%~D AF39 AP47
23 LCD_BCLK+_PCH LVDSB_CLK DDPC_AUXN
1 2 SUSACK#_R C12 E22 PCH_DPWROK AP49
41 SUSACK# SUSACK# DPWROK PCH_DPWROK 41 DDPC_AUXP
@ RH114 0_0402_5%~D AH45 AT38
23 LCD_B0-_PCH LVDSB_DATA#0 DDPC_HPD
23 LCD_B1-_PCH AH47
XDP_DBRESET# K3 PCH_PCIE_WAKE# LVDSB_DATA#1
7,14 XDP_DBRESET# B9 PCH_PCIE_WAKE# 41 23 LCD_B2-_PCH AF49 AY47
SYS_RESET# WAKE# LVDSB_DATA#2 DDPC_0N
AF45 AY49
B LVDSB_DATA#3 DDPC_0P B
AY43
SYS_PWROK_R P12 CLKRUN# DDPC_1N
7,41 SYS_PWROK 1 2 N3 CLKRUN# 34,41,42 23 LCD_B0+_PCH AH43 AY45
@ RH116 0_0402_5%~D SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA0 DDPC_1P
23 LCD_B1+_PCH AH49 BA47
LVDSB_DATA1 DDPC_2N
23 LCD_B2+_PCH AF47 BA48
PCH_PWROK L22 SUS_STAT#/LPCPD# @ T56 PAD~D LVDSB_DATA2 DDPC_2P
42 RESET_OUT# 1 2 G8 AF43 BB47
@ RH117 0_0402_5%~D PWROK SUS_STAT# / GPIO61 LVDSB_DATA3 DDPC_3N
BB49
DDPC_3P
1 2 PM_APWROK_R L10 N14 SUSCLK @ T57 PAD~D
42 PM_APWROK APWROK SUSCLK / GPIO62 PCH_CRT_BLU
@ RH118 0_0402_5%~D N48 M43
25 PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
@ T58 PAD~D PCH_CRT_GRN P49 M36
PM_DRAM_PWRGD_R B13 SIO_SLP_S5# 25 PCH_CRT_GRN PCH_CRT_RED CRT_GREEN DDPD_CTRLDATA
7 PM_DRAM_PWRGD 1 2 D10 25 PCH_CRT_RED T49
@ RH320 0_0402_5%~D DRAMPWROK SLP_S5# / GPIO63 SIO_SLP_S5# 42 CRT_RED
@ T59 PAD~D AT45

CRT
PCH_RSMRST#_R C21 SIO_SLP_S4# G_CLK_DDC2 DDPD_AUXN
14,42 PCH_RSMRST#_Q 1 2 H4 T39 AT43
@ RH120 0_0402_5%~D RSMRST# SLP_S4# SIO_SLP_S4# 41 G_DAT_DDC2 CRT_DDC_CLK DDPD_AUXP
M40 BH41
@ T60 PAD~D CRT_DDC_DATA DDPD_HPD
1 2 ME_SUS_PWR_ACK_R K16 F4 SIO_SLP_S3# RH123 20_0402_1%~D BB43
42 ME_SUS_PWR_ACK SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# SIO_SLP_S3# 41 DDPD_0N
@ RH121 0_0402_5%~D
25 PCH_CRT_HSYNC 1 2 HSYNC M47 BB45
CRT_HSYNC DDPD_0P
7,14 SIO_PWRBTN#_R
@ T61 PAD~D
25 PCH_CRT_VSYNC 1 2 VSYNC M49 BF44
SIO_PWRBTN#_R E20 RH124 20_0402_1%~D CRT_VSYNC DDPD_1N
42 SIO_PWRBTN# 1 2 G10 BE44
@ RH122 0_0402_5%~D PWRBTN# SLP_A# SIO_SLP_A# 41,56 DDPD_1P
BF42
@ T62 PAD~D CRT_IREF DDPD_2N
T43 BE42
SIO_SLP_SUS# DAC_IREF DDPD_2P
42 AC_PRESENT H20 G16 T42 BJ42
ACPRESENT / GPIO31 SLP_SUS# SIO_SLP_SUS# 41 CRT_IRTN DDPD_3N
BG42
DDPD_3P

1
@ T63 PAD~D
1 2 PCH_BATLOW# E10 AP14 H_PM_SYNC CougarPoint_Rev_1p0
+3.3V_ALW_PCH BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 7
RH139 8.2K_0402_5%~D RH126
1K_0402_0.5%~D
PCH_RI# A10 K14 SIO_SLP_LAN#

2
RI# SLP_LAN# / GPIO29 SIO_SLP_LAN# 32,41

CougarPoint_Rev_1p0
A A
1 2 PCH_CRT_BLU
RH131 150_0402_1%~D
1 2 PCH_CRT_GRN
RH132 150_0402_1%~D
1 2 PCH_CRT_RED
RH133 150_0402_1%~D DELL CONFIDENTIAL/PROPRIETARY
1 2 ENVDD_PCH
RH134 100K_0402_5%~D
Compal Electronics, Inc.
Title
PCH (3/8)
Size Document Number Rev

WWW.AliSaler.Com
1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 16 of 75
5 4 3 2 1
5 4 3 2 1

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+3.3V_RUN

1 2 PCI_PIRQA#
RH324 8.2K_0402_5%~D
UH4E
D PCI_PIRQB# D
1 2 RSVD1
AY7
RH325 8.2K_0402_5%~D AV7
RSVD2
BG26 AU3
PCI_PIRQC# TP1 RSVD3
1 2 BJ26 BG4
RH326 8.2K_0402_5%~D TP2 RSVD4
BH25
TP3
BJ16 AT10
PCI_PIRQD# TP4 RSVD5
1 2 BG16 BC8
RH329 8.2K_0402_5%~D TP5 RSVD6
AH38
TP6
AH37 AU2
PCI_REQ1# TP7 RSVD7
1 2 AK43 AT4
RH327 10K_0402_5%~D TP8 RSVD8
AK45 AT3
TP9 RSVD9
C18 TP10 RSVD10 AT1
1 2 ATG_MAC_LCD_DET# N30 AY3
RH330 10K_0402_5%~D TP11 RSVD11
H3 TP12 RSVD12 AT5
AH12 TP13 RSVD13 AV3
1 2 CAM_MIC_CBL_DET# AM4 AV1
RH331 10K_0402_5%~D TP14 RSVD14
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3
1 2 BT_DET# K24 BB5
RH328 10K_0402_5%~D TP17 RSVD17
L24 TP18 RSVD18 BB3
AB46 TP19 RSVD19 BB7
1 2 PCH_GPIO3 AB45 BE8

RSVD
@ RH332 10K_0402_5%~D TP20 RSVD20
RSVD21 BD4
RSVD22 BF6

B21 TP21 RSVD23 AV5


M20 TP22 RSVD24 AV10
AY16 TP23
High : Normal type panel BG46 TP24 RSVD25 AT8

LVDS_CBL_ID RSVD26 AY5


RSVD27 BA2
C C
Low : High contrast ratio brightness BE28 TP25
BC30 TP26 RSVD28 AT12
BE32 TP27 RSVD29 BF3
BJ32 TP28
BC28 TP29
BE30 TP30
BF32 TP31
BG32 C24 USBP0-
PCI_GNT3# TP32 USBP0N USBP0+ USBP0- 38
AV26
BB26
TP33 USBP0P
A24
C25 USBP1- USBP0+ 38 ----->Right Side 1
TP34 USBP1N USBP1+ USBP1- 38
AU28
TP35 USBP1P
B25 USBP1+ 38 ----->Right Side 2
1

AY30 C26 USBP2-


TP36 USBP2N USBP2- 39
@ RH333 USBP2+
1K_0402_5%~D
AU26
AY26
TP37 USBP2P
A26
K28 USBP3-
USBP2+ 39 ----->Right Side (ESATA)
TP38 USBP3N USBP3+ USBP3- 31
AV28
AW30
TP39 USBP3P
H28
E28 USBP4- USBP3+ 31 ----->Left Side
USBP4- 36
2

TP40 USBP4N USBP4+


USBP4P
D28
C28 USBP5- USBP4+ 36 ----->WLAN/WIMAX
USBP5N USBP5- 36
USBP5P
A28 USBP5+
USBP5+ 36
----->WWAN/UWB
C29 USBP6-
USBP6N USBP6- 36
USBP6P
B29 USBP6+
USBP6+ 36 ----->Flash
PCI_PIRQA# K40 N28 USBP7-
PIRQA# USBP7N USBP7- 33
PCI_PIRQB# K38 M28 USBP7+ ----->USH

PCI
PCI_PIRQC# PIRQB# USBP7P USBP8- USBP7+ 33
A16 swap override Strap/Top-Block H38 L30 USBP8- 40
PIRQC# USBP8N
PCI_PIRQD# G38
PIRQD# USBP8P
K30 USBP8+
USBP8+ 40
----->DOCK
Swap Override jumper G30 USBP9-
USBP9N USBP9- 40
PCI_REQ1# C46 E30 USBP9+ ----->DOCK

USB
REQ1# / GPIO50 USBP9P USBP9+ 40
C44 C30 USBP10-
36 PCIE_MCARD2_DET# REQ2# / GPIO52 USBP10N USBP10- 37
Low = A16 swap 43 BT_DET#
BT_DET# E40
REQ3# / GPIO54 USBP10P
A30 USBP10+
USBP10+ 37
----->Express Card +3.3V_ALW_PCH
PCI_GNT#3 L32 USBP11-
USBP11N USBP11- 43
High = Default BBS_BIT1 D47
GNT1# / GPIO51 USBP11P
K32 USBP11+
USBP11+ 43 ----->Blue Tooth RPH1
E42 G32 USBP12- USB_OC0# 4 5
GNT2# / GPIO53 USBP12N USBP12- 24
B PCI_GNT3# F46
GNT3# / GPIO55 USBP12P
E32 USBP12+
USBP12+ 24
----->Camera USB_OC1# 3 6 B
C32 USBP13- USB_OC3# 2 7
USBP13N USBP13- 24
USBP13P
A32 USBP13+
USBP13+ 24
----->LCD Touch USB_OC4# 1 8
ATG_MAC_LCD_DET# G42
24 ATG_MAC_LCD_DET# PIRQE# / GPIO2
PCH_GPIO3 G40 Within 500 mils 10K_1206_8P4R_5%~D
CAM_MIC_CBL_DET# C42 PIRQF# / GPIO3 USBRBIAS RPH2
24 CAM_MIC_CBL_DET# C33 1 2
FFS_PCH_INT D44 PIRQG# / GPIO4 USBRBIAS# RH151 USB_OC5#
28 HDD_FALL_INT 1 2 4 5
@ RH334 0_0402_5%~D PIRQH# / GPIO5 22.6_0402_1%~D USB_OC6#
33 PLTRST_USH# 1 2 3 6
@RH335
@ RH3351 2 0_0402_5%~D B33 2 7
35 PLTRST_MMI# USBRBIAS
@RH336
@ RH3361 2 0_0402_5%~D PAD~D T104 @ K10 USB_OC2# 1 8
7 PLTRST_XDP# PME#
@RH337
@ RH3371 2 0_0402_5%~D
32 PLTRST_LAN#
@RH338
@ RH3381 2 0_0402_5%~D PCH_PLTRST# C6 A14 USB_OC0#_R 1 2 10K_1206_8P4R_5%~D
46 PLTRST_GPU# PLTRST# OC0# / GPIO59 USB_OC1#_R USB_OC0# 39
@RH343
@ RH3431 2 0_0402_5%~D K20 @ RH3391 2 0_0402_5%~D
29 PLTRST_EMB# OC1# / GPIO40 USB_OC2# USB_OC1# 31,39
@RH340
@ RH340 0_0402_5%~D B17 @ RH341 0_0402_5%~D
OC2# / GPIO41 USB_OC2# 14
2 1 PCI_5028 H49 C16 USB_OC3# SIO_EXT_SMI# 2 1
41 CLK_PCI_5028 CLKOUT_PCI0 OC3# / GPIO42 USB_OC3# 14
RH160 2 1 22_0402_5%~D PCI_MEC H43 L16 USB_OC4# RH41 10K_0402_5%~D
42 CLK_PCI_MEC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# 14
RH102 1 2 22_0402_5%~D PCI_DOCK J48 A16 USB_OC5#
40 CLK_PCI_DOCK CLKOUT_PCI2 OC5# / GPIO9 USB_OC6# USB_OC5# 14
RH103 33_0402_5%~D K42 D14
PCI_LOOPBACKOUT CLKOUT_PCI3 OC6# / GPIO10 SIO_EXT_SMI# USB_OC6# 14
15 CLK_PCI_LOOPBACK 2 1 H40 C14 SIO_EXT_SMI# 14,42
RH105 22_0402_5%~D CLKOUT_PCI4 OC7# / GPIO14

USB_OC0#_R 14
CougarPoint_Rev_1p0
USB_OC1#_R 14

+3.3V_RUN CH102
0.1U_0402_16V4Z~D
1 2

Boot BIOS Strap


5

A A
UH3 SATA_SLPD
PCH_PLTRST# 1 BBS_BIT1 (BBS_BIT0) Boot BIOS Location
P

7,14 PCH_PLTRST# B BBS_BIT1


O 4 PCH_PLTRST#_EC 14,34,36,37,41,42
2 A
G

0 0 LPC
DELL CONFIDENTIAL/PROPRIETARY
1
TC7SH08FU_SSOP5~D
3

@ RH342
0 1 Reserved (NAND) 1K_0402_5%~D
Compal Electronics, Inc.
Title
2

1 0 PCI PCH (4/8)


Size Document Number Rev

WWW.AliSaler.Com
1 1 SPI 1.0
* LA-6592P
Date: Thursday, January 13, 2011 Sheet 17 of 75
5 4 3 2 1
5 4 3 2 1

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+3.3V_RUN

CONTACTLESS_DET# 1 2
RH256 10K_0402_1%~D
D D
UH4F
+3.3V_ALW_PCH 14 SIO_EXT_SCI#_R
SIO_EXT_SCI# 1 2 T7 C40 CONTACTLESS_DET#
42 SIO_EXT_SCI# BMBUSY# / GPIO0 TACH4 / GPIO68 CONTACTLESS_DET# 33
@ RH259 0_0402_5%~D
1 2 PCH_GPIO15 PCH_GPIO1 A42
TACH1 / GPIO1 TACH5 / GPIO69
B41 DGPU_PWROK 41,63
RH354 1K_0402_5%~D
IO_LOOP# H36 C41
31 IO_LOOP# TACH2 / GPIO6 TACH6 / GPIO70 PCIE_MCARD3_DET# 36
LEDB_DET# E38 A40
31 LEDB_DET# TACH3 / GPIO7 TACH7 / GPIO71 USB_MCARD2_DET# 36
PCH_GPIO15 TLS Confidentiality
SIO_EXT_WAKE# C10
41 SIO_EXT_WAKE# GPIO8
Low = Intel ME Crypto Transport Layer
Security (TLS) cipher suite with no 32 PM_LANPHY_ENABLE C4 LAN_PHY_PWR_CTRL / GPIO12
confidentiality
PCH_GPIO15 G2 P4 SIO_A20GATE 1 2
High = Intel ME Crypto TLS cipher suite 14 PCH_GPIO15 GPIO15 A20GATE SIO_A20GATE 42
@RH261
@ RH261 0_0402_5%~D
PECI_EC 42
with confidentiality AU16 H_PECI_R 1 2
PECI H_PECI 7
EN_ESATA_RPTR# U2 @ RH159 0_0402_5%~D
14 EN_ESATA_RPTR# SATA4GP / GPIO16 SIO_RCIN#
RCIN# P5 SIO_RCIN# 42
+3.3V_RUN

GPIO
+3.3V_ALW_PCH GPIO17 D40 AY11 H_CPUPWRGD +1.05V_RUN_VTT

CPU/MISC
TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 7
MEDIA_DET# T5 AY10 PCH_THRMTRIP#_R 2 1 SIO_A20GATE 2 1
31 MEDIA_DET# SCLOCK / GPIO22 THRMTRIP#
2

RH262 56_0402_5%~D RH158 10K_0402_5%~D


RH356 E8 T14 INIT3_3V# @ T106 1 SIO_RCIN# 2 1
36 PCIE_MCARD1_DET# GPIO24 / MEM_LED INIT3_3V#
4.7K_0402_5%~D RH203 10K_0402_5%~D
E3_PAID_TS_DET# E16 AY1 DF_TVS CH97 PCH_GPIO1 2 1
24 E3_PAID_TS_DET# GPIO27 DF_TVS 0.1U_0402_16V4Z~D RH164 10K_0402_5%~D
1

SLP_ME_CSW_DEV# 2 SIO_EXT_SCI#
14,41 SLP_ME_CSW_DEV# P8 GPIO28
1 2
SLP_ME_CSW_DEV# AH8 RH263 10K_0402_5%~D
DGPU_HOLD_RST# TS_VSS1
46 DGPU_HOLD_RST# K1 STP_PCI# / GPIO34
C C
TS_VSS2 AK11
2

14,36 USB_MCARD1_DET# K4 GPIO35


@ RH353 AH10
GPIO36 TS_VSS3
1K_0402_5%~D 14 GPIO36 V8 SATA2GP / GPIO36
TS_VSS4 AK10
GPIO37 M5
14 GPIO37
1

SATA3GP / GPIO37
TPM_ID0 N2 P37 NC_1 @ T108
SLOAD / GPIO38 NC_1
TPM_ID1 M3
SDATAOUT0 / GPIO39
Note: PCH has internal pull up 20k ohm on FFS_INT2 VSS_NCTF_15
28 FFS_INT2 V13 BG2
E3_PAID_TS_DET# (GPIO27) SDATAOUT1 / GPIO48 VSS_NCTF_15
TEMP_ALERT# V3 BG48 VSS_NCTF_16
14,41 TEMP_ALERT# SATA5GP / GPIO49 VSS_NCTF_16
KB_DET# D6 BH3 VSS_NCTF_17
43 KB_DET# GPIO57 VSS_NCTF_17
+3.3V_ALW_PCH BH47 VSS_NCTF_18
VSS_NCTF_18
VSS_NCTF_1 A4 BJ4 VSS_NCTF_19
SIO_EXT_WAKE# VSS_NCTF_1 VSS_NCTF_19
1 2
RH177 10K_0402_5%~D VSS_NCTF_2 A44 BJ44 VSS_NCTF_20
VSS_NCTF_2 VSS_NCTF_20
VSS_NCTF_3 A45 BJ45 VSS_NCTF_21
VSS_NCTF_3 VSS_NCTF_21

NCTF
VSS_NCTF_4 A46 BJ46 VSS_NCTF_22
VSS_NCTF_4 VSS_NCTF_22
VSS_NCTF_5 A5 BJ5 VSS_NCTF_23 PLACE RH150 CLOSE TO THE BRANCHING POINT
VSS_NCTF_5 VSS_NCTF_23
( TO CPU and NVRAM CONNECTOR)
VSS_NCTF_6 A6 BJ6 VSS_NCTF_24
VSS_NCTF_6 VSS_NCTF_24
VSS_NCTF_7 B3 C2 VSS_NCTF_25
B VSS_NCTF_7 VSS_NCTF_25 +VCCDFTERM B
VSS_NCTF_8 B47 C48 VSS_NCTF_26 RH149 need to close to CPU
VSS_NCTF_8 VSS_NCTF_26

1
Layout note: VSS_NCTF_9 BD1 D1 VSS_NCTF_27
VSS_NCTF_9 VSS_NCTF_27 RH149
Trace wide 10mil & length 30mil VSS_NCTF_10 VSS_NCTF_28
Layout note:
BD49 D49 2.2K_0402_5%~D
All NCTF pins should have thick
VSS_NCTF_10 VSS_NCTF_28 Trace wide 10mil & length 30mil
VSS_NCTF_11 VSS_NCTF_29
BE1 E1 All NCTF pins should have thick

2
traces at 45°from the pad. VSS_NCTF_11 VSS_NCTF_29
VSS_NCTF_12 BE49
VSS_NCTF_12 VSS_NCTF_30
E49 VSS_NCTF_30 traces at 45°from the pad. DF_TVS_R1 2 DF_TVS
RH150 0_0402_5%~D
VSS_NCTF_13 BF1 F1 VSS_NCTF_31
VSS_NCTF_13 VSS_NCTF_31
VSS_NCTF_14 BF49 F49 VSS_NCTF_32
+3.3V_ALW_PCH VSS_NCTF_14 VSS_NCTF_32

1 2 KB_DET# CougarPoint_Rev_1p0
RH170 10K_0402_5%~D DMI & FDI Termination Voltage

Set to Vss when LOW


+3.3V_RUN RH171, RH173 should be no pop as reverse strap. DF_TVS
Set to Vcc when HIGH
2 1 GPIO36
@ RH171 10K_0402_5%~D
2 1 GPIO37 +3.3V_RUN +3.3V_RUN
@ RH173 1K_0402_5%~D
2 1 EN_ESATA_RPTR#
RH265 10K_0402_5%~D
2

2 1 TEMP_ALERT#
RH266 10K_0402_5%~D 1@ RH267 3@ RH268
2 1 MEDIA_DET# 10K_0402_5%~D 20K_0402_5%~D TPM_ID0 TPM_ID1
A RH179 10K_0402_5%~D A
2 1 DGPU_HOLD_RST# China TPM 0 0
1

@ RH180 10K_0402_5%~D
1 2 GPIO17 TPM_ID0 TPM_ID1 No TPM, No China TPM 0 1
RH269 8.2K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
2

2@ RH270 4@ RH271
USH2.0 1 1
IO_LOOP#
1
RH163
2
10K_0402_5%~D
10K_0402_5%~D 2.2K_0402_5%~D
Compal Electronics, Inc.
1 2 LEDB_DET# Title
1

RH272
2
10K_0402_5%~D
1 GPIO17 PCH (5/8)
@ RH273 1K_0402_5%~D Size Document Number Rev

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Date: Thursday, January 13, 2011 Sheet 18 of 75
5 4 3 2 1
5 4 3 2 1

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+1.05V_RUN UH4G POWER S0 Iccmax
Voltage Rail Voltage Current (A)
LH1
AA23 U48 +VCCADAC 2 1 +3.3V_RUN
VCCCORE[1] VCCADAC
AC23 VCCCORE[2]
BLM18PG181SN1_0603~D V_PROC_IO 1.05 0.001

10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.01U_0402_16V7K~D

0.1U_0402_10V7K~D
CRT
1 1 1 1 AD21 VCCCORE[3]

10U_0805_4VAM~D
AD23 U47 1 1 1
VCCCORE[4] VSSADAC

CH30

CH32

CH33

CH31
V5REF 5 0.001

VCC CORE
AF21
VCCCORE[5]

CH34

CH35

CH36
AF23
D 2 2 2 2 VCCCORE[6] D
AG21
VCCCORE[7] 2 2 2
AG23
VCCCORE[8]
V5REF_Sus 5 0.001
AG24 AK36
VCCCORE[9] VCCALVDS
AG26
VCCCORE[10]
AG27
VCCCORE[11] VSSALVDS
AK37 Vcc3_3 3.3 0.266
AG29 +3.3V_RUN
VCCCORE[12]
AJ23

LVDS
VCCCORE[13]
AJ26
VCCCORE[14] VCCTX_LVDS[1]
AM37 VccADAC3 3.3 0.001
AJ27
VCCCORE[15] +1.8V_RUN_LVDS
AJ29 AM38 2 1 +1.8V_RUN
VCCCORE[16] VCCTX_LVDS[2]

0.01U_0402_16V7K~D

0.01U_0402_16V7K~D

22U_0805_6.3VAM~D
AJ31
VCCCORE[17]
LH8 VccADPLLA 1.05 0.08

CH103

CH104

CH105
+1.05V_RUN +1.05V_RUN AP36 1 1 1 HK1608R10J-T_0603~D
VCCTX_LVDS[3]
50 mA VCCTX_LVDS[4] AP37 VccADPLLB 1.05 0.08
AN19 VCCIO[28] 2 2 2
VccCore 1.05 1.3
1 2 +VCCAPLLEXP BJ22
@RH247
@RH247 VCCAPLLEXP
1UH_LB2012T1R0M_20%~D

10U_0805_4VAM~D
1 V33 +3.3V_RUN VccDMI 1.05 0.042

HVCMOS
VCC3_3[6]
AN16 VCCIO[15]

CH40
1
AN17 VCCIO[16]
VccIO 1.05 2.925
2 @ V34 CH43
VCC3_3[7]
0.1U_0402_10V7K~D
AN21 2 VccASW 1.05 1.01
VCCIO[17]
AN26 VCCIO[18]
VccSPI 3.3 0.020
AN27 VCCIO[19] VCCVRM[3] AT16 +1.05V_+1.5V_1.8V_RUN
+1.05V_RUN
AP21 VCCIO[20]
VccDSW3_3 3.3 0.003
C C
AP23 VCCIO[21] VCCDMI[1] AT20 +1.05V_RUN_VTT
VCCDFTERM 1.8 0.19

DMI
10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 1 1 1 1 AP24 1 2

VCCIO
VCCIO[22] CH49 1U_0402_6.3V6K~D
CH44

CH45

CH46

CH47

CH48

AP26 AB36 +VCCCLKDMI 2 1 VccRTC 3.3 2 (mA)


VCCIO[23] VCCCLKDMI +1.05V_RUN

1U_0402_6.3V6K~D

10U_0603_4VAM~D
1 1 LH9
2 2 2 2 2

@ CH106
AT24 HK1608R10J-T_0603~D
VCCIO[24]

CH50
VccSus3_3 3.3 0.119
AN33 2 2
VCCIO[25]
VccSusHDA 3.3 0.01
AN34 AG16
+3.3V_RUN VCCIO[26] VCCDFTERM[1] +VCCDFTERM
VccVRM 1.8 / 1.5 0.16
BH29 AG17 1 2 +3.3V_RUN

DFT / SPI
VCC3_3[3] VCCDFTERM[2] @ RH276 0_0805_5%~D
0.1U_0402_10V7K~D

1 VccClkDMI 1.05 0.02


AJ16 1 PJP51
VCCDFTERM[3]
CH51

1 2 +1.8V_RUN
+1.05V_+1.5V_1.8V_RUN AP16
VCCVRM[2]
CH52 VccSSC 1.05 0.095
2 AJ17 0.1U_0402_10V7K~D PAD-OPEN1x1m
VCCDFTERM[4] 2
+1.05V_RUN +VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VccAFDIPLL

1 2 +VCCAPLL_FDI +1.05V_RUN AP17 VccALVDS 3.3 0.001


VCCIO[27]
FDI

@RH195
@ RH195 0.022_0805_1% V1 +3.3V_M
VCCSPI

+1.05V_RUN_VTT AU20
VCCDMI[2] 1 VccTX_LVDS 1.8 0.06
CH54
B CougarPoint_Rev_1p0 1U_0402_6.3V6K~D B
2

+1.5V_RUN +1.05V_+1.5V_1.8V_RUN +1.05V_RUN

2 1
RH197 0_0603_5%~D
+1.8V_RUN
1 1

2 1 + @ CH41 + @ CH42
@ RH198 0_0603_5%~D 330U_D2_2VM_R6M~D 330U_D2_2VM_R6M~D
+1.05V_RUN
2 2

2 1
@ RH199 0_0603_5%~D
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (6/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 19 of 75
5 4 3 2 1
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WWW.AliSaler.Com +1.05V_RUN
@ RH202
1 2

1 2 +VCCACLK 0_0402_5%~D
+3.3V_ALW_PCH @ RH200 0.022_0805_1% +5V_ALW +5V_ALW_PCH

+3.3V_ALW2
UH4J POWER
1 2 1 3

S
@ RH201 0_0402_5%~D 1 AD49 N26 +1.05V_RUN
VCCACLK VCCIO[29]

0.1U_0402_10V7K~D

20K_0402_5%~D
1 2 @ QH4

@ RH278
@RH253
@ RH253 0_0402_5%~D CH55 P26 1 SSM3K7002FU_SC70-3~D 1

G
2
0.1U_0402_10V7K~D +VCCDSW3_3 VCCIO[30]
T16
2 VCCDSW3_3

CH98
D CH56 D
P28
Note: Check Intel VCCIO[31] 1U_0402_6.3V6K~D
+PCH_VCCDSW 2 44 ALW_ENABLE 2
V12 T27

2
+1.05V_RUN @ LH3 DCPSUSBYP VCCIO[32]
1
10UH_LBR2012T100M_20%~D T29
@ CH57 +3.3V_RUN_VCC_CLKF33 T38 VCCIO[33]
1 2 VCC3_3[5]
0.1U_0402_10V7K~D +3.3V_ALW_PCH
2

10U_0805_6.3V6M~D

0.1U_0402_10V7K~D
1 T23
+1.05V_RUN VCCSUS3_3[7]

@ CH58
+VCCAPLL_CPY_PCH BH23 1
VCCAPLLDMI2
T24 +3.3V_ALW_PCH
VCCSUS3_3[8] +5V_ALW_PCH +3.3V_ALW_PCH

CH59

0.1U_0402_10V7K~D
AL29
2 VCCIO[14]
V23 1

USB
VCCSUS3_3[9] 2

2
CH60
+VCCSUS1 AL24 V24
DCPSUS[3] VCCSUS3_3[10] RH208 DH2
1 2
P24 10_0402_5%~D RB751S40T1_SOD523-2~D
VCCSUS3_3[6]

@
CH61
1U_0402_6.3V6K~D AA19

1
2 VCCASW[1] +PCH_V5REF_SUS
VCCIO[34] T26 +1.05V_RUN
AA21 VCCASW[2] 1

AA24 M26 +PCH_V5REF_SUS CH63


VCCASW[3] V5REF_SUS

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D
1 1 +3.3V_ALW_PCH 0.1U_0402_10V7K~D
2

Clock and Miscellaneous


AA26 VCCASW[4]

CH64

CH65

0.1U_0402_10V7K~D
AN23 +VCCA_USBSUS 1
DCPSUS[4]
AA27 VCCASW[5]
2 2

CH66
VCCSUS3_3[1] AN24
AA29 VCCASW[6] 2
+1.05V_M AA31 +5V_RUN +3.3V_RUN
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN
VCCASW[8] V5REF

2
C C
1 1U_0402_6.3V6K~D 1 1

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
AC27 RH213 DH3
CH67 VCCASW[9]

CH68

CH69
N20 +3.3V_ALW_PCH 10_0402_5%~D RB751S40T1_SOD523-2~D
VCCSUS3_3[2]

PCI/GPIO/LPC
AC29 VCCASW[10] 1
2 2 2 N22

1
VCCSUS3_3[3] CH70 +PCH_V5REF_RUN
AC31 VCCASW[11]
P20 1U_0603_10V6K~D +3.3V_RUN
VCCSUS3_3[4] 2
AD29 1
VCCASW[12]
P22
+3.3V_RUN VCCSUS3_3[5] CH71
AD31 1
VCCASW[13] 1U_0603_10V6K~D
1 2 W21 AA16 CH72 2
@RH215
@ RH215 0.022_0805_1% VCCASW[14] VCC3_3[1] 0.1U_0402_10V7K~D
LH4 W23 W16 2 +3.3V_RUN
10UH_LBR2012T100M_20%~D VCCASW[15] VCC3_3[8]
1 2 +3.3V_RUN_VCC_CLKF33 W24 T34 +VCCA_USBSUS
VCCASW[16] VCC3_3[4]
10U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1 1 1
W26 1
VCCASW[17]
CH73

CH74

CH75
W29 +3.3V_RUN 0.1U_0402_10V7K~D @CH62
@CH62
2 2 VCCASW[18] 2 1U_0402_6.3V6K~D
W31 AJ2 2
VCCASW[19] VCC3_3[2]
1
W33
VCCASW[20] CH76
AF13 +1.05V_RUN
VCCIO[5] 0.1U_0402_10V7K~D
2 1
+VCCRTCEXT N16
DCPRTC CH77
1 AH13
VCCIO[12] 1U_0402_6.3V6K~D
CH78 Y49 AH14 2 Note: Check Intel
+1.05V_+1.5V_1.8V_RUN VCCVRM[4] VCCIO[13]
0.1U_0402_10V7K~D
2
B +1.05V_RUN AF14 @ LH5 B
+1.05V_RUN_VCCA_A_DPL VCCIO[6] 10UH_LBR2012T100M_20%~D
BD47

SATA
VCCADPLLA +VCCSATAPLL
AK1 1 2 +1.05V_RUN
+1.05V_RUN_VCCA_B_DPL VCCAPLLSATA
1 BF47 1
VCCADPLLB
CH79 AF11 +1.05V_+1.5V_1.8V_RUN @ CH80
1U_0402_6.3V6K~D VCCVRM[1] 10U_0805_6.3V6M~D
AF17
2 VCCIO[7] 2
AF33
VCCDIFFCLKN[1]
AF34 AC16 +1.05V_RUN
VCCDIFFCLKN[2] VCCIO[2]
1 2 CH81 AG34
VCCDIFFCLKN[3]
1U_0402_6.3V6K~D AC17 1
VCCIO[3]
AG33 AD17 CH82
VCCSSC VCCIO[4] 1U_0402_6.3V6K~D
1 2
+1.05V_M
CH96 +VCCSST V16 +1.05V_M
1U_0402_6.3V6K~D DCPSST
1 2 +1.05V_M_VCCSUS
@ RH248 0.022_0805_1% 2 +1.05V_M_VCCSUS
1
1 T17 T21
CH84 DCPSUS[1] VCCASW[22]
V19
DCPSUS[2]
MISC

0.1U_0402_10V7K~D @CH83
@CH83
+1.05V_RUN_VTT 2 1U_0402_6.3V6K~D V21
2 VCCASW[23]
CPU
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

BJ8
V_PROC_IO
1 1 1 T19
VCCASW[21]
+RTC_CELL
CH86

CH87

CH85
4.7U_0603_6.3V6K~D
2 2 2
RTC

A22 P32
HDA

VCCRTC VCCSUSHDA +3.3V_ALW_PCH


0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 1 1 1
LH6 CougarPoint_Rev_1p0
A A
CH88

CH89

10UH_LBR2012T100M_20%~D CH90 CH91


1 2 +1.05V_RUN_VCCA_A_DPL 1U_0402_6.3V6K~D 0.1U_0402_10V7K~D
+1.05V_RUN 2 2 2 2

1 2 +1.05V_RUN_VCCA_B_DPL
DELL CONFIDENTIAL/PROPRIETARY
220U_B2_2.5VM_R35M~D

220U_B2_2.5VM_R35M~D

LH7
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10UH_LBR2012T100M_20%~D 1 1
1 1 Compal Electronics, Inc.
CH94

CH92

CH95

CH93

+ +
Title
+1.05V_RUN_VCCA_A_DPL 1 2 +1.05V_RUN_VCCA_B_DPL
2 2 2 2 @RH279
@ RH279 0_0805_5%~D
PCH (7/8)
Size Document Number Rev

WWW.AliSaler.Com
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LA-6592P
Date: Thursday, January 13, 2011 Sheet 20 of 75
5 4 3 2 1
5 4 3 2 1

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UH4I

AY4 VSS[159] VSS[259] H46


AY42 VSS[160] VSS[260] K18
AY46 K26
VSS[161] VSS[261]
AY8 K39
VSS[162] VSS[262]
B11 K46
D UH4H VSS[163] VSS[263] D
B15 K7
VSS[164] VSS[264]
H5 B19 L18
VSS[0] VSS[165] VSS[265]
B23 L2
VSS[166] VSS[266]
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
VSS[2] VSS[81] VSS[168] VSS[268]
AA3 AK42 B35 L28
VSS[3] VSS[82] VSS[169] VSS[269]
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 AK8 B7 L48
VSS[5] VSS[84] VSS[171] VSS[271]
AB11 AL16 F45 M12
VSS[6] VSS[85] VSS[172] VSS[272]
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 AL19 BB16 M18
VSS[8] VSS[87] VSS[174] VSS[274]
AB4 VSS[9] VSS[88] AL2 BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26 BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27 BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33 BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48 BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11 BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14 BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43 BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46 BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7 BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3 BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31 BD5 VSS[195] VSS[295] R2
C C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19 BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28 BE40 VSS[198] VSS[298] T31
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38 BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 AP42 BF22 T47
VSS[37] VSS[116] VSS[203] VSS[303]
AD45 AP46 BF24 T8
VSS[38] VSS[117] VSS[204] VSS[304]
AD46 AP8 BF26 V11
VSS[39] VSS[118] VSS[205] VSS[305]
AD8 AR2 BF28 V17
VSS[40] VSS[119] VSS[206] VSS[306]
AE2 AR48 BD3 V26
VSS[41] VSS[120] VSS[207] VSS[307]
AE3 AT11 BF30 V27
VSS[42] VSS[121] VSS[208] VSS[308]
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 AT32 BG44 W17
VSS[49] VSS[128] VSS[215] VSS[315]
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 AU24 H10 Y38
VSS[55] VSS[134] VSS[221] VSS[321]
AF42 AU30 BH27 Y4
VSS[56] VSS[135] VSS[222] VSS[322]
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 AV20 BH33 Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 AV30 BH39 BG29
VSS[60] VSS[139] VSS[226] VSS[328]
AG19 AV38 BH43 N24
B VSS[61] VSS[140] VSS[227] VSS[329] B
AG2 AV4 BH7 AJ3
VSS[62] VSS[141] VSS[228] VSS[330]
AG31 AV43 D3 AD47
VSS[63] VSS[142] VSS[229] VSS[331]
AG48 AV8 D12 B43
VSS[64] VSS[143] VSS[230] VSS[333]
AH11 AW14 D16 BE10
VSS[65] VSS[144] VSS[231] VSS[334]
AH3 AW18 D18 BG41
VSS[66] VSS[145] VSS[232] VSS[335]
AH36 AW2 D22 G14
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 AW32 D32 BG24
VSS[71] VSS[150] VSS[237] VSS[343]
AH7 AW34 D34 C22
VSS[72] VSS[151] VSS[238] VSS[344]
AJ19 AW36 D38 AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 AW40 D42 M14
VSS[74] VSS[153] VSS[240] VSS[346]
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 AV11 E18 AP1
VSS[76] VSS[155] VSS[242] VSS[348]
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
CougarPoint_Rev_1p0 VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A

CougarPoint_Rev_1p0

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCH (8/8)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 21 of 75
5 4 3 2 1
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WWW.AliSaler.Com 47 VGA_THERMDP
VGA_THERMDP
DSC only

1
JFAN1 CONN@
+FAN1_VOUT FAN1_DET# 1 C1104
1 470P_0402_50V7K~D
Place under CPU 2 2 2

RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3 5
Place C266 close to the Q12 as possible 3 G1

22U_0805_6.3VAM~D
4 6 47 VGA_THERMDN VGA_THERMDN
4 G2

1
1

D2

C219
REM_DIODE1_P_4022 MOLEX_53398-0471~D

1
@ 2 C
D C266 2 +3.3V_M D
2

2
100P_0402_50V8J~D B
E Q12

3
1 MMBT3904WT1G_SC70-3~D REM_DIODE1_N_4022 BC_INT#_EMC4022 2 1
R385 10K_0402_5%~D

FAN1_TACH_FB 2 1
R426 10K_0402_5%~D

+5V_RUN FAN1_DET# 2 1
R402 10K_0402_5%~D

10U_0805_10V4Z~D

0.1U_0402_16V4Z~D
1 1

C276

C275
+3.3V_RUN
2 2

10U_0805_6.3V6M~D

0.1U_0402_16V4Z~D
1 1 U9

C305

C1171
2 VDDH
2 2 +3.3V_M 3 VDDH THERMATRIP2#
6 VDDL THERMTRIP2# 17
(1) DP3/DN3 for SODIMM on Q14, place Q14 close to SODIMM and C272 close to Q14 1 2 VDD_PWRGD 13 VDD_PWRGD
R389 10K_0402_5%~D 18 THERMATRIP3#
(2) DP5/DN5 for Skin on Q13, place Q13 close to JMINI1 for WWAN and C277 close Q13 THERMTRIP3#
1 2 REM_DIODE1_N_4022 23
C270 2200P_0402_50V7K~D REM_DIODE1_P_4022 DN1/THERM
24 DP1/VREF_T SYS_SHDN# 19 THERM_STP# 53
REM_DIODE3_P_4022
100P_0402_50V8J~D

VGA_THERMDN 26 20 POWER_SW# 1 2
DN2/DP4 POWER_SW# +RTC_CELL
1 1 VGA_THERMDP 27 @R390
@ R390 47K_0402_1%~D
DP2/DN4
1

E
C @
C277

C @C272
@ C272
B
REM_DIODE3_P_4022 C
2 2 2 1 30 DP3/DN5 ACAVAIL_CLR 21 ACAV_IN 42,60,62
100P_0402_50V8J~D B Q13 C271 2200P_0402_50V7K~D REM_DIODE3_N_4022 29 9 BC_INT#_EMC4022
2 E 2 C
MMBT3904WT1G_SC70-3~D DN3/DP5 ATF_INT#/BC_IRQ# BC_INT#_EMC4022 42
3

Q14 REM_DIODE3_N_4022
MMBT3904WT1G_SC70-3~D 2 1 VCP2 31
60 MAX8731_IINP VCP
4.7K_0402_5%~D R387 25 VIN
FAN_OUT 5 +FAN1_VOUT
VSET_4022 28 4
VSET FAN_OUT

8 BC_CLK_EMC4022 42
FAN1_TACH_FB SMCLK/BC_CLK
10 7 BC_DAT_EMC4022 42
TACH/GPIO1 SMDATA/BC_DATA
FAN1_DET# 11
GPIO2

+3.3V_M 2 1 PWM 15
10K_0402_5%~D R1178 GPIO3/PWM/THERMTRIP_SIO +3.3V_M

1
42 PCH_PWRGD# 1 2 3V_PWROK# 12
3V_PWROK#
R388
R391 1K_0402_5%~D 22_0402_5%~D

1 +VCC_4022

2
VDD +ADDR_XEN
32 1 2 +VCC_4022
ADDR_MODE/XEN

0.1U_0402_16V4Z~D

1U_0402_6.3V6K~D
4.7K_0402_5%~D R393 1 1
14
TEST1

C273

C1179
22
TEST2
+RTC_CELL 16 33
RTC_PWR3V VSS 2 2

1
1U_0402_6.3V6K~D
B EMC4022-1-EZK-TR_QFN32_5X5~D R403 B
1
10K_0402_5%~D
+3.3V_M

C274
SMSC request

2
2
1

R395
8.2K_0402_5%~D
2

+1.05V_RUN_VTT THERMATRIP2#
R398
1

2.2K_0402_5%~D C 1
1 2 2
B C278 +RTC_CELL C281
Q15 E 0.1U_0402_16V4Z~D VSET_4022 0.1U_0402_16V4Z~D
3

PMST3904_SOT323-3~D 2
1 2
7 H_THERMTRIP#
1

5
1 U10
C282 R406 TC7SH08FU_SSOP5~D 1

P
B DOCK_PWR_SW# 42
0.1U_0402_16V4Z~D 953_0402_1%~D POWER_SW# 4 O
2 POWER_SW_IN# 42
A

G
2
2

3
+3.3V_M
+3.3V_RUN_GFX
Rest=953, Tp=88degree
1
1

1
8.2K_0402_5%~D
@ R1111

2.2K_0402_5%~D

R405
R1112

8.2K_0402_5%~D
A A
2
2

THERMATRIP3#

DELL CONFIDENTIAL/PROPRIETARY
1

C 1
THERMB3 2
B C280
Q115 E 0.1U_0402_16V4Z~D
Compal Electronics, Inc.
3

PMST3904_SOT323-3~D 2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
46 THERMTRIP_VGA#
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 22 of 75
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Channel A +3.3V_RUN Channel B +3.3V_RUN

0.1U_0402_16V4Z~D
@ C1156

0.1U_0402_16V4Z~D
@ C1157

0.1U_0402_16V4Z~D
@ C1158

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
@ C1159

0.1U_0402_16V4Z~D
@ C1160

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
U84 1 1 1 1 1 1 U85 1 1 1 1 1

C1147

C1146

C1145

C1148

C1150

C1149
VCC 4 VCC 4
VCC 10 VCC 10
47 LCD_ACLK+_GPU 48 0B1 VCC 18 47 LCD_BCLK+_GPU 48 0B1 VCC 18
47 27 2 2 2 2 2 2 47 27 2 2 2 2 2
47 LCD_ACLK-_GPU 1B1 VCC 47 LCD_BCLK-_GPU 1B1 VCC
47 LCD_A2+_GPU 43 38 47 LCD_B2+_GPU 43 38
2B1 VCC 2B1 VCC
47 LCD_A2-_GPU 42 50 47 LCD_B2-_GPU 42 50
D 3B1 VCC 3B1 VCC D
47 LCD_A1+_GPU 37 56 47 LCD_B1+_GPU 37 56
4B1 VCC 4B1 VCC
47 LCD_A1-_GPU 36 47 LCD_B1-_GPU 36
5B1 5B1
47 LCD_A0+_GPU 32 2 SW_LVDS_ACLK+ 24 47 LCD_B0+_GPU 32 2 SW_LVDS_BCLK+ 24
6B1 A0 6B1 A0
47 LCD_A0-_GPU 31 3 SW_LVDS_ACLK- 24 47 LCD_B0-_GPU 31 3 SW_LVDS_BCLK- 24
LDDC_CLK_GPU 7B1 A1 7B1 A1
46 LDDC_CLK_GPU 22 7 SW_LVDS_A2+ 24 22 7 SW_LVDS_B2+ 24
LDDC_DATA_GPU 8B1 A2 8B1 A2
46 LDDC_DATA_GPU 23 8 SW_LVDS_A2- 24 23 8 SW_LVDS_B2- 24
9B1 A3 9B1 A3
11 SW_LVDS_A1+ 24 11 SW_LVDS_B1+ 24
A4 A4
12 SW_LVDS_A1- 24 12 SW_LVDS_B1- 24
A5 A5
14 SW_LVDS_A0+ 24 14 SW_LVDS_B0+ 24
A6 A6
15 SW_LVDS_A0- 24 15 SW_LVDS_B0- 24
A7 A7
16 LCD_ACLK+_PCH 46 19 LDDC_CLK_SW 24 16 LCD_BCLK+_PCH 46 19
0B2 A8 0B2 A8
16 LCD_ACLK-_PCH 45 1B2 A9 20 LDDC_DATA_SW 24 16 LCD_BCLK-_PCH 45 1B2 A9 20
16 LCD_A2+_PCH 41 2B2 16 LCD_B2+_PCH 41 2B2
40 17 DGPU_SELECT# 40 17 DGPU_SELECT#
16 LCD_A2-_PCH 3B2 SEL DGPU_SELECT# 25,41 16 LCD_B2-_PCH 3B2 SEL
16 LCD_A1+_PCH 35 4B2 16 LCD_B1+_PCH 35 4B2
16 LCD_A1-_PCH 34 5B2 GND 1 16 LCD_B1-_PCH 34 5B2 GND 1
16 LCD_A0+_PCH 30 6B2 GND 6 16 LCD_B0+_PCH 30 6B2 GND 6
16 LCD_A0-_PCH 29 7B2 GND 9 16 LCD_B0-_PCH 29 7B2 GND 9
LDDC_CLK_PCH 25 13 25 13
16 LDDC_CLK_PCH LDDC_DATA_PCH 8B2 GND 8B2 GND
16 LDDC_DATA_PCH 26 9B2 GND 16 26 9B2 GND 16
GND 21 GND 21
DGPU_SELECT# 54 24 DGPU_SELECT# 54 24
SEL2 GND SEL2 GND SEL Chanel Source
GND 28 SEL Chanel Source GND 28
GND 33 GND 33 0 COM=NC GPU
52 NC GND 39 0 COM=NC GPU 52 NC GND 39
5 NC GND 44 5 NC GND 44 1 COM=NO PCH
51 NC GND 49 1 COM=NO PCH 51 NC GND 49
GND 53 GND 53
57 Thermal_GND GND 55 57 Thermal_GND GND 55

PI3LVD400ZFEX_TQFN56_11X5~D PI3LVD400ZFEX_TQFN56_11X5~D
C C

+3.3V_RUN_GFX

1 2 LDDC_CLK_GPU
R1122 2.2K_0402_5%~D
1 2 LDDC_DATA_GPU
R1121 2.2K_0402_5%~D

+3.3V_RUN
B B
1 2 LDDC_CLK_PCH
R1124 2.2K_0402_5%~D
1 2 LDDC_DATA_PCH
R1123 2.2K_0402_5%~D

Fingerprint CONN.
JBIO1
1 @ U12 @ L8 @ R1135
1 +3.3V_FP +3.3V_FP
2 1 GND 4 DLW21SN121SQ2L_4P~D 0_0603_5%
2 FP_USB_D- VCC +3.3V_RUN FP_USB_D+
3 1
2 2
33 FP_USBD+ +3.3V_RUN 1 2 +3.3V_FP
3 FP_USB_D+ 1
4
4 FP_USB_D- FP_USB_D+ @R1136
@ R1136
7 5 FP_RESET# 33 2 3
G1 5 IO1 IO2 FP_USB_D- 0_0603_5%~D
8 G2 6 6 1 33 FP_USBD- 4 4 3 3
A PRTR5V0U2X_SOT143-4~D A
C285 Place +3.3V_ALW 1 2
TYCO_2041084-6~D C285 1 2
CONN@ close to JBIO1.1 0.1U_0402_16V4Z~D R409 0_0402_5%~D
2 1 2
R410 0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LVDS SW/FP Conn.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Tuesday, January 18, 2011 Sheet 23 of 75
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+15V_ALW
Q18
SI3456DDV-T1-GE3_TSOP6~D
+LCDVDD +3.3V_ALW

D
S
6
JLVDS1 +LCDVDD +15V_ALW 4 5

1
2
1 R412 1
GND

1
DMN66D0LDW-7_SOT363-6~D

130_0402_5%~D

100K_0402_5%~D
2 100K_0402_5%~D

G
BATT_WHITE_LED BATT_WHITE_LED 45 1

1
R413
3 BATT_YELLOW_LED 45

3
BATT_YELLOW_LED

R414
4 C292
BREATH_WHITE_LED 45

2
BREATH_WHITE_LED 0.1U_0402_16V4Z~D
VR_SRC 5 +BL_PWR_SRC 2

DMN66D0LDW-7_SOT363-6~D
6 1 2

6 2
VR_SRC

0.1U_0402_25V4Z~D
7 C246

2
VR_SRC

3
8 0.1U_0603_50V4Z~D D53 1
NC

Q19A
D DISP_ON RB751V-40GTE-17_SOD323-2~D D
9
DISP_ON/OFF#

Q19B

C293
10 1 2 BIA_PWM_LVDS 2 1
PWM 16,41 ENVDD_PCH
11 LE92 BLM18BB221SN1D_2P~D 2 5
CONNTST_GND 2
12
VR_GND

1
13

4
VR_GND D6
14
VR_GND
15 SW_LVDS_BCLK+ 23
LCD_B_CLK+
16 SW_LVDS_BCLK- 23 41 LCD_VCC_TEST_EN 2
LCD_B_CLK- EN_LCDPWR
17 1 2
GND
18 SW_LVDS_B2+ 23
LVDS_B2+ +3.3V_RUN Q20
19 SW_LVDS_B2- 23 46 ENVDD_GPU 3
LVDS_B2- PDTC124EU_SC70-3~D
LVDS_B1+ 20 SW_LVDS_B1+ 23
21 1 2 LDDC_CLK_SW
SW_LVDS_B1- 23

3
LVDS_B1- R159 2.2K_0402_5%~D BAT54CW_SOT323-3~D
LVDS_B0+ 22 SW_LVDS_B0+ 23
23 1 2 LDDC_DATA_SW
LVDS_B0- SW_LVDS_B0- 23
24 R160 2.2K_0402_5%~D
GND
LVDS_A_CLK+ 25 SW_LVDS_ACLK+ 23
LVDS_A_CLK- 26 SW_LVDS_ACLK- 23 Place near to JLVDS1
GND 27
LVDS_A2+ 28 SW_LVDS_A2+ 23
LVDS_A2- 29 SW_LVDS_A2- 23
30 +LCDVDD +3.3V_RUN
LVDS_A1+ SW_LVDS_A1+ 23
31 Q21
LVDS_A1- SW_LVDS_A1- 23

0.1U_0402_16V4Z~D
+PWR_SRC FDC654P-G_SSOT-6~D
LVDS_A0+ 32 SW_LVDS_A0+ 23 40mil
LVDS_A0- 33
LDDC_DATA_SW
SW_LVDS_A0- 23 40mil

D
EDID_DATA 34 LDDC_DATA_SW 23 1 1 6 +BL_PWR_SRC

C243
LDDC_CLK_SW

S
46 MGND6 EDID_CLK 35 LDDC_CLK_SW 23 4 5
45 36 LCD_TST C298 2
MGND5 BIST LCD_TST 41

1000P_0402_50V7K~D
44 37 0.1U_0402_16V4Z~D 1
MGND4 V_EDID +3.3V_RUN 2 2

G
43 MGND3 LCD_VDD 38 1

1
42 39 +LCDVDD 1

3
MGND2 LCD_VDD R422 C296
41 MGND1 CONNTST 40 ATG_MAC_LCD_DET# 17

C297
C C
Close to JLVDS1.42,43 Close to JLVD1.41 100K_0402_5%~D
2
0.1U_0603_50V4Z~D

ACES_59003-0400C-001 2

2
CONN@
PWR_SRC_ON
D66 D67
RB751V-40GTE-17_SOD323-2~D RB751V-40GTE-17_SOD323-2~D Q22
1 2 1 2 SSM3K7002FU_SC70-3~D
BIA_PWM_PCH 16 PANEL_BKEN_PCH 16
1 2 1 3

S
D63 D64 R423 47K_0402_5%~D
RB751V-40GTE-17_SOD323-2~D RB751V-40GTE-17_SOD323-2~D
BIA_PWM_LVDS 1 2 DISP_ON 1 2

G
BIA_PWM_GPU 46 PANEL_BKEN_DGPU 46

2
1

1
R1137 D68 R1138 D69 EN_INVPWR
42 EN_INVPWR
10K_0402_5%~D RB751V-40GTE-17_SOD323-2~D 100K_0402_5%~D RB751V-40GTE-17_SOD323-2~D FDC654P: P CHANNAL
1 2 BIA_PWM_EC 42 1 2 PANEL_BKEN_EC 41
2

2
Panel backlight power control by EC

+CAMERA_VDD

JCAM1 +5V_TSP +5V_RUN


CAM_MIC_CBL_DET#
For Webcam 1
2
1
2 USBP12_D+ CAM_MIC_CBL_DET# 17
@ R1592 Touch Screen Connector
3 USBP12_D- 0_0603_5%~D
3 +15V_ALW
4 1 2
B 4 DMIC_CLK B
5 DMIC_CLK 30
5 @U86
@ U86
6
6 DMIC0 PMV45EN_SOT23-3~D
7 DMIC0 30 1 GND 4 +3.3V_RUN
7 VCC

1
+CAMERA_VDD 8
8
1

1
SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D

0.1U_0402_25V4Z~D
S

D
9 3 1
G1 R430 USBP13- USBP13+
10 2 3
G2 IO1 IO2
@ D7

@ D8
S

3 1 +3.3V_RUN 100K_0402_5%~D Q32 1


+3.3V_ALW
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D

C306
JST_BM08B-SRSS-TB1-LF-SN~D PRTR5V0U2X_SOT143-4~D

G
2

2
Q23 CONN@
2

PMV45EN_SOT23-3~D
G

1 1
2

1
2
Place close JTCH1
C299

C300

R431
100K_0402_5%~D 1
2 2

DMN66D0LDW-7_SOT363-6~D
+5V_TSP

DMN66D0LDW-7_SOT363-6~D
C304

3
+15V_ALW @L10
@ L10 0.1U_0402_25V4Z~D
1

8
DLW21SN121SQ2L_4P~D 2 JTCH1 +5V_TSP

Q125B
C301 USBP12- 4 4 USBP12_D-
3 3
1 1

G2
0.1U_0402_16V4Z~D 17 USBP12-
1

0.1U_0402_10V7K~D
5 2 2
R429 2
3 1
18 E3_PAID_TS_DET# USBP13- 4 3

6
100K_0402_5%~D USBP12+ 1 2 USBP12_D+
17 USBP12+ 17 USBP13-

4
1 2 4

Q125A

C302
USBP13+ 5 5
17 USBP13+
6 6

G1
2

1 2 2 2
42 TOUCH_SCREEN_PD#
R427 0_0402_5%~D TYCO_1734595-6
Webcam PWR CTRL

7
1
1

D
SSM3K7002FU_SC70-3~D

1 2
CCD_OFF 2 1 R428 0_0402_5%~D
41 CCD_OFF
Q24

G CONN@
S C303
3

0.1U_0402_25V4Z~D
2
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP & CAM &TS Conn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 24 of 75
5 4 3 2 1
2 1

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+5V_RUN +3.3V_RUN

U93 1 1

B 46 GPU_CRT_RED 7
17
REDA
MAX14885E VCC 29 C1182
1U_0603_10V7K~D
C1181
1U_0402_6.3V6K~D B
16 PCH_CRT_RED REDB 2 2
VCC 21
46 GPU_CRT_GRN 8 GRNA
Channel A --> GPU 16 PCH_CRT_GRN 18 GRNB VL 11

46 GPU_CRT_BLU 9 BLUA
16 PCH_CRT_BLU 19 BLUB
RED1 33
RED_CRT 31
46 GPU_CRT_CLK_DDC 5 SCLA RED2 24
RED_DOCK 40
16 PCH_CRT_DDC_CLK 15 SCLB
GRN1 32
GREEN_CRT 31
Port 1 --> MB Port RGB
46 GPU_CRT_DAT_DDC 6 SDAA GRN2 23
GREEN_DOCK 40
16 PCH_CRT_DDC_DAT 16 SDAB
Channel B --> PCH +3.3V_RUN 1 2 CRT_EN 2 EN
BLU1
BLU2
31
22
BLUE_CRT
BLUE_DOCK
31
40
R1581 100K_0402_5%~D
46 GPU_CRT_HSYNC
16 PCH_CRT_HSYNC
3
13
SHA
SHB
SCL1
SCL2
35
26
CLK_DDC2_CRT 31
CLK_DDC2_DOCK 40
Port 2 --> Docking Port RGB
46 GPU_CRT_VSYNC 4 SVA SDA1 34 DAT_DDC2_CRT 31
16 PCH_CRT_VSYNC 14 SVB SDA2 25
DAT_DDC2_DOCK 40

41 EDID_SELECT# 1 S00 SH1 37


CRT_SWITCH HSYNC_BUF 31
41 CRT_SWITCH 40 28
S01 SH2 HSYNC_DOCK 40
23,41 DGPU_SELECT# 39
CRT_SWITCH S10
38 36
S11 SV1 VSYNC_BUF 31
27
SV2 VSYNC_DOCK 40
30
GND
20 12
GND NC
10
GND
41
GPAD
MAX14885EETL+T_TQFN40_5X5~D

CRT_SWITCH 0 0 1 1

DGPU_SELECT# 0 1 0 1

EDID_SELECT# 0 1 0 1

A --> Port 1 B --> Port 1 A --> Port 2 B --> Port 2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT/Video switch
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
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Date: Thursday, January 13, 2011 Sheet 25 of 75
2 1
2 1

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2
3
D4

NC
BAT1000-7-F_SOT23-3~D

1
+5V_RUN_HDMI

+VDISPLAY_VCC

2
0_1206_5%~D
+3.3V_RUN

@R5
@

10U_0805_10V4Z~D
F2

R5

0.1U_0402_10V7K~D
1 1
2A_8VDC_SMD1812P200TF

C337

C338
1

1
R443
4.7K_0402_5%~D 2 2

R1164

2
HDMI_OE# 10K_0402_5%~D JHDMI1
HDMI_HPD_SINK 1 2HDMI_HPD_SINK_R 19
HP_DET

1
+3.3V_RUN D
18 +5V
HDMI_HPD_SINK 2 Q25 +3.3V_RUN 17
G HDMI_SDA_SINK DDC/CEC_GND
SSM3K7002FU_SC70-3~D 16 SDA

1
1 2 HDMI_SDA_CTL S HDMI_SCL_SINK 15

3
@ R446 4.7K_0402_5%~D PJP54 SCL
14 Reserved
B HDMI_SCL_CTL HDMI_CEC B
1 2 PAD-OPEN1x1m 13 CEC
@ R447 4.7K_0402_5%~D TMDSE_CON_CLK# 12 CK-
11 CK_shield
TMDSE_CON_CLK 10

2
TMDSE_CON_N0 CK+
Close to U19 VCC pins 9 D0-
+3.3V_RUN_HDMI 8
TMDSE_CON_P0 D0_shield
7 D0+

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 1 1 1 1 1 1 1 TMDSE_CON_N1 6 D1-
5 D1_shield

C354

C339

C340

C341

C342

C343

C344

C345
TMDSE_CON_P1 4 20
TMDSE_CON_N2 D1+ GND
3 21

11
15
21
33
40
46
U19 2 2 2 2 2 2 2 2 D2- GND
2 D2_shield GND 22
TMDSE_CON_P2 1 23

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
D2+ GND
C346 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_P2 38 TYCO_2041270-1
47 TMDSE_GPU_P2 TMDSE_GPU_C_N2 IN1p
C347 2 1 0.1U_0402_10V7K~D 39 CONN@
47 TMDSE_GPU_N2 TMDSE_GPU_C_P1 IN1n
C348 2 1 0.1U_0402_10V7K~D 41
47 TMDSE_GPU_P1 TMDSE_GPU_C_N1 IN2p
C349 2 1 0.1U_0402_10V7K~D 42
47 TMDSE_GPU_N1 IN2n
C350 2 1 0.1U_0402_10V7K~D TMDSE_GPU_C_P0 44 23 TMDSE_RP_P2
47 TMDSE_GPU_P0 TMDSE_GPU_C_N0 IN3p OUT1p TMDSE_RP_N2
C351 2 1 0.1U_0402_10V7K~D 45 22
47 TMDSE_GPU_N0 TMDSE_GPU_C_CLK IN3n OUT1n TMDSE_RP_P1
C352 2 1 0.1U_0402_10V7K~D 47 20 1 2
47 TMDSE_GPU_CLK TMDSE_GPU_C_CLK# IN4p OUT2p TMDSE_RP_N1
C353 2 1 0.1U_0402_10V7K~D 48 19 @ R451 0_0402_5%~D
47 TMDSE_GPU_CLK# IN4n OUT2n TMDSE_RP_P0
+5V_RUN 17 L19
OUT3p TMDSE_RP_N0 TMDSE_RP_CLK TMDSE_CON_CLK
16 4 3
OUT3n TMDSE_RP_CLK 4 3
+3.3V_RUN 2 14
POW OUT4p TMDSE_RP_CLK#
13
HDMI_HPD_SINK OUT4n TMDSE_RP_CLK# TMDSE_CON_CLK#
30 1 2
HPD_SINK 1 2
2

+3.3V_RUN 1 2 26 DLW21SN900HQ2L_0805_4P~D
I2C_CTL_EN#
1
0_0402_5%~D

@ D65 R457 4.7K_0402_5%~D 1 2


R1163

32 @ R459 0_0402_5%~D
NC/DDCBUF_EN#
RB751V-40GTE-17_SOD323-2~D HDMI_OE# 25 7 DPE_GPU_HPD
NC/OE# HPD DPE_GPU_HPD 46
2

R460 2 1 1.5K_0402_5%~D HDMI_SDA_SINK 8


SDA
+5V_HDMI_DDC R461 2 1 1.5K_0402_5%~D HDMI_SCL_SINK 9
SCL TMDS_E_GPU_DDC#
29 TMDS_E_GPU_DDC# 47 1 2
HDMI_SDA_CTL SDAZ TMDS_E_GPU_DDC @ R462 0_0402_5%~D
34 28 TMDS_E_GPU_DDC 47
+3.3V_RUN HDMI_SCL_CTL SDA_CTL/CFG1 SCLZ L20
35
SCL_CTL/CFG0 TMDSE_RP_P0 TMDSE_CON_P0
4 3
PC0 4 3
1 2 3
I2C_ADDR0/PC0
R463 1 2 4.7K_0402_5%~D PC1 4
@R464
@ R464 4.7K_0402_5%~D I2C_ADDR1/PC1 TMDSE_RP_N0 TMDSE_CON_N0
1 2
PC2 1 2
1 2 1
GND/PC2
R465 4.7K_0402_5%~D DLW21SN900HQ2L_0805_4P~D
1 2
6 @ R466 0_0402_5%~D
REXT
GND10
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

10
CEXT
1
2

R467 C355 PS121QFN48G_QFN48_7X7 1 2


5
12
18
24
27
31
36
37
43
49

499_0402_1%~D 2.2U_0402_6.3V6M~D @ R468 0_0402_5%~D


2 L21
+3.3V_RUN TMDSE_RP_P1 4 3 TMDSE_CON_P1
1

4 3

TMDSE_RP_N1 1 2 TMDSE_CON_N1
HDMI_CEC 1 2
2 1
EQUALIZATION SETTING: R1165 10K_0402_5%~D DLW21SN900HQ2L_0805_4P~D
1 2
[PC2,PC1,PC0]=000, 12dB @ R469 0_0402_5%~D

[PC2,PC1,PC0]=001, 16dB
A A
[PC2,PC1,PC0]=010, 10dB 1 2
[PC2,PC1,PC0]=011, 7dB DPE_GPU_HPD 1 2 @ R470 0_0402_5%~D
R1128 100K_0402_5%~D L22
[PC2,PC1,PC0]=100, 1.5dB TMDSE_RP_P2 4 4
3
3 TMDSE_CON_P2

[PC2,PC1,PC0]=101, 4dB (Default)


TMDSE_RP_N2 TMDSE_CON_N2
[PC2,PC1,PC0]=110, 9dB 1
1 2
2

[PC2,PC1,PC0]=111, 7dB DLW21SN900HQ2L_0805_4P~D


1 2
@ R471 0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDMI port
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Tuesday, January 18, 2011 Sheet 26 of 75
2 1
5 4 3 2 1

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+3.3V_RUN
AUX/DDC GPU for DPC to E-DOCK 2
C356
1
AUX/DDC GPU for DPD to E-DOCK
+3.3V_RUN

2 1
C366
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C357 U20
D 0.1U_0402_10V7K~D C367 U23 D
1 BE0 VCC
14
DPC_GPU_AUX/DDC 2 1 DPC_GPU_AUX_C 2 13 0.1U_0402_10V7K~D 1 14
47 DPC_GPU_AUX/DDC A0 BE3 DPD_GPU_AUX/DDC BE0 VCC
47 DPD_GPU_AUX/DDC 2 1 DPD_GPU_AUX_C 2
A0 BE3 13
DPC_DOCK_AUX 3 12 DPC_GPU_AUX/DDC
40 DPC_DOCK_AUX B0 A3 DPD_DOCK_AUX DPD_GPU_AUX/DDC
40 DPD_DOCK_AUX 3 12
B0 A3
4 BE1 B3
11
DPC_GPU_AUX#/DDC 2 1 DPC_GPU_AUX#_C 5 10 4 11
47 DPC_GPU_AUX#/DDC A1 BE2 DPD_GPU_AUX#/DDC 2 BE1 B3
C360 0.1U_0402_10V7K~D
47 DPD_GPU_AUX#/DDC 1 DPD_GPU_AUX#_C 5
A1 BE2 10
DPC_DOCK_AUX# 6 9 DPC_GPU_AUX#/DDC C368 0.1U_0402_10V7K~D
40 DPC_DOCK_AUX# B1 A2 DPD_DOCK_AUX# 6 9 DPD_GPU_AUX#/DDC
40 DPD_DOCK_AUX# B1 A2
7 8
GND B2
7 GND B2 8
PI3C3125LEX_TSSOP14~D
PI3C3125LEX_TSSOP14~D

+5V_RUN
+5V_RUN
2 1
C365 2 1
0.1U_0402_16V4Z~D C369 0.1U_0402_16V4Z~D

1
P

NC
DPC_CA_DET 2 4 DPC_CA_DET#

NC
40 DPC_CA_DET A Y DPD_CA_DET DPD_CA_DET#
40 DPD_CA_DET 2 A Y 4

G
U21

G
NC7SZ04P5X-G_SC70-5~D U24

3
NC7SZ04P5X-G_SC70-5~D

3
C C

+3.3V_RUN

+3.3V_RUN
1

+15V_ALW
R1539

1
2.2K_0402_5%~D +15V_ALW
R1062
2.2K_0402_5%~D
2
1

+3.3V_ALW2 1 2
DMN66D0LDW-7_SOT363-6~D

R1537 @ R1538 0_0402_5%~D

2
6

1
100K_0402_5%~D +3.3V_ALW2 1 2

DMN66D0LDW-7_SOT363-6~D
R1063 @ R1064 0_0402_5%~D

6
Q113A

100K_0402_5%~D
2
1

Q111A
R1532

2
3

1
DMN66D0LDW-7_SOT363-6~D

100K_0402_5%~D 2
1

R1065

3
Q110B

DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D
2

1
B DPC_DOCK_AUX B
5
+3.3V_RUN

Q109B
2
6

DMN66D0LDW-7_SOT363-6~D

5 DPD_DOCK_AUX
4

+3.3V_RUN
1

6
Q110A

DMN66D0LDW-7_SOT363-6~D

4
DPC_CA_DET 2 R1530

1
Q109A
1 2.2K_0402_5%~D
DPD_CA_DET 2 R1066
1

C1174 2.2K_0402_5%~D
2

0.01U_0402_16V7K~D 1

1
2 1 2

2
@R1523
@ R1523 0_0402_5%~D C1175
3
DMN66D0LDW-7_SOT363-6~D

0.01U_0402_16V7K~D 1 2
2

DMN66D0LDW-7_SOT363-6~D
@ R1067 0_0402_5%~D

3
Q113B

Q111B
5
4

4
DPC_DOCK_AUX#

DPD_DOCK_AUX#

A A

DELL CONFIDENTIAL/PROPRIETARY
1 2 DPD_CA_DET
R491 1M_0402_5%~D
1 2 DPC_CA_DET Compal Electronics, Inc.
R492 1M_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DP AUX SW
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 27 of 75
5 4 3 2 1
5 4 3 2 1

+3.3V_RUN

WWW.AliSaler.Com

1
PJP63
PAD-OPEN1x1m

2
+3.3V_RUN_HDDR

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D
+3.3V_RUN
1 1

HDD Repeater

C381

C382
D D

2
2 2

0_0402_5%~D
@R1171
@

0_0402_5%~D
@ R1169

0_0402_5%~D
@R493
@

0_0402_5%~D
@R494
@
R1171

R493

R494
U25

1
7 6 +HDD_DEW2
EN VCC
18 10
PSATA_PTX_DRX_P0 CAD VCC +HDD_DEW1
14 PSATA_PTX_DRX_P0_C 2 1 VCC
16
C383 0.01U_0402_16V7K~D 1 20
PSATA_PTX_DRX_N0 AINP VCC
14 PSATA_PTX_DRX_N0_C 2 1 2
AINM
C384 0.01U_0402_16V7K~D 9 HDD_PE1
PSATA_PRX_DTX_N0 PA HDD_PE2
2 1 4 BOUTM PB 8
14 PSATA_PRX_DTX_N0_C C386 0.01U_0402_16V7K~D 5 BOUTP

10K_0402_5%~D

10K_0402_5%~D
2 1 PSATA_PRX_DTX_P0 15 PSATA_PTX_DRX_P0_RP
14 PSATA_PRX_DTX_P0_C AOUTP

1
@ R1172

@ R1170

0_0402_5%~D

0_0402_5%~D
@ R495
@R496
@
+3.3V_RUN C385 0.01U_0402_16V7K~D 3 14 PSATA_PTX_DRX_N0_RP
GND AOUTM

R496
13 GND
+HDD_EQ1 17 11 PSATA_PRX_DTX_P0_RP
+3.3V_RUN +HDD_EQ2 GND BINP PSATA_PRX_DTX_N0_RP
19 GND BINM 12
1

21

2
EP

10K_0402_5%~D

10K_0402_5%~D
PJP53

1
@ R1173

@ R1175
PAD-OPEN1x1m MAX4951BECTP+TGH7_TQFN20_4X4~D

Free Fall Sensor


2

2
+3.3V_RUN_FFS
10U_0805_6.3V6M~D

Note: +HDD_DEW1, +HDD_DEW2, +HDD_EQ1, +HDD_EQ2 need to route


1 1

1
10 mils and R1169,R1171,R1174,R1176 need to change to 10k and

0_0402_5%~D
@ R1174

0_0402_5%~D
@ R1176
U26
C387

C388 DE351DLTR
C 0.1U_0402_16V4Z~D no stuff R1174, R1176 to support TI SN75LVCP601 C
2 2 1 VDD_IO
6 2

2
VDD GND
GND 4
HDD_FALL_INT 8 5
17 HDD_FALL_INT FFS_INT2 INT 1 GND
9 INT 2 GND 10

12
SDO
7,12,13,14,15,36 DDR_XDP_WAN_SMBDAT 13
SDA / SDI / SDO
7,12,13,14,15,36 DDR_XDP_WAN_SMBCLK 14
SCL / SPC
3 +3.3V_RUN
RSVD
7
CS RSVD
11
HDD PWR
DE351DLTR8_LGA14_3X5~D
+5V_ALW
+15V_ALW

+3.3V_ALW2

1
@ R499

1
2
5
6
+3.3V_RUN 100K_0402_5%~D

1
JSATA1 D @ Q27
1 @ R500 G

2
DDR_XDP_WAN_SMBDAT PSATA_PTX_DRX_P0_RP C389 2 GND
1 2 1 0.01U_0402_16V7K~D SATA_PTX_DRX_P0 2 100K_0402_5%~D HDD_EN_5V 3 SI3456DDV-T1-GE3_TSOP6~D
PSATA_PTX_DRX_N0_RP C390 2 RX+
R501 10K_0402_5%~D 1 0.01U_0402_16V7K~D SATA_PTX_DRX_N0 3 S
RX-

DMN66D0LDW-7_SOT363-6~D
1 2 DDR_XDP_WAN_SMBCLK 4 +5V_HDD +5V_RUN

4
GND

3
R502 10K_0402_5%~D PSATA_PRX_DTX_N0_RP 2 1 SATA_PRX_DTX_N0 5 PJP3
TX-

@ Q28B

0.1U_0603_50V4Z~D
1 2 HDD_FALL_INT PSATA_PRX_DTX_P0_RP C391 2 1 0.01U_0402_16V7K~D SATA_PRX_DTX_P0 6 1 2
TX+ 1 2

10U_0805_10V4Z~D
R503 100K_0402_5%~D C392 0.01U_0402_16V7K~D 7
GND JUMP_43X79
PJP64 5 1 1

1
@ C393
8
3.3V SHORT DEFAULT

6
DMN66D0LDW-7_SOT363-6~D

C394
B +3.3V_RUN_HDD R504 B
+3.3V_RUN 1 2 9

4
3.3V

@ Q28A
10 100K_0402_5%~D
3.3V 2 2
11
PAD-OPEN1x1m HDD_DET# GND
12 42 HDDC_EN 2

2
14 HDD_DET# GND
13
GND
+5V_HDD 14

1
5V

1
15
+3.3V_RUN +5V_HDD +5V_HDD 5V R505
16
17
5V
GND
100K_0402_5%~D +5V_HDD Source
FFS_INT2_Q 18 23
Reserved GND1
1000P_0402_50V7K~D

19 24

2
GND GND2
1

20
@R506
@ R506 12V
1 1 21
100K_0402_5%~D 12V
22
12V
C395

C396
2
G

0.1U_0402_16V4Z~D JAE_SP100421-HDD
2

D16 2 2 CONN@
FFS_INT2 3 1 1 2 FFS_INT2_Q
18 FFS_INT2
Main SATA +5V Default
S

RB751S40T1_SOD523-2~D
Q29
SSM3K7002FU_SC70-3~D
Pleace near HDD CONN

+3.3V_RUN_HDD
0.1U_0402_16V4Z~D

A A
1 1
C402

C399
0.1U_0402_16V4Z~D
2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Pleace near HDD CONN BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDD CONNECTOR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 28 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
+3.3V_ALW

1 2 ZODD_WAKE#
R510 10K_0402_5%~D

1 2 MOD_MD
R513 10K_0402_5%~D
D D

+3.3V_ALW_PCH

2 USB30_SMI#
1
R514 100K_0402_5%~D +5VMOD Source
For ODD +15V_ALW +5V_ALW

1
+3.3V_ALW2
R507
100K_0402_5%~D

1
2
5
6
R509 D Q30

2
100K_0402_5%~D G
2 MOD_EN 3 SI3456DDV-T1-GE3_TSOP6~D
+5V_MOD S

3
DMN66D0LDW-7_SOT363-6~D
JSATA2 +5V_MOD +5V_RUN

4
0.1U_0603_50V4Z~D
PJP4
1000P_0402_50V7K~D

Q31B
1 GND 1 1 2 2
0.1U_0402_16V4Z~D

10U_0805_10V4Z~D
1 1 2 1 SATA_ODD_PTX_DRX_P1 2 MODC_EN# 5 1
14 SATA_ODD_PTX_DRX_P1_C A+

1
C407 2 1 0.01U_0402_16V7K~D SATA_ODD_PTX_DRX_N1 3 1 JUMP_43X79
14 SATA_ODD_PTX_DRX_N1_C A-

6
C397

C398

DMN66D0LDW-7_SOT363-6~D

C400
C406 0.01U_0402_16V7K~D 4 R511

4
GND

C401
2 1 SATA_ODD_PRX_DTX_N1 5 100K_0402_5%~D
2 2 14 SATA_ODD_PRX_DTX_N1_C B- 2

Q31A
C405 2 1 0.01U_0402_16V7K~D SATA_ODD_PRX_DTX_P1 6
14 SATA_ODD_PRX_DTX_P1_C C404 0.01U_0402_16V7K~D B+ 2
7 41 MODC_EN 2

2
GND

1
42 DEVICE_DET# 8

1
C DP R512 C
+5V_MOD 9 +5V
10 100K_0402_5%~D
MOD_MD +5V
11 MD
12

2
GND
Pleace near ODD CONN 13 GND
14 GND
15 CLK_PCIE_EMB 15
REFCLK+
15 CLK_PCIE_EMB# 16
REFCLK-
17
GND
15 PCIE_PRX_EMBTX_P4 18
PETX+
15 PCIE_PRX_EMBTX_N4 19
PETX-
20
GND
21
GND
15 PCIE_PTX_EMBRX_P4
0.1U_0402_10V7K~D 2 1 C409 PCIE_PTX_EMBRX_P4_C 22
PERX+
15 PCIE_PTX_EMBRX_N4
0.1U_0402_10V7K~D 2 1 C408 PCIE_PTX_EMBRX_N4_C 23
PERX-
24
GND

+5V_MOD 25
EMBCLK_REQ# +5V
15 EMBCLK_REQ# 26
PCIE_WAKE# CLKREQ#
36,37,41 PCIE_WAKE# 27
PLTRST_EMB# WAKE#
17 PLTRST_EMB# 28
BAY_SMBDAT PERST#
42,52 BAY_SMBDAT 29 32
BAY_SMBCLK SMB_DATA GND1
42,52 BAY_SMBCLK 30 33
SMB_CLK GND2
41 MOD_SATA_PCIE#_DET 31
HPD

+3.3V_ALW 1 2 TYCO_2-2129116-3
R1183 10K_0402_5%~D CONN@

B +3.3V_ALW B

1
R515
100K_0402_5%~D
Q76

2
SSM3K7002FU_SC70-3~D
USB30_EN
S

MOD_MD 3 1 ZODD_WAKE#
ZODD_WAKE# 41

6
Q123A
G

DMN66D0LDW-7_SOT363-6~D
2

MODC_EN# MOD_SATA_PCIE#_DET 2

1
Q123B
DMN66D0LDW-7_SOT363-6~D
4 3 USB30_SMI#
USB30_SMI# 14
5

USB30_EN

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ODD CONNECTOR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 29 of 75
5 4 3 2 1
2 1

DVDD_IO should match


WWW.AliSaler.Com
Internal Speakers Header Speaker Connector
with HDA Bus level
+3.3V_RUN +3.3V_RUN
Notes:
Keep PVDD supply and speaker traces routed on the DGND plane.
Keep away from AGND and other analog signals
L77
place close to pin27 place close to pin38 BLM21PG600SN1D_0805~D
+VDDA_AVDD 1 2 +5V_RUN

10U_0805_10V6K~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D
20 mils trace JSPK1 CONN@

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D

10U_0805_10V6K~D
INT_SPK_L+ L91 1 2 BLM18BD121SN1D_2P~D INT_SPK_L+_L 1
INT_SPK_L- L92 1 2 BLM18BD121SN1D_2P~D INT_SPK_L-_L 2
1 1 1 1 1 Place C951~C961 close to Codec 1 1 1 1 1
2

C994

C953

C955

C956

C957

C1172

C1173
INT_SPK_R+ L93 1 2 BLM18BD121SN1D_2P~D INT_SPK_R+_L 3 5
3 G1

C952

C954
INT_SPK_R- L94 1 2 BLM18BD121SN1D_2P~D INT_SPK_R-_L 4 6
4 G2 2 2 2 2 U72 2 2 2 2 2
MOLEX_53398-0471~D 1 27
DVDD_CORE AVDD1 R1095
38
AVDD2
680P_0402_50V7K~D

680P_0402_50V7K~D

680P_0402_50V7K~D

680P_0402_50V7K~D
0_0805_5%~D

2
PESD5V0U2BT_SOT23-3~D

PESD5V0U2BT_SOT23-3~D
3 45 +VDDA_PVDD 1 2
DVDD_IO PVDD +5V_RUN

@ DE1

@ DE2
39
PVDD

10U_0805_10V6K~D

0.1U_0402_16V4Z~D

10U_0805_10V6K~D

0.1U_0402_16V4Z~D
1 1 1 1 1 1 1 1
9 13 AUD_SENSE_A
DVDD SENSE_A
C973

C974

C975

C976

C958

C959

C960

C961
14 AUD_SENSE_B
SENSE_B
2 2 2 2 MIC_IN_L MIC_IN_R 31 2 2 2 2
28 1 2
PCH_AZ_CODEC_BITCLK PORTA_L MIC_IN_RR C1163 1U_0402_6.3V6K~D
14 PCH_AZ_CODEC_BITCLK 6 29
BITCLK PORTA_R
23 1 2 +VREFOUT_R

1
PCH_AZ_CODEC_SDOUT VrefOut_A R1143 2.2K_0402_5%~D
14 PCH_AZ_CODEC_SDOUT 5 SDATA_OUT +VREFOUT
31 AUD_HP_OUT_L
PORTB_L AUD_HP_OUT_R AUD_HP_OUT_L 31
14 PCH_AZ_CODEC_SYNC 10 SYNC PORTB_R 32
AUD_HP_OUT_R 31
Place R1096 close to codec MIC_IN_L and MIC_IN_RR Pop R161 0-ohm for Combo Jack,
1 2 PCH_AZ_SDIN0_R 8 40 INT_SPK_L+
B 14 PCH_AZ_CODEC_SDIN0 R1096 33_0402_5%~D SDATA_IN PORTD_+L INT_SPK_L- must symmetric in layout pop C1164 1UF for E2 backup circuit B
PORTD_-L 41
PCH_AZ_CODEC_RST# 11 MIC_IN_RR 1 2
14 PCH_AZ_CODEC_RST# RESET#
44 INT_SPK_R+ R161 0_0402_5%~D
PORTD_+R INT_SPK_R- +VREFOUT_R 2 MIC_IN_R
PORTD_-R 43 1
D70 RB751V-40GTE-17_SOD323-2~D
I2S_12MHZ 15 25 1 2 SPKR_R 1 2
I2S_MCLK MONO_OUT SPKR 14
C1105 0.1U_0402_16V4Z~D R1119 100K_0402_5%~D
I2S_BCLK 16 12 AUD_PC_BEEP 1 2 BEEP_R 1 2
I2S_SCLK PC_BEEP BEEP 42
C1106 0.1U_0402_16V4Z~D R1120 100K_0402_5%~D
I2S_DO 1 2 I2S_DO_R 17 LE93 1 2
R1097 33_0402_5%~D I2S_DOUT DMIC_CLK_L 1 @ R1141 10K_0402_5%~D
DMIC_CLK/GPIO 1 2 2
I2S_LRCLK BLM18BB221SN1D_2P~D DMIC_CLK 24
Place R1097 close to codec 18 I2S_LRCLK DMIC_0/GPIO 2 4 DMIC0 24 1 2
46 Place LE93 close to codec @ R1142 10K_0402_5%~D
I2S_DI# DMIC1/GPIO0/SPDIFOUT1
Close to U16 pin5 Close to U16 pin6 24 I2S_DIN SPDIFOUT0//GPIO3/Aux_Out 48

CAP+ 36
PCH_AZ_CODEC_SDOUT PCH_AZ_CODEC_BITCLK 1
19 C962
No Connect 4.7U_0603_10V6K~D
1

20 No Connect Place C962 close to Codec


@R1077
@ R1077 @ R1076 35 2
47_0402_5%~D 10_0402_5%~D CAP- +VREFOUT_R
Place C963~C966 close to Codec
41 AUD_NB_MUTE# 47 EAPD VREFFILT 21

1U_0603_10V6K~D
22 1
2

+3.3V_RUN CAP2
1 1 34
V-

C1180
7 37
DVSS Vreg

4.7U_0603_10V6K~D

4.7U_0603_10V6K~D

1U_0603_10V6K~D

10U_0805_10V6K~D
@C978
@C978 @ C977 1 1 1 1
0.1U_0402_10V7K~D 10P_0402_50V8J~D 1 2 42 26 2
2 2 PVSS AVSS1

C963

C964

C965

C966
R1099 10K_0402_5%~D 30
AVSS
49 33
GND AVSS 2 2 2 2
92HD90B2X5NLGXZBX8_QFN48_7X7~D

Place closely to Pin 13. +VDDA_AVDD


change C981 to jumper to solve audio noise issue ( Special Head phone only)
@ C981
R1083 100P_0402_50V8J~D
2.49K_0402_1%~D 1 2
AUD_SENSE_A 2 1 Tie Analog Ground to Digital ground
under codec by a single point +3.3V_RUN +3.3V_RUN
1000P_0402_50V7K~D

@ C982
+3.3V_RUN +3.3V_RUN PJP62
39.2K_0402_1%~D

1 100P_0402_50V8J~D
1

0.1U_0402_10V7K~D
2 1 1 2
C980
@ R352

R1086
20K_0402_1%~D
1

2
2

DA204U_SOT323-3~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D

DA204U_SOT323-3~D
PAD-OPEN1x1m @ C983 2

C1103

@ D54

@ D55

@ D56

@ D57
@ R1088 R1087 100P_0402_50V8J~D
2

100K_0402_5%~D 100K_0402_5%~D GNDA1 2


RE1101 CE574
6

1 U73 33_0402_5%~D 12P_0402_50V8J~D


2

16 1 2 1 2

1
VCC
2 5 I2S_BCLK 1 2 2 3
31 AUD_MIC_SWITCH AUD_HP_NB_SENSE 31,41 1A 1Y# DAI_BCLK# 40
RE1098 33_0402_5%~D
Q107A Q107B 1 PORT A External MIC I2S_LRCLK 4 5
1

DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D 2A 2Y# DAI_LRCK# 40


@C967
@C967 I2S_DO 6 7
3A 3Y# DAI_DO# 40
0.1U_0402_16V4Z~D PORT B HeadPhone Out
2 I2S_12MHZ 1 2 10 9
RE1100 33_0402_5%~D 4A 4Y# DAI_12MHZ# 40
PORT C Dock Audio 12 11 RE1102 CE573
5A 5Y#
Add for solve pop noise and detect issue 33_0402_5%~D 12P_0402_50V8J~D
A I2S_DI# A
14 13 1 2 1 2
6A 6Y#
PORT D Internal SPK
41 EN_I2S_NB_CODEC# 1
OE1#
2 1 15 8
OE2# GND
Place closely to Pin 14 R1110 +3.3V_RUN
+VDDA_AVDD Resistor SENSE_A SENSE_B 1K_0402_5%~D CD74HC366M96_SO16~D
R1078
2.49K_0402_1%~D

2
AUD_SENSE_B 2 1 39.2K PORT A PORT E
@ D58
1000P_0402_50V7K~D

1 DA204U_SOT323-3~D
20K PORT B PORT F
1

+3.3V_RUN
C979

R1079 R1080 +3.3V_RUN

1
39.2K_0402_1%~D 20K_0402_1%~D 2
2.49K Pull-up to AVDD
1

DAI_DI 40
1

R1081
2

100K_0402_5%~D R1082
100K_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
2

2 5
Compal Electronics, Inc.
41 DOCK_HP_DET DOCK_MIC_DET 41 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
Q106A Q106B TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Azalia (HD) Codec
1

DMN66D0LDW-7_SOT363-6~D DMN66D0LDW-7_SOT363-6~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 30 of 75
2 1
5 4 3 2 1

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SW1 I/O board CONN.
2 1
42,43 POWER_SW#_MB
Change to TYCO_2041300-2_60P-T and Horizonal reverse to SSI
4 3
JIO1
SKRBAAE010_4P~D 2 1
2 1 IO_LOOP# 18
32 SW_LAN_TX0+ 4 3 VSYNC_BUF 25
4 3
32 SW_LAN_TX0- 6 5 HSYNC_BUF 25
6 5
8 7
D @ D23 8 7 D
32 SW_LAN_TX1- 10 9 RED_CRT 25
10 9
3 32 SW_LAN_TX1+ 12
12 11
11 GREEN_CRT 25
1 PESD24VS2UT_SOT23-3~D 14 13
14 13 BLUE_CRT 25
2 32 SW_LAN_TX2+ 16 15
16 15
32 SW_LAN_TX2- 18 17 DAT_DDC2_CRT 25
18 17
20 19 CLK_DDC2_CRT 25
@ SW2 20 19
32 SW_LAN_TX3- 22 21
22 21
2 1 32 SW_LAN_TX3+ 24
24 23
23
42 LAT_ON_SW_BTN# XFR_ID_BIT# 42
26 25
26 25
+5V_RUN 28 27
28 27
4 3 +3.3V_LAN 30
30 29
29 AUD_HP_OUT_R 30
+5V_ALW 32 31 MIC_IN_R +5V_ALW
32 LED_100_ORG# 32 31 MIC_IN_R 30
SKRBAAE010_4P~D 34 33
32 LED_10_GRN# 34 33 AUD_HP_OUT_L 30
32 LAN_ACTLED_YEL# 36 36 35 35
38 38 37 37

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 40 40 39 39 1
42 42 41 41

C50

C1003
44 44 43 43 +3.3V_ALW_PCH
17,39 USB_OC1#
46 46 45 45
2 PCH_AZ_MDC_RST1# 2
48 47
POWER & INSTANT ON SWITCH 17
17
USBP3+
USBP3- 50
48
50
47
49 49 PCH_AZ_MDC_SDIN1 14
52 52 51 51 PCH_AZ_MDC_SYNC 14
39,41 ESATA_USB_PWR_EN# 54 54 53 53
PCH_AZ_MDC_SDOUT 14
56 56 55 55
30,41 AUD_HP_NB_SENSE
58 57
Defult on, Media Board DETECT_GND 60
58
60
57
59 59
PCH_AZ_MDC_BITCLK 14

WIRELESS_ON/OFF#: 62 GND GND 61


JMDIA1 64 63
LOW: ON 42 VOL_MUTE 1 1 66
GND
GND
GND
GND 65 Analog_GND
2
HIGH: OFF 42 VOL_DOWN
3
2
C 42 VOL_UP 3 C
4 4
+3.3V_ALW 5 TYCO_2041300-2
5 CONN@
6 6
41 WIRELESS_ON#/OFF
41,45 LID_CL# 7 7
8 8
9 +3.3V_ALW_PCH
9
10 10 +3.3V_LAN
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
1 11 13 1
11 GND
12 14
18 MEDIA_DET# 12 GND
C1001

0.1U_0402_16V4Z~D

C1000
1
TYCO_1-2041070-2~D
2 2

C997
CONN@
2

Place close
to JIO1.35
Place close
to JIO1.13
LED Board
JLED1
1
18 LEDB_DET# 1
45 BATT_WHITE 2
2
45 BATT_YELLOW 3
3
45 SATA_LED 4
4
45 WLAN_LED 5 7
5 G1 @ PJP65 PAD-OPEN1x1m
6 8
6 G2
1 2
B TYCO_2041084-6~D B
CONN@
+5V_MIC @ Q33
@ @ C307 +5V_RUN SI2301CDS-T1-GE3_SOT23-3~D
R425

D
1 2 1 2 3 1 +5V_MIC
0.1U_0402_16V4Z~D

1 100K_0402_5%~D
0.1U_0402_16V4Z~D

G
2
5
@ C308 @ U6

2
1

P
2 IN+ @ R424
4
O AUD_MIC_SWITCH 30
1
RB751V-40GTE-17_SOD323-2~D

3 47K_0402_5%~D
IN-

G
@ R38 LMV331IDCKRG4_SC70-5~D

1
560K_0402_1%~D
2

+5V_ALW_MIC_G
2
@

Q44
D71

SSM3K7002FU_SC70-3~D @ Q46
SSM3K7002FU_SC70-3~D
1

1 3 PCH_AZ_MDC_RST1# 1 3
D

S
14 PCH_AZ_MDC_RST#
@ R33
1

+5V_ALW 47K_0402_1%~D
G

G
2

2
1

MIC_IN_R
2

R751
1

100K_0402_5%~D AUD_HP_NB_SENSE
30,41 AUD_HP_NB_SENSE
R752 SI2301CDS: P CHANNAL
10K_0402_5%~D
need to route the trace as short as possible
2
2

A A
41 MDC_RST_DIS#

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PWR SW/Sub-board Connector
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev

WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6592P
Date: Thursday, January 13, 2011 Sheet 31 of 75
5 4 3 2 1
5 4 3 2 1

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+3.3V_LAN

+3.3V_RUN

1 2 TP_LAN_JTAG_TMS

1
@ R545 10K_0402_5%~D
1 2 TP_LAN_JTAG_TCK R547
@ R546 10K_0402_5%~D 10K_0402_5%~D

2
@ R1187 U31
0_0402_5%~D Default solution:
1 2 LANCLK_REQ#_R 48 13 LAN_TX0+ PCH +1.05V_M SVR - stuff R119, unstuff L99
15 LANCLK_REQ# CLK_REQ_N MDI_PLUS0 LAN_TX0-
17 PLTRST_LAN# 36 14 Also, option to use iSVR - stuff L99, unstuff R119
D PE_RST_N MDI_MINUS0 D
CLK_PCIE_LAN 44 17 LAN_TX1+
15 CLK_PCIE_LAN CLK_PCIE_LAN# PE_CLKP MDI_PLUS1 LAN_TX1-
15 CLK_PCIE_LAN# 45 18

PCIE
PE_CLKN MDI_MINUS1

MDI
15 PCIE_PRX_GLANTX_P7 2 1 PCIE_PRX_GLANTX_P7_C
C458 0.1U_0402_10V7K~D 38 20 LAN_TX2+
PETp MDI_PLUS2 +1.0V_LAN +1.05V_M
15 PCIE_PRX_GLANTX_N7 2 1 PCIE_PRX_GLANTX_N7_C 39
PETn MDI_MINUS2
21 LAN_TX2-
C459 0.1U_0402_10V7K~D @R548
@ R548
+3.3V_LAN 1 2 PCIE_PTX_GLANRX_P7_C 41 23 LAN_TX3+ L29 0_0805_5%~D
15 PCIE_PTX_GLANRX_P7 PERp MDI_PLUS3 LAN_TX3- REGCTL_PNP10
C460 0.1U_0402_10V7K~D 42 24 1 2 1 2
PERn MDI_MINUS3

10U_0805_6.3V6M~D

0.1U_0402_10V7K~D
15 PCIE_PTX_GLANRX_N7 1 2 PCIE_PTX_GLANRX_N7_C
1

C461 0.1U_0402_10V7K~D 4.7UH_CBC2012T4R7M_20%~D 1 1

C462

C463
R549 @R551
@ R551 0_0402_5%~D 28 6 Idc max=330mA

SMBUS
SMB_CLK RSVD_NC
10K_0402_5%~D
15 LAN_SMBCLK 1 2 LAN_SMBCLK_R 31 SMB_DATA
15 LAN_SMBDATA 1 2 LAN_SMBDATA_R 1 +RSVD_VCC3P3_1 2 1 +3.3V_LAN
@R552
@ R552 0_0402_5%~D RSVD_VCC3P3_1 +RSVD_VCC3P3_2 R553 2 2 2
2 1 4.7K_0402_1%~D
2

RSVD_VCC3P3_2
@R555
@ R555 SMBus Device Address 0xC8 VDD3P3_IN 5 R554 4.7K_0402_1%~D
1 2 LAN_DISABLE#_R 3
18 PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
VDD3P3_OUT 4
0_0402_5%~D 1
41 LAN_DISABLE#_R Place R548, C462, C463 and L29 close to U31
VDD3P3_15 15
1

LOM_ACTLED_YEL# 26 19 C464
@ R557 LOM_SPD100LED_ORG# LED0 VDD3P3_19 1U_0603_10V6K~D
27 LED1 VDD3P3_29 29

LED
10K_0402_5%~D LOM_SPD10LED_GRN# 25 +1.0V_LAN 2
LED2
47 +1.0V_LAN +3.3V_LAN
2

VDD1P0_47
VDD1P0_46 46
@ T142 PAD~D TP_LAN_JTAG_TDI 32 37
@ T143 PAD~D TP_LAN_JTAG_TDO JTAG_TDI VDD1P0_37
34 JTAG_TDO

JTAG

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D
TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK JTAG_TMS VDD1P0_43
35 JTAG_TCK 1 1 1 1 1 1

C1177

C1178
VDD1P0_11 11

C466

C467

C468

C469
C XTALO C
1 2 9 XTAL_OUT VDD1P0_40 40
@ R1144 0_0402_5%~D XTALI 10 22 2 2 2 2 2 2
Y3 XTAL_IN VDD1P0_22
VDD1P0_16 16
25MHZ_18PF_7A25000110~D 8
LAN_TEST_EN VDD1P0_8
1 2 30 TEST_EN
33P_0402_50V8J~D

33P_0402_50V8J~D

RES_BIAS 12 7 REGCTL_PNP10 Place C1178 close to pin5


RBIAS CTRL_1P0
2 2
49
VSS_EPAD
1

1
C470

C471

1K_0402_5%~D

3.01K_0402_1%~D

Note:
R561

R562

82579_QFN48_6X6~D +1.0V_LAN will work at 0.95V to 1.15V


1 1 +3.3V_M

+1.0V_LAN POWER OPTIONS


2

2
Shared with PCH
Need to verify A3 silicon drive R1200 Resistor Value: 1.05V SVR * Internal SRV @ R563
power before removing C427 3.01 kohm for Hanksville-M LOM 0_1206_5%~D
KDS crystal vender verify 2.37 kohm for Hanksville-D LOM STUFF: R548 STUFF: L29

1
driving level in A3 NO STUFF: L29 NO STUFF: R548 Q34
+3.3V_ALW +3.3V_LAN
SI3456DDV-T1-GE3_TSOP6~D
+15V_ALW

D
6
SWAP for layout routing

S
+3.3V_LAN +3.3V_ALW2 5 4

1
2
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_10V7K~D
R564 1 1 1
2 2 2 100K_0402_5%~D

C475

C476
3
1
C472

C473

C474

LAN ANALOG

2
R565 ENAB_3VLAN 2 2
B 1 1 1 100K_0402_5%~D B
SWITCH

3
DMN66D0LDW-7_SOT363-6~D

2200P_0402_50V7K~D
39
30
21
14

2
8
4
1

Q35B
U32 1
5
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C477
38 SW_LAN_TX3- 31
B0+

6
DMN66D0LDW-7_SOT363-6~D
37 SW_LAN_TX3+ 31

4
LAN_TX3- LAN_TX3-R B0- 2
1 2 2
A0+

Q35A
L37 12NH_0603CS-120EJTS_5%~D 34
LAN_TX3+ 1 LAN_TX3+R B1+ SW_LAN_TX2- 31
2 3
A0- B1-
33 42 AUX_ON 1 2 2
L36 12NH_0603CS-120EJTS_5%~D SW_LAN_TX2+ 31 @ R566 0_0402_5%~D
29 SW_LAN_TX1- 31

1
LAN_TX2- LAN_TX2-R B2+
1 2 6 28 SW_LAN_TX1+ 31 16,41 SIO_SLP_LAN# 1 2
L35 12NH_0603CS-120EJTS_5%~D A1+ B2- @ R567 0_0402_5%~D
LAN_TX2+ 1 2 LAN_TX2+R 7 25
A1- B3+ SW_LAN_TX0- 31
L34 12NH_0603CS-120EJTS_5%~D 24
B3- SW_LAN_TX0+ 31
LAN_TX1- 1 2 LAN_TX1-R 9 17
A2+ LEDB0 LAN_ACTLED_YEL# 31
L32 12NH_0603CS-120EJTS_5%~D 18
LAN_TX1+ 1 LAN_TX1+R LEDB1 LED_100_ORG# 31
2 10 41 LED_10_GRN# 31
L33 12NH_0603CS-120EJTS_5%~D A2- LEDB2
36 +3.3V_LAN C478
LAN_TX0- LAN_TX0-R C0+ DOCK_LOM_TRD3- 40
1 2 11 35 0.1U_0402_10V7K~D
A3+ C0- DOCK_LOM_TRD3+ 40
L31 12NH_0603CS-120EJTS_5%~D 1 2
LAN_TX0+ 1 2 LAN_TX0+R 12 32
L30 12NH_0603CS-120EJTS_5%~D A3- C1+ DOCK_LOM_TRD2- 40
31
C1- DOCK_LOM_TRD2+ 40

5
DOCKED 13 27 LOM_SPD100LED_ORG# 1

P
41 DOCKED SEL C2+ DOCK_LOM_TRD1- 40 B
26 DOCK_LOM_TRD1+ 40 4
C2- LOM_SPD10LED_GRN# O WLAN_LAN_DISB# 41
2
A

G
LOM_ACTLED_YEL# 15 23
LEDA0 C3+ DOCK_LOM_TRD0- 40
LOM_SPD100LED_ORG# 16 22 TC7SH08FU_SSOP5~D
DOCK_LOM_TRD0+ 40

3
A LOM_SPD10LED_GRN# LEDA1 C3- U15 A
Layout Notice : Place bead as 42 LEDA2
close PI3L720 as possible LEDC0 19 DOCK_LOM_ACTLED_YEL# 40
5 20 DOCK_LOM_SPD100LED_ORG#
PD LEDC1 DOCK_LOM_SPD100LED_ORG# 40
40 DOCK_LOM_SPD10LED_GRN#
LEDC2 DOCK_LOM_SPD10LED_GRN# 40
43 PAD_GND DELL CONFIDENTIAL/PROPRIETARY
1: TO DOCK
FROM NIC DOCKED
0: TO RJ45 TO
Compal Electronics, Inc.
PI3L720ZHEX_TQFN42_9X3P5~D Title
DOCK
Intel 82579 (Hanksville) / LAN SW
Size Document Number Rev

WWW.AliSaler.Com
1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 32 of 75
5 4 3 2 1
5 4 3 2 1

Q36 +3.3V_ALW_PCH +3.3V_ALW_USH +3.3V_ALW +3.3V_ALW_USH


USB_GPIO27 1

USBP7+
@ R575
1 WWW.AliSaler.Com 2
0_0402_5%~D
2
SI2301CDS-T1-GE3_SOT23-3~D

1
1
R577
2 RST_N
4.7K_0402_5%~D
PJP56

S
3 2 1

D
R576 1.5K_0402_5%~D 1 2 OVSTB U33D

2
+3.3V_ALW_USH R578 4.7K_0402_5%~D PAD-OPEN 2x2m~D
R580 1 2 FP_RESET# BCM5882

G
2
1 2 PLTRST1#_USH 4.7K_0402_5%~D R582 4.7K_0402_5%~D REF_XIN G14 REFCLK_XTALIN UART_TX_GPIO_1 D4 UART_TX/GPIO1
@ R579 10K_0402_5%~D 1 2 SPI_RST REF_XOUT F14 C4 UART_RX/GPIO0
REFCLK_XTALOUT UART_RX_GPIO_0
1 2 USH_LPCEN R645 4.7K_0402_5%~D JTAG_CLK_USH B3

UART
1
1@ R583 4.7K_0402_5%~D Q37 U33A @ R591 UART_CTS_GPIO_2 BT_COEX_STATUS2 FP_RESET# 23
UART_RTS_GPIO_3 A3 BT_COEX_STATUS2 43
+3.3V_ALW_USH

CLK
2 LPD# SSM3K7002FU_SC70-3~D @ R587 0_0402_5%~D RST_N
1
BCM5882 G1 RST_N

1
@ R584 4.7K_0402_5%~D D 0_0402_5%~D 1 2
1 2 IRQ_SERIRQ_R 2USB_GPIO27
17 USBP7- 1 2 USBP7-_R P5 USBD_DN USBH_DN_0 P7 FP_USBD-
FP_USBD- 23
R581 4.7K_0402_5%~D G 1 2 USBP7+_R P6 P8 FP_USBD+ JTAG_TDI_USH L14
D 17 USBP7+ USBD_UP USBH_UP_0 FP_USBD+ 23 NC D
1 2 USH_SMBCLK S USB_GPIO27 N7 P9 USBH_OC0# 2 1

3
R589 2.2K_0402_5%~D @ R588 USBD_ATTACH_GPIO_27 USBH_OC_0 R590 4.7K_0402_5%~D JTAG_TDO_USH JTAG_CLK_USH L1 JTAG_TCK
1 2 USH_SMBDAT 0_0402_5%~D
USBH_DN_1 P11 @ R599 JTAG_TDI_USH M1 JTAG_TDI GPIO_4 J1 CONTACTLESS_DET#
R585 2.2K_0402_5%~D P12 0_0402_5%~D JTAG_TDO_USH N1 D2 SCC_CMDVCC_N_R

JTAG
USBH_UP_1 JTAG_TDO GPIO_14
1 2 BCM5882_ALERT# 15 CLK_PCI_TPM
CLK_PCI_TPM P2 LCLK USBH_OC_1 P10 USBH_OC1 1 2 JTAG_TMS_USH N2 JTAG_TMS GPIO_15 C2 BCM5882_GPIO15
R592 2.2K_0402_5%~D R593 1 2 0_0402_5%~D N3 JTAG_RST#_USH L3 B1 BT_PRI_STATUS
14,34,41,42 LPC_LAD0 LAD0_GPIO_20 JTAG_TRSTN GPIO_16 BT_PRI_STATUS 43
1 2 USH_PWR_STATE# 14,34,41,42 LPC_LAD1
R594 1 2 0_0402_5%~D M4 LAD1_GPIO_21
JTAG_TMS_USH JTCE_USH L2 JTCE
R586 4.7K_0402_5%~D R595 1 2 0_0402_5%~D K5
14,34,41,42 LPC_LAD2 LAD2_GPIO_22

2
1 2 USBH_OC1 R597 1 2 0_0402_5%~D N4 G3 SPI_CLK JTAG_RST#_USH D3 CLKOUT

@
14,34,41,42 LPC_LAD3 LAD3_GPIO_23 SSP_CLK0_GPIO_6 CLKOUT T144 PAD~D
R596 4.7K_0402_5%~D R598 1 2 0_0402_5%~D K4 G2 SPI_CS @ R605 @ R601 OVSTB E1
14,34,41,42 LPC_LFRAME# IRQ_SERIRQ_R LFRAME_N_GPIO_18 SSP_FSS0_GPIO_7 SPI_RXD 0_0402_5%~D 0_0402_5%~D OVSTB
14,34,41,42 IRQ_SERIRQ 1 2 L4 LSERIRQ_GPIO_19 SSP_RXD0_GPIO_8 H1
@ R600 0_0402_5%~D H2 SPI_TXD 1 2 C1 SPI_RST
CLK_PCI_TPM PLTRST1#_USH SSP_TXD0_GPIO_9 SCANACCMODE RSTOUT_N
17 PLTRST_USH# 1 2 M3 E3

1
LRESET_N_GPIO_17 SCANACCMODE

SPI
@ R602 0_0402_5%~D USH_LPCEN M5 C3 BCMGPIO_10 JTCE_USH @ T145 PAD~D

@@@@
T146PAD~D

LPC
LPCEN SSP_CLK1_GPIO_10
1

1 2 LPD# N6 B2 BCMGPIO_11 T147PAD~D


34,41 SP_TPM_LPC_EN LPCPD_N_GPIO_24 SSP_FSS1_GPIO_11
@ R603 @ R604 0_0402_5%~D A2 BCMGPIO_12 HF_RX_TEST0 SBOOT E2 J13 POR_MONITOR

@
SSP_RXD1_GPIO_12 T148PAD~D SECURE_BOOT POR_MONITOR T149PAD~D
10_0402_5%~D A1 BCMGPIO_13 T150PAD~D @ R621
USH_SMBCLK SSP_TXD1_GPIO_13 0_0402_5%~D
42 USH_SMBCLK M9 SMBCLK
USH_SMBDAT L9 1 2 USH_TESTMODE D1 K11 SWV

@
42 USH_SMBDAT T151PAD~D
2

BCM5882_ALERT# SMBDAT TESTMODE SWV


41 BCM5882_ALERT# K9 SMBALERT_N

Smard Card
SC_DET R606 1 2 150_0402_5%~D M11 @ R607 2 0_0402_5%~D BCM5882_SCCLK HF_RX_TEST1
PCI_TPM_TERM

M7 SMB_GPIO_0 SC_CLK 1

2
BT_COEX_STATUS2 1 2 SMB_GPIO1 N8 M12 @ R608 2 1 0_0402_5%~D AUX1UC POR_EXTR J14 C13 PLL_TESTOUT

@
SMB_GPIO_1 SC_FCB POR_EXTR PLL_TESTOUT T153PAD~D
@ R1131 0_0402_5%~D F2 @@R609
R609 2 1 0_0402_5%~D BCM5882_GPIO25 HF_RX_TEST2 @ R626
SC_SEL5V_GPIO_25
4.7P_0402_50V8C~D

1 2 JTAG_RST#_USH SC_SEL18V_GPIO_26 F1 @ R611 2 1 0_0402_5%~D BCM5882_GPIO26 @ R618 1K_0402_5%~D


R610 1K_0402_5%~D 2 USH_PWR_STATE#_R M2 @ R614 2 0_0402_5%~D BCM5882_SCDET 0_0402_5%~D

SM BUS
41 USH_PWR_STATE# 1 L7 WAKEUP_N SC_DET 1
1 2 USH_LPCEN @ R613 0_0402_5%~D L11 @ R616 2 1 0_0402_5%~D BCM5882_IO 1 2 BCM5882KFBG_FBGA196~D

1
2@ R615 4.7K_0402_5%~D SC_IO BCM5882_SCRST
1 2 K1 IDDQ_EN SC_RST M10 @ R620 2 1 0_0402_5%~D
2 R619 1K_0402_5%~D N14 +SC_PWR HF_RX_TEST3
SC_PWR_N14
@ C486

1 2 P1 CORE_PWRDN SC_PWR_P14 P14


R622 1K_0402_5%~D L10 SC_TEST 2 1 SCC_CMDVCC_N U33C
SC_VCC @ R623 0_0402_5%~D

C
1 R624
1 2
1K_0402_5%~D
E12 ALDO_PWRDN
@ R625 1 2 0_0402_5%~D RFTAG_VRXP A6
BCM5882 A8 RFREADER_TXP1 C
HF_RFIDTAG_VRX_P HF_TX_P
1 2 REF_XOUT @ R628 1 2 0_0402_5%~D RFTAG_VRXN B6 HF_RFIDTAG_VRX_N HF_TX_N B8 RFREADER_TXN1
@ R627 0_0402_5%~D
C5 A10 RFREADER_RXP
REF_XIN HF_RFIDTAG_VTX HF_RX_P RFREADER_RXN
1 2 All XTAL components and traces should be BCM5882KFBG_FBGA196~D C487 should be placed HF_RX_N B10
@ R612 10M_0402_5%~D
placed/layout on top layer. The gnd/pwr closer to pin A5
Y4 layer below will provide shielding from +3.3V_ALW_USH 1 2 A5 B9 HF_RX_TEST0
XI XO +1.2V_ALW_AVDD +2.5V_ALW_AVDD C487 0.01U_0402_16V7K~D HF_RFIDTAG_VREF HF_RX_TEST0 HF_RX_TEST1
1 IN OUT 3 27.12Mhz interference which might affect HF_RX_TEST1 C9
B4 C10 HF_RX_TEST2
2 4
cellular certification. +3.3V_ALW_SC +3.3V_ALW +1.2V_ALW_AVDD HF_RFIDTAG_DVDD1P2 HF_RX_TEST2
E9 HF_RX_TEST3
GND GND HF_RX_TEST3

4.7K_0402_5%~D

5.1M_0402_5%~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

10U_0603_6.3V6M~D
1 1

2
27.12MHZ_12PF_1N227120CC0B~D +2.5V_ALW_AVDD C6 D7 +RFID_AVDD1P2
HF_RFIDTAG_AVDD2P5_C6 HF_TX_AVDD1P2

R629

R630
C492 C493 PJP52 2 2 1 2 2 1 1 E6 F8
HF_RFIDTAG_AVDD2P5_E6 HF_RX_AVDD1P2

C490

C491
12P_0402_50V8J~D 15P_0402_50V8J~D 1 2 D10
2 2 HF_RX_ADC_AVDD1P2

C494

C495

C488

C496

C489
PAD-OPEN1x1m F9 +RFID_AVDD2P5

1
1 1 2 1 1 2 2 HF_RX_AVDD2P5
D6 HF_RFIDTAG_AVSS_D6 HF_TX_AVDD2P5 A7
B5
Smart Card +3.3V_ALW_SC
SBOOT
POR_EXTR
+5V_ALW_SC +5V_ALW
A4
HF_RFIDTAG_AVSS_B5

HF_RFIDTAG_DVSS
HF_TX_AVDD3P3_D8
HF_TX_AVDD3P3_B7
D8
B7
+RFID_AVDD3P3

+3.3V_ALW_SC
3.3M_0402_5%~D
2 PJP55
1 2 PORADJ 1 2 HF_TX_AVSS_C7 C7
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_10V6M~D

2 PORADJ R634
1 @ R631 4.7K_0402_5%~D 1 1 1 C8
R632 4.7K_0402_5%~D +5V_ALW_SC HF_TX_AVSS_C8
1 2 CLKDIV2 PAD-OPEN1x1m
HF_TX_AVSS_E7 E7

1
C497

C498

C499

1 2 CLKDIV1 R633 4.7K_0402_5%~D


R635 4.7K_0402_5%~D R636 A9
1

2 2 2 HF_RX_AVSS_A9
0.1U_0402_16V4Z~D

10U_0805_10V6M~D

15K_0402_1%~D B11
C502 HF_RX_AVSS_B11
2 1
U34 0.1U_0402_16V4Z~D E8

2
HF_RX_ADC_AVSS1
C500

C501

1 RFREADER_RXP 1 2 RFREADER_RXP_C D9
B PORADJ VDD(intf) L39 HF_RX_ADC_AVSS2 B
18 PORadj VDD 17
CLKDIV1 1 2 150NH_0805CS-151EGTS_2%~D
6 CLKDIV1 +3.3V_ALW_USH 3
CLKDIV2 7 16 1 RFREADER_TXP1 1 2 BCM5882KFBG_FBGA196~D
SCC_CMDVCC_N_R CLKDIV2 VDDP
2

390P_0603_50V8G~D

390P_0603_50V8G~D
BCM5882_SCRST 3 15 +SC_VCC 1 1
RSTIN VCC

C503

C504
2 1SCC_CMDVCC_N 5 CMDVCCN
@ D25 DA204U_SOT323-3~D +3.3V_ALW_USH 3
BCM5882_GPIO25 2 14 R638 1 2 0_0402_5%~D SC_RST 1
@ R637 BCM5882_GPIO26 EN_5V/3VN RST R639 22_0402_5%~D SC_CLK
4 13 1 2 3 2
0_0402_5%~D
AUX1UC
AUX2UC
21
EN_1.8VN

AUX1UC
CLK
I/O
AUX1
9
10
R640
R641
R642
1
1
2
2
100_0402_5%~D
0_0402_5%~D
0_0402_5%~D
SC_IO
SC_C4
SC_C8
+3.3V_ALW_USH
2
1
@ D26
DA204U_SOT323-3~D
2 2
RFID
22 11 1 2
@

PAD~D T154 AUX2UC AUX2


BCM5882_IO 20 8 R643 1 2 0_0402_5%~D SC_DET @ D27 DA204U_SOT323-3~D C505
BCM5882_SCDET I/OUC PRESN 0.1U_0402_16V4Z~D JCS1 CONN@
19 OFFN RFREADER_RXN 1 2 RFREADER_RXN_C 1
BCM5882_SCCLK RFREADER_TXN1_PI 1
23 XTAL1 XTAL2 24 2 2
+SC_VCC
10P_0402_50V8J~D

10P_0402_50V8J~D

2 2 3 3

1
25 GPAD GND 12 Place C507,C575 close to JSC1 4 4
.47U_0402_6.3V6-K~D

C506

C507

R644 RFREADER_TXP1_PI 5 7
15K_0402_1%~D 5 G1
TDA8034HN_HVQFN24_4X4~D 2 18 CONTACTLESS_DET# 6 6 G2 8
1 1
C508

TYCO_2041084-6~D

2
SC_VCC should be 3X wide as +3.3V_ALW L40
1 CONN@ 150NH_0805CS-151EGTS_2%~D
+SC_VCC regular SC trace width to carry +3.3V_ALW_USH JBCM1 RFREADER_TXN1 1 2
~60mA max. current per ISO spec 1 connector list: 2041084-6
1
0.1U_0402_16V4Z~D

390P_0603_50V8G~D

390P_0603_50V8G~D
C1031 and C646 should be p UART_RX/GPIO0 2 1 1
2
10U_0805_10V4Z~D

0.22U_0402_10V6K~D

C511

C512
UART_TX/GPIO1 3 5 3
laced very close to SC cage pin Place C508 close 4
3 G1
6
+3.3V_ALW_USH
1
1 2 1 4 G2
@ C509

to U33 pin15 2
2 2 Hardware enable for USH TPM:Populate R841,
C510

C513

MOLEX_53398-0471~D
D28 @ No Stuff R483.
2 1 JSC1 CONN@ 2 DA204U_SOT323-3~D
A
Hardware disable for USH TPM:No Stuff A
1 +3.3V_ALW_USH
SC_RST 2
1 @ U35 U36 R841, Populate R483
SC_CLK 2 SPI_CS SPI_TXD SPI_RXD
3 3 1 /CS VCC 8 1 D Q 8
SC_C4 4 SPI_CLK 2 7 +3.3V_ALW_USH +2.5V_ALW_AVDD +1.2V_ALW_AVDD
4 SPI_RXD SPI_RST SPI_RST C VSS L41 BLM18BB100SN1D_2P~D L42 BLM18BB100SN1D_2P~D L43 BLM18BB100SN1D_2P~D
5 2 7 3 6
6
5
6
DO /HOLD SPI_CS 4
RESET#
S#
VCC
W# 5 BCM5882_GPIO15 2 1 +RFID_AVDD3P3 2 1 +RFID_AVDD2P5 2 1 +RFID_AVDD1P2 DELL CONFIDENTIAL/PROPRIETARY

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
SC_IO 7 BCM5882_GPIO15 3 6 SPI_CLK
7 /WP CLK
3.3U_0603_10V6K~D

1U_0603_10V6K~D

0.1U_0402_16V4Z~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D

1U_0603_10V6K~D
SC_C8
SC_DET
8
9
8
4 5 SPI_TXD
M45PE16-VMW6TG_SO8W8~D
1 2 1 2 2 1 1 1 1
Compal Electronics, Inc.
9 GND DIO Title
1 2 10 10
C516

C518

C519
C515

C517

C520

C521

C514

C522
BCM5882_GPIO15 1 2
R646 11 GND
W25X32VSSIG_SO8~D R647 4.7K_0402_5%~D USH BCM5882 (1/2)
1.5K_0402_5%~D 2 1 2 1 1 2 2 2 2 Size Document Number Rev
12 GND 1.0
FCI_10089709-010010LF~D LA-6592P
Date: Thursday, January 13, 2011 Sheet 33 of 75
5 4 3 2 1

WWW.AliSaler.Com
5 4 3 2 1

WWW.AliSaler.Com U33B

BCM5882
+1.2V_ALW_PLL H14 AVDD_1P2I_REF
+1.2V_ALW_AVDD A11 AVDD_1P2O_A11
A12 AVDD_1P2O_A12 AVSS_LDO12 C11
+2.5V_ALW_AVDD
H13 AVDD_2P5I AVSS_LDO25_B13 B13
E10 AVDD_2P5O_E10 AVSS_LDO25_C12 C12
+3.3V_ALW_USH E11 AVDD_2P5O_E11
B14
AVSS_PLL
A13
AVDD25_LDO12_A13

4.7U_0603_6.3V6K~D
B12 F13
D AVDD25_LDO12_B12 AVSS_REF D

1 D12
+1.2V_ALW_PLL PLL_AVSS
A14
AVDD25_PLL_A14

C523
E13
PLL_DVSS
+3.3V_ALW_USH 2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
1 1 1 D11
AVDD33_LDO25

C524

C525

C526
G13
POR_AVSS

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
+SC_PWR P13
2 2 2 OTP_PWR
2 2 2 2 2 2 2 1

C534
C527

C528

C529

C530

C531

C532

C533

1U_0402_6.3V6K~D

0.1U_0402_16V4Z~D
1 2 +1.2V_ALW_PLL D14 PLL_AVDD_1P2I
E14 PLL_AVDD_1P2O
1 1 1 1 1 1 1 2

C1161

C535
C14 PLL_DVDD_1P2I VSSC_F4 F4
VSSC_F5 F5
2 1 D13 F6
+VDDC_5882 VDDC_D13 VSSC_F6
F3 VDDC_F3 VSSC_F7 F7
J4 VDDC_J4 VSSC_F10 F10
J5 VDDC_J5 VSSC_F11 F11

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
J6 VDDC_J6 VSSC_F12 F12
2 2 2 2 2 2 2 J7 VDDC_J7 VSSC_G5 G5
J8 VDDC_J8 VSSC_G6 G6

C536

C537

C538

C539

C540

C541

C542
J10 VDDC_J10 VSSC_G7 G7
+VDDC_5882 J11 G8
1 1 1 1 1 1 1 VDDC_J11 VSSC_G8
K7 VDDC_K7 VSSC_G9 G9
+3.3V_ALW_USH K8 G10
VDDC_K8 VSSC_G10
VSSC_G11 G11

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
E4 VDDO_33_E4 VSSC_G12 G12
2 2 2 2 J2 VDDO_33_J2 VSSC_H5 H5
K3 VDDO_33_K3 VSSC_H6 H6

C543

C544

C545

C546
L8 VDDO_33_L8 VSSC_H7 H7
C C
N10 VDDO_33_N10 VSSC_H8 H8
1 1 1 1 H9
VSSC_H9
G4 VDDO_33CORE_G4 VSSC_H10 H10
H3 VDDO_33CORE_H3 VSSC_H11 H11
H4 VDDO_33CORE_H4 VSSC_H12 H12
J3 VDDO_33CORE_J3 VSSC_J9 J9
VSSC_J12 J12
M13 K2
VDDO_33SC_M13 VSSC_K2

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D
N13 K6
VDDO_33SC_N13 VSSC_K6
2 2 1 K13
VSSC_K13
L6 K14
VDDO_LPC_L6 VSSC_K14

C547

C548

C549
M6 L5
VDDO_LPC_M6 VSSC_L5
M8
1 1 2 VSSC_M8
M14
VSSC_M14
K10 N9
VDDO_SC_K10 VSSC_N9
K12 N11
VDDO_SC_K12 VSSC_N11
L12 N12
VDDO_SC_L12 VSSC_N12
L13 P3
VDDO_SC_L13 VSSC_P3
P4
VSSC_P4
D5
VDDO_VAR_D5
E5
VDDO_VAR_E5
N5
VESD
LOW:Power Down Mode
High:Working Mode BCM5882KFBG_FBGA196~D
China TCM: NationZ & Jetway co-lay
+3.3V_RUN

4@ U37
B B
10
USH BCM5882 and China TCM Z8H172T Option
VDD_0
19
VDD_1 PART/PIN Ref Des TCM Enable TPM Enable ALL TPM/TCM Disable
0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D
24
VDD_2

4@ C551

4@ C552

4@ C553

4@ C550
2 2 2 1 TCM circuit All 4@ POP @ @
1 2 C_TPM_LPC_EN 28
33,41 SP_TPM_LPC_EN
4@ R650 1 2 0_0402_5%~D LPC_LAD0_R 26
LPCPD#
11
PU R583 @ POP @
14,33,41,42 LPC_LAD0
4@ R649 1 2 0_0402_5%~D LPC_LAD1_R 23
LAD0 GND_11
18 1 1 1 2 USH_LPCEN
14,33,41,42 LPC_LAD1
4@ R648 1 2 0_0402_5%~D LPC_LAD2_R 20
LAD1 GND_18
25
PD R615 POP @ @
14,33,41,42 LPC_LAD2 LPC_LAD3_R LAD2 GND_25
4@ R651 1 2 0_0402_5%~D 17 4
14,33,41,42 LPC_LAD3
4@ R652 0_0402_5%~D LAD3 GND_4 SIO 5028 ->SP_TPM_LPC_EN PU R772 @ @ @
PU RH268 @ POP POP
21 5 JETWAY_PIN5 PCH GPIO39 ->TPM_ID1
15 CLK_PCI_TPM_CHA
1 2 LPC_LFRAME#_R 22 LCLK NC_5
12
PD RH271 POP @ @
14,33,41,42 LPC_LFRAME# LFRAME# NC_12
4@ R653 1 2 0_0402_5%~D PCI_RST#_R 16 13 JETWAY_CLK14M
+3.3V_RUN
14,17,36,37,41,42 PCH_PLTRST#_EC
4@ R654 0_0402_5%~D 27
LRESET# NC_13 JETWAY_CLK14M 15 PU RH267 @ POP @
14,33,41,42 IRQ_SERIRQ
1 2 CLKRUN#_R 15
SERIRQ
1
PCH GPIO38 ->TPM_ID0
1 2
16,41,42 CLKRUN#
4@ R655 0_0402_5%~D 7
CLKRUN# NC_1
2
PD RH270 POP @ POP
@ R656 4.7K_0402_5%~D TCM_BA1 PP NC_2
3 6
TCM_BA0 BA_1 NC_6
9 8
BA_0 NC_8
14
+3.3V_RUN NC_P
1 JETWAY_PIN5

4@ C554 2
1

1U_0402_6.3V6K~D
@ R657 @ R658 SSX44-B-D-T1_TSSOP28~D 2 @C555
@C555
10K_0402_5%~D 10K_0402_5%~D 0.1U_0402_16V4Z~D
1
2

A A
TCM_BA0
TCM Vender POP
TCM_BA1 NationZ R659, R660, C550, C554
Jetway C555, RH315
DELL CONFIDENTIAL/PROPRIETARY
1

4@ R659
1K_0402_5%~D
4@ R660
1K_0402_5%~D Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
USH BCM5882 (2/2)
2

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,


NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 34 of 75
5 4 3 2 1
A B C D E

WWW.AliSaler.Com

1 1

need to apply CIS symbol.

+3.3V_RUN
L45

0.1U_0402_16V4Z~D

4.7U_0603_10V6K~D
@ L46 BLM18PG471SN1D_0603~D
1 2 1 2 1 1
+1.5V_RUN

4.7U_0603_10V6K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
BLM18BD601SN1D_0603~D

0.1U_0402_16V4Z~D

4.7U_0603_10V6K~D

C559

C560
L47 1 1 1
1 2 1 1 2 2

4.7U_0603_10V6K~D

0.1U_0402_16V4Z~D

C556

C557

C558
BLM18BD601SN1D_0603~D

C563

C564
1 1 2 2 2

C561

C562

0.1U_0402_16V4Z~D

4.7U_0603_10V6K~D
U38
2 2
1 1

C566
+3.3VDDH 16 10 +OZ_DVDD
2 2 3.3VDDH DVDD

C565
+VDDH_SD 9 8 +OZ_AVDD
+PE_VDDH VDDH AVDD
1 2 32 PE_VDDH
L44 BLM18BD601SN1D_0603~D 2 2 +3.3V_RUN_CARD
17 +SKT_VCC
SKT_VCC
MMI_VCC_OUT 15
15 CLK_PCIE_MMI 2 PE_REFCLKP

1
0.1U_0402_16V4Z~D

4.7U_0603_10V6K~D

10K_0402_5%~D
1 28 SD/MMCDAT1_R R663 1 2 33_0402_5%~D SD/MMCDAT1 1 1
15 CLK_PCIE_MMI# PE_REFCLKM SD_D1
26 SD/MMCDAT2_R R664 1 2 33_0402_5%~D SD/MMCDAT2
SD_D2

C570

C572

R826
29 SD/MMC/MSDAT0_R R665 1 2 33_0402_5%~D SD/MMC/MSDAT0
C569 0.1U_0402_10V7K~D PCIE_PRX_MMITX_P6_C MMI_D0 MSDAT1_R R666 33_0402_5%~D MSDAT1
1 2 6 PE_TXP MS_D1 27 1 2
+PE_VDDH 15 PCIE_PRX_MMITX_P6 C571 0.1U_0402_10V7K~D PCIE_PRX_MMITX_N6_C MSDAT2_R R667 33_0402_5%~D MSDAT2 2 2
1 2 7 25 1 2

2
15 PCIE_PRX_MMITX_N6 C567 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_P6_C PE_TXM MS_D2 SD/MMC/MSDAT3_R R668 33_0402_5%~D SD/MMC/MSDAT3
15 PCIE_PTX_MMIRX_P6 1 2 5 24 1 2
PE_RXP MMI_D3
0.1U_0402_16V4Z~D

0.01U_0402_16V7K~D

1 1 C568 1 2 0.1U_0402_10V7K~D PCIE_PTX_MMIRX_N6_C 4 23 SD/MMCDAT4_R R669 1 2 33_0402_5%~D SD/MMCDAT4


15 PCIE_PTX_MMIRX_N6 PE_RXM MMI_D4
@C573
@

@C574
@

1 2 3 22 SD/MMCDAT5_R R670 1 2 33_0402_5%~D SD/MMCDAT5


PE_REXT MMI_D5
C573

C574

2 R677 191_0402_1%~D SD/MMCDAT6_R R672 33_0402_5%~D SD/MMCDAT6 2


MMI_D6 21 1 2
33 20 SD/MMCDAT7_R R673 1 2 33_0402_5%~D SD/MMCDAT7
2 2 GPAD MMI_D7
13 11 MS_CD#
PE_RST# MS_CD# SD/MMC/MS_CMD_R R674 1
17 PLTRST_MMI# 19 2 33_0402_5%~D SD/MMC/MS_CMD
SD_CMD/MS_BS SD/MMC/MS_CLK_R SD/MMC/MS_CLK
MMI_CLK 18 1 2
14 12 SD/MMCCD# R676 33_0402_5%~D
MULTI-IO1 SD_CD# SDWP
31 30
15 MMICLK_REQ# MULTI-IO2 SD_WPI
OZ600FJ0LN_QFN32_5X5~D
place close to pin U38.32

Note: The trace need to route as


daisy-chain and the trace of SD signals
need to route as short as possible

JSD1
+3.3V_RUN_CARD 7
VDD
9 44
VCC VCC
SD/MMC/MSDAT0 22
SD/MMCDAT1 DAT0
23 27
SD/MMCDAT2 DAT1 CD
1 28
SD/MMC/MSDAT3 DAT2 R/-B
2 29
3 SD/MMCDAT4 CD/DAT3 -RE 3
3 30
SD/MMCDAT5 DAT4 -CE
5 31
SD/MMCDAT6 DAT5 CLE
19 32
SD/MMCDAT7 DAT6 ALE
21 33
DAT7 -WE
34
SD/MMC/MS_CMD -WP
EMI request SD/MMC/MS_CLK
4
18
CMD
CLK
24 36
SD/MMC/MS_CLK SD/MMCCD# COM(SW) D0
25 37
SDWP CD(SW) D1
45 38
WP(SW) D2
39
SD/MMC/MSDAT0 D3
14 40
DATA0 D4

2
MSDAT1 15 41
@RE678 MSDAT2 DATA1 D5
13 42
SD/MMC/MSDAT3 DATA2 D6
33_0402_5%~D 11 43
DATA3 D7
SD/MMC/MS_CLK 10

1
MS_CD# SCLK
12 26
SD/MMC/MS_CMD INS GND
1 16 35
@ CE757 BS GND
6 46
10P_0402_50V8J~D VSS GND1
8 47
2 VSS GND2
17 48
VSS GND3
20 49
VSS GND4

T-SOL_152-1300302601_NR
CONN@
Support SD/MMC/MS
4 4

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Card Reader OZ600FJ0
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 35 of 75
A B C D E
5 4 3 2 1

+3.3V_PCIE_WWAN

WWW.AliSaler.Com +3.3V_RUN 1
@ R693
2
0_0402_5%~D
PCIE_MCARD1_DET# 1 2
+3.3V_ALW_PCH

2.2K_0402_5%~D

2.2K_0402_5%~D
1 2 WLAN_RADIO_DIS#_R R692 100K_0402_5%~D
41 WLAN_RADIO_DIS#

1
@ R1159

@ R1160
USB_MCARD2_DET# 2 1
R694 100K_0402_5%~D D31
RB751S40T1_SOD523-2~D

+3.3V_PCIE_WWAN Mini WLAN/WIMAX H=4

2
2 1 WWAN_SMBCLK USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET# +3.3V_RUN
7,12,13,14,15,28 DDR_XDP_WAN_SMBCLK
@ R1157 0_0402_5%~D @ R698 0_0402_5%~D
PCIE_MCARD2_DET#_R 1 2 2 1 WWAN_SMBDAT +3.3V_WLAN +3.3V_WLAN
7,12,13,14,15,28 DDR_XDP_WAN_SMBDAT
R695 100K_0402_5%~D @ R1158 0_0402_5%~D CONN@
D JMINI2 +1.5V_RUN PCIE_MCARD1_DET# 1 2 D
29,37,41 PCIE_WAKE# PCIE_WAKE# 1 2 @ R699 100K_0402_5%~D
Mini WWAN/GPS/LTE/UWB H=5.2 43 COEX2_WLAN_ACTIVE
43 COEX1_BT_ACTIVE
COEX2_WLAN_ACTIVE
COEX1_BT_ACTIVE
1
@ R7001
2
2 0_0402_5%~D
3
5
1
3
5
2
4
6
4
6
USB_MCARD1_DET# 1
R701
2
100K_0402_5%~D
@ R702 0_0402_5%~D 7 8
+3.3V_PCIE_WWAN CONN@ +3.3V_PCIE_WWAN 15 MINI2CLK_REQ# 7 8
9 10 1 2
JMINI1 9 10
15 CLK_PCIE_MINI2# 11 12
11 12 MSDATA C595 4700P_0402_25V7K~D
1 2 15 CLK_PCIE_MINI2 13 14
1 2 13 14
3 4 15 16 HOST_DEBUG_TX 42
3 4 15 16
5 6 +1.5V_RUN 17 18
MINI1CLK_REQ# 5 6 42 HOST_DEBUG_RX 17 18 WLAN_RADIO_DIS#_R
7 8 +SIM_PWR 19 20
15 MINI1CLK_REQ# 7 8 UIM_DATA 42 MSCLK 19 20
9 9 10 10 21 21 22 22 2 1 PCH_PLTRST#_EC
CLK_PCIE_MINI1# 11 12 UIM_CLK 23 24 @R703
@ R703 0_0402_5%~D
15 CLK_PCIE_MINI1# CLK_PCIE_MINI1 11 12 UIM_RESET 15 PCIE_PRX_WLANTX_N2 23 24
13 13 14 14 25 25 26 26
15 CLK_PCIE_MINI1 UIM_VPP 15 PCIE_PRX_WLANTX_P2
15 15 16 16 27 27 28 28
17 18 C596 0.1U_0402_10V7K~D 29 30
17 18 29 30
19 19 20 20 WWAN_RADIO_DIS# 41 15 PCIE_PTX_WLANRX_N2 1 2 PCIE_PTX_WLANRX_N2_C 31 31 32 32
21 21 22 22 1 2 PCH_PLTRST#_EC 14,17,34,37,41,42 15 PCIE_PTX_WLANRX_P2 1 2 PCIE_PTX_WLANRX_P2_C 33 33 34 34
23 24 @R704
@ R704 0_0402_5%~D C598 0.1U_0402_10V7K~D 35 36 USBP4-
15 PCIE_PRX_WANTX_N1 23 24 PCIE_MCARD1_DET# 35 36 USBP4+ USBP4- 17
25 25 26 26 37 37 38 38 USBP4+ 17
15 PCIE_PRX_WANTX_P1 18 PCIE_MCARD1_DET# USB_MCARD1_DET#
27 27 28 28 39 39 40 40 USB_MCARD1_DET# 14,18
C597 0.1U_0402_10V7K~D 29 30 WWAN_SMBCLK 41 42 WIMAX_LED#
29 30 41 42
15 PCIE_PTX_WANRX_N1 1 2 PCIE_PTX_WANRX_N1_C 31 32 WWAN_SMBDAT COEX2_WLAN_ACTIVE 43 44 WLAN_LED#
31 32 43 44
15 PCIE_PTX_WANRX_P1 1 2 PCIE_PTX_WANRX_P1_C 33 33 34 34 15 PCH_CL_CLK1 45 45 46 46
C599 0.1U_0402_10V7K~D 35 36 USBP5- 1 47 48 1 2 MSDATA
35 36 USBP5- 17 15 PCH_CL_DATA1 47 48 MSDATA 42
1
17 PCIE_MCARD2_DET# @ R725 2 PCIE_MCARD2_DET#_R 37 37 38 38 USBP5+
USBP5+ 17 15 PCH_CL_RST1# 1 2 49 49 50 50 @ R706 0_0402_5%~D
0_0402_5%~D 39 40 USB_MCARD2_DET# @ C600 @ R707 0_0402_5%~D 51 52
39 40 LED_WWAN_OUT# USB_MCARD2_DET# 18 51 52 WIMAX_LED# STUDY FOR DEBUG
41 42 33P_0402_50V8J~D
41 42 2
43 43 44 44 53 GND1 GND2 54
45
47
45 46 46
48
check
+1.5V_RUN 47 48 TYCO_1775861-1~D
49 49 50 50
C C
51 51 52 52
+3.3V_WLAN
53 GND1 GND2 54
33P_0402_50V8J~D

0.047U_0402_16V4Z~D

TYCO_1775861-1~D +1.5V_RUN +3.3V_WLAN


1 1

100K_0402_5%~D

100K_0402_5%~D
USB_MCARD2_DET# 1 2 PCIE_MCARD2_DET#

2
C593

C594

@ R697 0_0402_5%~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D

R718

R705
2 2 +3.3V_PCIE_WWAN
1 1 1 1 1 1 1 1

5
DMN66D0LDW-7_SOT363-6~D

@ C603

1
C601

C602

C604

C605

C606

C607

C608
WIMAX_LED# 4 3 WIRELESS_LED#
2 2 2 2 2 2 2 2
100K_0402_5%~D
2

+3.3V_PCIE_WWAN Q124B

2
R719

DMN66D0LDW-7_SOT363-6~D
0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

33P_0402_50V8J~D

22U_0805_6.3VAM~D

33P_0402_50V8J~D

330U_D2E_6.3VM_R25~D

330U_D2E_6.3VM_R25~D

WLAN_LED# 1 6
2
G

1 1
1

1 1 1 1 1 Q124A
@ C1176

+ + LED_WWAN_OUT# 3 1 WIRELESS_LED# 41,45


C610

C611

C612

C613

C614

C615

2 2 2 2 2 2 2 Q77
SSM3K7002FU_SC70-3~D 1/2 Minicard Flash Card H=4
+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH

JMINI3 USB_MCARD3_DET# 1 2 PCIE_MCARD3_DET#


Primary Power Aux Power PCIE_WAKE# 1 2 @R708
@ R708 0_0402_5%~D
COEX2_WLAN_ACTIVE 1 2
B
PWR Voltage 1 2 3
3 4
4
B
@ R709 0_0402_5%~D 5 6 +1.5V_RUN
Rail Tolerance Peak Normal Normal MINI3CLK_REQ# 7
5 6
8
15 MINI3CLK_REQ# 7 8
9
9 10
10 Confirm with DELL about UWB
CLK_PCIE_MINI3# 11 12
SIM Card Push-Push +3.3V +-9% 1000 750
15 CLK_PCIE_MINI3#
15 CLK_PCIE_MINI3
CLK_PCIE_MINI3 13
15
11
13
15
12
14
16
14
16
250 (Wake enable) 17
17 18
18
+3.3Vaux +-9% 330 250 5 (Not wake enable) 19
19 20
20 @ R710
21 22 2 1 PCH_PLTRST#_EC
+SIM_PWR 21 22
23 24
15 PCIE_PRX_WPANTX_N5 23 24
+1.5V +-5% 500 375 NA 15 PCIE_PRX_WPANTX_P5
25
25 26
26 0_0402_5%~D
JSIM1 27 28
0.1U_0402_10V7K~D C617 27 28
1 5 29 30
UIM_RESET VCC GND UIM_VPP PCIE_PTX_WPANRX_N5_C 29 30
2 6 15 PCIE_PTX_WPANRX_N5 2 1 31 32
UIM_CLK RST VPP UIM_DATA PCIE_PTX_WPANRX_P5_C 31 32
3 7 15 PCIE_PTX_WPANRX_P5 2 1 33 34
CLK I/O 0.1U_0402_10V7K~D C618 33 34 USBP6-
4 8 35 36 USBP6- 17
NC NC PCIE_MCARD3_DET# 35 36 USBP6+
9 37 38 USBP6+ 17
GND 18 PCIE_MCARD3_DET# 37 38 USB_MCARD3_DET#
GND
10
1 2
39
41
39 40
40
42
just reserve
1 +3.3V_RUN 41 42
MOLEX_475531001 R711 100K_0402_5%~D 43 44 2 1
43 44 +3.3V_ALW_PCH
C616 CONN@ 45 46 @ R712 100K_0402_5%~D
1U_0402_6.3V6K~D 45 46
47 48
2 47 48
49
49 50
50 WPAN Noise
51 52
51 52 USB_MCARD3_DET#
+1.5V_RUN +3.3V_PCIE_FLASH 53 54
GND1 GND2
1
@ U40
TYCO_1775861-1~D @ C627
0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.047U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

4.7U_0603_6.3V6K~D
4700P_0402_25V7K~D
UIM_VPP UIM_RESET 2
1 6 CONN@
1 1 1 1 1 1 1 1
@C621
@

A A
C619

C620

C621

C622

C623

C624

C625

C626
2 5 +SIM_PWR
2 2 2 2 2 2 2 2
UIM_CLK 3 4 UIM_DATA
DELL CONFIDENTIAL/PROPRIETARY
33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

1 1 1 1 Compal Electronics, Inc.


@ C628

@ C630

@ C629

@ C631

SRV05-4.TCT_SOT23-6~D
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
2 2 2 2 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 36 of 75
5 4 3 2 1
5 4 3 2 1

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Power Control for Mini card2
+15V_ALW +3.3V_ALW Q38
SI3456DDV-T1-GE3_TSOP6~D
+3.3V_WLAN Express Card PWR S/W

D
100K_0402_5%~D
6

S
1
100K_0402_5%~D
5 4

R714
2

R713
D D
1
+1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +3.3V_CARD +1.5V_CARD

1
2

3
R715

DMN66D0LDW-7_SOT363-6~D
20K_0402_5%~D

4700P_0402_25V7K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D

0.1U_0402_16V4Z~D

10U_0603_6.3V6M~D
1

2
Q39B
1 1 1 1 1 1 1 1 1

C632

C643
5

C635

C634

C633

C642

C640

C641

C637

C638
6
Q39A 2

4
DMN66D0LDW-7_SOT363-6~D 2 2 2 2 2 2 2 2 2

2 U41
41 AUX_EN_WOWL
17 AUXIN AUXOUT 15
1

2 3
1

3.3VIN 3.3VOUT
12 1.5VIN 1.5VOUT 11
R716
100K_0402_5%~D 20 8 CARD_RESET#
EXPRCRD_STBY_R# SHDN# PERST# EXPRCRD_CPPE#
11,41,44,55,63 RUN_ON 1 2 1 10
2

@ R717 0_0402_5%~D STBY# CPPE# CPUSB#


14,17,34,36,41,42 PCH_PLTRST#_EC 6 SYSRST# CPUSB# 9
19 OC#

+3.3V_RUN 4 NC
+3.3V_CARD 5 NC RCLKEN 18
+1.5V_CARD 13 NC
+1.5V_RUN 14 NC GND 7
16 21
Power Control for Mini card1 +3.3V_PCIE_WWAN
NC
TPS2231MRGPR-2_QFN20_4X4~D
PAD

C +15V_ALW +3.3V_ALW Q40 C


SI3456DDV-T1-GE3_TSOP6~D
100K_0402_5%~D

@ R720
@R720

D
6 0_0805_5%~D

S
1
100K_0402_5%~D

5 4 1 2 +3.3V_RUN Note: Add connection on pin4, pin5, pin 13


1

R722

2
and pin14 to support GMT 2nd source part
R721

1
G

R723
2

1K_0402_5%~D
2

DMN66D0LDW-7_SOT363-6~D
3

4700P_0402_25V7K~D

Express Card Conn.


2
1
Q41B

1
D
C644

SSM3K7002FU_SC70-3~D

MCARD_WWAN_PWREN# 5
Q73

2 MCARD_WWAN_PWREN#
6

Q41A 2 G +3.3V_SUS +1.5V_CARD


4

DMN66D0LDW-7_SOT363-6~D S
3

41 MCARD_WWAN_PWREN 2

2.2K_0402_5%~D

2.2K_0402_5%~D
1
1

1
1

R731

R732
R726 1 2 C645
100K_0402_5%~D @R724
@ R724 0_0402_5%~D 0.1U_0402_16V4Z~D
1 2 2
@R727
@ R727 0_0402_5%~D
2

2
L49 CONN@
1 2 JEXP1
17 USBP10- 1 2
1

B
Power Control for Mini card3 17 USBP10+ 4
4 3
3
USBP10_D-
USBP10_D+
CPUSB#
2
3
GND1
USB_D-
USB_D+ B
4
DLW21SN900SQ2L_0805_4P~D CPUSB#
5
RESERVED
6
CARD_SMBCLK RESERVED
42 CARD_SMBCLK 7
+15V_ALW +3.3V_ALW Q42 +3.3V_PCIE_FLASH CARD_SMBDAT SMB_CLK
42 CARD_SMBDAT 8
SI3456DDV-T1-GE3_TSOP6~D SMB_DAT
9
+1.5V
100K_0402_5%~D

10
+1.5V
D

6 11
S

29,36,41 PCIE_WAKE# WAKE#


1
100K_0402_5%~D

5 4 +3.3V_CARDAUX 12
+3.3VAUX
1

R729

2 CARD_RESET# 13
PERST#
R728

1 +3.3V_CARD 14
+3.3V
1

1 15
G

R730 +3.3V
16
2

20K_0402_5%~D C646 15 EXPCLK_REQ# EXPRCRD_CPPE# CLKREQ#


17
2

CPPE#
DMN66D0LDW-7_SOT363-6~D

0.1U_0402_16V4Z~D 18
15 CLK_PCIE_EXP# REFCLK-
3

2
4700P_0402_25V7K~D

1 15 CLK_PCIE_EXP 19
2

REFCLK+
1 20
GND
Q43B

C649 15 PCIE_PRX_EXPTX_N3 21
PER_N0
C650

5 0.1U_0402_16V4Z~D 15 PCIE_PRX_EXPTX_P3 22
2 C647 0.1U_0402_10V7K~D PER_P0
23
GND
6

Q43A 2 1 2 PCIE_PTX_EXPRX_N3_C 24
15 PCIE_PTX_EXPRX_N3
4

PET_N0
DMN66D0LDW-7_SOT363-6~D
15 PCIE_PTX_EXPRX_P3 1 2 PCIE_PTX_EXPRX_P3_C 25
PET_P0
C648 0.1U_0402_10V7K~D 26
GND
41 MCARD_MISC_PWREN 2
27
GND
1

28
1

GND
29
R733 GND
30
100K_0402_5%~D GND
T-SOL_5421005002000-9_NR
2

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PCIE-SATA SW / PCIE PWR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Tuesday, January 18, 2011 Sheet 37 of 75
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D D

+USB_SIDE_PWR

0.1U_0402_16V4Z~D
1

C656
2 USB conn update ok-6/5
JUSB2
C C
1 +5V
USBP0_D- 2
USBP0_D+ A-
3 A+ GND 6
4 GNDGND 5

SUYIN_020133GR004M53UZL

2
CONN@

D72

PESD5V0U2BT_SOT23-3~D
L51 L52
4 3 USBP0_D+ 4 3 USBP1_D+
17 USBP0+ 17 USBP1+

1
4 3 4 3

1 2 USBP0_D- 1 2 USBP1_D-
17 USBP0- 1 2 17 USBP1- 1 2
DLW21SN900SQ2L_0805_4P~D DLW21SN900SQ2L_0805_4P~D
1 2 1 2
@ R736 0_0402_5%~D @R737
@ R737 0_0402_5%~D

1 2 1 2
@ R738 0_0402_5%~D @R739
@ R739 0_0402_5%~D +USB_SIDE_PWR

150U_B2_6.3V-M~D

0.1U_0402_16V4Z~D
1 1

C657

C658
B + B

2
2 USB conn update ok-6/5
JUSB3
1
USBP1_D- +5V
2
USBP1_D+ A-
3 6
A+ GND
4 5
GNDGND

SUYIN_020133GR004M53UZL

2
CONN@

D73

PESD5V0U2BT_SOT23-3~D

1
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB x2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Tuesday, January 18, 2011 Sheet 38 of 75
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+3.3V_RUN

0.01U_0402_16V7K~D

0.1U_0402_16V4Z~D
1 1

2
@ R1586
C662

0_0402_5%~D

0_0402_5%~D
@ R1587

0_0402_5%~D
@ R742

0_0402_5%~D
@ R743
C661
2 2
+3.3V_RUN

1
1 2
D R741 0_0402_5%~D D

U44
7 6 +ESATA_DEW2
EN VCC
18 10
ESATA_PTX_DRX_P4_C 2 ESATA_PTX_DRX_P4 CAD VCC +ESATA_DEW1
14 ESATA_PTX_DRX_P4_C 1 16
C664 0.01U_0402_16V7K~D VCC
1 20
ESATA_PTX_DRX_N4_C 2 ESATA_PTX_DRX_N4 AINP VCC
14 ESATA_PTX_DRX_N4_C 1 2
AINM
C663 0.01U_0402_16V7K~D 9
ESATA_PRX_DTX_N4_C 2 ESATA_PRX_DTX_N4 PA
14 ESATA_PRX_DTX_N4_C 1 4
BOUTM PB
8
C666 0.01U_0402_16V7K~D 5
ESATA_PRX_DTX_P4_C 2 ESATA_PRX_DTX_P4 BOUTP ESATA_PTX_DRX_P4_RP
1 AOUTP 15
14 ESATA_PRX_DTX_P4_C C665 0.01U_0402_16V7K~D ESATA_PTX_DRX_N4_RP
3 GND AOUTM 14

1
10K_0402_5%~D

10K_0402_5%~D

0_0402_5%~D

0_0402_5%~D
13 GND

1
@ R1588

@ R1589

@ R745
+3.3V_RUN +ESATA_EQ1 17 11 ESATA_PRX_DTX_P4_RP
GND BINP

@R746
@
+ESATA_EQ2 19 12 ESATA_PRX_DTX_N4_RP
GND BINM

R746
21 EP

10K_0402_5%~D

10K_0402_5%~D

2
1

1
@ R1582

@ R1583
MAX4951BECTP+TGH7_TQFN20_4X4~D

2
2

2
1

@ R1585
@R1584
Note: +ESATA_DEW1, +ESATA_DEW2, +ESATA_EQ1, +ESATA_EQ2 need to

0_0402_5%~D

0_0402_5%~D
route 10 mils and R1584~R1587 need to change to 10k and no
C stuff R1584, R1585 to support TI SN75LVCP601 C

2
+USB_SIDE_PWR +SATA_SIDE_PWR

+SATA_SIDE_PWR

150U_B2_6.3V-M~D

0.1U_0402_16V4Z~D
+5V_ALW_FUSE
1
+5V_ALW U45 1
PJP7

C667

C668
1 10 +
GND FAULT1# USB_OC1# 17,31
2 1 +5V_ALW_FUSE 2 9
2 1 IN OUT1
10U_0805_10V4Z~D

3 8
IN OUT2 2 2
0.1U_0402_16V4Z~D

31,41 ESATA_USB_PWR_EN# 4 7
JUMP_43X79 EN1# ILIM
1 1 41 USB_SIDE_EN# 5 6 USB_OC0# 17
EN2# FAULT#2
11
T-PAD

1
C669

C670

TPS2560DRCR-PG1.1_SON10_3X3~D R747 JESA1


2 2 24.9K_0402_1%~D 1
USBP2_D- VBUS
2
USBP2_D+ D- USB
3

2
D+
4
GND

ESATA_PTX_DRX_P4_RP 1 2 SATA_PTX_DRX_P4 5
C671 0.01U_0402_16V7K~D GND
6
B ESATA_PTX_DRX_N4_RP A+ B
L90 1 2 SATA_PTX_DRX_N4 7
A-
ESATA
1 2 USBP2_D+ C672 0.01U_0402_16V7K~D 8
17 USBP2+ 1 2 ESATA_PRX_DTX_N4_RP GND
1 2 SATA_PRX_DTX_N4 9
B-
C673 0.01U_0402_16V7K~D 10
USBP2_D- ESATA_PRX_DTX_P4_RP B+
17 USBP2- 4 3 1 2 SATA_PRX_DTX_P4 11
4 3 C674 0.01U_0402_16V7K~D GND
DLW21SN900SQ2L_0805_4P~D
1 2 12
GND
3

@ R1150 0_0402_5%~D 13
GND
14
GND
1 2 15
@ R1151 0_0402_5%~D D74 GND

PESD5V0U2BT_SOT23-3~D TYCO_2129156-3
CONN@
1

Place D74 close to JESATA1

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB/ESATA/IO/MDC
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Tuesday, January 18, 2011 Sheet 39 of 75
5 4 3 2 1
2 1

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JDOCK1

DOCK_DET_1 1 2 DOCK_AC_OFF
1 2 DOCK_AC_OFF 41,62
3 3 4 4
32 DOCK_LOM_SPD10LED_GRN# DPD_CA_DET DPC_CA_DET DOCK_LOM_SPD100LED_ORG# 32
27 DPD_CA_DET 5 5 6 6 DPC_CA_DET 27
7 7 8 8
C690 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_P0_C 9 10 DPC_GPU_LANE_P0_C C691 2 1 0.1U_0402_10V7K~D
47 DPD_GPU_LANE_P0 DPD_GPU_LANE_N0_C 9 10 DPC_GPU_LANE_N0_C DPC_GPU_LANE_P0 47
C679 2 1 0.1U_0402_10V7K~D 11 12 C680 2 1 0.1U_0402_10V7K~D
47 DPD_GPU_LANE_N0 11 12 DPC_GPU_LANE_N0 47
13 14
C681 DPD_GPU_LANE_P1_C 13 14 DPC_GPU_LANE_P1_C
47 DPD_GPU_LANE_P1 2 1 0.1U_0402_10V7K~D 15
15 16
16 C682 2 1 0.1U_0402_10V7K~D DPC_GPU_LANE_P1 47
C683 2 1 0.1U_0402_10V7K~D DPD_GPU_LANE_N1_C 17 18 DPC_GPU_LANE_N1_C C684 2 1 0.1U_0402_10V7K~D
47 DPD_GPU_LANE_N1 17 18 DPC_GPU_LANE_N1 47
19 20
C692 DPD_GPU_LANE_P2_C 19 20 DPC_GPU_LANE_P2_C
47 DPD_GPU_LANE_P2 2 1 0.1U_0402_10V7K~D 21 22 C693 2 1 0.1U_0402_10V7K~D
C685 DPD_GPU_LANE_N2_C 21 22 DPC_GPU_LANE_N2_C DPC_GPU_LANE_P2 47
47 DPD_GPU_LANE_N2 2 1 0.1U_0402_10V7K~D 23 24 C686 2 1 0.1U_0402_10V7K~D
23 24 DPC_GPU_LANE_N2 47
25 26
C687 DPD_GPU_LANE_P3_C 25 26 DPC_GPU_LANE_P3_C
47 DPD_GPU_LANE_P3 2 1 0.1U_0402_10V7K~D 27 28 C688 2 1 0.1U_0402_10V7K~D
C689 DPD_GPU_LANE_N3_C 27 28 DPC_GPU_LANE_N3_C DPC_GPU_LANE_P3 47
47 DPD_GPU_LANE_N3 2 1 0.1U_0402_10V7K~D 29
29 30
30 C694 2 1 0.1U_0402_10V7K~D
DPC_GPU_LANE_N3 47
31 32
31 32
27 DPD_DOCK_AUX 33 34 DPC_DOCK_AUX 27
33 34
27 DPD_DOCK_AUX# 35 36 DPC_DOCK_AUX# 27
35 36
37 37 38 38
DPD_GPU_HPD 39 40 DPC_GPU_HPD
DPD_GPU_HPD 46 DPD_GPU_HPD 39 40 DPC_GPU_HPD 46
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# 62
1 43 43 44 44 1
BLUE_DOCK 45 46
B 25 BLUE_DOCK 45 46 DAT_DDC2_DOCK 25 B
@ C695 47 48 @ C696
47 48 CLK_DDC2_DOCK 25
2

0.033U_0402_16V7K~D 49 50 0.033U_0402_16V7K~D
2 49 50 2
R757 Close to DOCK 51 51 52 52
100K_0402_1%~D RED_DOCK 53 54 SATA_PRX_DKTX_P5 2 1
Its for Enhance ESD on dock issue. 25 RED_DOCK 53 54 SATA_PRX_DKTX_N5 SATA_PRX_DKTX_P5_C 14
55 55 56 56 C697 2 1 0.01U_0402_16V7K~D SATA_PRX_DKTX_N5_C 14 Close to DOCK
57 58 C698 0.01U_0402_16V7K~D
Its for Enhance ESD on dock issue.
1

GREEN_DOCK 57 58 SATA_PTX_DKRX_P5
25 GREEN_DOCK 59 59 60 60 1 2
SATA_PTX_DKRX_N5 C699 1 SATA_PTX_DKRX_P5_C 14
61 61 62 62 2 0.01U_0402_16V7K~D
C700 0.01U_0402_16V7K~D SATA_PTX_DKRX_N5_C 14
63 63 64 64
25 HSYNC_DOCK 65 65 66 66 USBP8+ 17
25 VSYNC_DOCK 67 67 68 68 USBP8- 17
69 70 DPC_GPU_HPD
69 70
42 CLK_MSE 71 71 72 72 USBP9+ 17
42 DAT_MSE 73 73 74 74 USBP9- 17
75 75 76 76

2
30 DAI_BCLK# 77 77 78 78 CLK_KBD 42
79 80 R758
30 DAI_LRCK# 79 80 DAT_KBD 42
81 81 82 82 100K_0402_1%~D
30 DAI_DI 83 83 84 84
30 DAI_DO# 85 86

1
85 86
87 87 88 88
30 DAI_12MHZ# 89 89 90 90
91 91 92 92
93 94
93 94
95 96
95 96
41 D_LAD0 97 98
97 98 BREATH_LED# 42,45
41 D_LAD1 99 100
99 100 DOCK_LOM_ACTLED_YEL# 32
101 102
101 102
41 D_LAD2 103 104
103 104 DOCK_LOM_TRD0+ 32
41 D_LAD3 105 106
105 106 DOCK_LOM_TRD0- 32
107 108
107 108 +3.3V_ALW
41 D_LFRAME# 109 110
109 110 DOCK_LOM_TRD1+ 32 +LOM_VCT
41 D_CLKRUN# 111 112
111 112 DOCK_LOM_TRD1- 32
113 114
113 114 DOCK_DET#
41 D_SERIRQ 115 116 1 1 2
115 116 R755 100K_0402_5%~D
41 D_DLDRQ1# 117 118 +LOM_VCT
117 118 C701
119 120
119 120 1U_0402_6.3V6K~D
17 CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ 32
121 122 2
123 124 DOCK_LOM_TRD2- 32
123 124
125 126
125 126
42 DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ 32
127 128
42 DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- 32
129 130
131 132
131 132
42,52,62 DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ 60
133 134
52 DOCK_PSID 135 136 DOCK_DCIN_IS- 60
135 136
137 138
137 138 D32
42 DOCK_PWR_BTN# 139 140 DOCK_POR_RST# 42
139 140 RB751S40T1_SOD523-2~D
141 142
SLICE_BAT_PRES# 141 142 DOCK_DET_R#
41,52,62 SLICE_BAT_PRES# 143 144 1 2 DOCK_DET# 41
143 144
145 149 +DOCK_PWR_BAR
GND1 PWR2
+DOCK_PWR_BAR 146 150
PWR1 PWR2
147 151
PWR1 PWR2
3

2
SM24.TCT_SOT23-3~D

148 152
PWR1 GND2
0.1U_0603_50V4Z~D

@ D33

0.1U_0603_50V4Z~D
C703
1
C702

1 153 159
Shield_G Shield_G
154 160
Shield_G Shield_G
155 161
Shield_G Shield_G 2
156 162
1

2 Shield_G Shield_G
157 163
Shield_G Shield_G
158 164
Shield_G Shield_G
CLK_PCI_DOCK
JAE_WD2F144WB1

1
A A
R756
33_0402_5%~D

2
1
C704
6.8P_0402_50V8D~D
2

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DOCKING CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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LA-6592P
Date: Thursday, January 13, 2011 Sheet 40 of 75
2 1
5 4 3 2 1

+3.3V_ALW

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1 2 PCIE_WAKE#
R759 10K_0402_5%~D
1 2 DCIN_CBL_DET# +3.3V_ALW
R761 100K_0402_5%~D
1 2 CPU_DETECT#
R763 100K_0402_5%~D
1 2 SLICE_BAT_PRES# 1 1 1 1 1 1
R760 100K_0402_5%~D
C706 C707 C708 C709 C710 C705
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10U_0805_6.3V6M~D
2 2 2 2 2 2
D D

A17
B30
A43
A54
B5
U46 +3.3V_ALW
+3.3V_ALW2

VCC1
VCC1
VCC1
VCC1
VCC1
ACAV_IN_NB 42,60,62 1 2 C711
B52 B63 0.1U_0402_16V4Z~D
25 CRT_SWITCH GPIOA0 GPIOI1 SIO_SLP_A# 16,56

5
1 2 USB_SIDE_EN# A49 A60 0.75V_DDR_VTT_ON
31 MDC_RST_DIS# GPIOA1 GPIOI2/TACH0 0.75V_DDR_VTT_ON 55
R768 10K_0402_5%~D B53 A61 1

P
37 MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# 16 B
1 2 ESATA_USB_PWR_EN# DCIN_CBL_DET# A50 B65
O 4D34 2
52 DCIN_CBL_DET# SIO_SLP_S3# 16 1
R769 10K_0402_5%~D LID_CL_SIO# GPIOA3 GPIOI4 DOCK_AC_OFF 40,62
B54 A62 IMVP_PGOOD 58 2
GPIOA4 GPIOI5 A

G
46 GPU_DEEP_CLKDWN A51 B66 1 2 RB751S40T1_SOD523-2~D
GPIOA5 GPIOI6 IMVP_VR_ON 58

1
PCIE_WAKE# B55 A63 @ R765 0_0402_5%~D U47
29,36,37 PCIE_WAKE#

3
GPIOA6 GPIOI7 DOCK_AC_OFF_EC TC7SH08FU_SSOP5~D R770
46 GPU_CLKDWN A52 GPIOA7
B67 33K_0402_5%~D
+3.3V_RUN USB_SIDE_EN# GPIOJ0 AUX_EN_WOWL 37
39 USB_SIDE_EN# A33 GPIOB0 GPIOJ1/TACH1 A64 WLAN_LAN_DISB# 32
30 EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN# 16,32

2
GPIOB1 GPIOJ2/TACH2 DOCK_AC_OFF_EC 62
33 USH_PWR_STATE# A34 GPOC2 GPIOJ3 B6 SIO_SLP_SUS# 16
62 EN_DOCK_PWR_BAR B37 GPOC3 GPIOJ4 A6
PANEL_BKEN_EC GPIO_PSID_SELECT 52
24 PANEL_BKEN_EC A35 GPOC4 GPIOJ5 B7
WIRELESS_ON#/OFF MODC_EN 29
1 2 16,24 ENVDD_PCH B38 A7 DOCK_HP_DET 30
R766 100K_0402_5%~D LCD_TST GPOC5 GPIOJ6
24 LCD_TST A36 GPOC6/TACH4 GPIOJ7 B8 DOCK_MIC_DET 30
1 2 SP_TPM_LPC_EN PSID_DISABLE# A37
@ R772 10K_0402_5%~D 52 PSID_DISABLE# PBAT_PRES# GPIOC7 ME_FWP
52,62 PBAT_PRES# B40 GPIOD0 GPIOK0 A8 ME_FWP 14
1 2 LCD_TST DOCKED A38 B9 MASK_SATA_LED# 45
32 DOCKED GPIOC1 GPIOK1/TACH3
R767 100K_0402_5%~D DOCK_DET# B41 B10
40 DOCK_DET# GPIOC0 GPIOK2 1.8V_RUN_PWRGD 55
A39 GPIOB7 GPIOK3 A10 LED_SATA_DIAG_OUT# 45
30 AUD_NB_MUTE# MCARD_WWAN_PWREN TEMP_ALERT#_R
B42 GPIOB6 GPIOK4 B11 1 2 TEMP_ALERT# 14,18
SYS_LED_MASK# 37 MCARD_WWAN_PWREN LCD_VCC_TEST_EN @ R1591 0_0402_5%~D
1 2 24 LCD_VCC_TEST_EN A40 GPIOB5 GPIOK5 A11
R775 10K_0402_5%~D CCD_OFF B43 B12 RUN_ON
24 CCD_OFF GPIOB4 GPIOK6 RUN_ON 11,37,44,55,63
1 2 DGPU_PWR_EN AUD_HP_NB_SENSE A41 A12
30,31 AUD_HP_NB_SENSE ESATA_USB_PWR_EN# GPIOB3 GPIOK7 SPI_WP#_SEL 14
R1152 100K_0402_5%~D B44
C GFX_MEM_VTT_ON 31,39 ESATA_USB_PWR_EN# GPIOB2 5048_GPIOL0 C
1 2 GPIOL0/PWM7 B60
R1153 100K_0402_5%~D A57 5048_GPIOL1
DP_HDMI_HPD GPIOL1/PWM8 5048_GPIOL2
1 2 62 MODULE_ON B32 B64
R1154 100K_0402_5%~D SLICE_BAT_ON GPIOD1 GPIOL2/PWM0 5048_GPIOL3
62 SLICE_BAT_ON A31 GPIOD2 GPIOL3/PWM1 B68
SLICE_BAT_PRES# B33 A9 5048_GPIOL4
40,52,62 SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 5048_GPIOL5
B15 B1 +3.3V_RUN
52,62 MODULE_BATT_PRES# GPIOD4 GPIOL5/PWM2 5048_GPIOL6
62 CHARGE_MODULE_BATT A15 GPIOD5 GPIOL6 A18
B16 A44 5048_GPIOL7 D_CLKRUN# 2 1
62 CHARGE_PBATT GPIOD6 GPIOL7/PWM5
A16 R777 100K_0402_5%~D
62 DEFAULT_OVRDE GPIOD7 5048_GPI0M1 D_SERIRQ
B34 2 1
GPIOM1 5048_GPI0M3 R780 100K_0402_5%~D
B39
GPIOM3/PWM4 5048_GPI0M4 D_DLDRQ1#
A1 B51 2 1
GPIOE0/RXD GPIOM4/PWM6 R782 100K_0402_5%~D
B2
GFX_MEM_VTT_ON GPIOE1/TXD
49 GFX_MEM_VTT_ON A2
GPIOE2/RTS#
B3 A27 LPC_LAD0 14,33,34,42
CPU_DETECT# GPIOE3/DSR# LAD0
7 CPU_DETECT# A3 A26 LPC_LAD1 14,33,34,42
+3.3V_ALW DGPU_PWR_EN GPIOE4/CTS# LAD1 RUN_ON
63 DGPU_PWR_EN B45 B26 LPC_LAD2 14,33,34,42 2 1
GPIOE5/DTR# LAD2 R786 100K_0402_5%~D
29 MOD_SATA_PCIE#_DET A42 B25 LPC_LAD3 14,33,34,42
GPIOE6/RI# LAD3
1 2 DYN_TUR_PWR_ALRT# 46 DP_HDMI_HPD
DP_HDMI_HPD B4
GPIOE7/DCD# LFRAME#
A21 LPC_LFRAME# 14,33,34,42
R796 10K_0402_5%~D B22 CPU_VTT_ON 2 1
LRESET# CLK_PCI_5028 PCH_PLTRST#_EC 14,17,34,36,37,42
A28 R789 100K_0402_5%~D
PCICLK CLK_PCI_5028 17
29 ZODD_WAKE# A59 B20 CLKRUN# 16,34,42
GPIOF0 CLKRUN# 0.75V_DDR_VTT_ON 2
33 BCM5882_ALERT# B62 A23 LPC_LDRQ0# 14 1
SUSACK#_EC GPIOF1 LDRQ0# R790 100K_0402_5%~D
16 SUSACK# 1 2 A58 A22 LPC_LDRQ1# 14
@ R1132 0_0402_5%~D GPIOF2 LDRQ1# SLICE_BAT_ON
25 EDID_SELECT# B61 B21 IRQ_SERIRQ 14,33,34,42 1 2
+3.3V_ALW GPIOF3/TACH8 SER_IRQ CLK_SIO_14M R791 100K_0402_5%~D
18,63 DGPU_PWROK A56 A32 CLK_SIO_14M 15
VGA_ID GPIOF4/TACH7 14.318MHZ/GPIOM0
B59 B35 EC_32KHZ_ECE5048 42
GPIOF5 CLK32/GPIOM2 5048_GPIOL0
15,49 3.3V_RUN_GFX_ON A55 2 1
SLP_ME_CSW_DEV# GPIOF6 5048_GPIOL1 @ R1567 1 10K_0402_5%~D
14,18 SLP_ME_CSW_DEV# B58 2
GPIOF7 5048_GPIOL2 R1568 1 10K_0402_5%~D
B29 2
VGA_ID DLAD0 D_LAD0 40 5048_GPIOL3 R1569 1 0_0402_5%~D
1 2 DLAD1
B28 2
@ R800 100K_0402_5%~D D_LAD1 40 5048_GPIOL4 @ R1570 1 0_0402_5%~D
32 LAN_DISABLE#_R B47 A25 2
B GPIOG0/TACH5 DLAD2 D_LAD2 40 5048_GPIOL5 R1571 1 0_0402_5%~D B
62 CHARGE_EN A45 A24 2
SYS_LED_MASK# GPIOG1 DLAD3 D_LAD3 40 5048_GPIOL6 @ R1572 1 0_0402_5%~D
45 SYS_LED_MASK# B48 B23 D_LFRAME# 40 2
DYN_TUR_PWR_ALRT# GPIOG2 DLFRAME# D_CLKRUN# 5048_GPIOL7 R1573 1 0_0402_5%~D
60 DYN_TUR_PWR_ALRT# A46 A19 D_CLKRUN# 40 2
GPIOG3 DCLKRUN# D_DLDRQ1# R1574 0_0402_5%~D
18 SIO_EXT_WAKE# 1 2 B49 B24 D_DLDRQ1# 40
@ R797 0_0402_5%~D GPIOG4 DLDRQ1# D_SERIRQ 5048_GPI0M1
36,45 WIRELESS_LED# A47 A20 D_SERIRQ 40 1 2
VGA_ID PCH_PCIE_WAKE# GPIOG5 DSER_IRQ 5048_GPI0M3@ R1575 1
1 2 B50
GPIOG6 2 0_0402_5%~D
R803 100K_0402_5%~D 16 PCH_PCIE_WAKE# 5048_GPI0M4 R1576 1
36 WLAN_RADIO_DIS# A48 2 0_0402_5%~D
GPIOG7/TACH6 R1577 0_0402_5%~D
A29 BC_INT#_ECE5028 42
BC_INT#
B31 BC_DAT_ECE5028 42
WIRELESS_ON#/OFF BC_DAT
31 WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5028 42
GPIOH0 BC_CLK
43 BT_RADIO_DIS# A13
GPIOH1 CLK_SIO_14M CLK_PCI_5028
VGA_ID 36 WWAN_RADIO_DIS# A53
SYSOPT1/GPIOH2
7,16 SYS_PWROK B57 A4 RUNPWROK 7,42
SYSOPT0/GPIOH3 PWRGD
Discrete 0 23,25 DGPU_SELECT# B14
GPIOH4

1
A14 B56 SP_TPM_LPC_EN
46 DGPU_DI_INT# GPIOH5 OUT65 SP_TPM_LPC_EN 33,34
UMA 1 CPU_VTT_ON B17 @ R794 @ R795
57,61 CPU_VTT_ON GPIOH6
1 2 B18 10_0402_5%~D 10_0402_5%~D
16 PCH_DPWROK GPIOH7
@R802
@ R802 0_0402_5%~D B19 2 1
TEST_PIN R804 1K_0402_5%~D

2
B46 +CAP_LDO
CAP_LDO
1 1 1
B27
VSS
C1 C714 +CAP_LDO trace width 20mil. @ C712 @C713
@ C713
EP 4.7U_0603_6.3V6K~D 4.7P_0402_50V8C~D 4.7P_0402_50V8C~D
+3.3V_ALW DB Version 0.4 2 2 2
ECE5028-LZY_DQFN132_11X11~D

ME_FWP PCH has internal 20K PD.


1

(suspend power rail) R805


ME_FWP 100K_0402_5%~D
2

A A
2

@ R793
1K_0402_5%~D LID_CL_SIO# 2 1 LID_CL# 31,45
R807 10_0402_5%~D
1
DELL CONFIDENTIAL/PROPRIETARY
1

C716
2
0.047U_0402_16V4Z~D
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5028
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 41 of 75
5 4 3 2 1
5 4 3 2 1

+3.3V_ALW +RTC_CELL

WWW.AliSaler.Com +3.3V_ALW C720


0.1U_0402_16V4Z~D +RTC_CELL R815 +3.3V_ALW

1
1 2 BC_DAT_ECE5028 1 2 0_0402_5%~D @C721
@ C721
R814 100K_0402_5%~D 1 2 +RTC_CELL_VBAT R810 1U_0402_6.3V6K~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D

10U_0805_6.3V6M~D
2 1 BC_DAT_EMC4022 1 100K_0402_5%~D 1 2

5
R816 100K_0402_5%~D U50 1 1 1 1 1 1 1 1 1

C723
2 1 BC_DAT_ECE1117 1

P
57,61 1.05V_VTTPWRGD

2
B

C724

C727

C729

C730

C731

C725

C726

C732

C728
R817 100K_0402_5%~D 4 1.05V_0.8V_PWROK
O 1.05V_0.8V_PWROK 14,58 2
2 POWER_SW_IN# 1 2
61 VCCSAPWROK A 22 POWER_SW_IN# POWER_SW#_MB 31,43

G
PBAT_SMBDAT 2 2 2 2 2 2 2 2 2 R811 10K_0402_5%~D
1 2 1
R818 2.2K_0402_5%~D TC7SH08FU_SSOP5~D

B64

A11
A22
B35
A41
A58
A52

A26
3
PBAT_SMBCLK C722

B3
1 2
R820 2.2K_0402_5%~D U51 1U_0402_6.3V6K~D
2 1 LPC_LDRQ#_MEC 2

VBAT

VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
@R821
@ R821 100K_0402_5%~D
D D
1 2 CHARGER_SMBDAT +RTC_CELL
R827 2.2K_0402_5%~D PS/2 INTERFACE MISC INTERFACE
1 2 CHARGER_SMBCLK A5 A10 SYSTEM_ID
15 SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA GPIO021/RC_ID1

1
R828 2.2K_0402_5%~D B6 B10 BOARD_ID @ C733
15 SML1_SMBCLK GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK GPIO020/RC_ID2
A37 B14 DDR_ON R819 1U_0402_6.3V6K~D
43 CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 GPIO025/UART_CLK DDR_ON 54,55
B40 B44 HOST_DEBUG_TX 100K_0402_5%~D 1 2
43 DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO120/UART_TX HOST_DEBUG_TX 36
+3.3V_ALW CLK_KBD A38 B46 HOST_DEBUG_RX
40 CLK_KBD GPIO112/PS2_CLK1A GPIO124/GPTP-OUT5/UART_RX HOST_DEBUG_RX 36
JTAG_RST# citcuit 40 DAT_KBD
DAT_KBD B41 B26 RUNPWROK

2
CLK_MSE GPIO113/PS2_DAT1A VCC_PRWGD EN_INVPWR RUNPWROK 7,41
close to U51.B57 40 CLK_MSE A39
GPIO114/PS2_CLK0A GPIO060/KBRST
A25 EN_INVPWR 24
1

DAT_MSE B42 B36 DOCK_PWR_SW# 1 2


40 DAT_MSE GPIO115/PS2_DAT0A GPIO101/ECGP_SCLK PCH_SATA_MOD_EN# 14 22 DOCK_PWR_SW# DOCK_PWR_BTN# 40
R824 PBAT_SMBDAT B59 B37 1 R825 10K_0402_5%~D
52 PBAT_SMBDAT GPIO154/I2C1C_DATA/PS2_CLK1B GPIO103/ECGP_MISO TOUCH_SCREEN_PD# 24
10K_0402_5%~D PBAT_SMBCLK A56 B38 XFR_ID_BIT#
52 PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO105/ECGP_MOSI XFR_ID_BIT# 31
A34 C734
GPIO102/HSPI_SCLK DYN_TUR_CURRNT_SET# DDR_HVREF_RST_GATE 7 1U_0402_6.3V6K~D
A35
2

JTAG_RST# GPIO104/HSPI_MISO CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# 60 2


GPIO106/HSPI_MOSI A36 CPU1.5V_S3_GATE 11
JTAG INTERFACE A40 MSDATA
GPIO116/MSDATA MSDATA 36
1 JTAG_TDI A51 B43 MSCLK
GPIO145/I2C1K_DATA/JTAG_TDI GPIO117/MSCLK MSCLK 36
1

1
0.1U_0402_16V4Z~D

JTAG_TDO B55 A45 +RTC_CELL


GPIO146/I2C1K_CLK/JTAG_TDO GPIO127/A20M SIO_A20GATE 18
100_0402_5%~D

C735

SHORT PADS~D

@ JTAG_CLK B56 A55


1

GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO153/LED3 PS_ID 52


R836

JTAG_TMS A53 A57 BAT1_LED# 45


Bat2 = Amber LED @C738
@ C738
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO156/LED1

1
2
@ JTAG1

JTAG_RST# B57 B61 Bat1 =White LED 1U_0402_6.3V6K~D


JTAG_RST# GPIO157/LED2 BAT2_LED# 45
B65 FWP# R870 1 2
2

C736 nFWP PROCHOT#_EC 20mA drive pins 100K_0402_5%~D


PROCHOT#/PWM4 A46
1 2 0.1U_0402_16V4Z~D
FAN PWM & TACH

2
2

DOCK_POR_RST# B22 GENERAL PURPOSE I/O R884 1 2 1K_0402_5%~D LAT_ON_SW# 1 2


40 DOCK_POR_RST# GPIO050/FAN_TACH1 VOL_MUTE 31 LAT_ON_SW_BTN# 31
SUS_ON A21 B2 1 R877 10K_0402_5%~D
44 SUS_ON
2

AUX_ON GPIO051/FAN_TACH2 GPIO001/ECSPI_CS1 DOCK_SMB_ALERT#


32 AUX_ON B23 GPIO052/FAN_TACH3 GPIO002/ECSPI_CS2 A2 DOCK_SMB_ALERT# 40,52,62
B24 B8 R886 1 2 1K_0402_5%~D C740
40,45 BREATH_LED# GPIO053/PWM0 GPIO014/GPTP-IN7/HSPI_CS1 VOL_UP 31 1U_0402_6.3V6K~D
PCH_ALW_ON A23 B18 R887 1 2 1K_0402_5%~D
44 PCH_ALW_ON GPIO054/PWM1 GPIO040/GPTP-OUT3/HSPI_CS2 VOL_DOWN 31 2
24 BIA_PWM_EC B25 GPIO055/PWM2 GPIO015/GPTP-OUT7 A8 ME_SUS_PWR_ACK 16
28 HDDC_EN A24 GPIO056/PWM3 GPIO016/GPTP-IN8 B9 1.5V_SUS_PWRGD 54
A9 +3.3V_ALW_PCH
+3.3V_ALW GPIO017/GPTP-OUT8 PM_APWROK 16
C GPIO026/GPTP-IN1 A14 1.05V_A_PWRGD 56 C
BC-LINK B15 AC_PRESENT 2 1
GPIO027/GPTP-OUT1 ALW_PWRGD_3V_5V 53
A43 A17 DEVICE_DET# R835 10K_0402_5%~D
41 BC_CLK_ECE5028 GPIO123/BCM_A_CLK GPIO041 DEVICE_DET# 29
BC_DAT_ECE5028 B45 B39 RESET_OUT#
41 BC_DAT_ECE5028 GPIO122/BCM_A_DAT GPIO107/nRESET_OUT RESET_OUT# 16
1

1
10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

100K_0402_5%~D
@R850
@

A42 A44 A_ON +3.3V_ALW


41 BC_INT#_ECE5028 GPIO121/BCM_A_INT# GPIO125/GPTP-IN5 A_ON 44,56
R847

R848

R849

R850

A12 B47 PCH_RSMRST#


22 BC_CLK_EMC4022 BC_DAT_EMC4022 GPIO022/BCM_B_CLK GPIO126 AC_PRESENT XFR_ID_BIT#
22 BC_DAT_EMC4022 B13 GPIO023/BCM_B_DAT GPIO151/GPTP-IN4 A54 AC_PRESENT 16 2 1
A13 B58 R1590 100K_0402_5%~D
22 BC_INT#_EMC4022 GPIO024/BCM_B_INT# GPIO152/GPTP-OUT4 SIO_PWRBTN# 16
B20 DOCK_SMB_DAT 2 1
2

@JDEG1
@ JDEG1 GPIO044/BCM_C_CLK R838 2.2K_0402_5%~D
A18
GPIO043/BCM_C_DAT DOCK_SMB_CLK
1 1
B19
GPIO042/BCM_C_INT# SMBUS INTERFACE 2 1
MSCLK DOCK_SMB_DAT R841 2.2K_0402_5%~D
2 2 43 BC_CLK_ECE1117 A20 A3 DOCK_SMB_DAT 40
MSDATA BC_DAT_ECE1117 GPIO047/LSBCM_D_CLK GPIO003/I2C1A_DATA DOCK_SMB_CLK DOCK_SMB_ALERT#
7
3 3 43 BC_DAT_ECE1117 B21 B4 DOCK_SMB_CLK 40 2 1
G1 HOST_DEBUG_TX GPIO046/LSBCM_D_DAT GPIO004/I2C1A_CLK LCD_SMBDAT R762 10K_0402_5%~D
8
4 4 @ R8531
2 43 BC_INT#_ECE1117 A19 A4
G2 GPIO045/LSBCM_D_INT# GPIO005/I2C1B_DATA
2 0_0402_5%~DHOST_DEBUG_RX LCD_SMBCLK LCD_SMBCLK
5 5 @ R8551 30 BEEP A16 B5 2 1
0_0402_5%~D GPIO032/GPTP-IN3/BCM_E_CLK GPIO006/I2C1B_CLK BAY_SMBDAT R418 2.2K_0402_5%~D
6 6 16 SIO_SLP_S5# B16 B7 BAY_SMBDAT 29,52
GPIO31/GPTP-OUT2/BCM_E_DAT GPIO012/I2C1H_DATA/I2C2D_DATA BAY_SMBCLK LCD_SMBDAT
41,60,62 ACAV_IN_NB A15 A7 BAY_SMBCLK 29,52 2 1
ACES_85204-06001~D GPIO30/GPTP-IN2/BCM_E_INT# GPIO013/I2C1H_CLK/I2C2D_CLK GPU_SMBDAT R420 2.2K_0402_5%~D
B48 GPU_SMBDAT 46
GPIO130/I2C2A_DATA GPU_SMBCLK VOL_MUTE
B49 GPU_SMBCLK 46 2 1
GPIO131/I2C2A_CLK CHARGER_SMBDAT R1166 100K_0402_5%~D
HOST INTERFACE GPIO132/I2C1G_DATA
A47 CHARGER_SMBDAT 60
+3.3V_ALW A6 B50 CHARGER_SMBCLK VOL_UP 2 1
14,17 SIO_EXT_SMI# GPIO011/nSMI GPIO140/I2C1G_CLK CHARGER_SMBCLK 60
A27 B52 R1167 100K_0402_5%~D
18 SIO_RCIN# GPIO061/LPCPD# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT 37
LPC_LDRQ#_MEC B29 A49 VOL_DOWN 2 1
LDRQ# GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK 37
A28 B53 R1184 100K_0402_5%~D
14,33,34,41 IRQ_SERIRQ SER_IRQ GPIO143/I2C1E_DATA USH_SMBDAT 33
49.9_0402_1%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

10K_0402_5%~D

B30 A50 DEVICE_DET# 2 1


14,17,34,36,37,41 PCH_PLTRST#_EC LRESET# GPIO144/I2C1E_CLK USH_SMBCLK 33
1

CLK_PCI_MEC A29 R1118 100K_0402_5%~D


17 CLK_PCI_MEC PCI_CLK
R857

R858

R859

R860

R861

B31 BAY_SMBDAT 2 1
14,33,34,41 LPC_LFRAME# LFRAME#
A30 DELL PWR SW INF R854 2.2K_0402_5%~D
14,33,34,41 LPC_LAD0 LAD0
B32 A59 BAY_SMBCLK 2 1
14,33,34,41 LPC_LAD1 LAD1 BGPO0
A31 B63 LAT_ON_SW# R856 2.2K_0402_5%~D
14,33,34,41 LPC_LAD2
2

@ JTAG2 LAD2 VCI_IN2# DYN_TUR_CURRNT_SET# 2


14,33,34,41 LPC_LAD3 B33 A60 ALWON 53 1
LAD3 VCI_OUT VCI_INT1# R764 10K_0402_5%~D
1 16,34,41 CLKRUN# A32 A63
1 JTAG_TDI CLKRUN# VCI_IN1# POWER_SW_IN#
2 18 SIO_EXT_SCI# A33 B67
2 JTAG_TMS GPIO100/nEC_SCI VCI_IN0# +5V_RUN
7 3 B1 ACAV_IN 22,60,62
G1 3 JTAG_CLK VCI_OVRD_IN DOCK_PWR_SW# +1.05V_RUN_VTT CLK_KBD
8 4 A1 2 1
G2 4 JTAG_TDO VCI_IN3# trace width 20 mils R845 4.7K_0402_5%~D
B
5
5 MASTER CLOCK B
6 MEC_XTAL1 A61 PECI B51 +PECI_VREF 1 2 DAT_KBD 2 1
6 XTAL1 PECI_VREF @R862
@ R862 1
MEC_XTAL2 2 1 MEC_XTAL2_R A62 A48 PECI_EC_R 2 0_0402_5%~D PECI_EC 18
R846 4.7K_0402_5%~D
XTAL2 PECI

0.1U_0402_16V4Z~D
ACES_85204-06001~D @R1068
@ R1068 0_0402_5%~D B62 DB Version 0.12 R863 43_0402_5%~D 1 CLK_MSE 2 1
GPIO160/32KHZ_OUT R863 close to R851 4.7K_0402_5%~D
I2S I2S_DAT
B17

C737
B27 1 2 U51 & least 250mils DAT_MSE 2 1
I2S_CLK

VSS_RO
VR_CAP
B34 B28 @ R864 1
@R864 2 0_0402_5%~D R852 4.7K_0402_5%~D
VSS[1]
VSS[4]

NC1 I2S_WS 2
AGND

A64 @R865
@ R865 0_0402_5%~D +3.3V_RUN
32 KHz Clock NC2 R864& R865 for MEC5045

EP
41 EC_32KHZ_ECE5048 1 2 B68
@R867
@ R867 0_0402_5%~D NC3 GPU_SMBDAT
should be populated 2 1
Depopulated R867 for ECE5028 use MEC5055-LZY_DQFN132_11X11~D R829 2.2K_0402_5%~D
B66

B11
B60

+VR_CAP B12

B54

C741 C1 GPU_SMBCLK 2 1
1 2 R822 2.2K_0402_5%~D
+3.3V_ALW 15mil least +3.3V_RUN +RTC_CELL
R875 C919 REV
33K_0402_5%~D

33P_0402_50V8J~D 15mil +3.3V_ALW +3.3V_ALW


Y6 VCI_INT1# 2 1
240K 4700p X00
2

MEC_XTAL2 4 G 3 R1156 100K_0402_5%~D

1
R875

MSDATA 1 2
130K 4700p X01 1

2
R799 R869 10K_0402_5%~D
MEC_XTAL1 1 C739 10K_0402_5%~D R871 R872 A_ON 1 2
G 2
62K 4700p X02 4.7U_0603_6.3V6K~D 1K_0402_5%~D 10K_0402_5%~D R873 100K_0402_5%~D
1

32.768KHZ_12.5PF_Q13MC1461000~D BOARD_ID 2 AUX_ON 2 1


* 33K 4700p A00

2
C743 R874 2.7K_0402_5%~D

1
4700P_0402_25V7K~D

1 2 1 2 RUNPWROK DDR_ON 2 1
1
8.2K 4700p R868 0_0402_5%~D SYSTEM_ID FWP# R876 100K_0402_5%~D
C744

33P_0402_50V8J~D SUS_ON 2 1
4.3K 4700p R878 100K_0402_5%~D

2
2 @ Q126 D PCH_ALW_ON 2 1
2K 4700p +3.3V_ALW_PCH MMBT3906WT1G_SC70-3~D
44 RUN_ON_ENABLE# 2 Q45
1
C742 @R879
@ R879 R880 100K_0402_5%~D
G SSM3K7002FU_SC70-3~D 4700P_0402_25V7K~D 10K_0402_5%~D DOCK_POR_RST# 2 1
Place closely pin A29 1K 4700p PCH_RSMRST# R881 100K_0402_5%~D
C

3 1 PCH_RSMRST#_Q 14,16 S

3
1

2 EN_INVPWR
E

2 1

1
CLK_PCI_MEC @ R866 R882 100K_0402_5%~D
+3.3V_RUN +3.3V_M 1.05V_0.8V_PWROK
B

4.7K_0402_5%~D 2 1
2
1

@D75A
@ D75A BAV99DW-7-F_SOT363-6~D R883 10K_0402_5%~D
A H_PROCHOT# 7,58,60 A
0_0402_5%~D

@ R885 1 RESET_OUT# 2 1
2
1

10_0402_5%~D 6 1=JTAG interface Reset disabled @R843


@ R843 8.2K_0402_5%~D
1

R893 2 CHIPSET_ID for BID 0=Reset JTAG interface CPU1.5V_S3_GATE 2 1


R1180

@R1179
@ R1179 100K_0402_5%~D R889 100K_0402_5%~D
function
2

1 10K_0402_5%~D
@D75B
@ D75B BAV99DW-7-F_SOT363-6~D
DELL CONFIDENTIAL/PROPRIETARY
2
1

@ C747 D
PCH_PWRGD# 22 4
2

4.7P_0402_50V8C~D PROCHOT#_EC 2 @ Q47 3


2 G SSM3K7002FU_SC70-3~D 5 Compal Electronics, Inc.
1

D
1 2 S
3

@ R812 RESET_OUT# 2 Q48 @ R823 Title


100K_0402_5%~D G SSM3K7002FU_SC70-3~D 2.2K_0402_5%~D
EMC5055

WWW.AliSaler.Com
S
3

Size Document Number Rev


2

INTEL RSMRST# circuit 1.0


LA-6592P
Date: Thursday, January 13, 2011 Sheet 42 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +3.3V_TP Pin reverse for PT BlueTooth @ R1129 +3.3V_BT


0_0603_5%
+3.3V_RUN 1 2
Touch Pad

4.7K_0402_5%~D

4.7K_0402_5%~D
Touch Pad Conn. Pitch=0.5mm

1
+3.3V_ALW 1 2 1 2

R903

R902
@R1130
@ R1130 0_0603_5%~D
C748
JTP1 0.1U_0402_16V4Z~D
1

2
TP_CLK 1 CONN@
2
L54 2 TP_DATA TP_DATA 2
42 DAT_TP_SIO 1 BLM18AG601SN1D_0603~D 3
3
JBT1
D D
4 1
L55 2 TP_CLK 4 1
42 CLK_TP_SIO 1 BLM18AG601SN1D_0603~D +3.3V_TP 5
5
2
2
PS2_DAT_TS 17 BT_DET#
6 9 36 COEX1_BT_ACTIVE 3
6 G1 3

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D

10P_0402_50V8J~D
1 1 PS2_CLK_TS 7 10 BT_COEX_STATUS2 4
7 G2 33 BT_COEX_STATUS2 4

C752
1 1 8 BT_PRI_STATUS 5
8 33 BT_PRI_STATUS 5

C751
6
45 BT_ACTIVE 6

C750

C749
TYCO_2041070-8 7
2 2 41 BT_RADIO_DIS# 7
CONN@ 8
2 2 36 COEX2_WLAN_ACTIVE 8
9
9
10
10
17 USBP11- 11
11
17 USBP11+ 12 12
13 G1
14 G2
+3.3V_ALW +3.3V_RUN +3.3V_TP
E&T_3703-E12N-03R
@ R1161

100P_0402_50V8J~D
0_0603_5%

33P_0402_50V8J~D

10K_0402_5%~D
1 2

1
+3.3V_TP

@ C754
1 1

C753

R904
TP_CLK @ R1162
TP_DATA 0_0603_5%~D

SD05.TCT_SOD323-2~D

SD05.TCT_SOD323-2~D
1 2
2 2
1

2
1

1
C755

@D36
@

@D37
@
0.1U_0402_16V4Z~D
2

D36

D37
2

2
+3.3V_BT 1 2 BT_COEX_STATUS2
@ R1133 1K_0402_5%~D
C C
1 2 BT_PRI_STATUS
@ R1134 1K_0402_5%~D
Place close to JTP1

Power Switch for debug


Change KB connector to same as JSC1

KB Conn. Pitch=1.0mm
1 2
JKB1 31,42 POWER_SW#_MB 1 2
+3.3V_ALW +5V_RUN KB_DET# 1
18 KB_DET# 1 1
PS2_CLK_TS 2
PS2_DAT_TS 2 @ C759
3
3 100P_0402_50V8J~D @ PWRSW1
1 1 +3.3V_ALW 4
4 2 @SHORT PADS~D
+5V_RUN 5
C756 C758 5
6
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 42 BC_INT#_ECE1117 6
42 BC_DAT_ECE1117 7 Place on Bottom
2 2 7
8
8
42 BC_CLK_ECE1117 9
9
10
10
11
GND
12
GND
B Place close to JKB1 FCI_10089709-010010LF~D @LED Board FFC @ MDC wire set cable B
CONN@ Part Number Part Number Description
Description
NBX0000RP0L FFC 6P H P1 PAD=0.7 87.4MM MB-LED/B 0FD DC30100BL0L CONN SET 0FD
MDC-RJ11
@MEDIA Board FFC
Part Number @ T/P FFC
Description
Part Number Description
NBX0000RS0L FFC 12P G P.5 PAD.3 75MM MB-VOLUME/B 0FD
@ LVDS cable FFC 8P F P0.5
NBX0000RR0L PAD=0.3 136MM
Part Number Description @ LVDS cable
MB-TP/B 0FD
Part Number Description
DC020003Y0L H-CONN SET ZJX MB-LCD @KB FFC
14 WXGA+(-1ch)
DC02C00180L H-CONN SET 0FD MB-LCD CAM LED 2CHANNEL Part Number Description

SP070007V0L S SOCKET TYCO 1770551-1


@ RTC BATT @ SG DC_IN wire cable 10P H5.9 SMART
Part Number Description Part Number Description
@BT wire cable
GC20323MX00 BATT CR2032 3V DC30100BO0L CONN SET 0FE DCJACK-MB WDMD-DCE30002-DF Part Number Description
220MAH MAXELL
@ Battery bridge cable DC020014Y0L H-CONN SET 0FD MB-BT
Part Number Description
@ FAN DC020014Z10 H-CONN SET 0FD M/B-BATTERY 9PIN
Part Number Description

DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA

@ Speak
A A
Part Number Description

PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Touch PAD/Int KB/BT
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 43 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
+3.3V_ALW_PCH Source
+15V_ALW +3.3V_ALW @ Q49 +3.3V_ALW_PCH +3.3V_ALW
DC/DC Interface
+5V_RUN Source
+3.3V_ALW2 SI3456DDV-T1-GE3_TSOP6~D
+3.3V_ALW2 +15V_ALW +5V_ALW Q50

D
6 PJP57 SI4164DY-T1-GE3_SO8~D +5V_RUN

S
1
5 4 1 2 8 1

1
10U_0805_6.3V6M~D

20K_0402_5%~D
2 7 2

10U_0805_10V4Z~D
@ R907 @ R905 1 1 PAD-OPEN 4x4m R906 6 3

1
@R908
@
100K_0402_5%~D 100K_0402_5%~D 100K_0402_5%~D 5 1

C760

R908
R909 R910

C761
ALW_ENABLE 100K_0402_5%~D 20K_0402_5%~D

4
20 ALW_ENABLE 2 5V_RUN_ENABLE

2
3
D 2 D

2
3

2200P_0402_50V7K~D
@ Q51B 1
ALW_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D Q52B
@C762
@C762 RUN_ON_ENABLE# 5 DMN66D0LDW-7_SOT363-6~D 1
42 RUN_ON_ENABLE#

6
3300P_0402_50V7K~D

4
2

C763
@Q51A
@ Q51A

4
DMN66D0LDW-7_SOT363-6~D

6
2
42 PCH_ALW_ON 2
Q52A
DMN66D0LDW-7_SOT363-6~D
1 11,37,41,55,63 RUN_ON 2

1
+3.3V_SUS Source +15V_ALW +3.3V_RUN Source
+3.3V_ALW Q54 +3.3V_ALW Q55 +3.3V_RUN
SI3456DDV-T1-GE3_TSOP6~D +3.3V_SUS +15V_ALW NTMS4920NR2G_SO8~D

1
8 1

10U_0805_6.3V6M~D
R911 6 7 2

1
+3.3V_ALW2 100K_0402_5%~D 5 4 6 3 1
2 R912 5 R913

1
10U_0805_6.3V6M~D

C764
1 1 100K_0402_5%~D 20K_0402_5%~D

2
R914

4
1

C765
20K_0402_5%~D

2
R915 SUS_ENABLE
100K_0402_5%~D 2 3.3V_RUN_ENABLE

2
3
2

1
Q53B D
1
SUS_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D 1 2
C G Q56 C766 C
6

C767 S SSM3K7002FU_SC70-3~D 470P_0402_50V7K~D


4

3
Q53A 4700P_0402_25V7K~D 2
DMN66D0LDW-7_SOT363-6~D 2

42 SUS_ON 2
1

Discharg Circuit
+3.3V_M +1.5V_RUN Source
+3.3V_M Source
+3.3V_ALW Q58 Q59

1
+15V_ALW SI3456DDV-T1-GE3_TSOP6~D +3.3V_M +1.5V_MEM NTGS4141NT1G_TSOP6~D
+3.3V_ALW2 R916 +15V_ALW +1.5V_RUN
D

D
6 39_0603_5%~D 6
S

S
1

5 4 5 4

1
10U_0805_6.3V6M~D

10U_0805_6.3V6M~D
R917 2 2

2
1

1
100K_0402_5%~D R920

+3.3V_M_CHG
1 1 1 1

C769
R918 @ R919 100K_0402_5%~D R921
G

G
C768

100K_0402_5%~D 20K_0402_5%~D 20K_0402_5%~D


2

3
A_ENABLE

2
2 2
2

2
3

SSM3K7002FU_SC70-3~D
1.5V_RUN_ENABLE

Q57B

1
A_ON_3.3V# 5 DMN66D0LDW-7_SOT363-6~D D
1 1

1
D

Q60
A_ON_3.3V# 2
6

C770 G 2 Q62 C771


4

Q57A 4700P_0402_25V7K~D S G SSM3K7002FU_SC70-3~D 4700P_0402_25V7K~D

3
B DMN66D0LDW-7_SOT363-6~D 2 S 2 B

3
42,56 A_ON 2
1

Discharg Circuit +1.05V_RUN Source


+3.3V_SUS +3.3V_ALW_PCH +5V_RUN +1.5V_RUN +3.3V_RUN +1.05V_RUN +1.5V_CPU_VDDQ +0.75V_DDR_VTT +15V_ALW +1.05V_M Q63
SI4164DY-T1-GE3_SO8~D +1.05V_RUN
8 1
1

1
7 2

10U_0805_6.3V6M~D
@ R922 @ R928 @ R923 @ R924 R929 @ R925 R926 R930 6 3

1
1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 1K_0402_5%~D 39_0603_5%~D 39_0402_5%~D 220_0402_5%~D R927 100K_0402_5%~D 5 1
22_0603_5%~D R931

C772
20K_0402_5%~D
2

4
1.05V_RUN_ENABLE
+3.3V_ALWPCH_CHG

+5V_RUN_CHG

+1.5V_RUN_CHG

+3.3V_RUN_CHG

+1.05V_RUN_CHG

+1.5V_CPU_VDDQ_CHG
2
+3.3V_SUS_CHG

2
+DDR_CHG

1
D

2200P_0402_50V7K~D
2 Q64
G SSM3K7002FU_SC70-3~D 1
7,11 RUN_ON_CPU1.5VS3# S

C773
1

1
D D D D D 2
SSM3K7002FU_SC70-3~D
@ Q67

SSM3K7002FU_SC70-3~D
@ Q68

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D
@ Q70

SSM3K7002FU_SC70-3~D

SSM3K7002FU_SC70-3~D
1

D D
SSM3K7002FU_SC70-3~D
@ Q65

SSM3K7002FU_SC70-3~D
@ Q66

Q69

Q72
RUN_ON_ENABLE# 2 2 2 2 2
1

SUS_ON_3.3V# ALW_ON_3.3V# 2 G G G G D G
2
Q71

G G S S S S 2 S
3

3
A G A
S S
3

S
3

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 44 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +3.3V_ALW
HDD LED solution for White LED
+5V_ALW
R938

3
+5V_ALW 100K_0402_5%~D Q83A

1
+5V_ALW 1 2
R932 +3.3V_ALW DMN66D0LDW-7_SOT363-6~D
10K_0402_5%~D 1 6 2
Q82A

6
Q74B DMN66D0LDW-7_SOT363-6~D Q81
Battery LED

2
DMN66D0LDW-7_SOT363-6~D Q74A PDTA114EU_SC70-3~D

2
1
D59 DMN66D0LDW-7_SOT363-6~D MASK_BASE_LEDS#
4 3 1 2 1 6 2 R940 1 2 2
14 SATA_ACT#

1
47K_0402_5%~D +5V_ALW 1 2 BATT_WHITE 31
D D
RB751S40T1_SOD523-2~D Q75 C774 R941 4.7K_0402_5%~D

1
5

1
PDTA114EU_SC70-3~D 0.1U_0402_16V4Z~D

1
+5V_ALW BATT_YELLOW 31

NC
P
2 4 BAT2_LED R942
41 MASK_SATA_LED# 42 BAT2_LED#

1
A Y 100K_0402_5%~D

3
G
D62 1 2 U54
MASK_BASE_LEDS# R934 4.7K_0402_5%~D SATA_LED 31 NC7SZ04P5X-G_SC70-5~D Q83B
41 LED_SATA_DIAG_OUT# 1 2

2
DMN66D0LDW-7_SOT363-6~D
RB751S40T1_SOD523-2~D 5 4 3 2

Q82B Q84

4
DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D

5
SYS_LED_MASK#
WLAN LED solution for White LED

1
+3.3V_ALW
+3.3V_ALW
R945

3
+5V_ALW 100K_0402_5%~D
Q92A

1
+3.3V_ALW 1 2
R937 DMN66D0LDW-7_SOT363-6~D
100K_0402_5%~D 1 6 2

3
2 Q78A Q88
DMN66D0LDW-7_SOT363-6~D +3.3V_ALW PDTA114EU_SC70-3~D

2
1 6 2 Q89A MASK_BASE_LEDS#
36,41 WIRELESS_LED#

6
DMN66D0LDW-7_SOT363-6~D

1
Q79

1
PDTA114EU_SC70-3~D

2
R947 1 2 2 +3.3V_ALW
MASK_BASE_LEDS# 47K_0402_5%~D 1 2

1
C775 R946 150_0402_5%~D

1
3

1
0.1U_0402_16V4Z~D

2
R948 +3.3V_ALW

NC
P
Q78B 2 4 BAT1_LED 100K_0402_5%~D
42 BAT1_LED# A Y
5 DMN66D0LDW-7_SOT363-6~D
43 BT_ACTIVE

3
G
U55

2
NC7SZ04P5X-G_SC70-5~D Q92B R949
4

3
C 1 2 DMN66D0LDW-7_SOT363-6~D 4.7K_0402_5%~D C
WLAN_LED 31
1

R939 4.7K_0402_5%~D 5 4 3 2 1 2 BATT_WHITE_LED 24


R950
100K_0402_5%~D Q89B Q93

4
DMN66D0LDW-7_SOT363-6~D PDTA114EU_SC70-3~D

5
R951
2

150_0402_5%~D

1
SYS_LED_MASK# 1 2 BATT_YELLOW_LED 24

+5V_ALW

1
+5V_ALW
R953
100K_0402_5%~D

3
Q95B

2
DMN66D0LDW-7_SOT363-6~D
DMN66D0LDW-7_SOT363-6~D
4 3 2
+3.3V_ALW

6
Q94
PDTA114EU_SC70-3~D

5
C777

Q95A
0.1U_0402_16V4Z~D 2 +5V_ALW

1
1
1 2 SYS_LED_MASK# 1 2 BREATH_WHITE_LED 24
R954 R955 4.7K_0402_5%~D

1
47K_0402_5%~D +5V_ALW
R956
B B
100K_0402_5%~D

3
Q101B

NC
P
40,42 BREATH_LED#

2
DMN66D0LDW-7_SOT363-6~D
2 4 BREATH_LED#_R DMN66D0LDW-7_SOT363-6~D
A Y
4 3 2

G
U57

6
NC7SZ04P5X-G_SC70-5~D Q96

3
PDTA114EU_SC70-3~D

5
Q101A
2

1
MASK_BASE_LEDS# LED1
1 2 BREATH_WHITE_LED_SNIFF 2 1

1
R957 1K_0402_5%~D
LTW-C193TS5_WHITE~D

Place LED1 close to SW1

+3.3V_ALW
C778
0.1U_0402_16V4Z~D
1 2
EMI CLIP
CLIP1
EMI_CLIP
5

U58
LED Circuit Control Table SYS_LED_MASK# 1 1
Fiducial Mark
P

41 SYS_LED_MASK# B GND
4 MASK_BASE_LEDS#
@ FD1 LID_CL# O
SYS_LED_MASK# LID_CL# 31,41 LID_CL# 2
A
G

1 CLIP2
TC7SH08FU_SSOP5~D EMI_CLIP
3

FIDUCIAL MARK~D
A
@ FD2
Mask All LEDs (Sniffer Function) 0 X GND
1 A

1 Mask Base MB LEDs (Lid Closed) 1 0


FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D

@ FD4 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H9 @ H10 @ H11 @ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H19 @ H20
Compal Electronics, Inc.
1 H_3P2 H_3P2 H_3P0 H_3P2 H_3P0 H_3P0 H_3P0 H_3P2 H_3P0 H_3P2 H_3P7 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_2P2 H_3P0x2P0 H_2P0N PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
FIDUCIAL MARK~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PAD and Standoff

WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1

PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0


LA-6592P
Date: Thursday, January 13, 2011 Sheet 45 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
UV1A
Part 1 of 5 DV2
PEG_CTX_GRX_P[0..15] PEG_CTX_GRX_P0 AE12 N1 DPC_GPU_HPD 2 1
6 PEG_CTX_GRX_P[0..15] PEG_CTX_GRX_N0 PEX_RX0 GPIO0 DPC_GPU_HPD DP_HDMI_HPD 41
AF12 PEX_RX0_N GPIO1 G1 DPC_GPU_HPD 40
PEG_CTX_GRX_N[0..15] PEG_CTX_GRX_P1 AG12 C1 BIA_PWM_GPU BIA_PWM_GPU 24 RB751V-40GTE-17_SOD323-2~D
6 PEG_CTX_GRX_N[0..15] PEG_CTX_GRX_N1 PEX_RX1 GPIO2 ENVDD_GPU
AG13 PEX_RX1_N GPIO3 M2 ENVDD_GPU 24
PEG_CRX_GTX_P[0..15] PEG_CTX_GRX_P2 AF13 M3 PANEL_BKEN_DGPU PANEL_BKEN_DGPU 24 DV3
6 PEG_CRX_GTX_P[0..15] PEG_CTX_GRX_N2 PEX_RX2 GPIO4 GPU_VID_0 DPD_GPU_HPD 2
AE13 K3 GPU_VID_0 63 1
PEG_CRX_GTX_N[0..15] PEG_CTX_GRX_P3 PEX_RX2_N GPIO5 GPU_VID_1
6 PEG_CRX_GTX_N[0..15] AE15 K2 GPU_VID_1 63
PEG_CTX_GRX_N3 PEX_RX3 GPIO6 RB751V-40GTE-17_SOD323-2~D
AF15 J2
D PEG_CTX_GRX_P4 PEX_RX3_N GPIO7 THERMTRIP_VGA# D
AG15 C2 THERMTRIP_VGA# 22
PEX_RX4 GPIO8

GPIO
PEG_CTX_GRX_N4 AG16 M1 GPU_GPIO9 DV4
PEG_CTX_GRX_P5 PEX_RX4_N GPIO9 DPE_GPU_HPD 2
AF16 D2 1
PEG_CTX_GRX_N5 PEX_RX5 GPIO10
AE16 D1
PEG_CRX_GTX_P0 CV1 PEG_CRX_GTX_C_P0 PEG_CTX_GRX_P6 PEX_RX5_N GPIO11 GPU_CLKDWN_R
2 1 0.22U_0402_16V7K~D AE18 J3 1 2 GPU_CLKDWN 41
RB751V-40GTE-17_SOD323-2~D
PEG_CRX_GTX_N0 CV2 PEG_CRX_GTX_C_N0 PEG_CTX_GRX_N6 PEX_RX6 GPIO12
2 1 0.22U_0402_16V7K~D AF18
PEX_RX6_N GPIO13
J1 @ RV20 0_0402_5%~D
PEG_CTX_GRX_P7 AG18 K1
PEG_CRX_GTX_P1 CV4 PEG_CRX_GTX_C_P1 PEG_CTX_GRX_N7 PEX_RX7 GPIO14 DPE_GPU_HPD
2 1 0.22U_0402_16V7K~D AG19
PEX_RX7_N GPIO15
F3 DPE_GPU_HPD 26
PEG_CRX_GTX_N1 CV3 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N1 PEG_CTX_GRX_P8 AF19 G3 GPU_DEEP_CLKDWN_R1 2
PEX_RX8 GPIO16 GPU_DEEP_CLKDWN 41
PEG_CTX_GRX_N8 AE19 G2 @ RV25 0_0402_5%~D
PEG_CRX_GTX_P2 CV5 PEG_CRX_GTX_C_P2 PEG_CTX_GRX_P9 PEX_RX8_N GPIO17 DGPU_DI_INT#_R
2 1 0.22U_0402_16V7K~D AE21
PEX_RX9 GPIO18
F1 1 2 DGPU_DI_INT# 41
PEG_CRX_GTX_N2 CV6 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N2 PEG_CTX_GRX_N9 AF21 F2 @ RV26 0_0402_5%~D
PEG_CTX_GRX_P10 PEX_RX9_N GPIO19 DPD_GPU_HPD
AG21 PEX_RX10 DPD_GPU_HPD 40
PEG_CRX_GTX_P3 CV7 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P3 PEG_CTX_GRX_N10 AG22 AD2 GPU_CRT_HSYNC
PEG_CRX_GTX_N3 PEG_CRX_GTX_C_N3 PEG_CTX_GRX_P11 PEX_RX10_N DACA_HSYNC GPU_CRT_VSYNC GPU_CRT_HSYNC 25
CV8 2 1 0.22U_0402_16V7K~D AF22 AD1
PEG_CTX_GRX_N11 PEX_RX11 DACA_VSYNC GPU_CRT_VSYNC 25
AE22

DACA
PEG_CRX_GTX_P4 CV9 PEG_CRX_GTX_C_P4 PEG_CTX_GRX_P12 PEX_RX11_N GPU_CRT_RED
2 1 0.22U_0402_16V7K~D AE24 PEX_RX12 DACA_RED AE2 GPU_CRT_RED 25
PEG_CRX_GTX_N4 CV10 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N4 PEG_CTX_GRX_N12 AF24 AD3 GPU_CRT_BLU
PEX_RX12_N DACA_BLUE GPU_CRT_BLU 25
PEG_CTX_GRX_P13 AG24 AE3 GPU_CRT_GRN
PEG_CRX_GTX_P5 PEG_CRX_GTX_C_P5 PEG_CTX_GRX_N13 PEX_RX13 DACA_GREEN GPU_CRT_GRN 25
CV11 2 1 0.22U_0402_16V7K~D AF25
PEG_CRX_GTX_N5 CV12 PEG_CRX_GTX_C_N5 PEG_CTX_GRX_P14 PEX_RX13_N DACA_VREF
2 1 0.22U_0402_16V7K~D AG25 AF1 CV13 1 2 0.1U_0402_10V7K~D
PEG_CTX_GRX_N14 PEX_RX14 DACA_VREF DACA_RSET
AG26 PEX_RX14_N DACA_RSET AE1 1 2

PCI EXPRESS
PEG_CRX_GTX_P6 CV14 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P6 PEG_CTX_GRX_P15 AF27 RV6 124_0402_1%~D ENVDD_GPU 1 2
PEG_CRX_GTX_N6 CV15 PEG_CRX_GTX_C_N6 PEG_CTX_GRX_N15 PEX_RX15
2 1 0.22U_0402_16V7K~D AE27 PEX_RX15_N DACB_HSYNC U6 RV1 100K_0402_5%~D
DACB_VSYNC U4
PEG_CRX_GTX_P7 CV16 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P7 PEG_CRX_GTX_C_P0 AD10

DACB
PEG_CRX_GTX_N7 CV17 PEG_CRX_GTX_C_N7 PEG_CRX_GTX_C_N0 PEX_TX0
2 1 0.22U_0402_16V7K~D AD11 PEX_TX0_N DACB_RED T5
PEG_CRX_GTX_C_P1 AD12 R4
PEG_CRX_GTX_P8 CV18 PEG_CRX_GTX_C_P8 PEG_CRX_GTX_C_N1 PEX_TX1 DACB_BLUE
2 1 0.22U_0402_16V7K~D AC12 PEX_TX1_N DACB_GREEN T4
PEG_CRX_GTX_N8 CV19 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_N8 PEG_CRX_GTX_C_P2 AB11
PEG_CRX_GTX_C_N2 PEX_TX2
PEG_CRX_GTX_P9 CV20 2 1 0.22U_0402_16V7K~D PEG_CRX_GTX_C_P9 PEG_CRX_GTX_C_P3
AB12
AD13
PEX_TX2_N DACB_VREF R6
V6
Close to GPU
C PEG_CRX_GTX_N9 CV21 PEG_CRX_GTX_C_N9 PEG_CRX_GTX_C_N3 PEX_TX3 DACB_RSET C
2 1 0.22U_0402_16V7K~D AD14 PEX_TX3_N
PEG_CRX_GTX_C_P4 AD15 GPU_CRT_RED 1 2
PEG_CRX_GTX_P10 CV22 PEG_CRX_GTX_C_P10 PEG_CRX_GTX_C_N4 PEX_TX4
2 1 0.22U_0402_16V7K~D AC15 RV3 150_0402_1%~D
PEG_CRX_GTX_N10 CV23 PEG_CRX_GTX_C_N10 PEG_CRX_GTX_C_P5 PEX_TX4_N GPU_JTAG_TCK GPU_CRT_GRN
2 1 0.22U_0402_16V7K~D AB14 PEX_TX5 JTAG_TCK AF3 @ TV1 1 2
PEG_CRX_GTX_C_N5 AB15 AG4 GPU_JTAG_TDI @ TV2 RV4 150_0402_1%~D
PEG_CRX_GTX_P11 CV24 PEG_CRX_GTX_C_P11 PEG_CRX_GTX_C_P6 PEX_TX5_N JTAG_TDI GPU_JTAG_TDO GPU_CRT_BLU
2 1 0.22U_0402_16V7K~D AC16 AE4 @ TV3 1 2

TEST
PEG_CRX_GTX_N11 CV25 PEG_CRX_GTX_C_N11 PEG_CRX_GTX_C_N6 PEX_TX6 JTAG_TDO GPU_JTAG_TMS
2 1 0.22U_0402_16V7K~D AD16 AF4 @ TV4 RV5 150_0402_1%~D
PEG_CRX_GTX_C_P7 PEX_TX6_N JTAG_TMS GPU_JTAG_TRST#
AD17 AG3 1 2
PEG_CRX_GTX_P12 CV26 PEG_CRX_GTX_C_P12 PEG_CRX_GTX_C_N7 PEX_TX7 JTAG_TRST_N
2 1 0.22U_0402_16V7K~D AD18 RV9 1K_0402_1%~D
PEG_CRX_GTX_N12 CV27 PEG_CRX_GTX_C_N12 PEG_CRX_GTX_C_P8 PEX_TX7_N GPU_TESTMODE
2 1 0.22U_0402_16V7K~D AC18 AD25
PEG_CRX_GTX_C_N8 PEX_TX8 TESTMODE
AB18
PEG_CRX_GTX_P13 CV28 PEG_CRX_GTX_C_P13 PEG_CRX_GTX_C_P9 PEX_TX8_N
2 1 0.22U_0402_16V7K~D AB19
PEG_CRX_GTX_N13 CV29 PEG_CRX_GTX_C_N13 PEG_CRX_GTX_C_N9 PEX_TX9
2 1 0.22U_0402_16V7K~D AB20
PEX_TX9_N
PEG_CRX_GTX_C_P10 AD19 R1 GPU_CRT_CLK_DDC_R 1 2
PEG_CRX_GTX_P14 PEG_CRX_GTX_C_P14 PEG_CRX_GTX_C_N10 PEX_TX10 I2CA_SCL GPU_CRT_DAT_DDC_R RV10 1 GPU_CRT_CLK_DDC 25
CV30 2 1 0.22U_0402_16V7K~D AD20 T3 2 33_0402_5%~D
PEG_CRX_GTX_N14 PEG_CRX_GTX_C_N14 PEG_CRX_GTX_C_P11 PEX_TX10_N I2CA_SDA GPU_CRT_DAT_DDC 25 +3.3V_RUN_GFX
CV31 2 1 0.22U_0402_16V7K~D AD21 RV11 33_0402_5%~D
PEG_CRX_GTX_C_N11 PEX_TX11 I2CB_SCL
AC21 R2
PEG_CRX_GTX_P15 CV32 PEG_CRX_GTX_C_P15 PEG_CRX_GTX_C_P12 PEX_TX11_N I2CB_SCL I2CB_SDA
2 1 0.22U_0402_16V7K~D AB21 R3
PEG_CRX_GTX_N15 CV33 PEG_CRX_GTX_C_N15 PEG_CRX_GTX_C_N12 PEX_TX12 I2CB_SDA
2 1 0.22U_0402_16V7K~D AB22
PEX_TX12_N
PEG_CRX_GTX_C_P13 AC22 A2 LDDC_CLK_GPU LDDC_CLK_GPU 23
PEX_TX13 I2CC_SCL

1
I2C
PEG_CRX_GTX_C_N13 AD22 B1 LDDC_DATA_GPU LDDC_DATA_GPU 23
PEG_CRX_GTX_C_P14 PEX_TX13_N I2CC_SDA @ RV7
AD23
PEG_CRX_GTX_C_N14 PEX_TX14 I2CH_SCL 10K_0402_5%~D
AD24 A3
PEG_CRX_GTX_C_P15 PEX_TX14_N GPIO20 I2CH_SDA
AE25
PEX_TX15 GPIO21
A4 FERMI Changed
PEG_CRX_GTX_C_N15 AE26

2
PEX_TX15_N GPU_SMBCLK GPU_TESTMODE
T1 GPU_SMBCLK 42
I2CS_SCL GPU_SMBDAT
AB10 T2 GPU_SMBDAT 42
15 CLK_PCIE_VGA PEX_REFCLK I2CS_SDA
AC10
15 CLK_PCIE_VGA# PEX_REFCLK_N

1
PEX_TSTCLK_OUT RV8
Differential signal 1
@ RV13
2
200_0402_1%~D PEX_TSTCLK_OUT#
AF10
AE10
PEX_TSTCLK_OUT
D11 XTALSSIN 1 2 10K_0402_5%~D
PEX_TSTCLK_OUT_N XTAL_SSIN RV12 10K_0402_5%~D
B XTALOUTBUFF B
2 1 AG10 E9 1 2

2
RV15 2.49K_0402_1%~D PEX_TERMP XTAL_OUTBUFF RV16 10K_0402_5%~D
DGPU_PEX_RST 1 2 DGPU_PEX_RST_R AD9 E10 1 2 NV_CLK_27M_OUT

CLK
@ RV18 0_0402_5%~D PEX_RST_N XTAL_OUT @RV19
@ RV19 0_0402_5%~D
+3.3V_RUN_GFX 1 2 CLK_REQ# AE9 D10 CLK_27M_IN
RV21 10K_0402_5%~D PEX_CLKREQ_N XTAL_IN

don't connect to PCH N12P-NS-S-A1_BGA533~D

YV1 27MHZ_10PF_X3S027000BA1H-U~D
CLK_27M_IN 1 3 NV_CLK_27M_OUT
2 G1 +3.3V_RUN_GFX
G2 4

22P_0402_50V8J~D

22P_0402_50V8J~D
1 1
+3.3V_RUN
CV34

CV35
1 2 GPU_CRT_CLK_DDC
@ RV23 4.7K_0402_5%~D
1

+3.3V_RUN +3.3V_RUN_GFX 2 2 1 2 GPU_CRT_DAT_DDC


@ RV33 @ RV24 4.7K_0402_5%~D
1

100K_0402_5%~D 1 2 I2CH_SCL
RV29 RV100 @ 10K_0402_5%~D
2.2K_0402_5%~D 1 2 I2CH_SDA FERMI Changed
2

RV101 @ 10K_0402_5%~D
1 2 1 I2CB_SCL
P

18 DGPU_HOLD_RST#
2

B DGPU_PEX_RST RV27 2.2K_0402_5%~D


4
O I2CB_SDA
17 PLTRST_GPU# 2 2 1
A
G

RV28 2.2K_0402_5%~D
74AHC1G09GW_TSSOP5~D 1 2 GPU_GPIO9
3

UV14 RV102 10K_0402_5%~D


1 2 THERMTRIP_VGA#
RV103 10K_0402_5%~D
1 2 GPU_CLKDWN_R
A RV104 10K_0402_5%~D A
1 2
1

RV22 @ DV1
RB751V-40GTE-17_SOD323-2~D
100K_0402_5%~D

Compal Electronics, Inc.


2

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N12P PCIE,I2C,DAC,GPIO
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 46 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com UV1C
Part 3 of 5
AC4 IFPA_TXC NC C15 GB1B-64 : PGOOD
23 LCD_ACLK+_GPU
AD4 IFPA_TXC_N NC D15
23 LCD_ACLK-_GPU

NC
V5 J5 PGOOD 1 2 UV1E
23 LCD_A0+_GPU IFPA_TXD0 PGOOD RV61 10K_0402_5%~D Part 5 of 5
V4 IFPA_TXD0_N B2 GND GND U2
23 LCD_A0-_GPU
23 LCD_A1+_GPU AA5 IFPA_TXD1 B5 GND GND U5
AA4 IFPA_TXD1_N
GB1B-64 : MULTI_STRAP_REF2_GND B8 GND GND U11
23 LCD_A1-_GPU
W4 B11 U12
23 LCD_A2+_GPU IFPA_TXD2 MULTI_STRAP_REF2_GND 1 GND GND
Y4 T6 2 B14 U13
23 LCD_A2-_GPU IFPA_TXD2_N MULTI_STRAP_REF2_GND RV62 40.2K_0402_1%~D GND GND
AB4 W6 B17 U14

DBG
D IFPA_TXD3 DBG_DATA1 GND GND D
AB5 Y6 B20 U15
IFPA_TXD3_N DBG_DATA2 GND GND
AA6 B23 U16
DBG_DATA3 GND GND
N3 B26 U17
DBG_DATA4 GND GND
AB3 E2 U23
23 LCD_BCLK+_GPU IFPB_TXC GND GND
AB2 E5 U26
23 LCD_BCLK-_GPU IFPB_TXC_N GND GND
W1 E8 V9
23 LCD_B0+_GPU IFPB_TXD4 STRAP0 GND GND
V1 C7 E11 V19
23 LCD_B0-_GPU IFPB_TXD4_N STRAP0 GND GND
W3 E17 W11

STRAP
IFPB_TXD5 GND GND

LVDS / TMDS
23 LCD_B1+_GPU STRAP1
W2 B9 E20 W14
23 LCD_B1-_GPU IFPB_TXD5_N STRAP1 GND GND
AA2 E23 W17
23 LCD_B2+_GPU IFPB_TXD6 STRAP2 GND GND
AA3 A9 E26 Y2
23 LCD_B2-_GPU IFPB_TXD6_N STRAP2 GND GND
AB1 IFPB_TXD7 H2 GND GND Y5

GND
AA1 IFPB_TXD7_N H5 GND GND Y23
J11 GND GND Y26
J14 GND GND AC2
DPC_GPU_AUX/DDC G4 N5 J17 AC5
27 DPC_GPU_AUX/DDC DPC_GPU_AUX#/DDC IFPC_AUX_I2CW_SCL BUFRST_N GND GND
27 DPC_GPU_AUX#/DDC G5 IFPC_AUX_I2CW_SDA_N K9 GND GND AC6
P4 IFPC_L0 VGA_THERMDN 22 K19 GND GND AC8
40 DPC_GPU_LANE_P0
TO DOCKING 40 DPC_GPU_LANE_N0
N4 IFPC_L0_N 1 L2 GND GND AC11

GENERAL
M5 IFPC_L1 THERMDN D8 L5 GND GND AC14
40 DPC_GPU_LANE_P1 @ CV37
40 DPC_GPU_LANE_N1 M4 IFPC_L1_N L11 GND GND AC17
L4 D9 100P_0402_50V8J~D L12 AC20
40 DPC_GPU_LANE_P2 IFPC_L2 THERMDP 2 GND GND
K4 IFPC_L2_N VGA_THERMDP 22 L13 GND GND AC23
40 DPC_GPU_LANE_N2
H4 IFPC_L3 L14 GND GND AC26
40 DPC_GPU_LANE_P3
J4 IFPC_L3_N L15 GND GND AF2
40 DPC_GPU_LANE_N3 STRAP4
STRAP4 N2 L16 GND GND AF5
DPD_GPU_AUX/DDC D3 F9 STRAP3
Fermi changed L17
M12
GND GND AF8
AF11
27 DPD_GPU_AUX/DDC DPD_GPU_AUX#/DDC IFPD_AUX_I2CX_SCL STRAP3 GND GND
27 DPD_GPU_AUX#/DDC D4 IFPD_AUX_I2CX_SDA_N M13 GND GND AF14
F5 IFPD_L0 M14 GND GND AF17
40 DPD_GPU_LANE_P0
40 DPD_GPU_LANE_N0 F4 IFPD_L0_N M15 GND GND AF20
C TO DOCKING 40 DPD_GPU_LANE_P1
E4
D5
IFPD_L1 ROM_CS_N B10 M16
P2
GND GND AF23
AF26 C
40 DPD_GPU_LANE_N1 IFPD_L1_N GND GND

SERIAL
C3 C9 ROM_SCLK_GPU P5 T16
40 DPD_GPU_LANE_P2 IFPD_L2 ROM_SCLK GND GND
C4 IFPD_L2_N P9 GND GND T15
40 DPD_GPU_LANE_N2 ROM_SI_GPU
40 DPD_GPU_LANE_P3 B3 IFPD_L3 ROM_SI A10 P19 GND GND T14
B4 IFPD_L3_N P23 GND GND F6
40 DPD_GPU_LANE_N3 ROM_SO_GPU
ROM_SO C10 P26 GND
T12 GND FB_CAL_PU_GND A15 1 2
TMDS_E_GPU_DDC F7 T13 RV42 40.2_0402_1%~D
26 TMDS_E_GPU_DDC TMDS_E_GPU_DDC# IFPE_AUX_I2CY_SCL GND
26 TMDS_E_GPU_DDC# G6 B16 1 2
IFPE_AUX_I2CY_SDA_N FB_CAL_TERM_GND RV43 60.4_0402_1%~D
D6
26 TMDSE_GPU_P2 IFPE_L0
C6 AB6 1 2 W16 F11 1 2
26 TMDSE_GPU_N2 IFPE_L0_N IFPAB_RSET @ RV32 1K_0402_1%~D GND_SENSE MULTI_STRAP_REF0_GND RV44 40.2K_0402_1%~D
TO MB HDMI 26 TMDSE_GPU_P1
A6
A7
IFPE_L1
R5 1 2 E14 F10 1 2
26 TMDSE_GPU_N1 IFPE_L1_N IFPC_RSET RV45 1K_0402_1%~D GND_SENSE MULTI_STRAP_REF1_GND RV46 40.2K_0402_1%~D
B6
26 TMDSE_GPU_P0 IFPE_L2
B7 M6 1 2
26 TMDSE_GPU_N0 IFPE_L2_N IFPD_RSET RV47 1K_0402_1%~D N12P-NS-S-A1_BGA533~D
E6
26 TMDSE_GPU_CLK IFPE_L3
E7 F8 1 2
26 TMDSE_GPU_CLK# IFPE_L3_N IFPE_RSET RV48 1K_0402_1%~D

N12P-NS-S-A1_BGA533~D 63 GPU_GND_SENSE

+3.3V_RUN_GFX
Decive ID change to 0x1056
10K_0402_1%~D
4.99K_0402_1%~D

10K_0402_1%~D
45.3K_0402_1%~D

45.3K_0402_1%~D

4.99K_0402_1%~D

34.8K_0402_1%~D
2

2
34.8K_0402_1%~D

set to multi-level straps


@ RV53

RV54
RV49

@ RV50

@ RV51

RV52

RV97

@ RV98

1 2 DPC_GPU_AUX/DDC
RV38 100K_0402_5%~D
1

B DPC_GPU_AUX#/DDC B
1 2
RV37 100K_0402_5%~D
STRAP0
STRAP1 1 2 DPD_GPU_AUX/DDC
STRAP2 RV35 100K_0402_5%~D
STRAP3 1 2 DPD_GPU_AUX#/DDC
STRAP4 RV36 100K_0402_5%~D
ROM_SCLK_GPU
ROM_SI_GPU RV39
15K_0402_1%~D
34.8K_0402_1%~D

10K_0402_1%~D

ROM_SO_GPU
4.99K_0402_1%~D

34.8K_0402_1%~D

2.2K_0402_5%~D
15K_0402_1%~D

20K_0402_1%~D
4.99K_0402_1%~D

1 2 TMDS_E_GPU_DDC
2

2
@ RV55

@ RV60
RV56

RV57

@ RV58

X76@ RV59

@ RV41

RV99

1 2 TMDS_E_GPU_DDC#
+3.3V_RUN_GFX
RV40
2.2K_0402_5%~D
1

Resistor Values Pull-up to +3V Pull-down to Gnd


5K 1000 0000
10K 1001 0001 ROM_SCLK PCIDEVID_EXT, SUB_VENDOR, SLOT_CLK, PEX_PLL_EN
** Hynix 64Mx16 DDR3 part stuff RV59=15K 15K 1010 0010
ROM_SI RAM_CFG[3:0]
Samsung 64Mx16 DDR3 part stuff RV59=20K 20K 1011 0011

Hynix 128Mx16 DDR3 part stuff RV59=35K 25K 1100 0100 ROM_SO XCLK_417, FB_0_BAR_SIZE, ALT_ADOOR, VGA_DEVICE
A Samsung 128Mx16 DDR3 part stuff RV59=45.3K 30K 1101 0101 A

35K 1110 0110


45K 1111 0111

STRAP0 USER[3:0]
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
STRAP1 3GIO_PADCFG_LUT_ADR[3:0] TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N12P DP, STRAP, GND
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
STRAP2 PCI_DEVID[3:0]

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 47 of 75
5 4 3 2 1
5 4 3 2 1

UV1D

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add for GB1b-64 +GPU_CORE J9
J10
VDD
VDD
Part 4 of 5
FBVDDQ
FBVDDQ
A13
B13
2.97A
Close to Pin C1747 to be close to the GPU
+1.5V_MEM_GFX

22U_0805_6.3VAM~D

22U_0805_6.3VAM~D

1U_0603_10V7K~D

1U_0603_10V7K~D

1U_0603_10V7K~D

4.7U_0603_6.3V6K~D

4.7U_0603_6.3V6K~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

10U_0805_6.3V6M~D
J12 VDD FBVDDQ C13
1 1 1 1 1 J13 VDD FBVDDQ D13 1 1 1 1 1 1

CV164

CV163

CV162

CV161

CV160

@CV159
@

@CV44
@

CV38

CV45

CV46

CV47

CV48

CV39
1 1 L9 VDD FBVDDQ D14

CV159

CV44
M9 VDD FBVDDQ E13
M11 VDD FBVDDQ F13
2 2 2 2 2 2 2 2 2 2 2
2 2
M17 VDD FBVDDQ F14 N10M SPEC FBVDDQ TYP. 1.8V.
N9 VDD FBVDDQ F15
N11 VDD FBVDDQ F16
N12 F17
VDD FBVDDQ
N13 F19
VDD FBVDDQ
N14 F22 +1.5V_MEM_GFX
VDD FBVDDQ

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

10U_0805_6.3V6M~D
D NV DG for VDD Cap: D
N15 H23
VDD FBVDDQ

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D

0.022U_0402_16V7K~D
0.022uF 10% X7R x5 N16 H26 1 1 1 1 1 1
VDD FBVDDQ

CV52

CV53

CV54

CV55

@ CV56

CV57
N17 J15
0.1uF 10% X7R x5 N19
VDD FBVDDQ
J16
1 1 1 1 1 1 1 VDD FBVDDQ
1uF 10% X7R x3

CV49

CV40

CV50

CV41

CV51

CV42

CV43
P11 J18
VDD FBVDDQ 2 2 2 2 2 2
22uF 10% X5R x2 P12
VDD FBVDDQ
J19
P13 L19
2 2 2 2 2 2 2 VDD FBVDDQ
P14 L23
VDD FBVDDQ
P15 L26
VDD FBVDDQ
P16 M19
VDD FBVDDQ +1.05V_RUN_VTT_GFX
P17 N22
VDD FBVDDQ
R9 VDD FBVDDQ U22
R11 Y22

POWER
VDD FBVDDQ

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

10U_0805_4VAM~D

22U_0805_6.3VAM~D
R12 VDD
R13 VDD PEX_IOVDDQ AG6
R14 VDD PEX_IOVDDQ AF6 1 1 1 1 1 1 1

CV61

CV62

CV63

CV64

CV65

CV66

CV67
R15 AE6
under GPU 1 1 1 VDD PEX_IOVDDQ

CV58

CV59

CV60
R16 VDD PEX_IOVDDQ AD6
R17 VDD PEX_IOVDDQ AC13
2 2 2 2 2 2 2
T9 VDD PEX_IOVDDQ AC7
2 2 2
T11 AB17
T17
VDD 2A PEX_IOVDDQ
AB16
VDD PEX_IOVDDQ
U9 VDD PEX_IOVDDQ AB13
U19 AB9 +1.05V_RUN_VTT_GFX
+3.3V_RUN_GFX LV1 220R 100MHZ W9
VDD PEX_IOVDDQ
AB8
PLACE CLOSE TO BALL PLACE NEAR GPU
BLM18PG221SN1D_2P~D VDD PEX_IOVDDQ
W10 VDD PEX_IOVDDQ AB7

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

22U_0805_6.3VAM~D

10U_0805_4VAM~D
1 2 +3.3V_RUN_VDD33 W12 VDD
W13 VDD PEX_IOVDD AG7 1 1 1 1 1 1 1
4.7U_0603_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

CV70

CV71

CV72

CV73

CV77

CV78

CV79
W18 VDD PEX_IOVDD AF7
1 1 1 1 1 W19 VDD PEX_IOVDD AE7
AD8
2A PEX_IOVDD 2 2 2 2 2 2 2
CV74

CV75

CV68

CV76

CV69
AD7
C 120mA A12
PEX_IOVDD
AC9 C
2 2 2 2 2 VDD33 PEX_IOVDD
B12 VDD33
C12 VDD33 PEX_PLLVDD AF9 +PEX_PLLVDD
D12 VDD33
E12 K6 +PLLVDD
F12
VDD33 VID_PLLVDD 45mA
+3.3V_RUN_GFX 1 2
VDD33
L6
45mA 120mA
@ RV30 0_0402_5%~D SP_PLLVDD
1 2 +PEX_SVDD_3V3 120mA AG9 K5
60mA
+1.05V_RUN_VTT_GFX
@ RV31 0_0402_5%~D PEX_SVDD_3V3 PLLVDD
20 mil
PLACE NEAR GPU LV2
4.7U_0603_6.3V6K~D

0.1U_0402_16V4Z~D

R19 +FB_AVDD 2 1
1 1 150mA FB_PLLAVDD +1.05V_RUN_VTT_GFX
CV80

CV81

0.1U_0402_10V7K~D
V3
IFPA_IOVDD 100mA

1U_0603_10V7K~D

10U_0805_4VAM~D
AC19 BLM18PG300SN1D_2P~D
150mA FB_PLLAVDD 1

CV83
+IFPAB_IOVDD V2 1 30R 100MHZ
2 2 IFPB_IOVDD

CV165

CV82
285mA FB_DLLAVDD
T19 100mA
J6

2
IFPCD_IOVDD 2
285mA +IFPCDE_IOVDD H6 AG2 +DACA_VDD 2
IFPE_IOVDD DACA_VDD
285mA W5 1 2
+IFPAB_PLLVDD DACB_VDD RV63 10K_0402_5%~D
AD5
220mA IFPAB_PLLVDD
add for GB1b-64
+IFPCD_PLLVDD P6 B15 +1.5V_MEM_VDDQ 2 1
220mA IFPC_PLLVDD FB_CAL_PD_VDDQ RV65 40.2_0402_1%~D
+1.5V_MEM_GFX
N6 W15
220mA IFPD_PLLVDD VDD_SENSE GPU_VDD_SENSE 63
+IFPE_PLLVDD D7 E15
+1.8V_RUN_GFX 220R 100MHZ 285mA 220mA IFPE_PLLVDD VDD_SENSE
route as 50ohm
LV11 BLM18PG221SN1D_2P~D
2 1 +IFPAB_IOVDD N12P-NS-S-A1_BGA533~D
1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

B B
1 1 1 1 1 1
CV175

CV166

CV174

CV170

+1.05V_RUN_VTT_GFX
CV173

CV172

+1.05V_RUN_VTT_GFX 120mAadd for GB1b-64


LV4
2 2 2 2 2 2 LV3 BLM18AG121SN1D_0603~D
BLM18PG221SN1D_2P~D 150mA , 10mil +PEX_PLLVDD 2 1
+3.3V_RUN_GFX 2 1 +PLLVDD

0.1U_0402_10V7K~D

1U_0603_10V7K~D

4.7U_0805_10V7K~D

4.7U_0603_6.3V6K~D
LV6
220mA
1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

22U_0603_6.3V6M~D

10U_0805_6.3V7K
MMZ1608D301BT_0603 1 1 1 1

1
CV84

@ CV181

CV90

CV91
1 2 +IFPCD_PLLVDD 1 1 1 1 1 1
4.7U_0603_6.3V6K~D

CV89

CV87

CV88

CV179

CV180

CV92

CV93
+1.05V_RUN_VTT_GFX 220R 100MHZ 285mA
4.7U_0805_10V7K~D

1U_0603_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2
LV9 BLM18PG221SN1D_2P~D 2 2 2 2
1 1 1 1 1
1

2 2 2 2 2 2
CV94

CV97

CV98

CV99

2 1 +IFPCDE_IOVDD
CV95

CV96
1U_0402_6.3V6K~D

4.7U_0603_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

2 2 2 2 2
1 1 1 1 1 1
CV119

CV121

CV122

CV123

+3.3V_RUN_GFX
CV118

CV120

2 2 2 2 2 2
add for GB1b-64 120mA
300ohm 100MHz ESR0.25ohm
LV7
add for GB1b-64 add for GB1b-64 MMZ1608D301BT_0603
+DACA_VDD 1 2

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

4.7U_0603_6.3V6K~D
4.7U_0805_10V7K~D
+3.3V_RUN_GFX
220mA 1 1 1 1 1 1 1

CV107

CV109

CV110

CV108

CV112

CV114
LV5

CV113
MMZ1608D301BT_0603
+1.05V_RUN_VTT_GFX 1 2 +IFPE_PLLVDD
LV10 285mA 2 2 2 2 2 2 2
4.7U_0603_6.3V6K~D

4.7U_0805_10V7K~D

1U_0603_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

BLM18AG121SN1D_0603~D
A +IFPAB_PLLVDD A
2 1 1 1 1 1 1
1
CV101

CV104

CV105

CV106
1U_0402_6.3V6K~D

4.7U_0805_10V7K~D

1U_0603_10V7K~D

0.1U_0402_10V7K~D

CV102

CV103

1 1 1
2
1

2 2 2 2 2
CV167
CV169

CV171

CV168
2

2 2 2
add for GB1b-64 Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
add for GB1b-64 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N12P Power
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 48 of 75
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
FBAD[0..63]
FBAD[0..63] 50,51
FBA_CMD[0..30]
FBA_CMD[0..30] 50,51
DQMA#[0..7]
DQMA#[0..7] 50,51
+1.8V_RUN_GFX Source
DQSA_RN[0..7]
DQSA_RN[0..7] 50,51 +1.8V_RUN +1.8V_RUN_GFX
DQSA_WP[0..7] QV7
DQSA_WP[0..7] 50,51 PMV45EN_SOT23-3~D

D D
1 3

10U_0805_6.3V6M~D
1

1
20K_0402_5%~D
UV1B
Mode E - Mirror Mode Mapping

CV187

RV96
Part 2 of 5

G
2
FBAD0 D22 G24 FBA_CMD0 1.05V_RUN_VTT_GFX#_EN 1 2 1.05V_RUN_VTT_GFX#_EN_R
FBAD1 FBA_D0 FBA_CMD0 FBA_CMD1 2
E24
FBA_D1 FBA_CMD1
F27 PAD~D TV6@ DATA Bus RV95 0_0402_5%~D
FBAD2 E22 F25 FBA_CMD2

2
FBAD3 FBA_D2 FBA_CMD2 FBA_CMD3
D24
FBA_D3 FBA_CMD3
F26 Address 0..31 32..63
FBA_CMD3 FBAD4 D26 G26 FBA_CMD4
FBAD5 FBA_D4 FBA_CMD4 FBA_CMD5
D27
FBA_D5 FBA_CMD5
G27 CMD0 ODT_L
1
10K_0402_5%~D

FBAD6 C27 G25 FBA_CMD6


FBA_D6 FBA_CMD6
RV66

CKE_1 FBAD7 B27 J25 FBA_CMD7 CMD1 CS1#_L


FBAD8 FBA_D7 FBA_CMD7 FBA_CMD8
A21 FBA_D8 FBA_CMD8 J24
FBAD9 B21 H24 FBA_CMD9 CMD2 CS0#_L
FBAD10 C21
FBA_D9 FBA_CMD9
H22 FBA_CMD10 +3.3V_RUN_GFX Source
2

FBAD11 FBA_D10 FBA_CMD10 FBA_CMD11


C19 FBA_D11 FBA_CMD11 J26 CMD3 CKE_L
FBAD12 C18 G22 FBA_CMD12
FBAD13 FBA_D12 FBA_CMD12 FBA_CMD13
D18 FBA_D13 FBA_CMD13 G23 CMD4 A9 A11
FBAD14 B18 J22 FBA_CMD14 +15V_ALW +3.3V_ALW QV5 +3.3V_RUN_GFX
FBAD15 FBA_D14 FBA_CMD14 FBA_CMD15
C16 FBA_D15 FBA_CMD15 J27 CMD5 A6 A7 +3.3V_ALW2 SI3456DDV-T1-GE3_TSOP6~D
FBA_CMD19 FBAD16 E21 M24 FBA_CMD16
FBA_D16 FBA_CMD16

D
FBAD17 F21 L24 FBA_CMD17 PAD~D TV5@ CMD6 A3 BA1 6

S
FBA_D17 FBA_CMD17
1

1
10K_0402_5%~D

FBAD18 D20 J23 FBA_CMD18 5 4


FBA_D18 FBA_CMD18

1
RV68

20K_0402_5%~D
FBAD19 F20 K23 FBA_CMD19 CMD7 A0 A12 2
FBA_D19 FBA_CMD19

1
10U_0805_6.3V6M~D
ODT_2 FBAD20 D17 K22 FBA_CMD20 RV92 RV91 1 1
FBA_D20 FBA_CMD20

RV90
FBAD21 F18 M23 FBA_CMD21 CMD8 A8 A8 100K_0402_5%~D 100K_0402_5%~D

G
FBA_D21 FBA_CMD21

CV185
FBAD22 D16 K24 FBA_CMD22
2

3
FBAD23 FBA_D22 FBA_CMD22 FBA_CMD23 3.3V_RUN_GFX_EN
E16 M27 CMD9 A12 A0

2
FBAD24 FBA_D23 FBA_CMD23 FBA_CMD24 2
A22 N27

2
FBA_D24 FBA_CMD24

3300P_0402_50V7K~D
FBAD25 C24 M26 FBA_CMD25 CMD10 A1 A2
FBA_D25 FBA_CMD25

MEMORY INTERFACE
FBAD26 D21 K26 FBA_CMD26
FBAD27 FBA_D26 FBA_CMD26 FBA_CMD27
B22 FBA_D27 FBA_CMD27 K27 CMD11 RAS# RAS# QV6B 1

CV186
C FBAD28 FBA_CMD28 3.3V_RUN_GFX_ON# 5 DMN66D0LDW-7_SOT363-6~D C
C22 FBA_D28 FBA_CMD28 K25
FBA_CMD0 FBAD29 A25 M25 FBA_CMD29 CMD12 A13 A14
FBA_D29 FBA_CMD29

6
FBAD30 B25 L22 FBA_CMD30

4
FBA_D30 FBA_CMD30
1

2
10K_0402_5%~D

FBAD31 A26 CMD13 BA1 A3 QV6A


FBA_D31
RV71

FBAD32 U24 C26 DQMA#0 DMN66D0LDW-7_SOT363-6~D


FBAD33 FBA_D32 FBA_DQM0 DQMA#1
ODT_1 V24 FBA_D33 FBA_DQM1 B19 CMD14 A14 A13 15,41 3.3V_RUN_GFX_ON 2
FBAD34 V23 D19 DQMA#2
FBAD35 FBA_D34 FBA_DQM2 DQMA#3
R24 D23 CMD15 CAS# CAS#
2

1
FBAD36 FBA_D35 FBA_DQM3 DQMA#4
T23 T24
FBAD37 FBA_D36 FBA_DQM4 DQMA#5
R23
FBA_D37 FBA_DQM5
AA23 CMD16 CKE_H
FBAD38 P24 AB27 DQMA#6
FBAD39 FBA_D38 FBA_DQM6 DQMA#7
P22
FBA_D39 FBA_DQM7
T26 CMD17 CS1#_H
FBAD40 AC24
FBAD41 AB23
FBA_D40
D25 DQSA_RN0 CMD18 CS0#_H +1.5V_MEM_GFX Source
FBA_CMD16 FBAD42 FBA_D41 FBA_DQS_RN0 DQSA_RN1
AB24 A18
FBAD43 FBA_D42 FBA_DQS_RN1 DQSA_RN2
W24
FBA_D43 FBA_DQS_RN2
E18 CMD19 ODT_H +3.3V_ALW2 +15V_ALW +1.5V_MEM QV1
1
10K_0402_5%~D

100K_0402_5%~D
FBAD44 AA22 B24 DQSA_RN3 SI4164DY-T1-GE3_SO8~D +1.5V_MEM_GFX
FBA_D44 FBA_DQS_RN3
RV72

FBAD45 W23 R22 DQSA_RN4 CMD20 RST RST 8 1


FBA_D45 FBA_DQS_RN4

1
CKE_2 FBAD46 W22 Y24 DQSA_RN5 7 2
FBA_D46 FBA_DQS_RN5

RV67
FBAD47 V22 AA27 DQSA_RN6 CMD21 A7 A6 6 3
FBA_D47 FBA_DQS_RN6

1
100K_0402_5%~D

10U_0805_6.3V6M~D

20K_0402_5%~D
FBAD48 AA25 R27 DQSA_RN7 5 1
2

FBA_D48 FBA_DQS_RN7

RV69

RV70
FBAD49 W27 CMD22 A4 A5
FBA_D49

CV124
FBAD50 W26 C25 DQSA_WP0

4
FBAD51 FBA_D50 FBA_DQS_WP0 DQSA_WP1 GFX_MEM_VTT_EN
W25
FBA_D51 FBA_DQS_WP1
A19 CMD23 A11 A9 2
FBAD52 AB25 E19 DQSA_WP2

2
FBA_D52 FBA_DQS_WP2

3
DMN66D0LDW-7_SOT363-6~D
FBAD53 AB26 A24 DQSA_WP3 CMD24 A2 A1
FBA_D53 FBA_DQS_WP3

2200P_0402_50V7K~D
FBAD54 AD26 T22 DQSA_WP4
FBA_D54 FBA_DQS_WP4

QV2B
FBA_CMD20 FBAD55 AD27 AA24 DQSA_WP5 CMD25 A10 WE#
FBAD56 FBA_D55 FBA_DQS_WP5 DQSA_WP6 GFX_MEM_VTT_ON# 5
V25 AA26 1
FBA_D56 FBA_DQS_WP6
1
10K_0402_5%~D

FBAD57 R25 T27 DQSA_WP7 CMD26 A5 A4


FBA_D57 FBA_DQS_WP7
RV75

CV125
FBAD58 V26

4
FBAD59 FBA_D58 +FB_VREF
RST V27
FBA_D59 FB_VREF
A16 CMD27 BA2 A15

6
2

DMN66D0LDW-7_SOT363-6~D
B FBAD60 B
R26
FBA_D60

QV2A
FBAD61 T25 F24 CMD28 WE# A10
CLKA0 50
2

FBAD62 FBA_D61 FBA_CLK0


N25 F23 CLKA0# 50
FBAD63 FBA_D62 FBA_CLK0_N
N26
FBA_D63 CMD29 BA0 BA0 41 GFX_MEM_VTT_ON 2
N24 CLKA1 51
FBA_CLK1
N23 CLKA1# 51 CMD30 A15 BA2

1
FBA_CLK1_N
M22 1 2 +1.5V_MEM_GFX
FBA_DEBUG RV76 10K_0402_5%~D

N12P-NS-S-A1_BGA533~D
+1.5V_MEM_GFX +1.05V_RUN_VTT_GFX Source
1.1K_0402_1%~D 1.1K_0402_1%~D

+15V_ALW +1.05V_M
1 @ RV77

QV3 +1.05V_RUN_VTT_GFX

100K_0402_5%~D
SI4164DY-T1-GE3_SO8~D

1
8 1

RV73

10U_0805_6.3V6M~D
16mil 7 2

1
20K_0402_5%~D
6 3 1
2

RV74
+FB_VREF 5

CV126
2
1 @ RV78

0.01U_0402_25V7K~D

4
2
@CV128
@

2
CV128

1.05V_RUN_VTT_GFX#_EN
2

SSM3K7002FU_SC70-3~D

2200P_0402_50V7K~D
2

1
D
1

QV4

CV127
2
G
S

3
2
A A

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, N12P Memory
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 49 of 75
5 4 3 2 1
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Memory Partition A - Lower 32 bits
change to Hynix
FBA_CMD[0..30]
FBA_CMD[0..30] 49,51
FBAD[0..63]
FBAD[0..63] 49,51
DQMA#[0..7]
DQMA#[0..7] 49,51
DQSA_RN[0..7]
DQSA_RN[0..7] 49,51
DQSA_WP[0..7]
D DQSA_WP[0..7] 49,51 D

UV4 X76@ UV3 X76@


+1.5V_MEM_GFX 16mil FBAD1 FBAD30
DQL0
E3
F7 FBAD6 16mil DQL0
E3
F7 FBAD24
DQL1 FBAD3 DQL1 FBAD31
F2 F2
DQL2 DQL2
1
1.1K_0402_1%~D

FBA_CMD7 N3 F8 FBAD4 FBA_CMD7 N3 F8 FBAD28


A0 DQL3 A0 DQL3
RV80

FBA_CMD10 P7 H3 FBAD0 Group0 FBA_CMD10 P7 H3 FBAD29 Group3


FBA_CMD24 A1 DQL4 FBAD5 FBA_CMD24 A1 DQL4 FBAD26
P3 H8 P3 H8
FBA_CMD6 A2 DQL5 FBAD2 FBA_CMD6 A2 DQL5 FBAD25
N2 G2 N2 G2
FBA_CMD22 A3 DQL6 FBAD7 FBA_CMD22 A3 DQL6 FBAD27
P8 H7 P8 H7
2

FBA_CMD26 A4 DQL7 FBA_CMD26 A4 DQL7


FBA_CMD5
P2
R8
A5
A6
FBA_CMD5
P2
R8
A5
A6
Mode E - Mirror Mode Mapping
+FBA_VREF0 FBA_CMD21 R2 D7 FBAD17 FBA_CMD21 R2 D7 FBAD14
FBA_CMD8 A7 DQU0 FBAD21 FBA_CMD8 A7 DQU0 FBAD10
T8 A8 DQU1 C3 T8 A8 DQU1 C3 DATA Bus
1.1K_0402_1%~D

0.01U_0402_25V7K~D

FBA_CMD4 R3 C8 FBAD19 FBA_CMD4 R3 C8 FBAD15


FBA_CMD25 A9 DQU2 FBAD20 FBA_CMD25 A9 DQU2 FBAD11
1 L7 A10/AP DQU3 C2 Group2 L7 A10/AP DQU3 C2 Address 0..31 32..63
1

RV79

CV129

FBA_CMD23 R7 A7 FBAD18 FBA_CMD23 R7 A7 FBAD12 Group1


FBA_CMD9 A11 DQU4 FBAD22 FBA_CMD9 A11 DQU4 FBAD8
N7 A12/BC# DQU5 A2 N7 A12/BC# DQU5 A2 CMD0 ODT_L
FBA_CMD12 T3 B8 FBAD16 FBA_CMD12 T3 B8 FBAD13
2 FBA_CMD30 A13 DQU6 FBAD23 FBA_CMD30 A13 DQU6 FBAD9
M7 A15 DQU7 A3 M7 A15 DQU7 A3 CMD1 CS1#_L
2

+1.5V_MEM_GFX +1.5V_MEM_GFX CMD2 CS0#_L


FBA_CMD29 M2 B2 FBA_CMD29 M2 B2 CMD3 CKE_L
FBA_CMD13 BA0 VDD FBA_CMD13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
FBA_CMD27 M3 G7 FBA_CMD27 M3 G7 CMD4 A9 A11
BA2 VDD BA2 VDD
VDD K2 VDD K2
CLKA0 K8 K8 CMD5 A6 A7
VDD VDD
VDD N1 VDD N1
J7 N9 CLKA0 J7 N9 CMD6 A3 BA1
49 CLKA0 CK VDD CK VDD
2

C CLKA0# C
49 CLKA0# K7 CK# VDD R1 K7 CK# VDD R1
RV81 FBA_CMD3 K9 R9 FBA_CMD3 K9 R9 CMD7 A0 A12
160_0402_1%~D CKE VDD CKE VDD
CMD8 A8 A8
FBA_CMD0 K1 A1 FBA_CMD0 K1 A1
1

FBA_CMD11 ODT VDDQ FBA_CMD11 ODT VDDQ


J3 RAS# VDDQ A8 J3 RAS# VDDQ A8 CMD9 A12 A0
CLKA0# FBA_CMD2 L2 C1 FBA_CMD2 L2 C1
FBA_CMD15 CS# VDDQ FBA_CMD15 CS# VDDQ
K3
CAS# VDDQ
C9 K3
CAS# VDDQ
C9 CMD10 A1 A2
FBA_CMD28 L3 D2 FBA_CMD28 L3 D2
WE# VDDQ WE# VDDQ
VDDQ
E9
VDDQ
E9 CMD11 RAS# RAS#
F1 F1
DQSA_WP0 VDDQ DQSA_WP3 VDDQ
F3
DQSL VDDQ
H2 F3
DQSL VDDQ
H2 CMD12 A13 A14
DQSA_WP2 C7 H9 DQSA_WP1 C7 H9
DQSU VDDQ DQSU VDDQ
CMD13 BA1 A3
DQMA#0 E7 A9 DQMA#3 E7 A9 CMD14 A14 A13
DQMA#2 DML VSS DQMA#1 DML VSS
D3 B3 D3 B3
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD15 CAS# CAS#
G8 G8
DQSA_RN0 VSS DQSA_RN3 VSS
G3
DQSL VSS
J2 G3
DQSL VSS
J2 CMD16 CKE_H
DQSA_RN2 B7 J8 DQSA_RN1 B7 J8
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD17 CS1#_H
M9 M9
VSS VSS
VSS
P1
VSS
P1 CMD18 CS0#_H
FBA_CMD20 T2 P9 FBA_CMD20 T2 P9
RESET VSS RESET VSS
VSS
T1
VSS
T1 CMD19 ODT_H
L8 T9 L8 T9
ZQ VSS ZQ VSS
CMD20 RST RST
1

1
243_0402_1%~D

+FBA_VREF0 M8 B1 +FBA_VREF0 M8 B1 CMD21 A7 A6


VREFCA VSSQ VREFCA VSSQ

243_0402_1%~D
H1 B9 H1 B9
VREFDQ VSSQ VREFDQ VSSQ
RV82

RV83
B VSSQ
D1
VSSQ
D1 CMD22 A4 A5 B
D8 D8
VSSQ VSSQ
E2 E2 CMD23 A11 A9
2

2
VSSQ VSSQ
J1 E8 J1 E8
NC VSSQ NC VSSQ
J9
NC VSSQ
F9 J9
NC VSSQ
F9 CMD24 A2 A1
L1 G1 L1 G1
NC VSSQ NC VSSQ
L9
NC VSSQ
G9 L9
NC VSSQ
G9 CMD25 A10 WE#
T7 T7
NC NC
96-BALL 96-BALL CMD26 A5 A4
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-12C_FBGA96~D H5TQ2G63BFR-12C_FBGA96~D CMD27 BA2 A15
CMD28 WE# A10
+1.5V_MEM_GFX CMD29 BA0 BA0
+1.5V_MEM_GFX
CMD30 A15 BA2
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CV139

CV140

CV141

CV142

CV143
CV176

CV177

CV130

CV131

CV132

CV133

CV134

CV135

CV136

CV178

CV188

CV137

CV138

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VRAM A Lower
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

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PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 50 of 75
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Memory Partition A - Upper 32 bits

FBAD[0..63]
FBAD[0..63] 49,50
FBA_CMD[0..30]
FBA_CMD[0..30] 49,50
D DQMA#[0..7] D
DQMA#[0..7] 49,50
DQSA_RN[0..7]
DQSA_RN[0..7] 49,50
DQSA_WP[0..7]
DQSA_WP[0..7] 49,50
UV5 X76@ UV6 X76@
16mil
FBAD35 FBAD61
16mil DQL0
E3
F7 FBAD32 DQL0
E3
F7 FBAD57
DQL1 FBAD38 DQL1 FBAD58
F2 F2
FBA_CMD9 DQL2 FBAD33 FBA_CMD9 DQL2 FBAD60
+1.5V_MEM_GFX
N3
A0 DQL3
F8 Group4 N3
A0 DQL3
F8
FBA_CMD24 P7 H3 FBAD37 FBA_CMD24 P7 H3 FBAD56 Group7
FBA_CMD10 A1 DQL4 FBAD34 FBA_CMD10 A1 DQL4 FBAD62
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1%~D

FBA_CMD13 N2 G2 FBAD39 FBA_CMD13 N2 G2 FBAD59


FBA_CMD26 A3 DQL6 FBAD36 FBA_CMD26 A3 DQL6 FBAD63
P8 A4 DQL7 H7 P8 A4 DQL7 H7
1

RV84

FBA_CMD22 P2 FBA_CMD22 P2
FBA_CMD21 A5 FBA_CMD21 A5
FBA_CMD5
R8
R2
A6
A7 DQU0 D7 FBAD42 FBA_CMD5
R8
R2
A6
A7 DQU0 D7 FBAD51 Mode E - Mirror Mode Mapping
FBA_CMD8 T8 C3 FBAD46 FBA_CMD8 T8 C3 FBAD52
FBA_CMD23 A8 DQU1 FBAD40 FBA_CMD23 A8 DQU1 FBAD49
R3 C8 R3 C8 Group6 DATA Bus
2

+FBA_VREF1 FBA_CMD28 A9 DQU2 FBAD45 FBA_CMD28 A9 DQU2 FBAD53


L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
FBA_CMD4 R7 A7 FBAD44 Group5 FBA_CMD4 R7 A7 FBAD48 Address 0..31 32..63
A11 DQU4 A11 DQU4
1.1K_0402_1%~D

0.01U_0402_25V7K~D

FBA_CMD7 N7 A2 FBAD43 FBA_CMD7 N7 A2 FBAD54


A12/BC# DQU5 A12/BC# DQU5
1

1 FBA_CMD14 T3 B8 FBAD41 FBA_CMD14 T3 B8 FBAD50 CMD0 ODT_L


A13 DQU6 A13 DQU6
RV85

CV144

FBA_CMD27 M7 A3 FBAD47 FBA_CMD27 M7 A3 FBAD55


A15 DQU7 A15 DQU7
+1.5V_MEM_GFX +1.5V_MEM_GFX
CMD1 CS1#_L
2 CMD2 CS0#_L
2

FBA_CMD29 M2 B2 FBA_CMD29 M2 B2
FBA_CMD6 BA0 VDD FBA_CMD6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD3 CKE_L
FBA_CMD30 M3 G7 FBA_CMD30 M3 G7
BA2 VDD BA2 VDD
C VDD K2 VDD K2 CMD4 A9 A11 C
VDD K8 VDD K8
VDD N1 VDD N1 CMD5 A6 A7
J7 N9 CLKA1 J7 N9
49 CLKA1 CK VDD CLKA1# CK VDD
49 CLKA1# K7 CK# VDD R1 K7 CK# VDD R1 CMD6 A3 BA1
FBA_CMD16 K9 R9 FBA_CMD16 K9 R9
CLKA1 CKE VDD CKE VDD
CMD7 A0 A12
FBA_CMD19 K1 A1 FBA_CMD19 K1 A1 CMD8 A8 A8
ODT VDDQ ODT VDDQ
2

FBA_CMD11 J3 A8 FBA_CMD11 J3 A8
FBA_CMD18 RAS# VDDQ FBA_CMD18 RAS# VDDQ
RV86
160_0402_1%~D
L2
CS# VDDQ
C1 L2
CS# VDDQ
C1 CMD9 A12 A0
FBA_CMD15 K3 C9 FBA_CMD15 K3 C9
FBA_CMD25 CAS# VDDQ FBA_CMD25 CAS# VDDQ
L3
WE# VDDQ
D2 L3
WE# VDDQ
D2 CMD10 A1 A2
E9 E9
1

VDDQ VDDQ
VDDQ
F1
VDDQ
F1 CMD11 RAS# RAS#
CLKA1# DQSA_WP4 F3 H2 DQSA_WP7 F3 H2
DQSA_WP5 DQSL VDDQ DQSA_WP6 DQSL VDDQ
C7
DQSU VDDQ
H9 C7
DQSU VDDQ
H9 CMD12 A13 A14
CMD13 BA1 A3
DQMA#4 E7 A9 DQMA#7 E7 A9
DQMA#5 DML VSS DQMA#6 DML VSS
D3
DMU VSS
B3 D3
DMU VSS
B3 CMD14 A14 A13
E1 E1
VSS VSS
VSS
G8
VSS
G8 CMD15 CAS# CAS#
DQSA_RN4 G3 J2 DQSA_RN7 G3 J2
DQSA_RN5 DQSL VSS DQSA_RN6 DQSL VSS
B7
DQSU VSS
J8 B7
DQSU VSS
J8 CMD16 CKE_H
M1 M1
VSS VSS
VSS
M9
VSS
M9 CMD17 CS1#_H
P1 P1
FBA_CMD20 VSS FBA_CMD20 VSS
T2 RESET VSS
P9 T2 RESET VSS
P9 CMD18 CS0#_H
T1 T1
VSS VSS
L8
ZQ VSS
T9 L8
ZQ VSS
T9 CMD19 ODT_H

1
CMD20 RST RST
1
243_0402_1%~D

243_0402_1%~D
B +FBA_VREF1 +FBA_VREF1 B
M8 B1 M8 B1
VREFCA VSSQ VREFCA VSSQ
RV87

RV88
H1
VREFDQ VSSQ
B9 H1
VREFDQ VSSQ
B9 CMD21 A7 A6
D1 D1
VSSQ VSSQ
D8 D8 CMD22 A4 A5

2
VSSQ VSSQ
E2 E2
2

VSSQ VSSQ
J1
NC VSSQ
E8 J1
NC VSSQ
E8 CMD23 A11 A9
J9 F9 J9 F9
NC VSSQ NC VSSQ
L1
NC VSSQ
G1 L1
NC VSSQ
G1 CMD24 A2 A1
L9 G9 L9 G9
NC VSSQ NC VSSQ
T7
NC
T7
NC CMD25 A10 WE#
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD26 A5 A4
H5TQ2G63BFR-12C_FBGA96~D H5TQ2G63BFR-12C_FBGA96~D
CMD27 BA2 A15
+1.5V_MEM_GFX +1.5V_MEM_GFX CMD28 WE# A10
CMD29 BA0 BA0
CMD30 A15 BA2
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV148

CV149

CV150

CV151

CV154

CV155

CV156

CV157

CV158
CV189

CV190

CV145

CV146

CV147

CV191

CV192

CV152

CV153

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Compal Electronics, Inc.


PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VRAM A Upper
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev

WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 1.0
LA-6592P
Date: Thursday, January 13, 2011 Sheet 51 of 75
5 4 3 2 1
5 4 3 2 1

+3.3V_ALW

WWW.AliSaler.Com ESD Diodes +COINCELL


COIN RTC Battery

DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

1
PR1
1K_0402_5%~D

PD33

PD34

PD32
PL21 +3.3V_ALW
@ @ @ FBMJ4516HS720NT_2P~D
1 2 +3.3V_RTC_LDO

2
Media Bay Battery Connector

1
JRTC1

Z4012
1
PJP36 +COINCELL 1 3

100K_0402_5%~D
MBATT+_C 1 G
2 1 MPBATT+ 2 4
MBATT1 PR501 2 G

PR504
0.1U_0603_25V7K~D
1
D D
1 100_0402_5%~D PR502 PAD-OPEN 2x2m~D TYCO_2-1775293-2~D
1

2
Z5304 100_0402_5%~D PR503

PC302
2 1 2 BAY_SMBCLK 45

2
2 Z5305 100_0402_5%~D +RTC_CELL
3 1 2 BAY_SMBDAT 45

2
3 Z5306
4 1 2 MODULE_BATT_PRES#
2200P_0402_50V7K~D

4
5
5
6 44
6
1
PC301

1
7 PD1
GND RB715FGT106_UMD3
8 1
2

GND PC1
1U_0603_10V4Z~D
SUYIN_150010GR006M500ZR +3.3V_ALW
2
Move to power schematic
ESD Diodes
GND
PL22
FBMJ4516HS720NT_2P~D
DA204U_SOT323~D

DA204U_SOT323~D

DA204U_SOT323~D
3

2
1 2
PD2

PD3

PD4
PL1 +3.3V_ALW
@ @ @ FBMJ4516HS720NT_2P~D
1 2
Primary Battery Connector
1

1
PJP43

100K_0402_5%~D
PBATT+_C 1 2 PBATT+

PR2
11

0.1U_0603_25V7K~D
GND

1
10 PAD-OPEN 4x4m
GND

PC2
9 PR4

2
9 100_0402_5%~D PR3
8

2
8 Z4304 100_0402_5%~D PR5
7 1 2 PBAT_SMBCLK <43>
2200P_0402_50V7K~D

7 Z4305 100_0402_5%~D
6 1 2 PBAT_SMBDAT <43>
6 Z4306
5 1 2 PBAT_PRES# <42,63>
5
1
PC3

4
4 @ PQ1
3
3
C 2 C
2

2 FDN338P_G_NL_SOT23-3~D
1
1 @ PD5
1 2 1 3

3
DOCK_SMB_ALERT# <41,42,63>
PBATT1
SUYIN_200275MR009G50PZR RB751V-40GTE-17_SOD323~D

2
2
@ PR6
GND 1 2
<41,42,63> SLICE_BAT_PRES#
0_0402_5%~D

@
PC4
1500P_0402_7K~D

2
+5V_ALW
+3.3V_ALW

DA204UGT106_SOT323~D
3

2
PD6
@ PR7 PU1

2.2K_0402_5%~D
2
1 2 GND <41> DOCK_PSID 1 6 GPIO_PSID_SELECT <42>
0_0402_5%~D NO IN

PR8
2 5 +5V_ALW
PL2 PR9 GND V+

1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D

S
NC COM PS_ID <43>
PQ2 TS5A63157DCKR_SC70-6~D
100K_0402_1%~D
2

FDV301N_G_NL_SOT23-3~D +5V_ALW
G
2

+5V_ALW
PR10

+5V_ALW

DA204U_SOT323~D
2

2
B B

10K_0402_1%~D
DA204U_SOT323~D

1
C
PQ3

PD8
PR11
2
3

B
PD9

MMST3904-7-F_SOT323~D
E @
15K_0402_1%~D

3
2

@
1

1
@ PD7
PR12

SM24_SOT23 PR13
GND 1 2
1

PSID_DISABLE# <42>
1

@ 10K_0402_5%~D
@ PR14
1 2 DCIN_CBL_DET# <42>
0_0402_5%~D
.47U_0402_6.3V6-K~D

DC_IN+ Source
2
PC5

@ +DC_IN +DC_IN_SS
PQ4
FDS6679AZ_G_SO8~D
1 8
PL3 S D
2 7
FBMA-L18-453215-900LMA90T_1812~D S D
3 6
+DC_IN S D
1 2 4 5
G D
1

1M_0402_5%~D
VZ0603M260APT_0603

2
0.022U_0805_50V7K~D

100K_0402_5%~D

10U_1206_25V6M~D
0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
1

1
PC6

PR15

1
PD10

1
1

PC7

PC8

PC9

PR16

PC11
2

2
0.1U_0603_25V7K~D
1

MOLEX_87438-0743 PR18
4.7K_0805_5%~D

2
1

7 @ 1 2 SOFT_START_GC
2
0.1U_0603_25V7K~D

7
1
PC10

6
2

6 -DCIN_JACK 10K_0402_5%~D
@ PR17

5
1M_0402_5%~D

5 <63>
1

2
PC12

4
2

4 +DCIN_JACK
PR19

A 3 A
2

3
2
2 @
1
1
2

PJPDC1

1 2

PL4
DELL CONFIDENTIAL/PROPRIETARY
FBMA-L18-453215-900LMA90T_1812~D
0.1U_0603_25V7K~D
1

Compal Electronics, Inc.


Title
PC13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN

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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.4
LA-6592
Date: Tuesday, January 18, 2011 Sheet 52 of 67
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP/ +3.3V_RTC_LDO

+DC1_PWR_SRC

PJP44
+PWR_SRC 1 2

PAD-OPEN 4x4m 3.3 Volt +/-5%


Pop 10 Ohm for MAX17020 Thermal Design Current : 5.079A

2
PJP45 +5V_VCC1

0_0805_5%~D

0_0805_5%~D
D D
1 2
+5V_ALW2
Peak current : 7.256A

0.1U_0805_50V7M~D
2200P_0402_50V7K~D
PR20

PR21
5 Volt +/-5%

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0805_50V7M~D
2200P_0402_50V7K~D
@ PR22
OCP_MIN : 8.707A

1
PAD-OPEN1x1m 10_0603_5%~D
Thermal Design Current : 7.869A

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

1
1

PC19

PC20

PC21

PC22

PC23
2 1

4.7U_0603_6.3V6K~D
PC14

PC15

PC16

PC17

PC18
Peak Current : 11.242A

2
Fsw = 300KHz

1
PC24
OCP_MIN : 13.490A
+3.3V_ALW2

2
0.1U_0603_25V7K~D
Fsw = 400KHz

1
PC25

1U_0402_6.3V4Z~D
@ PR24

1U_0603_10V6K~D
1

1
0_0402_5%~D
0_0402_5%~D

PC26
2

1
PC27
1 2

PR23

2
@ PR25
@

2
+5V_ALW2P
0_0402_5%~D

2
1 2

EN_3V_5V
+3.3V_ALW2
+3.3V_RTC_LDO +5V_3V_REF PC28
0.1U_0603_25V7K~D

1
GNDA_3V5V 1 2 GNDA_3V5V

VIN
PR27
LDOREFIN 1 2 0_0402_5%~D
@ PR26 0_0603_5%~D

0.1U_0402_10V7K~D
PR28

2
0.1U_0402_10V7K~D
3

PC30
PU2

8
7
6
5
4
3
2
1

5
6
7
8
FDS8878_G 1N SO8

GNDA_3V5V SN0608098_QFN32_5X5~D 1 2
D

1
+5V_ALWP 0_0402_5%~D

PC29

VREF3

TONSEL
VREF2
LDOREFIN

VIN
LDO

V5FILT
EN_LDO

AO4466L_SO8~D
REFIN2
PQ5

2
2

PQ6
2 @ PR29
G 274K_0402_1%~D
9 32 4
+5V_ALWP PR30 VSW REFIN2 GNDA_3V5V
10 31 1 2
VOUT1 TRIP2
S

348K_0402_1%~D +5V_FB1 11 30 +3.3V_OUT2


VFB1 VOUT2 PR31 1 0_0402_5%~D +3.3V_ALWP
C GNDA_3V5V 1 2 12 29 2 C
1

PL5 POK1 TRIP1 SKIPSEL POK2


13 28

3
2
1
EN_3V_5V PGOOD1 PGOOD2 EN_3V_5V PL6
14 27
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D +5V_ALW_UGATE EN1 EN2 +3.3V_ALW_UGATE 4.7UH_FDVE1040-H-4R7M=P3_10A_20%~D
15 26
+5V_ALWP +5V_ALW_PHASE DRVH1 DRVH2 +3.3V_ALW_PHASE +3.3V_ALWP
2 1 16 25 2 1
LL1 LL2
1000P_0603_50V7K~D

1000P_0603_50V7K~D
SECFB
V5DRV
VBST1
DRVL1

DRVL2
VBST2

0.1U_0603_25V7K~D
1

1
PGND
GNDA_3V5V

PC32
0_0402_5%~D

GND
PAD
0.1U_0603_25V7K~D

5
6
7
8

1
0_0402_5%~D
FDMS7692 1N POWER56-8
PC31

D
330U_V_6.3VM~D

330U_V_6.3VM~D
PR32

PR33
2

2
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D
1

1
PC34

PC35
1 1

AO4406AL_SO8~D
33

17
18
19
20
21
22
23
24
PQ7
2
1

1
+ @ +
PC33

PC36

PC37

PC38
2 GNDA_3V5V

2
G

PQ8
4
2

2
PR34 PR35

SECFB
2.2_1206_5%~D
2

2
2 2
S

@ 2.2_0603_5%~D 2.2_0603_5%~D @

2.2_1206_5%~D
2+5V_ALW_BOOT +3.3V_ALW_BOOT 1
PR36

PR37
1 2

0_0402_5%~D
1
1

1
0_0402_5%~D

3
2
1
+3.3V_ALW_LGATE
PR38

PR39
1

1
2

2
+5V_ALW_LGATE
GNDA_3V5V

GNDA_3V5V
GNDA_3V5V PC39 PJP46

1U_0603_10V6K~D
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2
+3.3V_ALWP +3.3V_ALWP

PC40
1 1 2
3

+5V_ALW2

2
0.1U_0603_25V7K~D

PAD-OPEN1x1m
1

PD11 GNDA_3V5V

100K_0402_1%~D

100K_0402_1%~D
PC41

BAT54SW-7-F_SOT323-3~D

2
2

PC42

PR40

PR41
2 0.1U_0603_25V7K~D PD13
1

1 1 2 BAT54CW_SOT323~D
B B
3 @

1
PR42 PD12 POK2
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D
<43> ALWON
3

0_0402_5%~D
1
@ PR43
200K_0402_5%~D
2

PR45
0_0402_5%~D
PR44

<23> THERM_STP# 2 1 @

2
1

POK1
PJP47 ALW_PWRGD_3V_5V <43>
1 2

PAD-OPEN 4x4m PR46


PJP48 PJP49 200K_0402_1%~D
+5V_ALWP 1 2 +15V_ALW 2 1 +15V_ALWP 2 1
ALW_PWRGD_3V_5V
+5V_ALW
PAD-OPEN 4x4m * connect to U51 (EC) Pin B15 (Vih =>2V)
0.1U_0603_25V7K~D

PAD-OPEN1x1m
(100mA,20mils ,Via NO.=1) PR47
1

39K_0402_5%~D
PC43

PJP50
1 2 +3.3V_ALW
2

+3.3V_ALWP
PAD-OPEN 4x4m
PJP9
1 2 PU2 PR22
PAD-OPEN 4x4m
GNDA_3V5V SN0608098 @
Main (X7630031L10)
2nd (X7630031L11) MAX17020 10 Ohm
A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DC/DC +3V/ +5V

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
LA-6592
Date: Tuesday, January 18, 2011 Sheet 53 of 67
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +1.5V_SUS_P

1.5 Volt +/-5%


Thermal Design Current: 12.275A
Peak current: 17.535A
OCP_MIN:21.042A
D D

@ PL601
FBMJ4516HS720NT_2P~D
1 2

PJP601
1.5V_PWR_SRC 1 2 +PWR_SRC
PAD-OPEN 4x4m

0.1U_0805_50V7M~D
2200P_0402_50V7K~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
1

1
PC605

PC604

PC603

PC602

PC601
5
PQ601

FDMS7692_SO8~D

2
PR603 @ @
255K_0402_1%~D
1 2
4

PR604
GNDA_1.5V PC612
@ PR606 2.2_0603_5%~D
DDR_ON 1 2 BST_1.5VP 1 2 1 2

3
2
1
45
1

0_0402_5%~D 0.1U_0603_25V7K~D
1

@ PR611 PL602

15

14
1
300K_0402_5%~D @ PC613 PU601 1UH 20% FDUE1040D-H-1R0M=P3_21.3A_20%~D
1U_0402_6.3V4Z~D 1 2

NC

BOOT
EN/DEM
+1.5V_SUS_P
2
2

2 13 DH_1.5VP
TON UGATE

1
C PR607 3 12 LX_1.5VP PC610 C

330U_SX_2VY~D

330U_SX_2VY~D

2200P_0402_50V7K~D

0.1U_0402_10V7K~D
VOUT PHASE

5
10_0402_5%~D 1000P_0603_50V7K~D

2
+5V_ALW

PQ602
1 2 4 11 1 2 1 1

0_0402_5%~D
+5V_ALW

FDMS0310S_DFN8-5
VDD CS

1
PR605
10K_0402_1%~D + +

PR601

PC609

PC608

PC607

PC606
5 10
FB VDDP

2
1

6 9 DL_1.5VP 4
PGOOD LGATE

2
PGND
PC614 2 2

GND

2.2_1206_5%~D

1
4.7U_0603_6.3V6K~D
2

2
PC611

PR602
PC615
@ RT8209MGQW_WQFN14_3P5X3P5 4.7U_0805_10V4Z~D

3
2
1
2 1

1
GNDA_1.5V +3.3V_ALW
47P_0402_50V8J~D GNDA_1.5V
PR608
10K_0402_1%~D
100K_0402_1%~D

1 2 GNDA_1.5V
1

1
PR610

PR609
10K_0402_1%~D
2

1.5V_SUS_PWRGD
45 GNDA_1.5V

1.5V_SUS_PWRGD
* connect to U51 (EC) Pin B9 (Vih => 2V)
PJP602
B B
PJP604 1 2
1 2
PAD-OPEN 4x4m

PAD-OPEN1x1m PJP603
+1.5V_SUS_P 1 2 +1.5V_MEM
GNDA_1.5V
PAD-OPEN 4x4m

A A

PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
DELL CONFIDENTIAL/PROPRIETARY
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_MEM

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
LA-6592
Date: Tuesday, January 18, 2011 Sheet 54 of 67
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +1.8V_RUNP
1.8 Volt +/-5%
Thermal Design Current: 0.981 A
Peak current: 1.402 A
+3.3V_ALW @ PJP14
OCP_MIN: 1.682 A
2 1 +1.8V_PWR_SRC
D D

PAD-OPEN 2x2m~D

10U_0805_6.3V6M~D

22U_0805_6.3V4Z~D

0.1U_0603_25V7K~D
PC68
2

1
PC66

PC67

1
PR60

2
@ 0_0603_5%~D

13

14

15

16

17
PU4

+1.8V_VDD

VIN

VIN

PGND

PGND

TPAD
PR61
PC69
24k_0402_1%~D
1 2 12 1 +1.8V_EN 2 1 RUN_ON <11,38,42,45,64>
VDD EN

GNDA_1.8V .1U_0402_16V7K~D

11 2
AGND RES
TPS51311RGTR_QFN16_3X3~D
PC70 PR63
1 2 2 1 +1.8V_FB 10 3 2 1 +3.3V_RUN
FB PGOOD
0.012U_0402_16V7K~D 10_0402_1%~D PR66 PC71 10K_0402_5%~D
+1.8V_RUNP

PR65 1.43K_0402_1%~D 0.018U_0402_16V7K~D PR64


2 1 2 1 2 1 +1.8V_COMP 9 4 +1.8V_VBST
COMP VBST
2K_0402_1%~D 1.8V_RUN_PWRGD <42>

3.3_0603_1%~D
MODE

2
1K_0402_1%~D PC72 100P_0402_50V8J~D

SW

SW

SW

PR67
2 1
1
PR68

C C
1.8V_RUN_PWRGD connect to

+1.8V_MODE 8

1
PC73 U46 Pin B10 (EC)
2

2 1

GNDA_1.8V 0.22U_0603_10V7K~D

2
@ PJP15 PL8
1 2 PR69 2UH_#A915AY-H-2R0M=P3_3.3A_20%~D
57.6K_0402_1%~D +1.8V_SW 2 1 +1.8V_RUNP
PAD-OPEN1x1m

680P_0603_50V8J~D

47P_0402_50V8J~D
22U_0805_6.3V4Z~D

22U_0805_6.3V4Z~D
GNDA_1.8V

PC74
1

1
GNDA_1.8V

PC75

PC76

PC77
@

2
1

PR70
4.7_0805_5%~D
2
@

@ PJP16
2 1
+0.75V_DDR_VTT +1.8V_RUNP
PAD-OPEN 2x2m~D
+1.8V_RUN

B B

DDR3 Termination

+5V_ALW
0.75Volt +/-5%
PJP17
PU5
+V_DDR_REF Thermal Design Current: 0.525A
1

+1.5V_MEM 2 1DC_1+0.75V_VTT_PWR_SRC 1
VDDQSNS VIN
10
PC78
Peak current: 0.75A
PAD-OPEN 2x2m~D 2 4.7U_0805_10V4Z~D
2

VLDOIN
+0.75V_P
8
GND
6
VTTREF
3
0.1U_0603_25V7K~D

VTT
5 9 +0.75V_S5
10U_0805_6.3V6M~D

0.1U_0603_25V7K~D

VTTSNS S5
2

PJP18
PC79
PGND

7 +0.75V_S3 2 1
GND

+0.75V_DDR_VTT
10U_0805_6.3V6M~D

10U_0805_6.3V6M~D

S3
2

+0.75V_P
PC82

PAD-OPEN 2x2m~D
PC83

RT9026GFP_MSOP10~D
PC80

PC81
1

11
1

A 1 2 DDR_ON A
<43,49>
@ PR72 0_0402_5%~D

1 2 0.75V_DDR_VTT_ON
<42>
@ PR71 0_0402_5%~D

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT +0.75V_DDR_VT/+1.8V_RUN

WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6592
Date: Tuesday, January 18, 2011 Sheet 55 of 67
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com
+1.05V_M

D D

PC84
PJP19
1U_0402_6.3V6K~D +1.05V_PWR_SRC 1 2 +5V_ALW
2 1 PAD-OPEN 4x4m
1.05 Volt +/-5%

10U_1206_25V6M~D

10U_1206_25V6M~D
0.1U_0603_25V7K~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
PC88

PC89
Thermal Design Current : 4.782A

1
+1.05VM_VX

PC85

PC86

PC87
Peak current : 6.832A

2
GNDA_1.05VM

17

16
OCP_MIN :8.198A

2
PU6
+3.3V_ALW PC90
VIN

VIN
0.22U_0603_10V7K~D

1
PR74 PR75 @
PC91 100P_0402_50V8J~D 3.3_0603_1%~D 0_0402_5%~D
2 1 1 15 +1.05VM_BST 1 2 2 1 SIO_SLP_A# <17,42>
VCCA VBST
C PR76 PC92 2 14 +1.05VM_PWRGD C
5.6K_0402_5%~D 680P_0402_50V7K~D GND PGOOD @ PR78
2 1 2 1 +1.05VM_COMP 3 13 +1.05VM_EN 2 1 A_ON <43,45>
COMP EN 22.1K_0402_1%~D
+1.05VM_VFB 4 12 +1.05VM_FSET 2 1 0_0402_5%~D
PR80 2K_0402_1%~D VFB FSET @ PR79
2 1 +1.05V_MP 5 11 +1.05VM_MODE
VOUT MODE

2
2 1 1 2 +1.05VM_SS 6 10 +1.05VM_IMON

22K_0402_1%~D
SS IMON GNDA_1.05VM

PR83
+1.05V_MP

2.67K_0402_1%~D

0.01U_0402_25V7K~D
1

0_0402_5%~D 1800P_0402_50V7K~D
PGND

PGND
PC94

PR81 +1.05V_MP
SW

PC93
2

1
PR82

SN1003055RUWR_QFN17_3P5X3P5~D
2

GNDA_1.05VM PL9
0.42UH_ETQP4LR42AFM_17A_20%~D
+1.05VM_VX

GNDA_1.05VM +1.05VM_VX 2 1
GNDA_1.05VM
1

1
@
1.33K_0402_1%~D

PC95
@ PR84

PC106

PC107
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

6800P_0402_25V7K~D
0.1U_0603_25V7K~D
1

1
0.1U_0603_25V7K~D

2
@ PR85 0_0402_5%~D

PC96

PC97

PC98

PC99

PC100

PC101

PC102

PC103

PC104

PC105
2

2 1

2
2
@ PR86
7.68K_0805_1%~D
GNDA_1.05VM

1
B B

+3.3V_ALW
100K_0402_1%~D
1
PR87

PJP21
PJP20 1 2
1 2
2

PAD-OPEN 4x4m
@ PR88 0_0402_5%~D
+1.05VM_PWRGD 2 1 1.05V_A_PWRGD <43> PAD-OPEN1x1m PJP22
+1.05V_MP 1 2 +1.05V_M
GNDA_1.05VM
PAD-OPEN 4x4m

1.05V_A_PWRGD
* connect to U51 (EC) Pin A14 (Vih => 2V)

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

+1.05V_M

WWW.AliSaler.Com
Size Document Number Rev
0.4
LA-6592
Date: Tuesday, January 18, 2011 Sheet 56 of 67
5 4 3 2 1
5 4 3 2 1

WWW.AliSaler.Com +1.05VTT 1.05Volt


=> (+/- 5% AC + DC +Ripple )
=> (+/- 2% DC + Ripple)
Thermal Design Current : 5.980A
PC108 Peack current : 8.970A
PJP23
1U_0402_6.3V6K~D +1.05VTT_PWR_SRC 1 2 +5V_ALW OCP_MIN : 10.764A
D D
2 1 PAD-OPEN 4x4m

22U_0805_6.3V4Z~D

22U_0805_6.3V4Z~D

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D

0.1U_0603_25V7K~D
PC112

PC113
2

1
+1.05VTT_VX

PC351

PC350

@ PC109

PC110

PC111
1

2
GNDA_1.05VTT @ @

17

16

2
PU7
+3.3V_ALW PC114

VIN

VIN
0.22U_0603_10V7K~D

1
PR89
PC115 100P_0402_50V8J~D 2.2_0603_5%~D
2 1 1 15 +1.05VTT_BST 1 2
VCCA VBST
PR90 PC116 2 14 +1.05VTT_PWRGD @ PR91
5.6K_0402_5%~D 680P_0402_50V7K~D GND PGOOD CPU_VTT_ON
0_0402_5%~D
2 1 2 1 +1.05VTT_COMP 3 13 +1.05VTT_EN 1 2
COMP EN 22.1K_0402_1%~D <42,62>
+1.05VTT_VFB 4 12 +1.05VTT_FSET 2 1
PR93 2K_0402_0.5%~D VFB FSET @ PR92
2 1 +1.05VTT_SENSE 5 11 +1.05VTT_MODE
VOUT MODE
+1.05VTT_SENSE

0_0402_5%~D
2 1 1 2 +1.05VTT_SS 6 10 +1.05VTT_IMON
SS IMON GNDA_1.05VTT

PR95
0.01U_0402_25V7K~D
0_0402_5%~D 1800P_0402_50V7K~D 1

PGND

PGND
PC118

PR94

SW
PC117
2

1
SN1003055RUWR_QFN17_3P5X3P5~D

9
1
20K_0402_0.5%~D
1

3.09K_0402_0.5%~D

GNDA_1.05VTT PL10 +1.05VTTP


0.42UH_ETQP4LR42AFM_17A_20%~D

+1.05VTT_VX
PR105

+1.05VTT_VX
PR96

2 1
GNDA_1.05VTT
2

1
2

1
@

22.1K_0402_1%~D
PC119

PR97

PC128

PC131
47U_0805_4V6M~D

47U_0805_4V6M~D
22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0603_25V7K~D

6800P_0402_25V7K~D
1

1
C 0.1U_0603_25V7K~D C

2
@ PR98 0_0402_5%~D

PC120

PC129

PC121

PC122

PC130

PC123

PC124

PC125

PC126

PC127
2
2 1

2
2

1
PR100
10_0402_5%~D
GNDA_1.05VTT @ PR99
7.68K_0805_1%~D
GNDA_1.05VTT

2
PR101
9.31K_0402_1%~D
2 1 PR102
+5V_RUN
+1.05VTT_SENSE 1 2 VTT_SENSE <10>
@ PR103 0_0402_5%~D
+1.05VTT_PWRGD 1 2 1.05V_VTTPWRGD <43,62>
0_0402_5%~D PR461
GNDA_1.05VTT 1 2 VTT_GND <10>
2 1
0_0402_5%~D
13.3K_0402_1%~D
PR104

1.05V_VTTPWRGD
* connect to PU13 Pin 15 (Vih => 2V)
* connect to U50 Pin 1 (Vih => 2.31V)
B B

PJP25
PJP24
1 2 2 1

PAD-OPEN 43X118
PAD-OPEN1x1m
PJP26
+1.05VTTP 1 2 +1.05V_RUN_VTT
GNDA_1.05VTT
PAD-OPEN 43X118

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ISL95870A +1.05V_RUN_VTT

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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6592
Date: Tuesday, January 18, 2011 Sheet 57 of 67
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+VCC_PWR_SRC

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10U_1206_25VAK~D

10U_1206_25VAK~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
5

5
PQ9

PQ10
VCC_Core

10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN

1
PC701 0.033U_0402_16V7K~D

PC132
Thermal Design Current : 53A @

PC400

PC133

PC134

PC135
2 1
Peak current : 94A

2
UGATE3 4 4

OCP_MIN :112.8A PC136 +5V_ALW


PR118 PR107 PC137
1 2 2 1 2.2_0603_5%~D 0.22U_0603_10V7K~D

3
2
1

3
2
1
PC138 BOST3 2 1 BT3_1 1 2
0.33U_0603_10V7K~D 1_0603_1%~D 1U_0603_10V6K~D PU8 PL11
2 1 5 1 0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D
PR109 VDD BST
2 1 6 8 PHASE3 4 1 +VCC_CORE
D
40.2K_0402_1%~D P1_SW SKIP DH D
2 1

1
2 7 P3_SW 3 2P3_Vo
PWM LX
Layout Note: PH1 PR111 PR110 4.32K_0402_1%~D PQ11 1000P_0603_50V7K~D

PQ12

PC139
AON6704L_DFN8-5

AON6704L_DFN8-5

1
1 2 2 1 2 1 P2_SW 3 4
PC142 close to PIN19

2
GND DL 2.1K_0402_1%~D PR114
10K_0402_1%_ERTJ0EG103FA~D 2.1K_0402_1%~D PR112 4.32K_0402_1%~D 9 PR113 1_0402_5%~D
P3_SW EP LGATE3
2 1 4 4

2
MAX17491GTA+T_TQFN8_3X3~D

1_1206_1%~D

2
PR115 4.32K_0402_1%~D

PR117
1
+Vcore_VCC PC140 PR120

3
2
1

3
2
1
@ PR121 0_0402_5%~D PR122 10_0402_5%~D 4700P_0402_25V7K~D 2 1

1
+5V_ALW 1 2 +Vcore_VDD 1 2 22.1K_0402_1%~D

1
1K_0402_1%~D

165K_0402_1%~D

165K_0402_1%~D
5.62K_0402_1%~D

5.62K_0402_1%~D
2.2U_0603_10V7K~D
1

2
PC143 PR128 @ PC144
1

2.2U_0603_10V7K~D
PC142

PR123

PR124

PR125

PR126

PR127
0_0402_5%~D 1 2
1U_0603_10V6K~D

+Vcore_CSPA3
PC141

GNDA_VCC 1 2
2

@ PC145 1000P_0402_50V7K~D
2

2
<15,43> 1.05V_0.8V_PWROK 1 2 GNDA_VCC 1 2 PC146

1
@ 0.22U_0603_16V7K~D
@ PR129 0_0402_5%~D 1000P_0402_50V7K~D 2 1
<42> IMVP_VR_ON 1 2 +Vcore_IMAXA
@ PR131 0_0402_5%~D
+GFX_IMAXB +Vcore_CSNA

100K_0402_1%_TSM0B104F4251RZ~D

100K_0402_1%_TSM0B104F4251RZ~D
+Vcore_CSPAAVE

+VGFX_THERMB

+Vcore_THERMA
1 2

10K_0402_1%~D

105K_0402_1%~D

105K_0402_1%~D
+VCC_PWR_SRC

2
+Vcore_CSPA3

+Vcore_CSPA2

+Vcore_CSPA1

+Vcore_PWMA
PR132 200K_0402_1%~D

+Vcore_CSNA
+Vcore_TONA

2
+Vcore_VCC

PR133

PR134

PR135
+Vcore_EN

+Vcore_SR
GNDA_VCC +VCC_PWR_SRC PJP27

PH2

PH3
1 2 +PWR_SRC
+VGFX_PWR_SRC 1 2 +VGFX_TONB @

1
PR136 200K_0402_1%~D PAD-OPEN 4x4m

10U_1206_25VAK~D

10U_1206_25VAK~D
2200P_0402_50V7K~D
1

0.1U_0603_25V7K~D
5

5
PQ13

PQ14

100U_25V_M~D

100U_25V_M~D

100U_25V_M~D
10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN
@ PR410 10_0402_1%~D 1 1 1

1
PC148

PC154

PC155

PC156
1 2

49

48

47

46

45

44

43

42

41

40

39

38

37
PU9 @ + + +

PC401

PC151

PC152

PC153
PR138 10_0402_1%~D

CSPA3

CSPA2

CSPA1
TPAD

EN

VCC

SR
TONA

CSNA

CSPAAVE

THERMB

THERMA

DRVPWMA

2
<10> VSSSENSE 1 2 +Vcore_GNDSA GNDA_VCC 4 4
C 2 2 2 C
1

PC149
1000P_0402_50V7K~D
1

@ PC150 1 36 +GFX_IMAXB
Local sense resister put HW side
2

3
2
1

3
2
1
1000P_0402_50V7K~D GNDA_VCC TONB IMAXB
2 35 +Vcore_IMAXA PR141 PC157 PL12
2

PR139 10_0402_1%~D PR140 12.7K_0402_1%~D GNDSA IMAXA 2.2_0603_5%~D 0.22U_0603_10V7K~D 0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D
<10> VCCSENSE 1 2 2 1 +Vcore_FBA 3 34 BOST2 2 1 BT2_1 1 2
FBA BSTA2
4 1 +VCC_CORE
1

@ PR411 10_0402_1%~D PC158 +Vcore_VRHOT# 4 33 PHASE2


VRHOT# LXA2

1
1 2 1000P_0402_50V7K~D GNDA_VCC P2_SW 3 2P2_Vo
UGATE2

PQ16
PQ15 1000P_0603_50V7K~D

PC159
5 32
2

AON6704L_DFN8-5

AON6704L_DFN8-5
AGND DHA2

1
@ PR143 75_0402_5%~D GNDA_VCC

2
+1.05V_RUN_VTT 1 2 +VGFX_FBB 6 31 LGAT2 2.1K_0402_1%~D PR145
FBB DLA2 PR144 1_0402_5%~D
@ PR146 +VGFX_GNDSB 7 30 4 4
GNDSB PGNDA

2
1 2

1_1206_1%~D

2
<7,43> H_PROCHOT# +Vcore_VDD
8 29
0_0402_5%~D CSPBAVE VDDA

PR148
2.2U_0603_10V7K~D
1

1
GNDA_VCC 1 2 +GFX_CSPB1 9 28 PC161 PR152

3
2
1

3
2
1
CSPB1 DLA1 4700P_0402_25V7K~D

PC160
2 1

1
@

PC168 43P_0402_50V8J 10 MAX17411GTM+_TQFN48_6X6~D 27 22.1K_0402_1%~D

2
CSNB DHA1

1
<60> +GFX_CSNB
<60> +GFX_CSPBAVE @ PR198
+Vcore_VCC 1 2 11 26 PR154 @ PC162
CSPB2 LXA1
1

0_0402_5%~D 1 2
@ PR199 0_0402_5%~D 12 25 +Vcore_CSPA2
POKB BSTA1 @ PC164 1000P_0402_50V7K~D
0_0402_5%~D

2
DRVPWMB

GNDA_VCC 1 2 PC166
+GFX_POKB

ALERT#

@ PC205 0.22U_0603_16V7K~D
PGNDB
2

AGND

POKA
VDDB
BSTB

1000P_0402_50V7K~D
VDIO

GNDA_VCC 1 2 2 1
DHB

DLB

CLK
LXB

PR149 10_0402_5%~D 1000P_0402_50V7K~D


1 2 +Vcore_CSNA
13

14

15

16

17

18

19

20

+Vcore_VDIO 21

+Vcore_ALERT# 22

23

+Vcore_POKA 24

PR153 10_0402_1%~D
+Vcore_VDD

<11> VSS_AXG_SENSE
+Vcore_CLK

1 2 +VGFX_GNDSB
1

PC163 +VCC_PWR_SRC
B
1000P_0402_50V7K~D <60> +GFX_BSTB B
1

@ PC165
GNDA_VCC

10U_1206_25VAK~D

10U_1206_25VAK~D
2

0.1U_0603_25V7K~D

2200P_0402_50V7K~D
<60> +GFX_LXB

5
1000P_0402_50V7K~D GNDA_VCC

PQ17

PQ18

10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN
2

<60> +GFX_DHB

1
PR156 10_0402_1%~D PR157 7.5K_0402_1%~D

PC169
<11> VCC_AXG_SENSE 1+VGFX_FBB @

PC402

PC170

PC171

PC172
1 2 2
<60> +GFX_DLB

2
1

+VCC_GFXCORE PC167 PC173 0.1U_0402_25V6K~D UGATE1 4 4


1 2 1000P_0402_50V7K~D 1 2
2

PR158 10_0402_5%~D GNDA_VCC 2 1 PR161 PC174


PR159 130_0402_1%~D 2.2_0603_5%~D 0.22U_0603_10V7K~D

3
2
1

3
2
1
+3.3V_RUN 2 1 BOST1 2 1 BT1_1 1 2
+1.05V_RUN_VTT
@ PR160 130_0402_1%~D PL13
2 1 0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D
+GFX_POKB PR162 54.9_0402_1%~D
PHASE1 4 1 +VCC_CORE
<10> VIDSOUT 1 2
10K_0402_1%~D
2

1
PR164 0_0402_5%~D P1_SW 3 2P1_Vo
0_0402_5%~D

<10> VIDALERT_N PQ19 1000P_0603_50V7K~D

PQ20
PR165

PR166

PC175
1 2

AON6704L_DFN8-5

AON6704L_DFN8-5

1
PR167 0_0402_5%~D

2
<10> VIDSCLK 1 2 2.1K_0402_1%~D PR170
@ PR168 0_0402_5%~D PR169 1_0402_5%~D
1

@ PR171 LGATE1 4 4

2
1 2 +Vcore_POKA

1_1206_1%~D
<42> IMVP_PGOOD

2
0_0402_5%~D

PR173
1

PC176 PR176

3
2
1

3
2
1
4700P_0402_25V7K~D 2 1

1
22.1K_0402_1%~D
2

1
IMVP_PGOOD connect to PR177 @ PC177
1 2
U46 Pin A62 (EC) +Vcore_CSPA1
0_0402_5%~D
@ PC178 1000P_0402_50V7K~D

2
GNDA_VCC 1 2 PC179
PQ9,PQ13,PQ18,PQ24,PQ60,PQ52 PQ11,PQ12,PQ15,PQ16,PQ19,PQ20,PQ25,PQ26,PQ53 0.22U_0603_16V7K~D
A
Vcore/VAXG H/S Mosfet Vcore/VAXG L/S Mosfet 1000P_0402_50V7K~D 2 1 A
PJP28
1 2
Main (X7630031L08) AON6414AL Main (X7630031L08) AON6704L +Vcore_CSNA
@ PC180
PAD-OPEN1x1m SIR472 SIR164DP 1 2
GNDA_VCC 2nd 2nd GNDA_VCC
1000P_0402_50V7K~D
3rd (X7630031L09) MDU2657RH 3rd (X7630031L09) MDU2653RH DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Vcore

WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6592
Date: Tuesday, January 18, 2011 Sheet 58 of 67
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VCC_AXG
Thermal Design Current : 21.5A
D
Peak current : 33A D

OCP_MIN :39.6A

+VGFX_PWR_SRC
PJP29
1 2 +PWR_SRC
PAD-OPEN 4x4m

10U_1206_25VAK~D

10U_1206_25VAK~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
5

5
PQ24

PQ60

10U_1206_25VAK~D
AON6414AL 1N DFN

AON6414AL 1N DFN

1
PC193
PC403

PC194

PC195

PC196
2

2
4 4
<59> +GFX_DHB

PR189 PC197
2.2_0603_5%~D 0.22U_0603_10V7K~D

3
2
1

3
2
1
2 1 GBT1_1 1 2
C <59> +GFX_BSTB PL15 C
0.36UH_FDUE1040J-H-R36M=P3 33A_20%~D

4 1 +VCC_GFXCORE
<59> +GFX_LXB

2200P_0402_50V7K~D
470U_D2_2VM_R4.5M~D
5

1
GP1_SW 3 2GP1_Vo

0.1U_0402_10V7K~D

470U_D2_2VM_R4.5M~D
PQ26
PQ25 1000P_0603_50V7K~D

PC198
1 1

AON6704L_DFN8-5

AON6704L_DFN8-5

1
2

1
+ +

PC201

PC202

PC199
PC200

2
4 4

2
2
<59> +GFX_DLB 2 2

1_1206_1%~D
PR193
1

PC203

3
2
1

3
2
1
4700P_0402_25V7K~D

1
2

1_0402_5%~D
PR191
PC702 0.033U_0402_16V7K~D
2 1

2
PC208
PR119
1 2 2 1

0.33U_0603_10V7K~D 0_0603_1%~D

PR201
2 1
40.2K_0402_1%~D
PR190
PH4 PR203
1 2 2 1 2 1

10K_0402_1%_ERTJ0EG103FA~D 2.1K_0402_1%~D
1.43K_0402_1%~D
B B

<59> +GFX_CSNB @ PC207


GNDA_VCC 1 2

1000P_0402_50V7K~D

<59> +GFX_CSPBAVE

A A

Compal Electronics, Inc.


Title
+VCORE/+GFXCORE

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Size Document Number Rev
0.4
LA-6592
Date: Tuesday, January 18, 2011 Sheet 59 of 67
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PU11

BQ24747
PR215

10K
PR214

@
PR222

@
@ PD14
2 1 PL16 ISL88731C @ 10K 15.8K
FBMJ4516HS720NT_2P~D 2nd (X7630031L13)
SBR3A40SA-13_SMA2 2 1
PQ27 PR205
SI4835DDY-T1-GE3_SO8~D +SDC_IN 0.01_1206_1%~D +PWR_SRC CHAGER_SRC
8 1 PJP33
7 2 4 1 1 2
+DC_IN_SS
6 3 PR217 PC229 PR226

0.1U_0603_25V7K~D
5 3 2 PAD-OPEN 4x4m

0.1U_0603_25V7K~D
@

47P_0402_50V8J~D
1

1
D D

PC209

PC211
Adapter Protection Event Main 316K 220P 4.7K

PC210
@ PR206

2
1
1 2 @ PR207 D @ 226K @ 2.2K
DC_BLOCK_GC <63>
1 2 2 PQ28 2nd
0_0402_5%~D
<63> CSS_GC
G NTR4502PT1G_SOT23-3~D PR813 PR814 PR812

1
0_0402_5%~D D S

3
2 PQ30A
G NTGD4161PT1G_TSOP6~D PC231 PR224 PR225
PQ29 S SW 0 Ohm @ 100k

S
NTR4502PT1G_SOT23-3~D

D
5 6 DOCK_DCIN_IS+ <41>
E2 AC_OK=17.7 Volt Main @ 200K 7.5K
HW @ 0 Ohm @

CSSN_1
CSSP_1

G
1
PR218 PQ30B 0.01u @ @
PR208 NTGD4161PT1G_TSOP6~D 2nd
TI bq24745 = 316K 10K_0402_5%~D

S
Intersil ISL88731 = 226K

D
2 1 2 4

0_0402_5%~D
DOCK_DCIN_IS- <41>

100K_0402_1%~D
0_0402_5%~D
Maxim = 383K

1
PR228 PC225 PC227

PR209

100K_0402_1%~D
1

1
PR210

PR211

G
3
+SDC_IN @ PR216
MAX8731A_LDO MAX8731_REF PC212 PC213 10K 2200P 56P

PR212
1 2
PR213 0.1U_0603_25V7K~D 0.1U_0603_25V7K~D
DK_CSS_GC <63>
@ PR813 0_0402_5%~D Main
10K_0402_1%~D

10K_0402_5%~D

2
1 2 1 2 1 2 1 2 0_0402_5%~D 1 2 DYN_TUR_PWR_ALRT# <23>
<63> +CHGR_DC_IN

2
1

1
2nd @ @ @
316K_0402_1%~D

1_0805_5%~D ICREF @ PC292 PR814 0_0402_5%~D


PR214

PR215
2

0.1U_0603_25V7K~D DYN_TUR_PWR_VO H_PROCHOT# <7,43>


PR217

1 2
GNDA_CHG @ PC803

28

27
1
@ PC215 GNDA_CHG PU11 ICOUT 2 1 1 2 GNDA_CHG
2

0.1U_0805_50V7M~D PC228 PC234 PC233

CSSN
ICREF

CSSP

1U_0603_10V6K~D
PR218 2 1 DCIN 22 26 @ PR220 @ PR811 220P_0402_50V8J~D
1

DCIN ICOUT

1
49.9K_0402_1%~D PR219 33_0603_1%~D 0_0402_5%~D

10U_1206_25V6M~D

10U_1206_25V6M~D
2200P_0402_50V7K~D

0.1U_0603_25V7K~D
2
2.2_0603_1%~D 120P 1u @

@ PC214
2 1 2
@ PR221
ACIN BOOT
25 1 2 BOOT_D @ PR812 Main
BOOT

1
PC218

PC219

PC220

PC221
1 2 13 100K_0402_5%~D
15.8K_0402_1%~D

PC216

1
BAT54HT1G_SOD323-2~D
<23,43,63> ACAV_IN ACOK

1
@ @ 0.01u

PC217
2nd

2
0.1U_0603_25V7K~D
1

1
C 2 1 0_0402_5%~D 11 C

2
VDDSMB

PD15
PR222

5
0.01U_0402_25V7K~D GNDA_CHG +3.3V_ALW

PQ31
10

2
SCL

SIR472DP-T1-GE3_SO8~D
PC222

2
GNDA_CHG +5V_ALW @ 9 21 MAX8731A_LDO 1 2 PC240 PC241 PR232
2

SDA VDDP

GNDA_CHG 14 1U_0603_10V6K~D
NC CHG_UGATE
MAX8731_IINP UGATE
24 4
Main 0.1u 0.1u 0 ohm
8
VICM
1

23 2 PR223 1 +VCHGR_B
PC223 PHASE
6
2nd @ 0.22u 10 ohm

3300P_0402_50V7K~D
FBO

1
0.1U_0402_10V7K~D 1_0603_1%~D
2

3
2
1
1 2 5 @ PC224
EAI 220P_0402_50V7K~D

1
GNDA_CHG PR224 1 2 1 2 4 20 CHG_LGATE
4.7K_0402_5%~D

200K_0402_5%~D PC225 PR225 EAO LGATE PR227 +VCHGR

PC226
<43> CHARGER_SMBCLK
56P_0402_50V8~D
1

2200P_0402_50V7K~D 7.5K_0402_5%~D 0.01_1206_1%~D

2
PL17
PR226

<43> CHARGER_SMBDAT
2

MAX8731_REF @ 1+VCHGR_L
PC227

3 19 2 4 1
VREF PGND 5.6UH 20% FDVE1040-H-5R6M=P3_9.2A_20%~D
18
PC228 PR228 CSOP
3 2

1.8K_1206_5%~D
2

<23> MAX8731_IINP

1
120P_0402_50VNPO~D 1 2 7 17

10U_1206_25V6M~D

10U_1206_25V6M~D

10U_1206_25V6M~D
0.1U_0603_25V7K~D
CE CSON

5
6
7
8
10K_0402_5%~D

PR231
1 2

0_0402_5%~D

0_0402_5%~D
8.45K_0402_1%~D

220P_0402_50V8J~D
1

1
15 VFB 1 PR230 2 +VCHGR PC230

2
0.1U_0402_10V7K~D
VFB
1

1
SI4812BDY-T1-GE3_SO8~D
1000P_0603_50V7K~D
PR229

PC229

12
1U_0603_10V6K~D

GND
0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

0.01U_0402_25V7K~D

100_0402_5%~D @

PR232

PR233

PC236

PC237

PC238

PC239
16

2
NC
1

PQ33
PC231

PC232

PC233

PC234

PC235

29
2

2
TP

2
@ 4 PR234
2

2
4.7_1206_5%~D
2

@ @ @ @ BQ24747RHDR_QFN28_5X5~D
PJP34

1
PC240 D
1 2

3
2
1

1
0.1U_0603_25V7K~D PC241 0.1U_0603_25V7K~D 2
1 2 1 2 1 2 G
PAD-OPEN1x1m S

3
GNDA_CHG 0.1U_0603_25V7K~D @ PC293
GNDA_CHG GNDA_CHG GNDA_CHG
Maximum charging current is 6.3A ACAV_IN @
B B
PQ34
MAX8731_REF RHU002N06_SOT323-3~D
+3.3V_ALW
+DC_IN MAX8731_REF
PR236

10K_0402_1%~D
1M_0402_1%~D

47K_0402_1%~D
232K_0402_1%~D
1

1
+5V_ALW +5V_ALW 1 2
DYN_TUR_CURRENT_SET#

100K_0402_1%~D
1
PR235

PR237

PR239
+5V_ALW
DYN_TUR_PWR_VO

PR238
90W High
2

+3.3V_ALW2
100P_0402_50V8J~D

2
0.01U_0402_25V7K~D

PR809

2
1

8
221K_0402_1%~D PU12A @
1
@ PC244

PC245

3 @ PR240
130W Low

P
PR810 +
1 1 2
2

PR808 O ACAV_IN_NB <42,43,63>


@ 0_0402_5%~D 2

22.6K_0402_1%~D

41.2K_0402_1%~D
100P_0402_50V8J~D
-

G
1.8M_0402_1% 0_0402_5%~D

42.2K_0402_1%~D

100P_0402_50V8J~D
1

1
1 2 LM393DR_SO8~D
2

4
1

1
PR803 PC242

PR241

PC243

PR243
150K_0402_1%~D PR805 PR807

PR242
20K_0402_1%~D 0_0402_5%~D 2

2
8

RHU002N06_SOT323-3~D

@
2

2
1

MAX8731_IINP D
1 2 1 2 5
P

2
@ PR801 +
PQ802

7 2
ICOUT O
1 2ICREF 1 2 6 G
-
G

S
3

649K_0402_1%~D PR806 0_0402_5%~D PU12B


4
220P_0402_50V8J~D

LM393DR_SO8~D
1

1
PC802

PR802
162K_0402_1%~D PR223 PR220 PC214 PC292 PR209 PR210 PC213
2

@
100P_0402_50V8J~D
2

Main 1 ohm @ @ @ 0 ohm 0 ohm 0.1u


113K_0402_1%~D

1
RHU002N06_SOT323-3~D

PR804

PC801
1

D
PQ801

A DYN_TUR_CURRNT_SET# 2
2nd 0 ohm 4.7 ohm 1u 0.1u 10 ohm 10 ohm 0.047u A
2

G
1

<57> S
3

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title

Adapter Protection Circuit for Turbo Mode THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger

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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6592
Date: Tuesday, January 18, 2011 Sheet 60 of 67
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D
VCCSA D
Thermal Design Current : 4.2A
Peak current : 6A
OCP_MIN :7.2A

PJP35
+VCCSA_PWR_SRC 1 2 +PWR_SRC
PAD-OPEN 43X118

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D

2200P_0402_50V7K~D
+5V_RUN
1 1 2

1
PC246

PC247

PC249
PC248
2
PC250 2 2 1

1
1U_0603_10V6K~D
1 2 PR244
2.2_0805_5%~D

+VCCSA_LGATE

5
6
7
8
+VCCSA_VCC

AO4466L_SO8~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D

PQ35
1

1
PC251

PC252
4

2
2

20
1
PU13

PVCC
LGATE

3
2
1
GNDA_VCCSA GNDA_VCCSA
PL18
2 19 1UH 20% FDVE0630-H-1R0M=P3 11.9A
PGND VCC PR245
C 2 1 +VCCSA_P C
2.2_0603_1%~D PC253

330U_D2_2VY_R7M~D
GNDA_VCCSA 3 18 +VCCSA_BT 1 2 1 2

10U_0805_6.3V6M~D

10U_0805_6.3V6M~D
2200P_0402_50V7K~D
0.1U_0402_10V7K~D
GND BOOT
1

5
6
7
8

1
0.22U_0603_10V7K~D @ PC254

1
+VCCSA_RTN +VCCSA_UGATE 1000P_0603_50V7K~D +

PC255
4 17

10_0402_5%~D
AO4406AL_SO8~D
RTN UGATE

PR246

PC258

PC256

PC257

PC260
1 2

2
VCCSA_VID_1 +VCCSA_PHASE 2

PQ36
5 16 PR247
VID1 PHASE @ PR248
@PR248
4 12.7K_0402_1%~D

2
2.2_1206_1%~D
+VCCSA_VID0 6 15 +VCCSA_EN +VCCSA_LGATE
PC261

1
+1.05V_RUN VID0 EN

2
2 1

3
2
1
+VCCSA_SREF 7 14 +VCCSA_PWRGD
SREF PGOOD .015U_0603_25V7K~D
.068U_0603_16V7~D

@ PR251 PR253
2

PR250 +VCCSA_SET0 8 13 +VCCSA_FSEL 1 2 1.05V_VTTPWRGD <43,58>


SET0 FSEL

1
@PR249
@ PR249 113K_0402_1%~D
PC262

2 1

0_0402_5%~D
0_0402_5%~D +VCCSA_SENSE <11>
0_0402_5%~D

PR252
1

+VCCSA_SET1 9 12 @ PR254
2

SET1 VO CPU_VTT_ON <42,58> 0_0402_5%~D


1 2
OCSET
1

1
0_0402_5%~D 2 1
FB

10_0402_5%~D
<11> VCCSA_VID_1 +3.3V_RUN
1

GNDA_VCCSA PR255

PR257
PR256 ISL95870AHRUZ_UTQFN20_1P8X3P2 10K_0402_5%~D
10

11
2

140K_0402_1%~D GNDA_VCCSA @ PR258


PR295 1 2 VCCSAPWROK <43>

2
+VCCSA_FB

1K_0402_5%~D
2

0_0402_5%~D
@ PR260 +VCCSA_OCSET
PR259
1

4.12K_0402_1%~D
1 2 1 2
PR262
47.5K_0402_1%~D
0_0402_5%~D
1

+VCCSA_VO 2 1
+1.05V_RUN
PR261

GNDA_VCCSA
B 12.7K_0402_1%~D B
2
2

@ PR263
10K_0402_5%~D
1

PR265
2 1 +GND_VCC_SA <11>
2

PR266 0_0402_5%~D
1

1K_0402_5%~D
@ PR267 0.8_VCCPWROK
4.12K_0402_1%~D * connect to U50 Pin 2 (Vih => 2.31V)
1

GNDA_VCCSA

A A

PJP37
2 1
0.9V 0.8V
PAD-OPEN1x1m
VCCSA_VID_1 0 1
PJP38
+VCCSA_P 1 2 +VCC_SA DELL CONFIDENTIAL/PROPRIETARY
GNDA_VCCSA
PAD-OPEN 4x4m
Compal Electronics, Inc.
Title
output voltage adjustable network
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ISL95870A 0.8V_VCC_SA

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AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6592
Date: Tuesday, January 18, 2011 Sheet 61 of 67
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5 4 3 2 1

PQ39 PD17

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SI4835DDY-T1-GE3_SO8~D 2
1 8 MPBATT+ PR283 1
2 7 1 8 330K_0402_5%~D 3
+VCHGR S D
3 6 2 7
S D PDS5100H-13_POWERDI5-3~D ES2AA-13-F SMA
5 3 6 1 2

0.1U_0603_25V7K~D
S D PQ41 PD16
4 5

100K_0402_5%~D
G D

1
8 1 2 1

390K_0402_5%~D

620K_0402_5%~D
4
D S

1
FDS6679AZ_G_SO8~D

PR270

PC264

PR271

PR272
7 2

0.47U_0805_25V7K~D
PQ40 MPBATT_IN_SS D S
6 3 PQ37
D S
5 4

2
D G
8 1

2
PR274 FDS6679AZ_G_SO8~D D S
7 2
33_0603_5%~D D S
+DOCK_PWR_BAR 6 3
D S

1
PD18

PC263
1 2 5 4
D G

2N7002DW-T/R7_SOT363-6~D
RB751V-40GTE-17_SOD323~D

1
2 1

10K_0402_5%~D

2
0.22U_0603_25V7K~D
3
PR273 FDS6679AZ_G_SO8~D

2
D D
PD19

1
2N7002DW-T/R7_SOT363-6~D

PQ42B
RB751V-40GTE-17_SOD323~D PR268

PC265
390K_0402_5%~D
PR276
2 5 2 1 330K_0402_5%~D

2
2

1
PR269

499K_0402_1%~D
4

1
6

PR275
0_0402_5%~D

2
PQ42A
@
CHARGE_MODULE_BATT @ PR277

1
1 2 2

2
PR278

STSTART_DCBLOCK_GC
0_0402_5%~D 330K_0402_5%~D
1

PQ45 1 2 PD20
FDS6679AZ_G_SO8~D 2
PQ44 PBATT+ 1 8 1
SI4835DDY-T1-GE3_SO8~D S D
2 7 3
S D PBATT_IN_SS
1 8 3 6
S D PDS5100H-13_POWERDI5-3~D
2 7 4 5

390K_0402_5%~D
+VCHGR G D

1
3 6 PQ46

620K_0402_5%~D
1

PR282
5 8 1
0.1U_0603_25V7K~D

D S

PR281
7 2
100K_0402_5%~D

D S
2

6 3 +PWR_SRC
4

D S
1
PR279

PC266

5 4

2200P_0402_50V7K~D

0.1U_0603_25V7K~D
PR284 D G

2
2
33_0603_5%~D FDS6679AZ_G_SO8~D
2

1
PR297

PC267

PC268
1 2
1

20K_0402_1%~D

3
2N7002DW-T/R7_SOT363-6~D
PD21

2
1 RB751V-40GTE-17_SOD323~D

0.22U_0603_25V7K~D
2 1
5
1

1
PQ49B

PC270
10K_0402_5%~D

390K_0402_5%~D
1
PD23
PR286

4
2
2N7002DW-T/R7_SOT363-6~D

RB751V-40GTE-17_SOD323~D

PR291

2
6
2N7002DW-T/R7_SOT363-6~D

PR280 2 1
20K_0402_1%~D
2

PQ47A

1
2N7002DW-T/R7_SOT363-6~D

C 2 C

499K_0402_1%~D
1
6

2N7002DW-T/R7_SOT363-6~D

PR292
PQ49A

6
PQ47B

2N7002DW-T/R7_SOT363-6~D
@ PR293
CHARGE_PBATT 1 2 2 5

2
3
PQ48A

2N7002DW-T/R7_SOT363-6~D
6
0_0402_5%~D 2
1

PQ48B
@ PR287
@ PR323 0_0402_5%~D

PQ50A
51 2 MODULE_ON
1
2

RB751V-40GTE-17_SOD323~D
0_0402_5%~D

PD30 2 1 2 DEFAULT_OVRDE
RB751V-40GTE-17_SOD323~D

RB751V-40GTE-17_SOD323~D

0_0402_5%~D
PR285

499K_0402_1%~D
4

1
RB751V-40GTE-17_SOD323~D

2 1

1
2

PR289
@
PD22
1

RB751V-40GTE-17_SOD323~D
RB751V-40GTE-17_SOD323~D
PD24

PD25

PD26

@
PD31

2
@ PR355 MPBATT+
1

PBATT+
PD27
CHARGE_EN 1 2 2 1
200K_0402_1%~D
1

0_0402_5%~D 510K_0402_5%~D
1

RB751V-40GTE-17_SOD323~D
1
2N7002DW-T/R7_SOT363-6~D

2N7002DW-T/R7_SOT363-6~D
PR290

PR471

SLICE_BAT_ON
@ PR296
3
PQ54B

0_0402_5%~D
2

5
2
2N7002DW-T/R7_SOT363-6~D

PQ50B

@ PR473 100K_0402_5%~D
2
6

5 1 2
2 4
0_0402_5%~D
PQ54A

@ PR294
4
PR298

1 2 2 SLICE_BAT_PRES# @ PR472
DEFAULT_OVRDE 1 2 MODULE_BATT_PRES#
0_0402_5%~D
1
1

@ 0_0402_5%~D
499K_0402_1%~D

PBATT+
1
PR288

PBAT_PRES# +DOCK_PWR_BAR 1 2
@ @ PR299 0_0402_5%~D @ PR301
2

2
1 2 0_0402_5%~D
B +DC_IN_SS @ PR306
B
@ PR302 0_0402_5%~D
0_0402_5%~D
1

1 2
+CHGR_DC_IN
@ PR305 0_0402_5%~D

1
<55>
CHGVR_DCIN

DK_PWRBAR

+DC_IN 1 2 CD3301_DCIN
DC_IN_SS

PR307 47_0805_5%~D
1

PC271

0.1U_0603_50V4Z~D
2

+5V_ALW
P50ALW
36
35
34
33
32
31
30
29
28

1 2
PU14 @ PR309 0_0402_5%~D
<47> SOFT_START_GC
1 2
NC
CHARGERVR_DCIN

DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
DC_IN_SS

+3.3V_ALW2
CD_PBATT_OFF 1 2 SLICE_BAT_ON <42>
PR310 100K_0402_5%~D @ PR311 0_0402_5%~D
<41> ACAV_DOCK_SRC# 1 2ACAVDK_SRC
@ PR312 0_0402_5%~D 1 2 DOCK_AC_OFF <41,42>
1 27 @ PR313 0_0402_5%~D
DC_IN P50ALW
2 26
ERC1 SS_GC PBATT_OFF DK_AC_OFF
+SDC_IN 1 2 3 25 1 2
ERC1 DK_AC_OFF_EN
@ PR314 0_0402_5%~D 4 24 1 2 3301_ACAV_IN_NB ACAV_IN_NB <42,43,55>
ACAVDK_SRC ACAV_IN_NB 1M_0402_5%~D
5 23 @ PR316
0_0402_5%~D
CD3301_SDC_IN GND GND DK_AC_OFF_EN PR315
6 22 1 2 DOCK_AC_OFF_EC <42>
SDC_IN DK_AC_OFF_EN SL_BAT_PRES#
7 21 @ PR317 0_0402_5%~D
<55> DC_BLOCK_GC ACAVIN DC_BLK_GC SL_BAT_PRES# BLKNG_MOSFET_GC
8 20
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC
19
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR

<23,43,55> ACAV_IN 1 2
SS_DCBLK_GC

@ PR318 0_0402_5%~D
DK_CSS_GC

1 2 SLICE_BAT_PRES# <41,42,47>
PWR_SRC
RB751V-40GTE-17_SOD323~D

@ PR320 0_0402_5%~D
CSS_GC

P33ALW
RB751V-40GTE-17_SOD323~D

37
TP
1

ERC3
ERC2

1 2 1 2
GND

+3.3V_ALW2 +NBDOCK_DC_IN_SS
PD29

PD28

@ PR319 0_0402_5%~D @ PR322 0_0402_5%~D


CD3301RHHR_QFN36_6X6~D
10
11
12
13
14
15
16
17
18

A PQ51 A
2

0.1U_0603_25V7K~D

FDN338P_G_NL_SOT23-3~D <55> CSS_GC P33ALW 1 2


ERC2

<55> DK_CSS_GC +3.3V_ALW


@ PR324 0_0402_5%~D
1

ERC3
PC273

1 3
1

DOCK_SMB_ALERT#
<41,42,47>
EN_DK_PWRBAR 1 2 EN_DOCK_PWR_BAR <42>
2

0.047U_0603_25V7K~D

@ PR325
DELL CONFIDENTIAL/PROPRIETARY
2

0_0402_5%~D
2

0.1U_0402_25V4Z~D

1 2
PC274

SLICE_BAT_PRES# 1 2
1

1M_0402_5%~D
STSTART_DCBLOCK_GC
Compal Electronics, Inc.
PC275

<41,42,47> @ PR321 0_0402_5%~D


@ PR326
1

Title
2

PC272 @ 3301_PWRSRC PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
1500P_0402_7K~D
1
@ PR327
2
0_0402_5%~D
+PWR_SRC TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
2

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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.4
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-6592
Date: Tuesday, January 18, 2011 Sheet 62 of 67
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D D

GPU_CORE
PJP39
+GPU_PWR_SRC 1 2 +PWR_SRC
Thermal Design Current : 15.615A
PAD-OPEN 43X118 Peak current : 20.2A

10U_1206_25V6M~D

10U_1206_25V6M~D

0.1U_0603_25V7K~D

2200P_0402_50V7K~D
+5V_RUN
1 1 2
OCP min : 24.2A

1
PC276

PC277

PC279
PC278
2
PC280 2 2 1

1
1U_0603_10V6K~D
1 2 PR328
2.2_0805_5%~D

3
GPU_CORE_VCC

GPU_LGATE

D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1

1
PC281

PC282

AON6414AL 1N DFN
PQ52
2

2
2 G

20
1

S
PU15

PVCC
LGATE

1
GNDA_GPU_CORE GNDA_GPU_CORE PL19
0.56UH +-20% MPC1040LR56C 23A
2 19
PGND VCC PR329
C 4 1 +VCC_GPU_CORE C
2.2_0603_1%~D PC283

2200P_0402_50V7K~D
470U_D2_2VM_R4.5M~D

470U_D2_2VM_R4.5M~D
GNDA_GPU_CORE 3 18 GPU_BOOT1 2 1 2 3 2

0.1U_0402_10V7K~D
GND BOOT
1 1

1
0.22U_0603_10V7K~D PC284

1
GPU_UGATE 1000P_0603_50V7K~D + +

PQ53

PC286

PC287

PC288
4 17

AON6704L
D

10_0402_5%~D
RTN UGATE

PR330

PC285
2 2

2
2

2
GPU_VID1 5 16 GPU_PHASE PR332 2 2

1_1206_1%~D
VID1 PHASE
2 5.9K_0402_1%~D

2
G

PR331
GPU_VID0 6 15 GPU_EN GPU_LGATE
PC289

1
VID0 EN

S
+3.3V_RUN

1
2 1

1
SREF 7 14 GPU_PWRGD
SREF PGOOD 0.15U_0603_16V7K~D
.056U_0603_16V7~D

1
2

PR334 SET0 8 13 1 PR335 2 GNDA_GPU_CORE PR336


@ PR333 30.1K_0402_1%~D SET0 FSEL GPU_OCSET
PC290

1 2 GPU_VDD_SENSE <49>
10K_0402_5%~D 0_0402_5%~D
1

SET1 9 12 0_0402_5%~D
2

SET1 VO
OCSET
1

@ PR337
PR339
2 1
FB

<47> GPU_VID_1
1

GNDA_GPU_CORE GPU_VO 2 1
0_0402_5%~D PR338
10

11

71.5K_0402_1%~D ISL95870AHRUZ_UTQFN20_1P8X3P2
5.9K_0402_1%~D
2

PR340
2

10K_0402_5%~D PR403
2 1
38.3K_0402_1%~D
412K_0402_1%~D
1

PR344
PR341

GPU_FB 2 1
+3.3V_RUN 3.09K_0402_1%~D
2

2
B B

PR346 PR402
2

GNDA_GPU_CORE 5.11K_0402_1%~D 10_0402_5%~D


PR343
10K_0402_5%~D
2

1
1

@ PR345
<47> GPU_VID_0 2 1
GNDA_GPU_CORE
0_0402_5%~D
2

@ PR347
10K_0402_5%~D
1

PR400 PR474
2 1 1 2 GPU_GND_SENSE <49>
3.09K_0402_1%~D 0_0402_5%~D
1

PR401
5.11K_0402_1%~D
2

+3.3V_RUN
2

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