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etching (to make the surface flat). A typical net in an integrated circuit has a driver (source or drain)
which is then connected to a receiver gate electrode over a thin gate dielectric. The modern wafer
processing uses plasma etching techniques which apart from its various benefits over wet etching
techniques also has a lot of unwanted results like accumulation of charges. Now the gate dielectric is
so thin that there is always the danger of it getting damaged due to potentials higher than its
breakdown potential. This phenomenon is known as antenna effect and the FAB has its own set of
rules (which differs with technology node) to avoid such antenna violations while designing the
integrated circuit.
n my PNR script I define the antenna rules (from a file provided by the fab), specifying that the max
MET4 to gate area ratio should be 400. At the end of my finishing section after inserting redundant
vias and re-running route_opt, I load these antenna rules and run check_routes. It detects no
antenna violations.
Straight after I run signoff_check_drc with the runset provided by the fab. It detects a couple of
antenna violations on MET4. It thinks the ratios are ~530. All errors are in the same area of the
design, 4 are all right next to each other, 2 a bit further away but still close. all with MET4 (out of 6
metal layers, MET1-4, METTP, METTPL).
I'm a bit lost here. I'm pretty sure if my pnr script detected the violations it would be able to fix
them, but since it doesn't detect them I'm not sure how to fix them. I could try to manually cut the
routes, but I'm sure there's a better way.
I've compared the antenna rules in my pnr script (and run report_antenna_rules, to check they
applied correctly), with the runset, but I don't really know how to make sense of the runset, the
values given (400.0) are the same, but maybe there's some subtlety I'm missing, for example I'm not
sure how to check the -mode and -diode_mode parameters from my pnr script against the runset.
Both these rules came from the fab so they <should> be correct.
The affected nets are all internal nets named stuff like n2223, so I don't think it's anything to do with
my IO pins, although all 6 of the violations are pretty close to those pins.
In my PNR script if I reduce the max antenna ratio for MET4 to 1 (from 400) and then re-run
check_routes, it still gives no error, this sort of suggests it's not really running the checks at all.
However the output to check_routes does suggest it's using the new value.
Antenna/diode mode:
..
..
..
MergeGate == true
...
Warning: Skipping antenna analysis for net blah. The pin blah on cell my_design does not have
enough gate area information. (ZRT-311).
I'd been ignoring that (temporarily) as it didn't seem related to the nets specified by ICV as being the
problem. However two of those warnings mapped to the nets with long paths on MET4.
The solution was to tell the tools to ignore gate sizes on terminals:
My understanding of this is ICC2 doesn't know if this input net is connected to another gate outside
of my block. And so it just refuses to do any analysis on that net. I don't really get why it doesn't just
assume there's nothing out there and warn you that it's doing that, but ...