Information Technology

NIST Institute of Science & Technology (AUTONOMOUS)

(Approved by AICTE, New Delhi, Affiliated to BPUT: Rourkela)
www.nist.edu INSTITUTE PARK, PALLUR HILLS, BERHAMPUR, ODISHA -761 008

QUIZ-1
Sub- Digital Electronics (19CS3ES03T) Date: 16-11-2022
B. Tech, 3rd Semester Duration: 30 Minutes Full Marks: 50
Student Name: Student Roll no.

No Of Question Level Wise

CO Wise Marks
20 CO-3, 0 CO-4, 0
10 CO-2,
0 17.5 CO-1,
32.5
CO-1 CO-2 CO-3 CO-4

Answer all Questions.

QNo. CO* Level (1) Remembering (2) Understanding (3) Applying (4) Analyzing Marks
(5) Evaluating 6) Creating
1 1 1 Which gate is known as equivalence gate?
(a) NAND (b) EX-OR (c) NOR (d) EX- 2.5
NOR
2 1 2 The invalid codes in a BCD representation are
2.5
(a) 1010 -1111 (b) 0000 -1001 (c) 1001 -10010 (d) 0000 -1111
3 1 2 In Gray code each successive code differs from its preceding code by
(a) 1-bit (b) 2-bits (c) 0-bits (d) 4-bits 2.5

4 1 3 A Boolean expression A+AB+ABC+ABCD+ABCDE+.......... will be reduced to

2.5
(a) 1 (b) 0 (c) A (d) AB
5 1 2 In a 4 variable K-Map, if the function contains all Min-terms, then it will be reduced
to 2.5
(a) 0 (b)one Min-term (c) 16 Max-terms (d) 1
6 1 2 Product of all the Maxterms in a 2n-variables function is
(a) 0 (b) 1 (c) 2n (d) 2n-1 2.5

7 1 4 The minimum no. of NAND gates required to implement a EX-OR gate is

(a) 4 (b) 3 (c) 5 (d) 2.5
6
8 1 2 The values of A, B, C that make the product term ABC equal to 1 are
(a) 0,0,1 (b) 0,1,0 (c) 1,1,1 (d) 2.5
1,0,1
9 1 2 For odd number of A’s, A  A  A...  A = ____
(a) 1 (b) A (c) A’ (d) (A ʘ B)’ 2.5

10 1 2 The dual function for P= x’y + xy’ will be

(a) x+y (b) x’+y’ (c) x ʘ y (d) (x EX-OR y) 2.5

11 1 2 The code used for labeling the cells of a K-Map is

2.5
(a) Gray code (b) Excess-3 code (c) BCD code (d) 2-4-2-1 code
12 1 2 In a 16 inputs NAND gate, if one of the input is connected to ‘0’ (GND) and the 2.5

• CO1: Acquire basic knowledge about binary codes and the design of simplified circuits using
Boolean laws and mapping methods.
• CO2: Understand the behavior of combinational arithmetic and logic circuits for development of
complex digital systems.
 Information Technology
NIST Institute of Science & Technology (AUTONOMOUS)
(Approved by AICTE, New Delhi, Affiliated to BPUT: Rourkela)
www.nist.edu INSTITUTE PARK, PALLUR HILLS, BERHAMPUR, ODISHA -761 008

remaining inputs are ‘B’, it’s output will be

(a) B AND 0 (b) 0 (c) 1 (d) B
13 1 2 F=p’q+q’r+p’q’r’+pqr is to be implemented using AND-OR-NOT logic. The no. of
levels used for this will be 2.5
(a) 5 (b) 3 (c) 4 (d) None of these
14 2 1 In Combinational logic circuit, output depends upon
2.5
(a) Present and past inputs (b) Present inputs only (c) Binary 1 and 0 (d) None
15 2 4 If 5 single-bit binary numbers are to be added serially, the no. of Full adders and Half
adders required will be 2.5
(a) 2, 3 (b) 1, 3 (c) 1,4 (d) 2,0
16 2 3 The sum and carry of Half adder can be implemented using
(a) Equivalence, AND (b) OR-NAND-NOR (c) EX-NOR, AND gate (d) OR-AND- 2.5
NOT logic
17 2 2 The Sum function of the Full adder in ∏ form is
2.5
(a) ∏M(1,2,4,7) (b) ∏M(0,3,5,6) (c) ∑m(1,2,5,6) (d) ∑m(1,2,4,7)

18 2 2 A Full adder can be designed by using

(a) 2 Half adders and one AND gate (b) 2 Half subtractors and one OR gate (c) 5 logic 2.5
gates (d) 2 Half adders only
19 2 3 999 single-bit binary numbers having all their values ‘1’ are added using half adders
and full adders only. The result will be of
2.5
(a) 2-bits (b) 10 -bits (c) 4-bits (d) 3 -bits

20 2 3 The no. of levels present in Full adder(FA) will be

2.5
(a) More than that of HA (b) Both options a & c (c) 3 (d) 2

• CO1: Acquire basic knowledge about binary codes and the design of simplified circuits using
Boolean laws and mapping methods.
• CO2: Understand the behavior of combinational arithmetic and logic circuits for development of
complex digital systems.