Scientech 110

ST110
Universal Development Platform

Scientech 110
Product Tutorial
Ver. 1.1
Designed & Manufactured by-

An ISO 9001:2008 company
Scientech Technologies Pvt. Ltd.
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+ 91-731 4211100, : info@scientech.bz , : www.ScientechWolrd.com
Scientech Technologies Pvt. Ltd. 1

Scientech 110
Universal Development Platform

Scientech 110
Table of Contents
1. Safety Instructions 3
2. Overview 4
3. Features 5
4. Technical Specifications 6
5. Introduction to FPGA 8
6. Introduction to CPLD 15
7. Mode Select 18
8. Xilinx Web Pack Introduction 19
9. Design Procedure for Web Pack 20
10. Summary 42
11. Pin Detail Scientech 110 daughter Cards (FPGA & CPLD) 43
12. VLSI Lab 53
• VHDL Lab 54
• Verilog Lab 66
13. Universal Development Platform Lab 117
14. Data Sheet 118
15. VLSI Design Cycle 155
16. Appendix 160
17. Warranty 168
18. List of Accessories 168

Scientech 110
Safety Instructions
Read the following safety instructions carefully before operating the product.
To avoid any personal injury, or damage to the product, or any products connected to
it;
Do not operate the instrument if you suspect any damage within.
The instrument should be serviced by qualified personnel only.
For your Safety:
Use proper Mains cord : Use only the mains cord designed for this product.
Ensure that the mains cord is suitable for your
country.
Ground the Instrument : This product is grounded through the protective earth
conductor of the mains cord. To avoid electric shock
the grounding conductor must be connected to the
earth ground. Before making connections to the input
terminals, ensure that the instrument is properly
grounded.
Observe Terminal Ratings : To avoid fire or shock hazards, observe all ratings and
marks on the instrument.
Use only the proper Fuse : Use the fuse type and rating specified for this product.
Use in proper Atmosphere : Please refer to operating conditions given in the

manual.
1. Do not operate in wet / damp conditions.
2. Do not operate in an explosive atmosphere.
3. Keep the product dust free, clean and dry.

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Overview
Programmable Logic Devices are playing major role in system design due to their
flexible architecture; reprogram ability and fast time to market resulting in a smaller
design-cycle period. Also lower design risk is involved with the use of PLDs. PLDs
provide greater design flexibility because of their flexible architecture, allowing small
design changes without any PCB changes. Hence they are more appreciated day by
day.
The Universal Development Platform Scientech 110 is an ideal platform to
implement and test design both for the beginner and the expert. This platform makes
it execute and verify basic digital experiments using VHDL and Verilog, the standard
Hardware Description Languages. User can write their VHDL code and verify the
result on this platform using FPGA, CPLD, Coolrunner CPLD, or ARM7 controller .
It is “assembled ready” for various interfaces that include ADC/DAC, display,
SRAM, serial communication etc.

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Features
• Xilinx CPLD Daughter Card
• Xilinx Virtex 2 FGPA Daughter Card (Optional)
• Xilinx Cool Runner CPLD Daughter Card (optional)
• Xilinx Spartan 3E FPGA (Optional)
• Altera cyclone II FPGA (Optional)
• ARM7 Daughter Card (optional)
• 16 bit logic input
• 16 bit logic output
• ADC interface
• DAC interface
• SRAM interface
• 4 Digit seven segment display
• keypad interface
• 16X2 LCD interface
• Push Buttons
• USB interface
• Serial communication interface
• VGA interface
• PS2 interface
• External I/Os for user interface applications

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Technical Specifications
Mother Board Specifications:-
• On board : +5V, 3.3V, 2.5V,1.8V supply

• One LCD display : 16 X 2 Character LCD
• 7 Segment : 4 digits
• 8 Channel ADC : 8-bit Resolution
• Push button :4
• Output LEDs : 16
• DIP switches : 16
• One-20 pin connectors : For external input outputs
• HEX keypad :1
• DAC : 8-bit Resolution
• Memory : SRAM 32KB
• Peripheral Interface : Serial, PS2, VGA, USB etc.
FPGA Daughter Card:

– Xilinx Family : Spartan 3, XC3S400PQ208
– Device density : 400k gates,
– On board : 8 MHz crystal
– Master reset Key : For hardware reset
– On board : EPROM for FPGA boot.
– Configuration Method : JTAG / Boundary scan interface
: PROM interface
CPLD Daughter Card:
– Xilinx Family : CPLD, XC95108TQ100
– Device density : 2400 gates, 108 macro cells,
– On board : 8 MHz crystal
– Configuration Method : JTAG interface (boundary scan)

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Software: - Xilinx Webpack Ver. / 10.1Ver.

Cool Runner CPLD Daughter Card:
• Xilinx Family:
Cool Runner: XCR3128
Package: VQ100
• Device Density:
128 macrocells
Configuration Methods:
IEEE 1149 JTAG Interface (Boundary Scan)
Spartan3E FPGA Daughter Card: (Optional)
Xilinx Family : Spartan 3E, XC3S500EPQ208
Device density : 500k gates
On board : 8 MHz crystal
Master reset Key : For hardware reset
On board : EPROM for FPGA boot.
Configuration Method : JTAG / Boundary scan interface,
: PROM interface
ARM7 Daughter Card:
• Device Family:
Philips Semiconductor: LPC2292/94
Package: LQFP144
• Device Density:
16/32-bit ARM microcontroller
256 KB flash memory
Configuration Methods:
JTAG Interface
RS232 Interface
Peripheral Card
Ø RS232(serial port)
Ø RS232 port for ARM programming
Ø VGA port
Ø PS2 port
Ø USB port (Serial to USB)

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Altera Cyclone II FPGA Daughter Card

Ø Device - EP2C8Q208C8
Ø Family - Cyclone II
Ø Number of logic elements/cells -8250
Ø Number of free dedicated input -5
Ø Number of clocks -2
Ø USB Blaster configuration Cable
Ø Quartus -II web adition

Scientech 110
VLSI
Introduction to FPGA (Field-Programmable Gate Arrays)
A Field-Programmable Gate Array is a semiconducter device containing
programmable logic components called "logic blocks", and programmable
interconnects. Logic blocks can be programmed to perform the function of basic logic
gates such as AND, and XOR, or more complex combinational functions such as
Decoders or Mathematical Functions. In most FPGAs, the logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of
memory.
A hierarchy of programmable interconnects allows logic blocks to be interconnected
as needed by the system designer, somewhat like a one-chip programmable
breadboard. Logic blocks and interconnects can be programmed by the customer or
designer, after the FPGA is manufactured, to implement any logical function—hence
the name "Field-Programmable".
FPGAs are usually slower than their “Application Specific Integrated Circuit(ASIC)
counterparts, cannot handle as complex a design, and draw more power (for any given
semiconducter process). But their advantages include a shorter time to market, ability
to re-program in the field to fix bugs, and lower engineering costs. Vendors can sell
cheaper, less flexible versions of their FPGAs which cannot be modified after the
design is committed. The designs are developed on regular FPGAs and then migrated
into a fixed version that more resembles an ASIC.
"Complex Programmable Logic Devices" (CPLDs) are an alternative for simpler
designs. They also retain their programming over powerdowns.
To configure ("program") an FPGA or CPLD you specify how you want the chip to
work with a logic circuit diagram or a source code using a Hardware Description
Language (HDL). The HDL form might be easier to work with when handling large
structures because it is possible to just specify them numerically rather than having to
draw every piece by hand. On the other hand, schematic entry might allow for a more
tight specification of what you want.
Going from schematic/HDL source files to actual configuration : The source files are
fed to a software suite from the FPGA/CPLD vendor that through different steps will
produce a file. This file is then transferred to the FPGA/CPLD via a serial interface
(JTAG) interface or to external memory device like an EEPROM.
Mask-Programmable Gate Arrays are fabricated in a foundry, where final layers of
metal customize the wafer to the specifications of the end user. FPGAs are sold as
fully fabricated and tested generic products. Their functionality is determined by
programming done in the field by the customer and/or end user. FPGAs allow
designers to turn a design into working silicon in a matter of minutes, making rapid
prototyping a reality.
FPGAs are distinguished on the basis of several features: architecture, number of
gates, mechanism for programming, program volatility, the granularity and
robustness of a functional logical unit, physical size (footprint), pin out, time-to-

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prototype, speed, power, and the availability of internal resources for connectivity [9,
10]. We will focus on the dominant technology: SRAM-based FPGAs, which lose
their programming when power is removed from the part.
SRAM-based FPGAs have a fixed architecture that is programmed in the field for a
particular application. A typical, fundamental architecture, as shown in Figure 1,
consists of (1) an array of programmable functional units (FUs) for implementing
combinational
FPGA Architecture
Figure 1
and sequential logic, (2) a fixed, but programmable, interconnection fabric, which es-
tablishes the routing of signals, (3) a configuration memory, which programs the
functionality of the device, and (4) I/O resources, which provide an interface between
the device and its environment. The performance and density of FPGAs have
advanced with improvements in process technology. Today's leading-edge devices
include block memory as well as distributed memory, robust interconnection fabrics,
global signals for high-speed synchronous operation, and programmable I/O resources
matching a variety of interface standards.
Volatile FPGAs are configured by a program that can be downloaded and stored in
static CMOS memory, called a Configuration Memory. The contents of the static
RAM are applied to the control lines of static CMOS transmission gates and other
devices to:
(1) Program the functionality of the functional units,
(2) Customize configurable features, such as slew rate,
(3) Establish connectivity between functional units, and
(4) Configure I/O/bidirectional ports of the device.

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The configuration program is downloaded to the FPGA from either a host machine or
from an on-board PROM. When power is removed from the device the program
stored in memory is lost, and the device must be reprogrammed before it can be used
again.
The volatility of a stored-program FPGA is a double-edged sword-the FPGA must be
reprogrammed in the event that power is disrupted, but the same generic part can
serve a boundless variety of applications, and it can be reconfigured on the same
circuit board under the control of a processor. One of the programs that can be
executed by an FPGA can even test the host system in which it is embedded. The ease
of reprogramming a stored-program FPGA supports rapid-prototyping, enabling
design teams to compete effectively in an environment characterized by narrow and
ever-shrinking windows of opportunity. Tune-to-market is critical in many designs,
and FPGAs provide a path to early entry. FPGAs can be reconfigured remotely, via
the Internet, allowing designers to repair, enhance, upgrade, or completely reconfigure
a device in the field.
XILINX Spartan II FPGAs :
Aside from improvements in speed (200 MHz I/O switching frequency), density (up
to 200,000 system gates), and operating voltage (2.5 V), four other features
distinguish the Spartan II devices from the Spartan devices: (1) on-chip block
memory, (2) a novel architecture, (3) support for multiple I/O standards, and (4)
delay-locked loops.
The Spartan II device family, manufactured in 0.22/0.18 11m CMOS technology with
six layers of metal for interconnect, incorporates configurable block memory in
addition to the distributed memory of the previous generations of devices, and the
block memory does not reduce the amount of logic and/or distributed memory that is
available for the application. The availability of a large on-chip memory can improve
system performance by eliminating or reducing the need to access off-chip storage.
Reliable clock distribution is the key to the synchronous operation of high-speed
digital circuits. If the clock signal arrives at different times at different parts of a
circuit the device may fail to operate correctly. Clock skew reduces the available time
budget.
2"The Spartan-II devices do not support LVDS (Low Voltage Differential Signaling)
and LVPECL (Low Voltage/Power Emitter-Coupled Logic) I/O standards of a circuit
by lengthening the setup time at registers. It can also shorten the effective hold time
margin of a flip-flop in a shift register and cause the register to shift incorrectly. At
high clock frequencies, the effect of skew is more significant because it represents a
larger fraction of the clock cycle time. Buffered clock trees are commonly used to
minimize clock skew in FPGAs. Xilinx provides all-digital delay-locked loops
(DLLs) for clock synchronization/management in high-speed circuits. DLLs eliminate
the clock distribution delay and provide frequency multipliers, frequency dividers,
and clock mirrors.

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Spartan-II devices are suitable for applications such as implementation of the glue
logic of a video capture system, and the glue logic of an ISDN modem. Device
attributes are summarized in Table 8-14, and the evolution of technology in the
Spartan series is evident in the data in Table.
The top-level tiled architecture of the Spartan-II device, shown in figure marks a new
organization of the Xilinx parts. Each of four quadrants of CLBs is supported by a
DLL and is flanked by a 4096-bit block 25 of RAM, and the periphery of the chip is
lined with lOBs.
Each CLB contains four logic cells, organized as a pair of slices. Each logic cell,
shown in figure, has a four-input LUT, logic for carry and control, and a D-type flip
flop. The CLB contains additional logic for configuring functions of five or six inputs
Spartan II Device Attributes :
Spartan-II FPGAs XC2S XC2S30 XC2S50 XC2S10 XC2S15 XC2S20

15 0 0 0
System Gates1 6K- 13K- 23K- 37- 52K- 71K-
Logic Cells2 15K 30K 50K 100K 150K 200K
Block RAM Bits 432 972 1,728 2,700 3,888 5,292
Maximum Available 16,384 24,576 32,768 40,960 49,152 57,344
I/O 86 132 176 196 260 284
1
20-30% of CLBs as RAM
2
1Logic cell = four –input LUT + flip-flop
Comparison of the Spartan device families :

Part Spartan Spartan /XL Spartan-II
Architecture XC4000 Based XC4000 Based Virtex Based
Maximum No. of 5K-40K 5K-40K 15K-200K
System Gates
Memory Distributed Distributed Block +Distributed
RAM RAM
I/O Performance 80 MHz 100MHz 200MHz
I/O Standards 4 4 16
Core Voltage 5V 3.3 2.5
DLLs No No Yes

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Spartan II Architecture
Figure 2
The Spartan-II part family provides the flexibility and capacity of an on-chip block
RAM; in addition, each LUT can be configured as a 16 x 1 RAM (distributed), and
the pair of LUTs in a logic cell can be configured as a 16 x 2 bit RAM or a 32 x 1 bit
RAM.
The lOBs of the Spartan-II family are individually programmable to support the
reference, output voltage, and termination voltages of a variety of high-speed memory
and bus standards (see figure). Each lOB has three registers, which can function as D-
type flip-flops or as level-sensitive latches. One register (lFF) can be used to register
the signal that controls (synchronously) the programmable output buffer. A second
(‘Off’) can be programmed to register a signal from the internal logic (alternatively, a
signal from the internal logic can pass directly to the output buffer). The third device
can register the signal coming from the I/O pad (alternatively, this signal can pass
directly to the internal logic. A common clock drives each register, but each has an
independent clock enable. A programmable delay element on the input path can be
used to eliminate the pad-to-pad hold time.

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Spartan II CLB Slice (Two per CLB)

Figure 3

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Spartan II IOB
Figure 4

Scientech 110
Introduction to CPLD (Complex Programmable Logic Devices)

A Complex Programmable Logic Device (CPLD) is a programmable logic device
with complexity between that of PALs and FPGAs, and architectural features of both.
The building block of a CPLD is the macro cell, which contains logic implementing
disjunctive normal form expressions and more specialized logic operations.
Features in common with PALs :
• Non-volatile configuration memory. Unlike many FPGAs, an external
configuration ROM isn't required, and the CPLD can function immediately on
system start-up.
• For many legacy CPLD devices, routing constrains most logic blocks to have
input and output signals connected to external pins, reducing opportunities for
internal state storage and deeply layered logic. This is usually not a factor for
larger CPLDs and newer CPLD product families.
Features in common withFPGAs :
• Large number of gates available. CPLDs typically have the equivalent of
thousands to tens of thousands of logic gates , allowing implementation of
moderately complicated data processing devices. PALs typically have a few
hundred gate equivalents at most, while FPGAs typically range from tens of
thousands to several million.
• Some provisions for logic more flexible than sum-of-product expressions,
including complicated feedback paths between macro cells, and specialized
logic for implementing various commonly-used functions, such as integer
arithmetic.
The most noticeable difference between a large CPLD and a small FPGA is the
presence of on-chip non-volatile memory in the CPLD. This distinction is rapidly
becoming less relevant, as several of the latest FPGA products also offer models with
embedded configuration memory.
The characteristic of non-volatility makes the CPLD the device of choice in modern
digital designs to perform ‘boot loader’ functions before handing over control to other
devices not having this capability. A good example is where a CPLD is used to load
configuration data for an FPGA from non-volatile memory.
CPLDs were an evolutionary step from even smaller devices that preceded them,
PLAs (first shipped by Signetics), and PALs. These in turn were preceded by standard
logic products, that offered no programmability and were "programmed" by wiring
several standard logic chips together.
As CPLDs and FPGAs become more advanced the differences between the two
device types will continue to blur. While this trend may appear to make the two types
more difficult to keep apart, the architectural advantage of CPLDs combining low
cost, non-volatile configuration, and macro cells with predictable timing
characteristics will likely be sufficient to maintain a product differentiation for the
foreseeable future.

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Figure 5
Each PLD block of a CPLD has a PAL–like internal structure that forms
combinational logic functions of its inputs.
Xilinx XC9500 :
The Xilinx XC9500 family of CPLDs is flash-based (EEPROM) and in-system pro-
grammable. The devices are organized as an array of functional blocks in a PAL-like
structure with wide and gates and fast flip-flops. Each function block contains up to
18 independent macrocells, and can accommodate 54 inputs and drive 18 outputs
(depending on the packaging). A fast connect switch-matrix technology ensures that
an application can be fully routed even when the device utilization is high. I/O blocks
(lOBs) buffer the inputs and outputs to the device and also receive the global clock
and S-R signals. The output buffers have a programmable slew rate,

Scientech 110
Xillinx XC9500 Architecture

Figure 6
The PAL-like architecture of a function block receives 54 complemented and un-
complemented inputs and can form up to 90 product terms from the inputs. A "Prod-
uct-Term Allocator" allocates up to 90 product terms to each macro-cell in the
function block to form an SOP expression. Each macro cell can receive five direct
product terms from the AND array, and up to 10 more product terms can be made
available from other uncommitted product terms in other macro-cells in the same
functional block, with a negligible increase in delay. Moreover, partial sums of
products can be combined over several macro-cells to produce expressions with more
than 18 product terms.
Each macro-cell can be independently configured for combinational or registered
functionality, and receives global clock, output enable, and S-R signals. The pin-to-
pin delays of the XC9500 device family are short, and support high system clock rates
up to 150 MHz. They should be used in high fan-in state machines, in which speed is
a dominant constraint.
The flip-flop can be configured as a D or T-type flip-flop, with synchronous or
asynchronous S-R operation. The register's clock can be any of three global clocks, or
a product term. The register can also be bypassed to provide direct output. Each
macro-cell has five direct inputs from the AND-array, which can be used to
implement combinational functions or control inputs (clock, clock enable, set-reset,
and output enable).

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Mode Select
1. FPGA Programming Mode :
MODE A :- Boundary Scan Mode

`
J2 1 2 3 J2
JTAG-CLK JP1
JP2 1&2 3
Short 2
JP3 1
SW2
JP4 1 0 0 0
MODE B :- Slave Serial Mode

J3
CCLK-CLK JP1 J3 1 2 3
JP2 2&3 3
Short 2
JP3
SW2 1
JP4 1 1 0 0
2. EPROM Programming Mode :

JP1 J2
J2 1&2 Short
JP2 1&2 3
J3 1&2 Short 2
JP3 Short
SW2 1 0 0 0 1
JP4
3. EPROM to FPGA Mode:

JP1 J2
J2 1&2 Short
JP2 1&2 3
J3 1&2 Short 2
JP3 Short
0 0 0 0 1
SW2
JP4
Figure 7

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Xilinx Web Pack Introduction

Overview :
This document is intended to assist new entry-level users of the Xilinx ISE Web Pack
software. It uses simple logic circuits to illustrate the various CAD tools in the ISE
environment. This document should be referenced while the reader has access to a
computer running the Xilinx tools, so that all procedures can be preformed as the
document proceeds.
Background:
Over the past several generations, engineers have created Computer Aided Design
(CAD) tools to assist in all aspects of modern design. From architectural design, to
mechanical engineering, to circuit design, CAD tools have revolutionized the way in
which engineers work. Since the 1960’s, CAD tools have been used in digital circuit
design to “capture” a virtual copy of a circuit on a computer, and then to simulate the
circuit so that various behaviours could be investigated and modified before the
circuit was actually built. Since their inception, CAD tools have been continuously
evolving. Modern tools allow very precise simulations (down the Pico second), they
allow circuits to be automatically synthesized from an easily written high-level
definition, and they allow designs to be reformatted so they can be implemented in a
variety of technologies. Starting in the 1980’s, digital engineers could use powerful
new technologies to implement complex digital systems on a single chip, right on the
desktop. These chips, called “Field Programmable Gate Arrays” (or FPGAs), and the
software used to program them, has revolutionized digital design and ushered in a
new class of CAD tools. FPGA CAD software typically includes schematic capture,
simulation, implementation, and device programming tools. All of these tools can be
started from a single “navigator” tool that coordinates the files and processes
associated with a given design project. The navigator shows all source files, all CAD
tools that can be used with the source files, and any output or status messages and
files that result from running a given tool.
CDA Tool General Design Flow

Figure 8

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Procedure for Designing in Xilinx ISE WebPack

Step 1 : Open the Xilinx software, the following window will appear.
Figure 9

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Step 2 : Go to file menu “New Project”.
click on the “New Project” .

Figure 10

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Step 3 : “New Project Wizard” will appear
Figure 11
Give project location and project name of your choice and select the type of Top
Level Source for the Project and then click on “Next”
Figure 12

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Step 4 : Select the Family, Device and Package of the chip.

Family : Spartan2 (For FPGA daughter card)
: XC9500 CPLD (For CPLD daughter card)
Device : XC2S200 (For FPGA daughter card)
: XC95108 (For CPLD daughter card)
Package : PQ208 (For FPGA daughter card)
: TQ100 (For CPLD daughter card)
Then click “Next”.
Figure 13

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Step 5 : “New Project Wizard- Create New Source” Window will appear click on
“New Source”.
Figure 14

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Step 6 : “New Project Wizard – Select Source Type” select the Source type and give
the name to the source then click “Next”.
Figure 15
Figure 16

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Step7 : “New Source Wizard- Define Module”. Enter the entity used in design and
then click “Next”.
Figure 17
Figure 18

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New Source Wizard Summary will appear click “Finish”.
Figure 19
Again New Project Wizard- Create New Source window appear click “Next”
Figure 20

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Step 8 : New Project Wizard “Add Existing Sources” window will appear. Any
existing Source can be added to the project from here. Click on “Add Source” and add
the source from its location. To skip adding any existing source just click on “Next”.
Figure 21
New Project Wizard Project summary will appear click “Finish”
Figure 22

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Step 9 : Next window appearing will be :
Close the Design summary by clicking on the 2nd cross button, shown above “close”.
Figure 23
Figure 24

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Step 10 : Next appearing window should be the below one. If it do not appear then
double click on the design file in the source window shown in “blue” below.
Figure 25
This is the source code window and design coding is done in this window.
We have taken a small example of two inputs “AND” gate.
Write the design code in the source window below the begin keyword given in blue.
For the entity selected earlier we have given the code for two inputs “AND” gate as
follows : c< = a and b ;
As shown in the figure below:
Then Save the source file.

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Step 11 : Now we have to assign the pins on the hardware with the design. So click
on the “+” sign button of the “Processes” window “User Constraints” shown in the
left and then double click on the “Create Area Constraints”. As shown in the figure
below.
Figure 26
Next window appearing will be “Project Navigator”. In this window the Project
Navigator shows the requirement to add an implementation constraint file (UCF) to
the Project. Click “Yes”.

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Figure 27
Next appearing Window will be Xilinx PACE.
Figure 28

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Step 12 : Now in the “Design Object List” window give the pin assignments using the
pin detail information provided in the manual. For example, in here as we are
designing an “AND” gate on Scientech 110A we will assign the two inputs ‘a’ and ‘b’
on “DIP switches 1 and 2” and output ‘C’ on “LED D1”.
Given pin assignments for DIP 1 - “p81” DIP Switch 1 on FPGA daughter card
DIP 2 - “p82” DIP Switch 2 on FPGA daughter card
LED D1 - “p17” LED D1 on Mother Board.
The pin numbers “p81”, “p82” and “p17” are to be entered in the “LOC” table.
After assignment you will see three blue dashes on the “device architecture as shown
in the window below. These three dashes indicate the assignment of the entity on the
device. Now save the file and close the window. (See figure below).
Figure 29

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Step 13 : After closing the above window the next window will be again the Xilinx
source code window.
Figure 30
Now right click on the “Configure Device Impact” of the “Generate Programming
File” of the “Processes” window and then click on the properties. Now change the
settings in the properties window.
Figure 31

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Set the properties as shown in the window below and then click “Apply” and then
click “OK”.
Port to be used “LPT1 (PC)”, Baud rate “Auto” and Configuration Mode “Slave
Serial” (For FPGA daughter card) and Configuration Mode “Boundary Scan” (For
CPLD daughter card).
Figure 32
Step 14 : Now double click on the “Configure Device Impact”. The CAD tool will
generate the “bitstream” file (In case of FPGA daughter card) and “.jed” file (In case
of CPLD daughter card) for the design to be burned on the device. The process will
take some time depending on the design size. Wait for the next window shown below:

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Figure 33
Step 15 : Select the Configure Devices “using Slave Serial Mode” (For FPGA
daughter card) or “Configure devices using Boundary Scan(JTAG)” (For CPLD
daughter card) in the above window and click “Finish” (Make sure for the hardware
connections, JTAG must be connected to parallel port of PC and the JTAG port on the
board and Power supply to the main board must be in “ON” position.)
Figure 34

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Step 16 (A) : For programming FPGA daughter card we have to add the device as
shown in the window appearing. Select the “.bit” file and click “Open”.
Figure 35
Next window appearing will be as follows :
Figure 36

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Now right click on the device and click “Program…” And before doing this ensure all
connections and setting on the board are correct. JTAG is plugged, power supply to
the board is on and jumper setting and DIP switch setting on the board is correct.
As the programming completes “Program Successful” message appears in the end in
blue.
Step 16 (B) : For programming CPLD daughter card as soon as we click “Finish” in
Step 15 JTAG chain will be initialized and the following window will appear on
screen
Figure 37
Next window appearing on the screen will be :

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Figure 38
Select the respective “.jed” file and click “Open”. Next window appearing will be as
follows:
Figure 39

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Now right click on the device to select options and click on “Program”.
Figure 40
Next window appearing on screen will be as shown below. Check the “Erase before
programming” option, then click on “Apply” and then click on “OK”.

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Figure 41
Next window appearing on screen will be as follows:
Figure 42
As the programming completes “Program Successful” message appears in the end in
blue.
If “Program Failed” in red appears then check the hardware settings and all other
connections and reprogram the device.

Scientech 110
Summary
Scientech 110
Scientech 110
Figure 43

Scientech 110
Scientech 110 Pin Detail
Pin Number Interface Detail Interface Detail

Daughter Card FPGA Daughter Card
CPLD
1 GND RS_LCD
2 TMS RW_LCD
3 RW_LCD NC
4 EN_LCD NC
5 LCD_0 VCCINT(5V)
6 LCD_1 EN_LCD
7 GND LCD_0
8 LCD_2 LCD_1
9 LCD_3 LCD_2
10 LCD_4 LCD_3
11 GND LCD_4
12 VCCO LCD_5
13 VCCINT LCD_6
14 LCD_5 LCD_7
15 LCD_6 LED_1
16 LCD_7 LED_2
17 LED_1 LED_3
18 LED_2 LED_4
19 GND LED_5
20 LED_3 LED_6
21 LED_4 GND
22 LED_5 GCK0
23 LED_6 NC
24 LED_7 LED_7
25 GND LED_8
26 VCCO VCCIO(5V)
27 LED_8 NC

Scientech 110

Daughter Card FPGA Daughter Card
CPLD
28 VCCINT LED_9
29 LED_9 LED_10
30 LED_10 LED_11
31 LED_11
32 GND LED_12
33 LED_12 LED_13
34 LED_13 LED_14
35 LED_14 LED_15
36 LED_15 LED_16
37 LED_16 CA
38 VCCINT GND
39 VCCO CB
40 GND CC
41 CA CD
42 CB A
43 CC B
44 CD GND
45 A TDI
46 B C
47 C TMS
48 D TCK
49 E D
50 M1 E
51 GND VCCIO(5V)
52 M0 F
53 VCCO G
54 M2 DP

Scientech 110

Daughter Card Daughter Card
FPGA CPLD
55 NC HEX1
56 NC HEX2
57 F VCCINT(5V)
58 G HEX3
59 DP HEX4
60 HEX1 HEX5
61 HEX2 HEX6
62 HEX3 GND
63 HEX4 HEX7
64 GND HEX8
65 VCCO PB1
66 VCCINT PB2
67 HEX5 PB3
68 HEX6 PB4
69 HEX7 GND
70 HEX8 DIP_1
71 PB1 DIP_2
72 GND DIP_3
73 PB2 DIP_4
74 PB3 DIP_5
75 PB4 GND
76 VCCINT DIP_6
77 Global Clock GCK1 DIP_7
78 VCCO DIP_8
79 GND DIP_9
80 Global Clock GCK0 DIP_10
81 DIP_1 DIP_11

Scientech 110

Daughter Card Daughter Card
FPGA CPLD
82 DIP_2 DIP_12
83 DIP_3 TDO
84 DIP_4 GND
85 GND DIP_13
86 DIP_5 DIP_14
87 DIP_6 DIP_15
88 DIP_7 VCCIO(5V)
89 DIP_8 DIP_16
90 DIP_9 TX_1
91 VCCINT RX_1
92 VCCO VGA_VS
93 GND VGA_HS
94 DIP_10 VGA_R
95 DIP_11 VGA_G
96 DIP_12 VGA_B
97 DIP_13 NC
98 DIP_14 VCCINT(5V)
99 DIP_15 NC
100 DIP_16 GND
101 TX_1 (to serial port)
102 RX_1 (from serial
port)
103 GND
104 DONE
105 VCCO
106 Prog_B
107 Init_B
* 108 VGA_VS / IO

Scientech 110
Pin Number Interface Detail

Daughter Card FPGA
* 109 VGA_HS / IO
* 110 VGA_R / IO
* 111 VGA_G /IO
* 112 VGA_B / IO
* 113 BLANK1
* 114 BLANK2
* 115 TXU / IO
116 GND
117 VCCO
118 VCCINT
* 119 RXU / IO
* 120 BLANK3
* 121 BLANK4
122 RS_LCD
* 123 BLANK5
124 GND
* 125 PS2_CLK / IO
* 126 PS2_DATA / IO
127 SRAM_IO_0
128 VCCINT
129 SRAM_IO_1
130 VCCO
131 GND
132 SRAM_IO_2
133 SRAM_IO_3
134 SRAM_IO_4
135 SRAM_IO_5

Scientech 110

Daughter Card FPGA
136 SRAM_IO_6
137 GND
138 SRAM_IO_7
139 SRAM_A0
140 SRAM_A1
141 SRAM_A2
142 SRAM_A3
143 VCCINT
144 VCCO
145 GND
146 SRAM_A4
147 SRAM_A5
148 SRAM_A6
149 SRAM_A7
150 SRAM_A8
151 SRAM_A9
152 SRAM_A10
153 DNI_FP
154 SRAM_A11
155 CCLK
156 VCCO
157 TDO_FP
158 GND
159 TDI_FP
160 SRAM_A12
161 SRAM_A13
162 SRAM_A14

Scientech 110

Daughter Card FPGA
163 SRAM_CE
164 SRAM_OE
165 SRAM_WE
166 ADC_START
167 ADC_EOC
168 ADC_OE
169 GND
170 VCCO
171 VCCINT
172 ADC_CLK
173 ADC_ALE
174 ADC_ADD0
175 ADC_ADD1
176 ADC_ADD2
177 GND
178 ADC_D0
179 ADC_D1
180 ADC_D2
181 ADC_D3
182 Global Clock GCK2
183 GND
184 VCCO
185 Global Clock GCK3
186 VCCINT
187 ADC_D4
188 ADC_D5
189 ADC_D6

Scientech 110

Daughter Card FPGA
190 GND
191 ADC_D7
192 DAC_CS
193 DAC_WR
194 DAC_D7
195 DAC_D6
196 VCCINT
197 VCCO
198 GND
199 DAC_D5
200 DAC_D4
201 DAC_D3
202 DAC_D2
203 DAC_D1
204 DAC_D0
205 DAC_A_B_1
206 RST
207 TCK
208 VCCO
* These pins will be available as a free Input/output (IO), when Peripheral Card is not
connected. User can use them as a general purpose IO.

Scientech 110
2 20
CN1
1 19
Daughter
Card
2 20
ST110 Mother Board CN2
19
1
Figure 44
Connections :- CN1 & CN2
CN1 Pin No. 2 4 6 8 10 12 14 16 18 20

Connections NC RX1 NC NC Blank PS2_DATA ARM_RX NC NC NC
5
2 4 6 8 10 12 14 16 18 20
CN1
1 3 5 7 9 11 13 15 17 19
CN1 Pin No. 1 3 5 7 9 11 13 15 17 19

Connections Gnd NC TX1 NC NC PS2_CLK ARM_TX NC NC NC

Scientech 110
CN2 Pin No. 2 4 6 8 10 12 14 16 18 20

Connections VGA_HS VGA_R NC NC NC Blank TXU Blank 4 TX_ARMGND
2
2 4 6 8 10 12 14 16 18 20
CN2
1 3 5 7 9 11 13 15 17 19
CN2 Pin No. 1 3 5 7 9 11 13 15 17 19

Connections 5V VGA_VS VGA_G VGA_B NC Blank1 RXU Blank Rx_ARM NC
3
Note :- The Blank pins are not available on Peripheral Card. They will be available on
mother board only.
Peripheral Card must be connected to the mother Board, while programming the
ARM7 daughter card using serial port, given on the card, since the IC MAX232
is placed on the peripheral card.
** Refer Image of Scientech 110 mother board for the locations of CN1 &
CN2.

Scientech 110
VLSI Lab
VHDL Lab :
Perform the following experiments with Scientech 110 using VHSIC Hardware
Description Language.
VHDL-Lab 1 :
Objective :
Designing of 2 input AND gate.
Design Code :
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity IO_test is
Port ( a: in std_logic; --input 1
b: in std_logic; -- input 2
c: out std_logic); -- output
end IO_test;
architecture Behavioral of IO test is
begin
c<= a and b;
end Behavioral;
UCF for AND Gate :
#*****************Scientech 110 _UCF *************
DC_FPGA DC_CPLD
NET a LOC = P81; LOC = P70; #DIP 1
NET b LOC = P82; LOC = P71; #DIP 2
NET c LOC = P17; LOC = P15; # LED D1

Scientech 110
VHDL Lab 2 :
Objective :
Designing of 4:1 multiplexer using case statement
Design Code :
Library IEEE;
Entity mux4to1 is
Port ( i0 : in std_logic; -- input data
i1 : in std_logic; -- input data
s : in std_logic_vector(1 downto 0); -- input selection lines
y: out std_logic); --output line
End mux4to1;
Architecture Behavioral of mux4to1 is
Begin
Process (s, i0, i1, i2, i3)--processing inputs and selection lines
Begin
Case s is --deciding which input has to be placed at output
When "00" => y<=i0 ; --data line i0 selected
When others => y<='0';--no data line selected
End case;
End process;
End Behavioral;
UCF for 4:1 Multiplexer :
#================ Scientech 110 _UCF =================
DC_FPGA DC_CPLD
NET "i0" LOC = "P81"; LOC = "P70"; # DIP1 Input 1
NET "s<0>" LOC = "P87"; LOC = "P76"; # DIP6 Select 1 LSB
NET "s<1>" LOC = "P86"; LOC = "P74"; # DIP5 Select 2 MSB
NET "y" LOC = "P17"; LOC = "P15"; # LED D1 Output

Scientech 110
VHDL Lab 3 :
Objective :
Designing of 1:4 De-multiplexer.
Design Code :
Library IEEE;
Entity demux14 is
Port ( mux_in : in STD_LOGIC; -- demux input
mux_out : out STD_LOGIC_VECTOR (3 downto 0);--demux output lines
mux_sel : in STD_LOGIC_VECTOR (1 downto 0));--selection lines
End demux14;
Architecture Behavioral of demux14 is
Begin
Process (mux_in,mux_sel)--processing input data and selection inputs
Begin
Case mux_sel is -- – putting data on to the selected line
When "00" => mux_out(0)<=mux_in; --data input on line 1
When others=> mux_out<="0000";
End Case;
End process;
End Behavioral;
Design UCF for 1:4 de-multiplexer :
#================== Scientech 110 _UCF ============
DC_FPGA DC_CPLD
NET "mux_in" LOC = "p81"; LOC = "p70"; # DIP1
NET "mux_out<0>" LOC = "p17"; LOC = "p15"; # LED1
NET "mux_out<1>" LOC = "p18"; LOC = "p16"; # LED 2
NET "mux_sel<0>" LOC = "p86"; LOC = "p74"; # DIP5

Scientech 110
NET "mux_sel<1>" LOC = "p87"; LOC = "p76"; # DIP6
VHDL Lab 4 :
Objective :
Designing of D Flip flop using Asynchronous Reset
Design Code :
---------------------------------------------------------------
Entity D_FF is
Port ( d : in STD_LOGIC; --data input
clk : in STD_LOGIC; --latch input
reset : in std_logic; --reset input
q : out std_logic --output
);
End D_FF;
Architecture D_FF of D_FF is
Begin
--------------code starts here---------------------------------
Process (Clk, reset)
begin
if (reset = '1')then
q <= '0';
elsif (clk'event and clk = '0')then
q <= d;
end if;
End process;
--------------End of the code----------------------------------
End D_FF;

Scientech 110
Design UCF for D Flip Flop using Asynchronous Reset :

#================== Scientech 110 _UCF =============
DC_FPGA DC_CPLD
NET "clk" LOC = "p80"; LOC = "p22";
NET "d" LOC = "p81"; LOC = "p70";
NET "q" LOC = "p17"; LOC = "p15";
NET "reset" LOC = "p71"; LOC = "p65";
VHDL Lab 5 :
Objective :
Designing of D Flip Flop using synchronous Reset
Design Code :
---------------------------------------------------------------
Entity dff_sync_reset is
Port ( data : in STD_LOGIC;--data input
clk : in STD_LOGIC;--clock input
reset : in std_logic;--reset input
q : out std_logic-- output
);
End dff_sync_reset;
Architecture dff_sync_reset of dff_sync_reset is
Begin
--------------code starts here---------------------------------
process (clk,reset)
begin
if (clk'event and clk = '1')then
q <= '0';
else
q <= data;
end if;
end if;
end process;
--------------end of the code----------------------------------
end dff_sync_reset;

Scientech 110
Design UCF for D Flip Flop using Synchronous Reset :

#================ Scientech 110 _UCF =============
DC_FPGA DC_CPLD

NET "data" LOC = "p81"; LOC = "p70";
NET "q" LOC = "p17"; LOC = "p15";
VHDL Lab 6 :
Objective :
Designing of D Latch with reset.
Design Code :
---------------------------------------------------------------
Entity dlatch_reset is
en : in STD_LOGIC;--latch input
);
End dlatch_reset;
Architecture dlatch_reset of dlatch_reset is
Begin
--------------code starts here---------------------------------
Process (en,reset)
begin
q <= '0';
elsif (en = '1')then
q <= data;
end if;
End process;
--------------end of the code----------------------------------
End dlatch_reset;

Scientech 110
Design UCF for D Latch with reset :

#================Scientech 110 _UCF =====================
DC_FPGA DC_CPLD
NET "en" LOC = "p82"; LOC = "p71";
NET "q" LOC = "p17"; LOC = "p15";
VHDL Lab 7 :
Objective :
Design of 2:1 Multiplexer using “IF Statement”.
Design Code :
---------------------------------------------------------------
Entity mux_using_if is
Port ( din_0 : in STD_LOGIC;--mux first input
din_1 : in STD_LOGIC;--mux second input
sel : in std_logic;--select input
mux_out : out std_logic--mux output
);
End mux_using_if;
Architecture Behavioral of mux_using_if is
Begin
--------------code starts here--------------------------------
Process (sel)
begin
if(sel = '0')then
mux_out <= din_0;
else
mux_out <= din_1;
end if;
End process;
--------------end of the code---------------------------------
End Behavioral;

Scientech 110
Designing of UCF for 2:1 Mux using “IF” :

#================Scientech 110 _UCF =================
DC_FPGA DC_CPLD
NET "din_0" LOC = "p81"; LOC = "p70";
NET "din_1" LOC = "p82"; LOC = "p71";
NET "mux_out" LOC = "p17"; LOC = "p15";
NET "sel" LOC = "p90"; LOC = "p79";
VHDL Lab 8 :
Objective :
Designing of T Flip Flop using Asynchronous Reset
Design Code :
---------------------------------------------------------------
Entity tff_asynchronous_reset is
clk : in STD_LOGIC;--clock input
);
End tff_asynchronous_reset;
Architecture tff_asynchronous_reset of tff_asynchronous_reset is
Signal x : std_logic;
Begin
--------------code starts here---------------------------------
Process (clk,reset,data)
begin
if(reset = '0')then
x <= '0';
elsif (clk'event and clk = '1')then
if (data = '1')then
x <= not x;
else
x <= x;
end if;
end if;
End process;
q <= x;
--------------end of the code----------------------------------
end tff_asynchronous_reset;

Scientech 110
Design UCF for :

#====================== Scientech 110 _UCF ============
DC_FPGA DC_CPLD
NET "q" LOC = "p17"; LOC = "p15";
VHDL Lab 9 :
Objective :
Designing of BCD to Seven Segment Decoder
Design Code :
Library IEEE;
Entity deco7seg is
Port (q : in STD_LOGIC_VECTOR (3 downto 0);
a : out STD_LOGIC_VECTOR (7 downto 0));
End deco7seg;
Architecture behavioral of deco7seg is
Begin
Process (q)
Begin
Case q is --decoding
When "0000" => a<="10111111"; --showing 0
When "0001" => a<="10000110"; --showing 1
When "0010" => a<="11011011"; --showing 2
When "0011" => a<="11001111"; --showing 3
When "0100" => a<="11100110"; --showing 4
When "0101" => a<="11101101"; --showing 5
When "0110" => a<="11111101"; --showing 6
When "0111" => a<="10000111"; --showing 7
When "1000" => a<="11111111"; --showing 8

Scientech 110
When "1001" => a<="11101111"; --showing 9

When "1010" => a<="11110111"; --showing A
When "1011" => a<="11111100"; --showing B
When "1100" => a<="10111001"; --showing C
When "1101" => a<="11011110"; --showing D
When "1110" => a<="11111001"; --showing E
When "1111" => a<="11110001"; --showing F
When others => a<="ZZZZZZZZ"; --showing nothing
End case;
End process;
End Behavioral;
Design UCF for BCD to seven segment decoder :
#================== Scientech 110 _UCF ==============
DC_FPGA DC_CPLD
NET "q<3>" LOC = “p81”; LOC = “p70”; # DIP 1
NET "a<0>" LOC = “p45”; LOC = “p42”; # displaying (A)
NET "a<1>" LOC = “p46”; LOC = “p43”; # displaying (B)
NET "a<2>" LOC = “p47”; LOC = “p46”; # displaying (C)
NET "a<3>" LOC = “p48”; LOC = “p49”; # displaying (D)
NET "a<4>" LOC = “p49”; LOC = “p50”; # displaying (E)
NET "a<5>" LOC = “p57”; LOC = “p52”; # displaying (F)
NET "a<6>" LOC = “p58”; LOC = “p53”; # displaying (G)
NET "a<7>" LOC = “p41”; LOC = “p37”; # cathode for seven segment
display

Scientech 110
VHDL Lab 10 :
Objective :
Designing of counter to count from 0 to F. Output of the counter to be displayed
on seven-segment.
Design Code :
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity sevenseg_dis is
Port (Reset: in std_logic; --reset
Clk : in std_logic; --system clock 8 Mhz
Segment : out std_logic_vector(7 downto 0); --seven segment output
Base1 : out std_logic_vector(3 downto 0) --seven segment display cathodes
);
End sevenseg_dis;
Architecture sevenseg_dis_arch of sevenseg_dis is
Signal Counter:std_logic_vector(24 downto 0); --counter to divide frequnecy
Signal Decoder:std_logic_vector(1 downto 0); -- decoder for display scanner
Signal Bts:std_logic_vector(3 downto 0); -- bits for BCD counter
Signal Enable:std_logic; --enable signal
Begin
Decoder <= Counter (14 downto 13) ; -- Set the ‘On’ and ‘Off’ Frequency
Enable <= Counter (12) ;
Bts <= Counter (24 downto 21) ;
Process (Clk,Reset)
Begin
If (Reset='1')then
Counter <= (others =>'0') ;
elsif Clk'event and clk = '1' then
Counter <=Counter +'1';
End if;
End process;
Process (Decoder, Enable) -- Make the cathode Transistors ‘On’ and ‘Off’

Scientech 110
begin -- scanning for seven segment display

if (Enable='1')then
Base1 <= (others=>'0') ;
Else
Case Decoder is
When "00" => Base1 <= "0001" ;
When "01" => Base1 <= "0010" ;
When "10" => Base1 <= "0100" ;
When "11" => Base1 <= "1000" ;
When others =>Base1 <= "1111" ;
End case;
End if;
End process;
Process (Bts)
Begin
Case Bts is
-- bcdefg Binary to 7-segment decoder
When "0000" => Segment <= "10111111"; -- displaying 0.
When "1010" => Segment <= "11110111"; -- displaying A.
When "1011" => Segment <= "11111100"; -- displaying B.
When "1100" => Segment <= "10111001"; -- displaying C.
When "1101" => Segment <= "11011110"; -- displaying D.
When "1110" => Segment <= "11111001"; -- displaying E.

Scientech 110
When "1111" => Segment <= "11110001"; -- displaying F.

When others => Segment <= "ZZZZZZZZ";
End case;
End process;
End sevenseg_dis_arch;
Design UCF for 0 to F counter :
###################### Scientech 110 _UCF ################

DC_FPGA DC_CPLD
NET reset LOC = “p71”; LOC = p65”; # PB1
NET clk LOC = “p80”; LOC = p22”; # system
clock 8 MHz
NET segment<0> LOC = “p45”; LOC = “ p42”; # (A)
NET segment<1> LOC = “p46”; LOC = “ p43”; # (B)
NET segment<2> LOC = “p47”; LOC = “ p46”; # (C)
NET segment<3> LOC = “p48”; LOC = “ p49”; # (D)
NET segment<4> LOC = “p49”; LOC = “ p50”; # (E)
NET segment<5> LOC = “p57”; LOC = “ p52”; # (F)
NET segment<6> LOC = “p58”; LOC = “ p53”; # (G)
NET segment<7> LOC = “p59”; LOC = “ p54”; # (.)
NET base1<0> LOC = “p41”; LOC = “ p37”; # (CA)
Cathode
NET base1<1> LOC = “p42”; LOC = “ p39”; # (CB)
Cathode
NET base1<2> LOC = “p43”; LOC = “ p40”; # (CC)
Cathode
NET base1<3> LOC = “p44”; LOC = “ p41”; # (CD)
Cathode

Scientech 110
Verilog Lab
Perform the following experiments with ST102 and VB1 using Verilog Hardware
Description Language.
Verilog Lab 1 :
Objective :
Designing of 2 input AND gate
Design Code :
module and_gate(a,b,c);
input a;
input b;
output c;
wire c;
assign c = a & b;
endmodule
UCF for AND gate :
#*****************Scientech 110_UCF *************
DC_FPGA DC_CPLD
NET a LOC = P81; LOC = P70; #DIP 1

NET b LOC = P82; LOC = P71; #DIP 2
NET c LOC = P17; LOC = P15; # LED D1

Scientech 110
Verilog Lab 2 :
Objective :
Designing of 4:1 multiplexer using case statement
Design code :
Module Mux_4_1(sel,mux_in,mux_out);
Input [1:0] sel;
Input [3:0] mux_in;
Output mux_out;
reg mux_out;
always@(sel or mux_in)
begin
case (sel)
2'b00 : mux_out <= mux_in[0];
endcase
end
endmodule
Design UCF for 4:1 MUX :
#================ ST102A or Scientech 110B_UCF =================
DC_FPGA DC_CPLD
NET mux_in<0> LOC = "P81"; LOC = "P70"; # DIP 1 Input 1

NET sel<1> LOC = "P87"; LOC = "P76"; # DIP 5 Select 2 MSB
NET sel<0> LOC = "P86"; LOC = "P74"; # DIP 6 Select 1 LSB
NET mux_out LOC = "P17"; LOC = "P15"; # LED 1 D1 Output

Scientech 110
Verilog Lab 3 :
Objective :
Designing of 1:4 De-multiplexer.
Design Code :
module de_mux_1_4(sel,de_mux_in,de_mux_out);
input [1:0] sel;
input de_mux_in;
output [3:0]de_mux_out;
reg [3:0]de_mux_out;
always@(sel or de_mux_in)
begin
case (sel)
2'b00 : de_mux_out[0] <= de_mux_in;
endcase
end
endmodule
Design UCF for 1:4 De-multiplexer :
#================== Scientech 110_UCF============
DC_FPGA DC_CPLD
NET sel<1> LOC = "p81"; LOC = "p70"; # DIP 1

NET sel<0> LOC = "p82"; LOC = "p71"; # DIP 2
NET de_mux_in LOC = "p83"; LOC = "p72"; # DIP 3
NET de_mux_out<0> LOC = "p17"; LOC = "p15"; # LED 1

Scientech 110
Verilog Lab 4 :
Objective :
Designing of a D Flip flop using asynchronous reset.
Design Code :
Module D_FF(clk,reset,d,q);
Input clk; //clock input
Input reset; //reset input
Input d; //data input
Output q; //output
reg q;
always@(posedge reset or negedge clk)
if(reset)
q <= 1'b0;
else
q <= d;
endmodule
Design UCF for D Flip Flop Using Asynchronous Reset :
#================== Scientech 110_UCF=============
DC_FPGA DC_CPLD

NET "d" LOC = "p81"; LOC = "p70";
NET "q" LOC = "p17"; LOC = "p15";

Scientech 110
Verilog Lab 5 :
Objective :
Designing of D Flip Flop Using Synchronous Reset
Design Code :
Module dff_sync_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_sync_reset
Design UCF for D Flip flop using synchronous reset :
#================ Scientech 110_UCF=============
DC_FPGA DC_CPLD

NET "q" LOC = "p17"; LOC = "p15";

Scientech 110
Verilog Lab 6 :
Objective :
Designing of D Latch
Design Code:
module dlatch_reset(
en , // LatchInput
q // Q output
);
//-----------Input Ports---------------
input data, en, reset ;
//-----------Output Ports---------------
output q;
reg q;
//-------------Code Starts Here---------
always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end
endmodule //End Of Module dlatch_reset
Design UCF for D Latch :
#================Scientech 110_UCF=====================
DC_FPGA DC_CPLD

NET "en" LOC = "p82"; LOC = "p71";
NET "q" LOC = "p17"; LOC = "p15";

Scientech 110
Verilog Lab 7 :
Objective :
Designing of 2:1Multiplexer using “IF Statement”
Design Code :
module mux_using_if(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
reg mux_out;
//-------------Code Starts Here---------
always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
endmodule //End Of Module mux
Design UCF for 2:1 Mux :
#================Scientech 110_UCF=================
DC_FPGA DC_CPLD
NET "din_0" LOC = "p81"; LOC = "p70";
NET "din_1" LOC = "p82"; LOC = "p71";
NET "mux_out" LOC = "p17"; LOC = "p15";
NET "sel" LOC = "p90"; LOC = "p79";

Scientech 110
Verilog Lab 8 :
Objective :
Designing of T Flip flop using asynchronous reset.
Design Code :
module tff_async_reset (
clk , // Clock Input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
//-----------Output Ports---------------
output q;
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= ! q;
end
endmodule // End Of Module tff_async_reset
Design UCF for :
#====================== Scientech 110_UCF============
DC_FPGA DC_CPLD

NET "q" LOC = "p17"; LOC = "p15";
Verilog Lab 9 :

Scientech 110
Objective :
Designing of BCD to Seven Segment Decoder
Design Code :
module bcd_seven_seg(q,a);
input [3:0] q;
output [7:0] a;
reg [7:0] a;
always@(q)//decoding
begin
case(q)
4'b0000 : begin a<=8'b10111111; end//showing 0
4'b1010 : begin a<=8'b11110111; end//showing A
4'b1011 : begin a<=8'b11111100; end//showing B
4'b1100 : begin a<=8'b10111001; end//showing C
4'b1101 : begin a<=8'b11011110; end//showing D
4'b1110 : begin a<=8'b11111001; end//showing E
4'b1111 : begin a<=8'b11110001; end//showing F
endcase
end
endmodule

Scientech 110
Design UCF for BCD to Seven-segment decoder.:

#================== Scientech 110_UCF==============
DC_FPGA DC_CPLD

NET "a<0>" LOC = “p45”; LOC = “p42”; # displaying (A)
NET "a<1>" LOC = “p46”; LOC = “p43”; # displaying (B)
NET "a<2>" LOC = “p47”; LOC = “p46”; # displaying (C)
NET "a<3>" LOC = “p48”; LOC = “p49”; # displaying (D)
NET "a<4>" LOC = “p49”; LOC = “p50”; # displaying (E)
NET "a<5>" LOC = “p57”; LOC = “p52”; # displaying (F)
NET "a<6>" LOC = “p58”; LOC = “p53”; # displaying (G)
NET "a<7>" LOC = “p41”; LOC = “p37”; # cathode for seven
segment display

Scientech 110
Verilog Lab 10 :
Objective :
Designing of counter to count from 0 to F. Output of the counter to be displayed
on seven-segment
Design Code :
module sevenseg_dis(Reset,Clk,Segment,Base1);
input Reset,Clk;
output [7:0]Segment;
output [3:0]Base1;
reg [7:0]Segment;
reg [3:0]Base1;
reg [24:0] Counter;
reg [1:0] decoder;
reg [3:0]Bts ;
reg Enable;
always @(posedge Clk)
begin
decoder = Counter [14:13];
Enable = Counter[12];
Bts = Counter[24:21];
if (Reset)
begin
Counter <= 25'b0;
end
else
begin
Counter <= Counter +1'b1;
end
end
always @(decoder or Enable) // Make the Transistors ‘On’ and ‘Off’
begin
if (Enable)
begin

Scientech 110
Base1= 4'b0;
end
else
begin
case(decoder) // Scan code for turning display ON
2'b00:Base1=4'b0001;
2'b01:Base1=4'b0010;
2'b10:Base1=4'b0100;
2'b11:Base1=4'b1000;
endcase
end
end
always @(Bts)
begin
case(Bts)
4'b0000 : Segment=8'b10111111 ;// 0
4'b0001 : Segment=8'b10000110 ;// 1
4'b0010 : Segment=8'b11011011 ;// 2
4'b0011 : Segment=8'b11001111 ;// 3
4'b0100 : Segment=8'b11100110 ;// 4
4'b0101 : Segment=8'b11101101 ;// 5
4'b0110 : Segment=8'b11111101 ;// 6
4'b0111 : Segment=8'b10000111 ;// 7
4'b1000 : Segment=8'b11111111 ;// 8
4'b1001 : Segment=8'b11101111 ;// 9
4'b1010 : Segment=8'b11110111 ;// A
4'b1011 : Segment=8'b11111100 ;// B
4'b1100 : Segment=8'b10111001 ;// C
4'b1101 : Segment=8'b11011110 ;// D
4'b1110 : Segment=8'b11111001 ;// E
4'b1111 : Segment=8'b11110001 ;// F
endcase
end
endmodule

Scientech 110
Design UCF for 0 to F Counter :

###################### Scientech 110_UCF################
DC_FPGA DC_CPLD
NET reset LOC = “p71”; LOC = p65”; # PB1

NET clk LOC = “p80”; LOC = p22”; # system clock 8 MHz
NET segment<0> LOC = “p45”; LOC = “ p42”; # (A)
NET segment<1> LOC = “p46”; LOC = “ p43”; # (B)
NET segment<2> LOC = “p47”; LOC = “ p46”;# (C)
NET segment<3> LOC = “p48”; LOC = “ p49”; # (D)
NET segment<4> LOC = “p49”; LOC = “ p50”; # (E)
NET segment<5> LOC = “p57”; LOC = “ p52”; # (F)
NET segment<6> LOC = “p58”; LOC = “ p53”; # (G)
NET segment<7> LOC = “p59”; LOC = “ p54”; # (.)
NET base1<0> LOC = “p41”; LOC = “ p37”;# (CA) Cathode
NET base1<1> LOC = “p42”; LOC = “ p39”;# (CB) Cathode
NET base1<2> LOC = “p43”; LOC = “ p40”;# (CC) Cathode
NET base1<3> LOC = “p44”; LOC = “ p41”;# (CD) Cathode

Scientech 110
Test Files
1. Interfacing Lcd, LEDs, Seven Segment Display.
Entity for LCD interface
Figure 45
Block Diagram
Figure 46

Scientech 110
Theory (LCD)
LCD is a powerful display options for stand-alone systems. LCD modules are
available in a wide range like 8x1, 8x2, 16x1, 16x2, 20x2, 20x4, and 40x4. Here we
have used 16x2- that means 2 rows of 16 characters. It is a Hitachi HD44780
compatible module, having 16 pins including 2 pins for backlight.
Following table gives pin structure of LCD module. LCD modules without backlight
will have only 14 pins. If you are using such LCDs, simply ignore 15th and 16th pins.
Pin No Symbol Details
1 GND Ground
2 Vcc Supply Voltage +5V
3 Vo Contrast adjustment
0->Control input, 1-> Data
4 RS
input
5 R/W Read/ Write
6 E Enable
7 to 14 D0 to D7 Data
15 VB1 Backlight +5V
16 VB0 Backlight ground
To program the LCD module, first we have to initialize the LCD by sending some
control words. RS should be low and E should be high when we send control. R/W
pin 0 means write data or control to LCD and R/W pin 1 means read data from the
LCD. To send a data to LCD, make RS high, R/W low, place the data in pins 7 to 14
and make pin E high and low once.
Pin number 3 of the LCD is for adjusting the contrast, connected in such a way that it
can be varied from 0V to 5V.
If everything is OK, you should get the LCD module as follows when power is
switched ON.
Figure 47

Scientech 110
Following table explains how to write control words. When RS=0 and R/W=0, data in
the pins D0 to D7 will have following meaning.
Instructio
D7 D6 D5 D4 D3 D2 D1 D0 Description
n
Clears Display
Clear and returns
0 0 0 0 0 0 0 1
Display cursor to home
position.
Returns cursor
to home
position. Also
Cursor
0 0 0 0 0 0 1 X returns display
home
being shifted to
the original
position.
I/D = 0 -->
cursor is in
decrement
position. I/D
= 1 --> cursor is
Entry
0 0 0 0 0 1 I/D S in increment
mode set
position. S = 0 -
-> Shift is
invisible. S=
1 --> Shift is
visible
D- Display, C-
Display cursor, B-
ON- OFF 0 0 0 0 1 D C B Blinking
Control cursor = 0 -->
OFF =1 --> ON
S/C = 0 -->
Move cursor.
S/C = 1 -->
Cursor/
Shift display.
Display 0 0 0 1 S/C R/L X X
R/L = 0 -->
Shift
Shift left. R/L
= 1 --> Shift
right
Function DL = 0 --> 4 bit

0 0 1 DL N F X X interface. DL =
Set
1 --> 8 bit

Scientech 110
interface. N = 0
--> 1/8 or 1/11
Duty (1 line). N
= 1 --> 1/16
Duty (2 lines).
F = 0 --> 5x7
dots. F = 1 --
> 5x10 dots.
Figure 48

Scientech 110
Parameter Symbol Min Max Unit Test Pin
Enable cycle tc 500 ns E

time
Enable High tw 220 ns E
pulse width
Enable tr. tf 25 ns E
rise/fall time
RS. R/W setup tsu 40 ns RS. R/W

time
RS. R/W hold th 10 ns RS. /RW
time
Read data tD 60 120 ns DBO-DB7
output delay
Read data tDH 20 ns DBO-DB7

hold time
Write data tsu 1 40 ns DBO-DB7
setup time
Read data th1 10 ns DBO-DB7
hold time
The manufacturer requires that a startup sequence with specific timings be followed to
ensure proper LCD operation. After power-on, at least 20ms must elapse before the
function-set instruction code can be written to set the bus width, number of lines, and
character patterns (8-bit interface, 2 lines, and 5x8 dots are appropriate). After the
function-set instruction, at least 37us must elapse before the display-control
instruction can be written (to turn the display on, turn the cursor on or off, and set the
cursor to blink or no blink). Then after another 37us, the display-clear instruction can
be issued, followed by a 1.52ms delay. The entry-mode instruction code is then issued
which is used to set the address increment (or address decrement) mode, and display
shift mode (on or off). After the entry-mode instruction is issued, the Set CGRAM
and Set DDRAM address instructions are then issued. Once this sequence is complete,
ASCII data can be written into the DDRAM to cause information to appear on the
display.

Scientech 110
Figure 49

Scientech 110
Procedure to program the FPGA Daughter Card and test the “.bit” file.
A. Place the FPGA Daughter card on the Scientech 110 Mother Board.
B. Connect the JTAG cable from PC parallel port to the JTAG port given on the
Daughter Card.
C. Change the jumper and DIP switch settings as per the required programming
mode (refer the Mode select section).
1. To program the FPGA in slave serial mode, Set the DIP switch SW2 to
“1100”.
2. Short the pins 2&3 of jumper JP1,JP2, JP3,& JP4.
3. Short the pins 2&3 of jumper J3. J2 remains OPEN.
D. Now connect the JTAG cable to the JTAG connector from parallel port of the
PC to the JTAG port given on the daughter card
E. Switch ON the power by touching the power button given on the top left corner
of the Mother Board.
F. Program the device with the respective “.bit” file. (refer Xilinx Webpack
Introduction Section for Programming the device).
The LCD display will show:- “ SCIENTECH TECHNOLOGIES
WELLCOMES YOU TO THE WORLD OF VLSI”.
The seven segment display will show the counter from 0 to 7.
The LEDs display will show a counter of 16 bit from “0000000000000000” to
“1111111111111111”.
2. Interfacing Telephone keypad/Hex Keypad
Entity :
Figure 50

Scientech 110
Block Diagram
Figure 51

Scientech 110
Theory
A keypad is wired in matrix form with a switch at the intersection of each row and
column. Pressing a key establishes a connection between a row and column. The
purpose of the scanner is to determine which key has been pressed and output a binary
number N= N3 N2 N1 N0 which corresponds to the key number.
Figure 52
This is how the HEX keypad is connected, each square with a number or letter in it is
a push to make switch, which connects the horizontal wires (rows) with the vertical
wires (columns). So if you press button 'A' it will connect COL1 with ROW4, or
pressing button '6' will connect COL3 with ROW2.
When a valid key has been detected, the scanner should output a signal to individual
column for one clock time. We will assume that only one key is pressed at time.
Resistors to ground are connected to each row of the keyboard, so that R1R2R3R4=0
when no key is pressed.
Scanner scans the column continuously with the system clock. A ‘1’ or logic high is
continuously assigned to the columns one by one. As soon as a key is pressed the
logic high assigned to the column is again interrupted by the design through the row
input and a valid key is detected. The respective codes assigned to the keys are then
outputted on the detection of the key in the design entity.
Daughter Card.

Scientech 110
“1100”.
D. Switch ON the power by touching the power button given on the top left corner
E. Program the device with the respective “.bit” file. (refer Xilinx Webpack
F. Now press the keys of Hex keypad, the respective key will be displayed on the
seven segment display, and the respective binary value will be shown on the
leds.
3. Interfacing PS2 port
Entity :
Figure 53
Input :
• Clock 8MHz (clock)
• PS2 Clock (ps2_clk)
• PS2 Data (ps2_dta)
• Reset (resetn)
Output :
• 8 bit output (key codes) (leds(7:0))

Scientech 110
Theory PS2 Interface

The above entity represents a PS2 keyboard interface using a VLSI chip. The design
follows the PS2 protocol. Input is given through the PS2 keyboard and the output is
the scan key code for the specific key in 8bit and is visible over the LED. The detail
about the PS2 port and the protocol is mentioned below. One can use the detail
provided here to develop its own design for the purpose.
Figure 54
The Electrical Interface :
Note : Throughout this document, We will use the more general term "host" to refer
to the computer--or whatever the keyboard is connected to- and the term "device" will
refer to the keyboard/mouse.
Vcc/Ground provide power to the keyboard/mouse. The keyboard should not draw
more than 275mA from the host and care must be taken to avoid transient surges.
Such surges can be caused by "hot-plugging" a keyboard/mouse (i.e.
connect/disconnect the device while the computer's power is on.)
Summary: Power Specifications
Vcc = + 4.5V to + 5.5V.
Max Current = 275mA.
The Data and Clock lines are both open-collector with pull-up resistors to Vcc. An
"open-collector" interface has two possible state: low, or high impedance. In the
"low" state, a transistor pulls the line to ground level. In the "high impedance" state,
the interface acts as an open circuit and doesn't drive the line low or high.
Furthermore, a "pull-up" resistor is connected between the bus and Vcc so the bus is
pulled high if none of the devices on the bus are actively pulling it low. A general
open-collector interface is shown below:
Fig 24 : General open-collector interface. Data and Clock are read on the
microcontroller's pins A and B, respectively. Both lines are normally held at +5V, but
can be pulled to ground by asserting logic "1" on C and D. As a result, Data equals D,
inverted, and Clock equals C, inverted.

Scientech 110
Figure 55
Communication: General Description :
The PS/2 keyboard implement a bidirectional synchronous serial protocol. The bus is
"idle" when both lines are high (open-collector). This is the only state where the
keyboard is allowed begin transmitting data. The host has ultimate control over the
bus and may inhibit communication at any time by pulling the Clock line low.
The device always generates the clock signal. If the host wants to send data, it must
first inhibit communication from the device by pulling Clock low. The host then pulls
Data low and releases Clock. This is the "Request-to-Send" state and signals the
device to start generating clock pulses.
Summary: Bus States
Data=high, Clock=high: Idle-State.
Data=high, Clock=low: Communication-Inhibited.
Data=low, Clock=high: Host Request-to-Send
All data is transmitted one byte at a time and each byte is sent in a frame consisting of
11-12 bits. These bits are :
• 1 start bit. This is always 0.
• 8 data bits, least significant bit first.
• 1 parity bit (odd parity).
• 1 stop bit. This is always 1.
• 1 acknowledge bit (host-to-device communication only)

Scientech 110
The parity bit is set if there is an even number of 1's in the data bits and reset (0) if
there is an odd number of 1's in the data bits. The number of 1's in the data bits plus
the parity bit always add up to an odd number (odd parity.) This is used for error
detection. The keyboard/mouse must check this bit and if incorrect it should respond
as if it had received an invalid command.
Data sent from the device to the host is read on the falling edge of the clock signal;
data sent from the host to the device is read on the rising edge. The clock frequency
must be in the range 10 - 16.7 kHz. This means clock must be high for 30 - 50
microseconds and low for 30 - 50 microseconds.. If you're designing a keyboard,
mouse, or host emulator, you should modify/sample the Data line in the middle of
each cell. I.e. 15 - 25 microseconds after the appropriate clock transition. Again, the
keyboard/mouse always generates the clock signal, but the host always has ultimate
control over communication.
Timing is absolutely crucial. Every time quantity I give in this article must be
followed exactly.
Communication: Device-to-Host :
The Data and Clock lines are both open collector. A resistor is connected between
each line and +5V, so the idle state of the bus is high. When the keyboard or mouse
wants to send information, it first checks the Clock line to make sure it's at a high
logic level. If it's not, the host is inhibiting communication and the device must buffer
any to-be-sent data until the host releases Clock. The Clock line must be
continuously high for at least 50 microseconds before the device can begin to transmit
its data.
As mentioned in the previous section, the keyboard and mouse use a serial protocol
with 11-bit frames. These bits are :
• 1 start bit. This is always 0.
• 8 data bits, least significant bit first.
• 1 parity bit (odd parity).
• 1 stop bit. This is always 1.
The keyboard/mouse writes a bit on the Data line when Clock is high, and it is read by
the host when Clock is low. Figures 25 and 26 illustrate this.
Fig 25: Device-to-host communication. The Data line changes state when Clock is
high and that data is valid when Clock is low.
Figure 56

Scientech 110
Figure 26: Scan code for the "Q" key (15h) being sent from a keyboard to the
computer. Channel A is the Clock signal; channel B is the Data signal.
---
Figure 57
The clock frequency is 10-16.7 kHz. The time from the rising edge of a clock pulse
to a Data transition must be at least 5 microseconds. The time from a data transition
to the falling edge of a clock pulse must be at least 5 microseconds and no greater
than 25 microseconds.
The host may inhibit communication at any time by pulling the Clock line low for at
least 100 microseconds. If a transmission is inhibited before the 11th clock pulse, the
device must abort the current transmission and prepare to retransmit the current
"chunk" of data when host releases Clock. A "chunk" of data could be a make code,
break code, device ID, mouse movement packet, etc. For example, if a keyboard is
interrupted while sending the second byte of a two-byte break code, it will need to
retransmit both bytes of that break code, not just the one that was interrupted.
If the host pulls clock low before the first high-to-low clock transition, or after the
falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit
any data. However, if new data is created that needs to be transmitted, it will have to
be buffered until the host releases Clock. Keyboards have a 16-byte buffer for this
purpose. If more than 16 bytes worth of keystrokes occur, further keystrokes will be
ignored until there's room in the buffer. Mice only store the most current movement
packet for transmission.
Host-to-Device Communication :
The packet is sent a little differently in host-to-device communication First of all, the
PS/2 device always generates the clock signal. If the host wants to send data, it must
first put the Clock and Data lines in a "Request-to-send" state as follows :
• Inhibit communication by pulling Clock low for at least 100 microseconds.
• Apply "Request-to-send" by pulling Data low, then release Clock.
The device should check for this state at intervals not to exceed 10 milliseconds.
When the device detects this state, it will begin generating Clock signals and clock in

Scientech 110
eight data bits and one stop bit. The host changes the Data line only when the Clock
line is low, and data is read by the device when Clock is high. This is opposite of
what occurs in device-to-host communication.
After the stop bit is received, the device will acknowledge the received byte by
bringing the Data line low and generating one last clock pulse. If the host does not
release the Data line after the 11th clock pulse, the device will continue to generate
clock pulses until the Data line is released (the device will then generate an error)
The host may abort transmission at time before the 11th clock pulse (acknowledge
bit) by holding Clock low for at least 100 microseconds.
To make this process a little easier to understand, here's the steps the host must follow
to send data to a PS/2 device :
1. Bring the Clock line low for at least 100 microseconds.
2. Bring the Data line low)
3. Release the Clock line.
4. Wait for the device to bring the Clock line low.
5. Set/reset the Data line to send the first data bit
6. Wait for the device to bring Clock high.
7. Wait for the device to bring Clock low.
8. Repeat steps 5-7 for the other seven data bits and the parity bit
9. Release the Data line.
10. Wait for the device to bring Data low.
11. Wait for the device to bring Clock low.
12. Wait for the device to release Data and Clock.
Fig 27 shows this graphically and Figure 28 separates the timing to show which
signals are generated by the host, and which are generated by the PS/2 device. Notice
the change in timing for the "ack" bit--the data transition occurs when the Clock line
is high (rather than when it is low as is the case for the other 11 bits.)
Figure 27: Host-to-Device Communication.
Figure 58
Figure 28 : Detailed host-to-device communication.

Scientech 110
Figure 59
Referring to Figure 28, there's two time quantities the host looks for. (a) is the time it
takes the device to begin generating clock pulses after the host initially takes the
Clock line low, which must be no greater than 15 ms. (b) is the time it takes for the
packet to be sent, which must be no greater than 2ms. If either of these time limits is
not met, the host should generate an error. Immediately after the "ack" is received,
the host may bring the Clock line low to inhibit communication while it processes
data. If the command sent by the host requires a response, that response must be
received no later than 20 ms after the host releases the Clock line. If this does not
happen, the host generates an error.
A. Place the FPGA Daughter card and PERIPHERAL card on the Scientech 110
Mother Board.
Daughter Card.
“1100”.
F. Connect the Keyboard with the PS2 connector given on the PERIPHERAL card.
G. Now press the keys of Keyboard, and the respective Hex value will be shown on
the leds in the binary format.
4. Interfacing DAC

Scientech 110
Entity:
output(7:0) DAC
clock FPGA
reset CS
Analog out
A_B
WR
Led(7:0)
Figure 60
Output :
• 8 bit digital input to DAC (sine wave of 4096 samples, generated from FPGA)
• Conversion Start (CS)
• Output select on DAC (DAC_A_B)
• WRITE of DAC (WR)
Theory
DAC can be interfaced with the VLSI chip by providing the necessary digital input
from the chip. The digital output can be then converted and seen using any analog
measurement instrument or testing equipment. The detail of the DAC IC used here
.i.e. TLC 7528 is given below.
Figure 61
TLC7528 :
The TLC7528C is a dual, 8-bit, digital-to-analog converters designed with separate
on-chip data latches and feature exceptionally close DAC-to-DAC matching. Data is
transferred to either of the two DAC data latches through a common, 8-bit, input port.
Control input DACA/DACB determines which DAC is to be loaded. The load cycle
of these devices is similar to the write cycle of a random-access memory, allowing

Scientech 110
easy interface to most popular microprocessor/VLSI chip buses and output ports.
Segmenting the high-order bits minimizes glitches during changes in the most
significant bits, where glitch impulse is typically the strongest.
These devices operate from a 5-V to 15-V power supply and dissipates less than
15mW (typical). The 2- or 4-quadrant multiplying makes these devices a sound
choice for many microprocessor-controlled gain-setting and signal-control
applications. It can be operated in voltage mode, which produces a voltage output
rather than a current output.
Key Specification of DAC
Resolution 8 bits
Linearity Error 1/2 LSB
Power Dissipation at VDD = 5V 20mW
Settling Time at VDD = 5V 100ns
Propagation Delay Time at VDD = 5V 80ns
Daughter Card.
“1100”.
F. Now connect the output and ground (given on the left side of the mother board,
below the analog input section) to the DSO. It will show a sine wave of 1.5 KHz
(approx).
G. This sine wave is internally generated in the code.

Scientech 110
5. Interfacing ADC
eoc_adc
clock FPGA ADC
reset clk_adc
st_adc
ale_adc
sel_adc
oe_adc
dbus(7:0)
Led(7:0)
Figure 62
For theory refer the datasheet of ADC0809, in datasheet section
Daughter Card.
“1100”.
F. Now connect the external analog input to the A1 (channel one) of the analog
input section. Make sure that pins 1&2 of the jumper in front of the channel A1
are short. The external input should not exceed + 5V.
G. Now change the external analog input and the respective binary value will be
shown on the LED display in the 8 bit format.
H. If you do not have any external input source for the ADC, just take a wire and
connect the channel one of the analog input to the test points of the power
supply section. It will show the binary value with respective to the voltages (
+5V, +3.3V, +2.5V, +1.8V).

Scientech 110
6. Interfacing VGA Port
Figure 63
Inputs :
• Clock 25MHZ (clock)
• Reset (resetb)
• To move screen left (stop)
Outputs :
• Red, Green, Blue color line (rgb(2:0))
• Horizontal Synch (hsyncb)
• Vertical Synch (vsyncb)
• Reset output on led (reseto)

Scientech 110
Theory
The above shown entity represents a VGA interface using a VLSI chip and VB2 VGA
interface port.
VGA Port :
The five standard VGA signals red (R), green (G), blue (B), horizontal
synchronization (HS), and vertical synchronization (VS) are routed from FPGA pins
to the VGA connector. The color signals pass through 270-ohm resistors on the
Pegasus board to create a resistor-divider with the 75-ohm VGA cable termination.
This limits the voltage at the VGA connector to the specified 0V (fully-off) to 0.7V
(fully-on) range. This three-bit color system allows for eight different colors as shown
in the table.
Color Red Green Blue

Black 0 0 0
Blue 0 0 1
Green 0 1 0
Cyan 0 1 1
Red 1 0 0
Purple 1 0 1
Yellow 1 1 0
White 1 1 1
CRT Display Systems Background :
Cathode ray tube (CRT)-based VGA displays use amplitude-modulated, moving
electron beams (or cathode rays) to display information on a phosphor-coated screen.
LCD displays use an array of switches that can impose a voltage across a small
amount of liquid crystal, thereby changing light permittivity through the crystal on a
pixel-by-pixel basis. Although the following description is limited to CRT displays,
LCD displays have evolved to use the same signal timings as CRT displays (so the
"signals”. discussion below pertains to both CRTs and LCD’s).
CRT displays use three electron beams (one for red, one for blue, and one for green)
to energize the phosphor that coats the inner side of the display end of a cathode ray
tube (see drawing below). Electron beams emanate from electron guns, which are
finely-pointed heated cathodes placed in close proximity to a positively charged
annular plate called a "grid".
The electrostatic force imposed by the grid pulls away rays of energized electrons as
current flows into the cathodes. These cathode rays are initially accelerated towards
the grid. But they soon fall under the influence of the much larger electrostatic force
that results from the entire phosphor-coated display surface of the CRT being charged
to 20kV (or more). The particle rays are focused to a fine beam as they pass through

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the center of the grids and then they accelerate to impact on the phosphor-coated
display surface. The phosphor surface glows brightly at the impact point and the
phosphor continues to glow for several hundred microseconds after the beam is
removed. The larger the current fed into the cathode, the brighter the phosphor will
glow.
Between the grid and the display surface, the beam passes through the neck of the
CRT where two coils of wire produce orthogonal electromagnetic fields. Because
cathode rays are composed of charged particles (electrons), they can be deflected by
these magnetic fields. Current waveforms are passed through the coils to produce
magnetic fields that interact with the cathode rays and cause them to transverse the
display surface in a "raster" pattern, horizontally from left to right and vertically from
top to bottom.
As the cathode ray moves over the surface of the display, the current sent to the
electron guns can be increased or decreased to change the brightness of the display
at the cathode ray impact point. Information is only displayed when the beam is
moving in the "forward" direction (left to right and top to bottom), and not during
the time the beam is reset back to the top left edge of the display. Much of the
potential display time is therefore lost in "blanking" periods when the beam is reset
and stabilized to begin a new horizontal or vertical display pass.
The size of the beams, the frequency at which the beam can be traced across the
display, and the frequency at which the electron beam can be modulated determine
the display resolution. Modern VGA displays can accommodate different resolutions,
and a VGA controller circuit dictates the resolution by producing timing signals to
control the raster patterns. The controller must produce synchronizing pulses at 5V to
set the frequency at which current flows through the deflection coils, and it must
ensure that video data is applied to the electron guns at the correct time.
Raster video displays define a number of "rows" that corresponds to the number of
horizontal passes the cathode makes over the display area, and a number of
"columns" that corresponds to an area on each row that is assigned to one "picture
element" or pixel. Typical displays use.
Figure 64

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From 240 to 1200 rows, and from 320 to 1600 columns. The over all size of a
display. and the number of rows and columns determines the size of each pixel.
Video data typically comes from a video refresh memory with one or more bytes
assigned to each pixel location (the DI04 board uses three bits per pixel). The
controller must index into video memory as the beams move across the display, and
retrieve and apply video data to the display at precisely the time the electron beam is
moving across a given pixel.
VGA System Timings :
VGA signal timings are specified. Published, copyrighted and sold by the VESA
organization (WWW.vesa.org). The following VGA system timing information is
provided as an example of how a VGA monitor might be driven in 640 by 480 modes.
For more precise information, or for information on higher VGA frequencies refer to
the VESA website above.
A VGA controller circuit must generate the HS and VS timing signals and coordinate
the delivery of video data based on the pixel clock. The pixel clock defines the time
available to display one pixel of information. The VS signal defines the "refresh"
frequency of the display. i.e. the frequency at which all information on decoding logic
for sync pulse generation.
The display is redrawn. The minimum refresh frequency is a function of the display's
phosphor and electron beam intensity, with practical refresh frequencies falling in the
50Hz to 120Hz range.
The number of lines to be displayed at a given refresh frequency defines the
horizontal "retrace" frequency. For a 640-pixel by 4SD-row display using a 25MHz
pixel clock and 60 +/-1 Hz refresh, the signal timings shown in the table below can be
derived. Timings for sync pulse width and front and back porch intervals (porch
intervals are the pre- and post-sync pulse times during which information cannot be
displayed) are based on observations taken from VGA displays.
A VGA controller circuit decodes the output of a horizontal-sync counter driven by
the pixel clock to generate HS signal timings. This counter can be used to locate any
pixel location on a given row. Likewise, the output of a vertical-sync counter that
increments with each HS pulse can be used to generate VS signal timings, and this
counter can be used to locate any given row. These two continually running counters
can be used to form an address into video RAM. No time relationship between the
onset of the HS pulse and the onset of the VS pulse is specified, so the designer can
arrange the counters to easily form video RAM addresses, or to minimize decoding
logic for sync pulse generation.

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Figure 65
A. Place the FPGA Daughter card and Peripheral card on the Scientech 110 Mother
Board.
Daughter Card.
“1100”.
F. Now connect the computer monitor with the VGA port given on the
PERIPHERAL card. It will show a scrolling strip patterns of different colors on
the screen, if the DIP 1 is ‘0’. To stop the scrolling, make it ‘1’.
7. Interfacing Serial Port

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Figure 66
Inputs :
• 8 bit data input (dbus(7:0))
• Reset (rst_b)
• Receiver line from PC (rxd)
• Clock 8MHz (sysclk)
Outputs :
• 8 bit data output on LED (ASCII Data) (rdr(7:0))
• Transmitter Line to PC (txd)

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Theory
The above shown entity represents a RS232 serial port interface design for
transmission and reception of data using VLSI chip. The communication is done
between the PC and the VLSI development platform using the VB2 and VB1 boards.
Serial communication is done by using the RS232 protocol. MAX232 IC is being
used to match the PC and the development platform voltage level. i.e. the TTL and the
CMOS level. The detail about the IC and the platform is given below that can be used
to develop the application.
MAX232 :
• Meet or Exceed TIA/EIA-232-F and ITU
• Recommendation V.28
• Operate With Single 5-V Power Supply
• Operate Up to 120kbit/s
• Two Drivers and Two Receivers
• 30-V Input Levels
• Low Supply Current 8mA Typical
• Designed to be Interchangeable With
• Maxim MAX232
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• Applications
• TIA/EIA-232-F
• Battery-Powered Systems
• Terminals
• Modems
• Computers

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Figure 67
Typical Operating Circuit

Figure 68
Serial Protocol
The serial port on your PC and VB2 is a full-duplex device meaning that it can send
and receive data at the same time. In order to be able to do this, it uses separate lines
for transmitting and receiving data.
Once the start bit has been sent, the transmitter sends the actual data bits. There may
either be 5, 6, 7, or 8 data bits, depending on the number you have selected. Both
receiver and the transmitter must agree on the number of data bits, as well as the baud
rate. Almost all devices transmit data using either 7 or 8 data bits.
Notice that when only 7 data bits are employed, you cannot send ASCII values greater
than 127. Likewise, using 5 bits limits the highest possible value to 31. After the data
has been transmitted, a stop bit is sent. A stop bit has a value of 1 - or a mark state -
and it can be detected correctly even if the previous data bit also had a value of 1.
This is accomplished by the stop bit's duration. Stop bits can be 1, 1.5, or 2 bit periods
in length.

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Transmitter :
Transmitting is sending bytes out of the serial port away from the computer. Once you
understand transmitting, receiving is easy to understand since it's similar. When the
computer wants to send a byte out the serial port (to the external cable) the CPU sends
the byte on the bus inside the computer to the I/O (Input Output) address of the serial
port. I/O is often written as just IO. The serial port takes the byte, and sends it out one
bit at a time (a serial bit-stream) on the transmit pin of the serial cable connector.
At the EIA-232 serial port, voltages are bipolar (positive or negative with respect to
ground) and should be about 5 volts in magnitude. For the transmit and receive pins
+5 volts is a 0-bit (sometimes called "space") and -5 volts is a 1-bit (sometimes called
"mark"). This is known as inverted logic since normally a 0-bit is both false and
negative while a one is normally both true and positive. Although, receive and
transmit pins are inverted logic, other pins (modem control lines) are normal logic
with a positive voltage being true (or "on" or "asserted") and a negative voltage being
false (or "off" or "negated"). Zero voltage has no meaning (except it usually means
that the unit is powered off).
Note that normal computer logic normally is just a few volts (5 volts was once the
standard) so that if you try to use test equipment designed for testing 3-5 volt
computer logic (TTL) on the 12 volts of a serial port, it may damage the test
equipment.
The transmit pin (TxD) is held at -5V (mark) at idle when nothing is being sent. To
start a byte it jumps to +5V (space) for the start bit and remains at +5V for the
duration (period) of the start bit. Next comes the low-order bit of the data byte. If it's a
0-bit nothing changes and the line remains at +5V for another bit-period. If it's a 1-bit
the voltage jumps from +5 to -5V .After that comes the next bit (-5V if a 1 or +5V if a
0), etc., etc. After the last data bit a parity bit may be sent and then a -5V (mark) stop
bit. Then the line remains at -5V (idle) until the next start bit. Note that there is no
return to 0 volts and thus there is no simple way (except by a synchronizing signal) to
tell where one bit ends and the next one begins for the case where 2 consecutive bits
are the same polarity (both zero or both one).
In serial transmission of bytes via EIA-232 ports, the low-order bit is always sent first
(the bit-order). Serial ports on PC's use asynchronous communication where there is a
start bit and a stop bit to mark the beginning and end of a byte. This is called framing
and the framed byte is sometimes called a frame. As a result a total of 9, 10, or 11 bits
are sent per byte with 10 being the most common. 8-N-1 means 8 data bits, No parity,
1 stop bit. This adds up to 10 bits total when one counts the start bit. One stop bit is
almost universally used. At 110 bits/sec (and sometimes at 300 bits/sec) 2 stop bits
were once used but today the 2nd stop bit is used only in very unusual situations (or
by mistake since it still works OK that way but wastes bandwidth).

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Receiver :
Receiving bytes by a serial port is similar to sending them only it's in the opposite
direction. It's also interrupt driven. For the obsolete type of serial port with 1-byte
buffers, when a byte is fully received from the external cable it goes into the 1-byte
receive buffer. Then the port gives the CPU an interrupt to tell it to pick up that byte
so that the serial port will have room for storing the next byte which is currently being
received.
DTE and DCE :
Two terms you should be familiar with are DTE and DCE. DTE stands for Data
Terminal Equipment, and DCE stands for Data Communications Equipment. These
terms are used to indicate the pin-out for the connectors on a device and the direction
of the signals on the pins. Your computer is a DTE device, while most other devices
are usually DCE devices.
BAUD Rate :
Baud refers to modulation rate or the number of times per second that a line changes
state. This is not always the same as bits per second (BPS). If you connect two serial
devices together using direct cables then baud and BPS are in fact the same. Thus, if
you are running at 19200 BPS, then the line is also changing states 19200 times per
second. But when considering modems, this isn't the case.
Male
RS 232
DB9
Pin No Direction of signal
1 Carrier Dated (CD) (From DCE) Incoming signal
from a modern
2 Received Data (RD) Incoming Data from a DCE
3 Transmitted Data (TD) Outgoing Data to a DCE
4 Data terminal Ready (DTR) outgoing handshaking
signal
5 Signal Ground common reference voltage
6 Data Set Ready (DSR) incoming handshaking signal
7 Request to Send (RTS) Outgoing flow control signal
8 Clear to Send (CTS) Outgoing incoming control
signal
9 Ring Indicator (RI) (from DCE) Incoming signal
from a ,modern

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Board.
Daughter Card.
“1100”.
E. Now connect the PC with the serial port given on the PERIPHERAL CARD.
G. Go to the STAR menu à All programs à Accessories à Communication à
Hyper terminal.
Figure 68
H. Now cancel the location information and confirm the cancel. Then Press OK
button.

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Figure 69
I. Now it is showing the New connection-hyper terminal window. Give the name
for the connection press ok, then again cancel the location information and
confirm the cancel, then OK.
J. Now connect it to COM1.

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Figure 70
K. Now set the COM1 properties as :-
1. Bits per second : 4800
2. Data bit : 8
3. Parity : none
4. Stop bit : 1
5. Flow control : None
L. Then Press OK
M. Now press reset button given on the FPGA daughter card. Now change the input
8 bit data from DIP switches 1 to 8. The Character with respect to the 8 bit data
will be shown on the hyper terminal.
N. Press any key on the keyboard and the respective ASCII value will be displayed
on the LEDs.
8. Interfacing USB port.
Board.
Daughter Card.

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“1100”.
D. Switch ON the power by touching the power button given on the top left
corner of the Mother Board.
E. Now connect the PC with the serial port given on the PERIPHERAL CARD.
G. Open the HYPER TERMINAL. The procedure and settings for hyper terminal
are already given in the serial port testing(steps G to L).
H. Now press reset button given on the FPGA daughter card. Now change the
input 8 bit data from DIP switches 1 to 8. The Character with respect to the 8
bit data will be shown on the hyper terminal.
I. Press any key on the keyboard and the respective ASCII value will be
displayed on the LEDs.
8. Interfacing SRAM
sysclk Da_data_out(7:0)
reset Ram_address_buf(14:0)
STATIC RAM Bar_ram_ce20
play CY62256 Bar_ram_oe22
rec Bar_ram_we27
Ad_data_in(7:0) Ram_data_inout(7:0)
Inputs :
• Address (ad_data_in(7:0))
• Play command (play)
• Record Command (rec)
• System Reset (reset)
• System Clock (sysclk)
Outputs :
• Data output (da_data_out(7:0))
• Ram address buffer (ram_address_buf(14:0)
• Write Enable of RAM (bar_ram_we27)
• Chip Enable of RAM (bar_ram_ce20)

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• Output Enable of RAM (bar_ram_oe22)

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Input Output :
1. RAM data (ram_data_inout(7:0)
Theory
This design code can be used to interface a 256K (32X8) Static RAM with a VLSI
platform. Using this VB board one can store and then access the data on the RAM.
The detail about CYPRESS CY62256 256K (32X8) Static RAM is given below that
can be used to develop the design code.
Logic diagram :
Figure 71
For more details of SRAM IC CY62256, refer datasheet section
Daughter Card.
“1100”.
F. Now press reset button given on the daughter card.

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G. Set the input data by DIP switch 1 to 8. This data will be shown on leds 1 to 8.
H. Now keep the push button PB1 press for few seconds (about 10 seconds). This
will record the 8 bit data in the SRAM.
I. Now keep the push button PB2 press for few seconds(about 10 seconds). The
recorded data will play be shown on leds 9 to 16.
How to Do programming with CPLD daughter card.
The process for writing HDL code and; generating “.jed” file for CPLD is same as for
FPGA. But there is a difference in the programming method. The CPLDs gets
program in “boundary scan mode”.
1. Connect the JTAG cable for the CPLD daughter card.
2. If you have the “Impact” window open, then double click on the “boundary
scan” option.
3. Right click in the window, and click on the “initialize chain” option. ( power
should be ON at this instant).
4. Add the device and program the device.
Or
2. If you are generating a new “.jed” file, then select “boundary scan” in the
welcome to Impact window.
Figure 72
Make sure that the power is ON at this instant.

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2. Add the device from folder “CPLD daughter card” in the product CD, and
program the device.
For more details refer the section “How to use Xilinx software”.
***** The programming procedure for Cool Runner CPLD daughter card is
same as for CPLD daughter Card.
How to Do programming with ARM 7 Daughter Card.
Step 1 : Install the Programmer software (Philips Flash Utility) in your PC
You can download the hex code you have prepared, into the microcontroller using
programmer software. To install this software, choose the folder “ARM7” in the
accompanying CD (Scientech 110_Product_CD). You will find file Setup.exe. Now
double click on Setup.exe to run the installation program. Follow the instructions on
the screen. Click finish to complete the installation. After the completion of the
installation, your system loaded with software's:
1. Port Communication software
2. Philips Flash Utility
3. Sample Programs
To run the programmer software goes to the Start menu/All programs/Philips
semiconductor/Flash utility/Launch LPC210x_ISP.exe.
To do programming, following steps must be carried out :
1. Connect the serial cable from PC to the serial programming port given on the
Daughter Card.
2. Jumper settings for ARM7 Card.
Jumper SW2 2&3 short :- Programming mode.
1&2 short :- Application mode.
*Short pin no. 2 & 3 of Jumper SW2 while programming the Daughter card.
*Short pin no. 1 & 2 of Jumper SW2 for application mode.
3. switch ‘On’ the power switch.
4. Start the Philips flash utility (available in the all programs on the Start menu of
Windows OS: Start menu/All programs/Philips semiconductor/Flash
utility/Launch LPC210x_ISP.exe.) and select the appropriate port number
settings (use baud rate 9600).
5. Click the ‘Read device ID’ button on the LPC ISP utility to verify that the
Device ID is read properly.

Scientech 110
Figure 73
6. Push the reset switch ‘On’ the Daughter Card.
7. Click ‘OK ‘button, on the LPC ISP utility “Reset Message” dialog box.
8. The message “Read Part ID Successfully” will be display in the status bar
(Located at the left bottom) of the LPC ISP utility dialog box.
Figure 74
9. If any errors in communication check the COM port settings of your PC and
make sure that, the serial cable is connected to the trainer properly. I still it is
showing error, then switch OFF the power supply and switch it ON and try
again.

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Figure 75
10. Select the HEX file from the ARM 7 folder in the product CD , and upload it to
flash.
Figure 76
11. Switch OFF the power supply and change the jumper SW2 for application
mode. i.e. short pin no. 1 & 2.
12. Switch ON the power supply and press RESET button SW1 given on the
daughter card. You will see leds blinking and counter running on the seven
segment display.

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Universal Development Platform Lab

Lab Setup :
1. One Personal Computers or Laptops with following configuration:
a. Processor - Celeron 1GHz and above
b. Memory - 1 GB (Min.)
c. RAM – 512MB (Min.)
d. CDROM Drive
e. Parallel Port –Standard Port Type
f. USB or Serial Port.
g. Operating System – Software runs on Windows XP/2000/NT
2. Scientech 110 with FPGA and CPLD daughter cards.
3. Optional daughter cards (If required)
Note : Refer “Getting Started” section in Smart Manual from Scientech 110 Software
CD for better graphical understanding of Lab Setup and Labs.

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Data Sheet
ADC0809

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Datasheet SRAM
Updated 7-10-2008

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Datasheet DAC

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VLSI Design Cycle

A typical design flow for designing of VLSI circuits is shown below.
Figure 77

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1. Specifications :
The design cycle starts with the specifications, which describe the functionality,
interface and the architecture of the design that has to be designed. Timing
diagrams of the interfaces (inputs and outputs) are also specified, which is a part
of the specification.
2. Block Diagram and Waveform Analysis :
Block diagram representation of designs makes easier understanding of design.
The top-level block diagram of the design represents interfacing signals as per
the specifications. The design is also further split into smaller blocks according
to the functionality with the inputs and outputs names of the internal blocks
specified.
Timing diagram for all the internal blocks are drawn after the internal block
division, which is helpful in analyzing and designing the blocks.
3. Behavioral Description :
Describes the basic functionality of the design and its internal blocks, helpful in
analyzing the design's verification and implementation issues.
Basically it is described through HDL or with software languages like C or C++.
4. Register Transfer Level (RTl) Description :
The divided internal blocks are represented with basic components like registers,
multiplexers, decoders etc., in accordance to functionality. Logic reduction of
the design and synthesis issues is taken into consideration while doing the RTL
description. It is especially helpful in larger and high speed designs.
If the target device of the design to be implemented is a PLO, RTl has to be
described according to the architecture of the PLO, which makes the design
efficient in area and speed wise.
5. Design Entry :
The representation of the RTL description to CAD/EOA tools is known as
design entry. The design entry can be through HDL (Hardware description
Language) or schematic or FSM (Finite State Machines). As schematic and
FSM entry takes longer time to represent larger designs, HDL entry takes
precedence in design entry than the others.
HDI description offers the following advantages :
1. Easy representation of larger and smaller designs which makes designing
process faster.
2. Fully technology-independent.
3. Easier and faster verification of design.

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Design Flow :
Figure 78
6. Functional Verification :
Functional verification is done to check only the functionality of the design.
Usually it is done before synthesis so the delays of the gates and interconnects
are not taken into consideration. In case of verification failure, the process has to
start again from RTL description. Verification of designs is done through HDL
simulators.
7. Synthesis :
It is the process of converting a high level description of the design into an
optimized gate level representation, given standard cell libraries and design
constraints. From the synthesis process the design becomes fully technology
dependent, as the standard cell libraries characteristics varies from vendor to
vendor. Standard cell libraries have the gate level primitives like AND, OR,
NOR, NAND gates.
In case of PLDs synthesis process the synthesizer generates netlist file.
In case of XILINX, the synthesizer generates Xilinx Net Format (XNF) file that
uses Xilinx primitives.

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Figure 79
8. Logical Verification :
Logical verification is done with unit delay gates and interconnects, usually
done after synthesis.
9. Implementation :
The process of implementing the design for a specific target device is known as
Implementation. The Implementation flow is device or vendor specific. In case
of Xilinx, the flow engine runs following steps for implementation.
a. Translation : At this process, the flow engine merges all the netlist inputs
generated during synthesis and the whole design is translated according to
the device architecture.
b. Map (FPGA only) : The flow engine maps the translated design into the
components in the Xilinx FPGA.
c. Place and Route (FPGA only) : The flow engine places and routes the
mapped design at this process.
d. Fit (CPLD only) : The Flow engine launches the CPLD fitter to minimize
and collapse the design's combinational logic, to make the design to fit into
the available resources of the device. Fitting is done after translation.
e. Configure (FPGA only) : Done after the design is completely routed. A
binary format configuration file (.bit) is generated in this process, contains
all.
Configuration information defining the internal logic and interconnections of the
FPGAs, plus the device specific information from other files associated with the
target device. The generated bit file is downloaded into the device through the
Hardware debugger.
Configuration of FPGA device can be done in various modes such as,
i. Slave serial mode,
ii. Master serial mode, etc.
The mode of configuration can be selected according to the mode pins selection
in the FPGA, as specified by Xilinx.

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f. Bit stream (CPLD only) : Configuration file (.jed) for the CPLD is
generated at this stage. The CPLD device is configured through the JTAG
programmer. Configuration of CPLD device can be done in various modes
such as Boundary-scan mode, scan chain mode etc.
Setting the implementation options using options command can change the aspects of
the implementation.
Figure 80
10. Post Layout Simulation : Done after the design is placed and routed, with the
simulation primitives given by the device vendor. Dynamic timing analysis is
done at this stage i.e. whether the design is working functionally at the desired
speed under worst-case conditions. In case of verification failure the design
process has to restart from RTL description.The typical design flow of VLSI
design cycle ends up with the implementation of design into the device and is
checked with proper physical constraints. In case of verification failure of the
device's function in board level, process has to restart from RTL description.

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Appendix
Glossary :
A:
ASIC (Application Specific Integrated Circuit) : A custom integrated circuit
designed specifically for one end product or a closely related family of end products.
B:
Back Annotation : The updating of a circuit design using simulation and other post-
processing information that reflects implementation dependent characteristics of the
design such as pin selection, component location, or parasitic electrical
characteristics.
Behavioral Model : A high-level representation of an electronic design that describes
the behavior of various modules or subsystems in the design, usually without regard
to the underlying technology used to implement the design.
BiCOMS (Bipolar, Complementary Symmetry Metal Oxide Semiconductor) : An
integrated circuit fabrication technology that combines the two major IC technologies,
bipolar and CMOS, on one IC.
Bipolar : The original semiconductor manufacturing process technology. Usually
characterized by high speed, high power operation.
C:
Clock : A master timing signal that sets the operating pace of all other components in
the embedded system.
Clock Skew : Variation from the ideal clock timing across an entire electronic design
(usually in an IC) caused by parasitic elements. Seymour Cray was an early
combatant of clock skew and had to design serpentine traces on the Cray I
supercomputer’s circuits boards to compensate for clock skew.
Clock Tree : A tree like configuration of circuitry designed to minimize the effects of
clock skew.
CMOS (Complementary Symmetry Metal Oxide Semiconductor) : An IC process
technology developed in the 1960s which typically runs at lower power than bipolar
circuitry. Early on, CMOS was much slower than bipolar but has steadily gained in
speed over the decades to rival today’s bipolar speeds. Most ICs are now made using
CMOS technology.
Concurrency : The ability of an electronic circuit to do several (or at least two)
different things at the same time. Contrast with computer programs which usually
execute only one instruction at a time unless the program is running on a processor
with multiple, concurrent execution units.
Core : A pre-designed block of logic employed as a building block for ASIC design.

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Crosstalk : A condition where signal activity on one wire in an electronic circuit

couples to another wire and causes noise through electrostatic (capacitive) or
electromagnetic (inductive) coupling.
CPLD (Complex Programmable Logic Device) : A programmable IC which is
more complex than the original Programmable Logic Devices such as AMD’s
(originally MMI’s) PAL’s but somewhat less complex than Field Programmable
Logic Arrays.
CPU (Central Processing Unit) : The core circuitry of a computer including the
ALU (arithmetic logic unit), address control circuitry, and bus control circuitry.
Usually implemented with a microprocessor or microcontroller in an embedded
system.
CUPL : A hardware description language originally developed for PLD’s.
D:
Debugging : The art of finding and eliminating errors in system designs.
Design Capture (also Design Entry) : The process of entering an electronic system
design into a computer using EDA tools.
Design Rule Check : Verification of an IC or pc board layout for conformance to the
physical of electrical limitations of the implementation technology in use.
DFT (Design for Test) : A design methodology that includes special attention to the
design of a circuit and the addition of special circuitry that eases the testing of that
design.
Digital Simulation : A computer simulation of an electronic circuit that uses simple
Boolean or logic states to represent the instantaneous state of the circuit. Because the
representation is simplified from the actual voltage and currents present in the circuit,
digital simulation is much faster than analog simulation.
Digital-to-Analog Converter (also D/A and DAC) : A circuit that translates a signal
from a numeric, digital representation used by microprocessors and microcontrollers
into an analog signal.
DSP (Digital Signal Processor or Digital Signal Processing) : A specialized
microprocessor or electronic system designed to be very fast at processing continuous
signals such as sound and video.
E:
EDA (Electronic Design Automation) : A large collection of software tools that
enhance and aid in the development of complex electronic systems.
EDIF (Electronic Design Interchange Format) : A standard representation format
for describing electronic circuits, used to allow the interchange of circuit design
information between EDA tools.
Emulator (also ICE or In-Circuit Emulator) : A complex, expensive, and often
balky electronic system that simulates the presence of an embedded system’s

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microprocessor or microcontroller. Used often and extensively in the development

and debugging of embedded system programs.
Event : A point in time where a change occurs in the state of an electronic circuit.
Event-Driven Simulator : A simulator that only calculates circuit conditions when
events (changes) such as the start of a new clock cycle occur in the state of the
system. In contrast, timing simulation computes the state of a system using elapsed
time (usually in nanoseconds of picoseconds).
F:
Fast Prototype : A working product model built quickly to try out product concepts.
May lack the fit, finish, and complete capabilities of the planned final product while
still giving users an idea of how the product will work. Often assembled specifically
for a conference or other dog and pony show.
Fault : An actual problem in an electronic circuit that disables or degrades the
performance of the circuit. Also, for EDA purposes, a point in the circuit where a
potential flaw could damage the circuit’s operation.
Fault Coverage : The percentage of potential faults identified and tested by a test
program or suite of test programs. If the tests can uncover all potential faults, the fault
coverage for those tests is 100 %.
Finite Element Modeling : A relatively complicated numerical method (computer
algorithm) that can model complex electrical phenomena such as electromagnetic
wave front propagation.
Floor Planning : The task of determining where each major block of circuitry will go
within an IC design.
FPGA (Field Programmable Gate Array) : An integrated circuit containing a large
number of logic cells or gates that can be programmably configured after the IC has
been manufactured. Some FPGAs use fuses for this programming and others store the
configuration in an on-chip EEPROM or RAM memory. Fuse programmed parts
cannot be reprogrammed so they can only be configured once. EEPROM-based
FPGAs can be erased and reprogrammed so they can be configured many times. RAM
based FPGAs can be reconfigured quickly, even while the circuit is in operation.
G:
GaAs (Gallium Arsenide) : A high speed IC process technology that does not use
silicon. Instead, GaAs uses the semiconductor element Gallium doped with the
impurity Arsenic. GaAs process technology currently produces the fasted ICs possible
but advanced CMOS processing has greatly reduced the speed gap in the past few
years. GaAs is most often used today for very high frequency radio circuits such as
the transmitter circuits in cellular phones.
Gate Array : A type of ASIC in which the transistors, gates, and other active circuit
elements are fixed on a wafer called a “master slice”. The customization for a
particular application is done using the metal interconnection layers on the chip. Thus,
the IC vendor can fabricate and stockpile master slices well in advance of a customer
order and then finish the fabrication by adding the metal layer or layers when the

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order is received. Because of this style of fabrication, gate arrays are the easiest
ASICs to design and offer the fastest turnaround time between order and shipment of
the finished parts. In the extreme, Chip Express offers laser programmed gate arrays
with 24-hour turnaround time (or less if you really have the money).
H:
HDL (Hardware Description Language) : A synthetic computer based language
used for the formal description of electronic circuits. An HDL can describe a circuits
operation, its design, and a set of tests to verify circuit operation through simulation.
The two most popular digital HDLs are VHDL and Verilog. An analog HDL called
AHDL is under development by many vendors. HDLs make it easier to develop very
large designs through formal software engineering methods that define ways to divide
a large team project into smaller pieces that can be implemented by individual team
members.
Hierarchy : A method for describing and modeling an electronic system using
different abstraction levels. At the bottom level of the hierarchy is the actual physical
layout of the design (a concrete level, not at all abstract). At the top of the hierarchy is
a functional description of the system or a block diagram (a very high level of
abstraction). Intermediate levels include the register-transfer level (RTL), the gate
level, and the transistor level.
I:
IC (Integrated Circuit) : A silicon chip containing hundreds, thousands, or millions
of circuit elements such as transistors, resistors, capacitors, and inductors. RAM,
ROM, microprocessors, and microcontrollers are all examples of integrated circuits.
I/O (Input/Output) : The wide range of circuits and sensors used to bring
information into an embedded-system processor and to transport processed
information back out of the processor. Serial and parallel ports, keyboard and keypad
controllers, floppy and hard disk drives, and displays are all examples of I/O devices.
M:
MCM (Multi-Chip Module) : A hybrid manufacturing technique which places
several IC chips into a single package. MCMs are a way of "creating" an integrated
circuit using otherwise incompatible IC fabrication technologies (such as CMOS and
GaAs). MCMs are also a way of extending the reach of existing ASIC technologies
which may lack the ability to implement an entire system design on one chip.
Microcontroller (also mC) : A real "computer on a chip" incorporating a
microprocessor, memory, and I/O circuits on one integrated circuit. In many
embedded systems, the microcontroller may well be the only integrated circuit in the
design.
Mixed-Mode : Operation in both the digital and analog domains (usually refers to
simulation as in "mixed-mode simulation").
Mixed-Signal : An electronic circuit that has both analog and digital sections.
Because many "real-world" systems have analog interfaces (for example, most
temperature, pressure, sound, and video sensors are analog), most electronic systems
must accommodate analog signals. However, signal processing is now most

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efficiently performed by digital circuits. Therefore, almost all modern electronic

systems are mixed-signal systems although individual ICs in such systems need not be
mixed-signal chips. Instead, a design can achieve mixed signal operation by
combining separate analog and digital ICs.
Microprocessor (also mP) : The original "processor on a chip" introduced by Intel in
1971. An integrated circuit that contains all of the processing components of a
computer CPU including the ALU, program sequencer, and bus interface. Newer
microprocessors also incorporate cache memory for increased processing speed.
Comes in 4-,8-, 16-, 32-, and 54-bit varieties. Usually requires other ICs to make up
an embedded system.
Microprocessor Emulator : A piece of equipment that substitutes in a circuit for the
circuit's microprocessor. The emulator gives more control over the circuits operation
and eases debugging and troubleshooting efforts.
MIPS (Millions of Instructions Per Second) : A performance figure of merit
(numeric score or rank) for microprocessors and microcontrollers.
Moore's Law : An empirical law developed and later revised by Intel's Gordon
Moore which predicts that the IC industry is capable of doubling the number of
transistors on a silicon chip every 18 months (originally every year) resulting in
declining IC prices and increasing performance. Most design cycles in the electronics
industry including embedded-system development firmly rely on Moore's law.
Multitasking : A programming style that splits the overall job to be performed by the
embedded system into a number of smaller tasks which then execute on the system's
processor in a time-shared fashion.
N:
Net : 1. For ASICs, an individual signal path including all of its branches and
extensions. 2. An abbreviation for the Internet.
Net Extraction : The identification and cataloging of all signal paths in a circuit. The
combination of all nets and circuit elements (transistors, resistors, capacitors, ICs,
etc.) of an electronic design completely describes an electronic circuit.
Net List (or Netlist) : A computer file (sometimes a printed listing) containing a list
of the signals in an electronic design and all of the circuit elements (transistors,
resistors, capacitors, ICs, etc.) connected to that signal in the design.
O:
Object-Oriented Programming : A programming style that combines data blocks
and the associated software processing algorithms into "encapsulated" modules with
narrowly defined entry and exit points. This programming style was developed as a
way of dealing with extremely large and complex software programming projects by
breaking the project down into smaller chunks more easily handled by an individual
programmer. The narrowly defined entry and exit points of each module prevent one
programmer's module from disrupting another's.

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P:
PAL (Programmable Array Logic) : The first truly successful family of
programmable logic, originally introduced by Monolithic Memories in the early
1980s.
PGA (Pin Grid Array) : A type of IC package, usually square with many
interconnection pins (often hundreds).
Place and Route : A layout task that positions major functional blocks or electronic
components within an IC or on a PC board (Place) and the subsequent routing of
appropriate electrical connections to those components (Route).
PLCC (Plastic leaded Chip Carrier) : A low-cost IC package (usually square).
PLCCs have interconnection leads on either two (usually only for memory chips) or
all four sides (f or logic and ASIC chips).
PLD (Programmable Logic Device) : The generic term for all programmable-logic
ICs including PLAs (programmable logic arrays), PALs, CPLDs (complex PLDs),
and FPGAs (field programmable gate arrays).
PROM (Programmable Read-Only Memory) : An integrated circuit that stores
programs and data in many embedded systems. PROM stores retains information even
when the power is off but it can only be programmed or initialized once.
R:
RAM (Random-Access Memory) : An integrated circuit that stores programs and
data in many embedded systems. RAM does not retain information when the power is
off and must therefore be reinitialized every time the embedded system is switched
on.. There are many varieties of RAM including the two most popular types: Dynamic
RAM (DRAM) and Static RAM (SRAM).
RC Extraction : The mathematical computation of an electronic circuits fundamental
circuit elements: resistors (abbreviated R), and capacitors (abbreviated C). RC
extraction allows a simulator to determine the expected behaviour of the electronic
circuit through the mathematical modeling of simple circuit elements.
Register : A location inside of a microprocessor, microcontroller, or I/O controller
chip that stores control or status information.
ROM (Read-Only Memory) : An integrated circuit that stores programs and data in
many embedded systems. PROM stores retains information even when the power is
off but it can only be programmed or initialized once and only at the semiconductor
factory.
RTL (Register Transfer Level or Register Transfer Logic) : A register-level
description of a digital electronic circuit (see "Hierarchy". Registers store intermediate
information between clock cycles in a digital circuit, so an RTL description describes
what intermediate information is stored, where it is stored within the design, and how
that information moves through the design as it operates.

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S:
Schematic : A graphical representation of an electronic circuit. Until the 1980s,
schematics were really the only representation system used to describe circuits.
However, with the advent of HDLs and an explosion in circuit complexity, schematics
are becoming less important as a representation tool.
Simulation : Modeling of an electronic circuit (or any other physical system) using
computer-based algorithms and programming. Simulations can model designs at
many levels of abstraction (system, gate, transistor, etc.). Simulation allows engineers
to test designs without actually building them and thus can help speed the
development of complex electronic systems. However, the simulations are only as
good as the mathematical models used to describe the systems; inaccurate models lead
to inaccurate simulations. Therefore, accurate component models are essential for
accurate simulations.
SPICE (Simulation Program with Integrated Circuit Emphasis) : The granddaddy
analog simulation program developed at the University of California at Berkeley in
the early 19705.
SRAM (Static Random-Access Memory) : An integrated circuit that stores
programs and data in many embedded systems. SRAM does not retain information
when the power is off and must therefore be reinitialized every time the embedded
system is switched on. SRAM is more expensive than DRAM on a cost-per-bit basis
but is usually easier to connect to a microprocessor or microcontroller.
Standard Cell : A form of ASIC design that employs predefined logic cells and
circuit component s to create an ASIC. All mask layers of a standard-cell ASIC are
custom for that ASIC, in contrast to a "Gate Array" in which only the metal-layer
masks are custom. Standard-cell ASICs usually run faster and use less silicon (and are
therefore usually cheaper on a per-part basis) than Gate Arrays. However, because the
standard-cell ASIC uses predefined circuit components, its usually easier to design
(and therefore requires less time to design) than a full custom ASIC where every
resistor, capacitor, and transistor is custom built.
State Diagram : A graphical representation of state machine's operation. State
diagram editors are EDA tools specifically design to aid in the development of state
machine designs.
State Editor : A design-entry EDA tool used to create state diagrams.
State Machine : A digital circuit built from registers and gates that controls the
operation of other circuitry. For example, microprocessors contain many state
machines that sequence the flow of information over the processor's bus and through
its data-manipulation circuits.
Static Timing Analyzer : An EDA tool that exhaustively checks every signal path in
a circuit to identify timing-related design problems.
Symbol : A graphic, schematic library element that represents an electronic
component such as a resistor, a capacitor, a transistor, or an IC.

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Synchronous : A digital circuit where all of the operations occur in lock step to a
master clock signal.
Synthesis (also Logic Synthesis) : A computer process that transforms a circuit
description from one level of abstraction to a lower level, usually towards some
physical implementation. Synthesis is to hardware design what compilation is to
software development. In fact, logic synthesis was originally called hardware
compilation.
T:
Test Vector : A stimulus pattern applied to a circuit to verify the circuit's operation.
Timing Diagram : A graphical representation of the signals in an electronic circuit
that shows how the signals change over time in relationship to each other. Timing
Simulation - Simulation of an electronic circuit's operation over time using calculated
circuit parameters such as resistance, capacitance, inductance, and timing delays.
Transmission Line : A conductor or wire that is suited to carrying high-frequency
signals.
Top-Down Design : A design methodology that starts the design of an electronic
system at the very highest level of abstraction and then methodically broadens the
design through lower abstract layers until finally reaching the concrete, physical
design layer which accurately represents the implementation technology for the
system.
U:
Unit Delay Simulation ; A simplified form of timing simulation where every digital
gate is assumed to introduce one unit of delay to a signal. In reality, different gates
have different speeds, but unit delay simulation trades off accuracy for simulation
speed.
V:
Verification : The task of establishing the correctness of a design using EDA tools to
automatically check the timing, connections, and rules used to design the circuit.
Verilog-A hardware description language developed by Gateway Design Automation
(riow part of Cadence) in the 1980s which became very popular with ASIC and IC
designers.
VHDL (VHSIC Hardware Description Language) : A hardware description
language developed in the 1980s by IBM, Texas Instruments, and Intermetrics under
US government contract for the Department of Defense's VHSIC (Very High Speed
Integrated Circuit) program. VHDL enjoys a growing popularity with ASIC designers
as VHDL development tools mature.

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Warranty
1. We guarantee this product against all manufacturing defects for 24 months from
the date of sale by us or through our dealers.
2. The guarantee will become void, if
a. The product is not operated as per the instruction given in the Learning
Material.
b. The agreed payment terms and other conditions of sale are not followed.
c. The customer resells the instrument to another party.
d. Any attempt is made to service and modify the instrument.
3. The non-working of the product is to be communicated to us immediately giving
full details of the complaints and defects noticed specifically mentioning the
type, serial number of the product and date of purchase etc.
4. The repair work will be carried out, provided the product is dispatched securely
packed and insured. The transportation charges shall be borne by the customer.
Hope you enjoy the Scientech Experience.
List of contents
1. Scientech 110 Mother board………………… ............................................ 1 No.
2. Scientech 110 FPGA Daughter Card........................................................... 1 No.
3. JTAG cable for FPGA/CPLD Daughter Card ............................................ 1 No.
4. Scientech 110 CPLD Daughter Card........................................................... 1 No.
5. Scientech 110 Peripheral Card .................................................................... 1 No.
6. Power Supply ............................................................................................. 1 No.
7. Serial Cable (Male to Female) ................................................................. 2 Nos.
8. USB Cable (Male to Female D-Type) ......................................................... 1 No.
9. Xilinx ISE Web Pack
10. Mains Cord................................................................................................. 1 No

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ST110

Universal Development Platform

Designed & Manufactured by-

Scientech Technologies Pvt. Ltd. 1

Universal Development Platform

Scientech Technologies Pvt. Ltd. 2

Use in proper Atmosphere : Please refer to operating conditions given in the

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• On board : +5V, 3.3V, 2.5V,1.8V supply

FPGA Daughter Card:

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Software: - Xilinx Webpack Ver. / 10.1Ver.

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Altera Cyclone II FPGA Daughter Card

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Spartan-II FPGAs XC2S XC2S30 XC2S50 XC2S10 XC2S15 XC2S20

Comparison of the Spartan device families :

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Spartan II CLB Slice (Two per CLB)

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Introduction to CPLD (Complex Programmable Logic Devices)

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Xillinx XC9500 Architecture

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MODE A :- Boundary Scan Mode

MODE B :- Slave Serial Mode

2. EPROM Programming Mode :

3. EPROM to FPGA Mode:

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Xilinx Web Pack Introduction

CDA Tool General Design Flow

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Procedure for Designing in Xilinx ISE WebPack

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Step 2 : Go to file menu “New Project”.

click on the “New Project” .

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Step 3 : “New Project Wizard” will appear

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Step 4 : Select the Family, Device and Package of the chip.

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New Source Wizard Summary will appear click “Finish”.

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Step 9 : Next window appearing will be :

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