A B C D E

MODEL NAME : LA-F371P non-AR

PCB NO : DAA000EC010
BOM P/N : 431A8C31L01

1 1

Dell/Compal Confidential
2 2

Schematic Document
Pebble Creek MLK (Kabylake R/U)

3 3

2017-11-03
Rev: 1.0
ZZZ
MB_PCB

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P01-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 1 of 65
A B C D E
 A B C D E

VCC_EC
12.3" 3:2 VSW_3V3
eDP x2 lanes
Samsung WUXGA+ p.22 eDP
Channel A - 4GB

ALS Memory Bus Channel A - 4GB

on WF camera module I2C LPDDR3 1866/2133
AMS-TAOS TSL2591 p.31 ISH Channel A
32Gb x 32 QDP p.19
I2C I2C 3.3V LDO Boost
Touch Cntrl TPS61200
Wacom G12T-W9015 SPI SPI#2 Channel B - 4GB
p.22
Memory Bus Channel B - 4GB
Channel B LPDDR3 1866/2133
1 Gyro + Accelerometer I2C I2C (iSH) 32Gb x 32 QDP p.20
1

ST LSM6DS3TR p.31

MIPI CSI-2 x 2lanes

SPI ROM 16M (Main) CSI-2#2 5MP FFC
E-Compass SPI SPI#1
SPI ROM 4M(2nd) p.7 I2C 5BF501T2/OV5670
ST LIS2MDLTR p.31 I2C p.33

I2C SKYCAM PMIC

NPCT750JBAYX p.31 I2C
TPS68470YFFR_DBSGA56 VSW_3V3 VCC

Finger Print Reader SPI MIPI CSI-2 x 2lanes 8MP RFC I2C
CSI-02#0 5BA802T2/OV8858
NB 2023-S USH Control Vault USB 2.0 p.33 A/D
USB#7 p.34 TX/RX Pi-Matching i-pex conn
Broadcom 58102
Module : DWRFID1603 A/D
D+/D- Face IR Module
USB2.0#5
LiteOn 5SF106N2B
Smart Card Reader p.43
RDIF/NFC
NXP TDA8034HN Antenna
on IO board IOB conn p.43
KabyLake U
I2C_CLK I2C_CLK
HDA Audio Codec Universal
HDA I2C_DAT I2C_DAT
1.5V ALC3253-VA3-CG p.28 Headset Jack p.29
SSD M.2 2280 0 PCIe x 2lanes
8 PCIe#7,8 SPI ROM 2MB SPI I2C_INT I2C_INT
Slot 3-Key-M 2 SPI
p.23 2

GNSS I2C 4x DMIC 2x

Speaker
CSR1021 GPIO
PTP_MODE#
PTP_SLP#
PTP_MODE# USB_D+ USB 2.0 D+
WWAN 4G LTE I2C (iSH) p.29 GPIO EN USB_D- USB 2.0 D-
p.28
M.2 3042 Slot 2-Key-B PCIe x 2lanes
2 PCIe#11/PCIe#12 3DMIC on M/B 5V 5V
4
0 USB 3.0 / SSIC 1DMIC on WFCAM
Hardware Crypto Accelerator 3 USB3 # 2 / SSIC
Module : EM7455 p.25 USB 2.0
USB2 # 4 GND GND CLK Charge/Low_BAT#
DAT
LTE Coex
uSIM INT
p.26 Dock_Detect KB_LED_PWM
GPIO DET_L DET_L I/O Expander KB_BL_DET#
2
TI TCA6416 MASK_LED# 2

MUTE_LED#
WLAN / BT 4.1 PCIe x 1lane
PCIe#5 BT_LED#
M.2 2230 Slot 1-Key-A PCIe x 1lane I2C1 I2C1
3x3(UI) 0 PCIe#6 I2C_CLK
3 CLK CLK
2 USB2.0
WiGig (UI) 2 USB2#7 I2C_DAT
Module : eLBS
RFFEM UART I2C_INT I2C_CLK
8265NGW/QCNFA344A CLINK
18265NGW
p.24 CLINK I2C1 I2C1 I2C_DAT Accelermeter
DAT DAT ST LNG2DMTR
I2C_INT
SD4.0/SDXC
RealTek I2C_INT
uSD Connector PCIe x 1lane I2C1 I2C1
SD_WP RTS5242 PCIe to SD p.27 PCIe#9
p.27 INT INT

GPIO
(BIOS Controlled)
5V/2A 5V 5V KSO/KSI

USB3.0 TypeA BC1.2 USB2.0USB2.0 GPIO

USB2#9
BC1.2 TI TPS2544 p.38 UART
with Power Share USB3.0 USB3.0
USB3#3 USB2#2
D+ D+ USB 2.0 D+
USB 2.0 D-
Keyboard Matrix
TI TPS2544
p.38 5V@1.5A
D- D-
USB3.0 / DP x 2lanes or DP x 4 lanes
Parade DP1.2 x 4lanes
DDI#2
MUX
VBUS to EC PS8743A USB3.0 USB3.0#1
CHRG_IN p.37
MOSFET CHRG_IN 12V 12V

From EC
USB3.0
Parade USB3.0#4
Port-A VBUS PP_5V0 5V_ALW
MUX DP1.2 x 4lanes HEAD_DET# GPIO GPIO BT ON/OFF Button
USB Type-C CC 2 CC DDI#1 DET_R DET_R
ALT mode PS8743A
p.37
with PD I2C to EC
TI-ACE 65982-DC
USB (Top) EC JTAG XDP DEbug GND GND VR_OUT
3 ESPI 3

USB (Bottom)
to PCH
p.35 SAR Proximity Sensor I2C 3
p.39 Smtech SX9310 I2C_CLK SPI Programmer ESPI Debug
p.31
WCFW_EN
I2C_DAT
Hall Sensor (On USH board) I2C_INT
USB3.0 / DP x 2lanes or DP x 4 lanes TCS40DPR USB PD Debug APS Debug +VCC_EC
p.31
EC
WC_OUT
VBUS
CHRG_IN Kickstand Open /Close detection MEC5105
MOSFET (mechanical switch) DCI Debug Coin Cell
p.42 p.30

From EC POGO_DET_R#
Port-B VBUS PP_5V0 5V_ALW
USB Type-C CC 2 CC
WC_DISC
WC PRU Board
ALT mode
with PD I2C to EC

TABLET
CHG_DICS(NC)
TI-ACE 65982-DC
USB (Top)
I2C#1_INT
USB (Bottom)
to PCH
I2C#1_DAT
p.36
p.39
I2C#1_CLK

GND

Keyboard
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P02-Block Diagram
Si ze Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Dat
Date:
e: Tuesday, November 07, 2017 Sheet 2 of 65
A B C D E
 A B C D E

Rear Camera + 4th DMIC

BTB FPC 34 pin

Front Camera + ALS sensor+ LED

1 1

BTB FPC 30 pin

JUFC1
p.33
PWR_BUTTON Board
JWFC1
p.33
LS-F371P

IOB
M/B LS-F371P

BATT_CONN
2
LA-F371P 2

IOB Cable
p.47

JIOB1 BTB FPC 40pin

p.43
JIOB2

p.43 BTB FPC 30pin

eDP+iTouch

Dock Board LS-F372P

3 p.22 (K/B + Bluetooth + Wireless Charge) 3

iTouch
eDP+itouch Y-Cable
Coaxial cable 50P 14pin

LCD Panel
Base Board 40pin
LS-D893P

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P03-DaughterB block diagram
Size Document Number Rev
LA-F371P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 3 of 65
A B C D E
 A

Board ID Table Board ID Table USB 3.0

Vcc 3.3V +/- 5%
Board ID R C REV Board ID PCB Revision Interface DESTINATION
Flexible I/O
0 240K +/- 5% 4700p 0
1 130K +/- 5% 4700p Pre-EVT1 1 0.1 1 USB 3.0 #1 USB Type-C Port-A
2 62K +/- 5% 4700p EVT1 2 0.2
3 33K +/- 5% 4700p DVT1 3 0.3 2 USB 3.0 #2/SSIC NGFF (WWAN)
4 8.2K +/- 5% 4700p DVT2 4 0.4
5 4.3K +/- 5% 4700p PVT 5 1.0 3 USB 3.0 #3 USB 3.0 Type-A
6 2K +/- 5% 4700p 6
7 NC 7 4 USB 3.0 #4 USB Type-C Port-B

5 PCI-E#1 / USB 3.0#5 Reserved for AR

SMBUS Control Table 6 PCI-E#2 / USB 3.0#6 Reserved for AR
PD Trinity IO
SOURCE Base BATT Charger XDP USH P-Sensor MUX IMVP
Controller Dock EXpendor 7 PCI-E #3 Reserved for AR
No use PCH_SML0CLK PCH
PCH_SML0DATA 8 PCI-E #4 Reserved for AR
PCH_SML1CLK PCH
PCH_SML1DATA 9 PCI-E #5 NGFF (WLAN)
SMBCLK
SMBDATA
PCH
V 10 PCI-E #6
EC_SMB00_CLK MEC5105 11 PCI-E #7 NGFF (SSD)
EC_SMB00_DAT
V V V Link
EC_SMB01_CLK MEC5105 12 PCI-E #8 /SATA #1 NGFF (SSD) #7/#8 2lane PCI-E
EC_SMB01_DAT
V
EC_SMB02_CLK MEC5105 13 PCI-E #9 Card Reader
EC_SMB02_DAT
V V
EC_SMB03_CLK MEC5105
EC_SMB03_DAT 14 PCI-E #10
EC_SMB04_CLK MEC5105
15 PCI-E #11 NGFF (WWAN/2nd SSD)
1
EC_SMB04_DAT
V V V 1

EC_SMB05_CLK MEC5105
16 PCI-E #12 NGFF (WWAN/2nd SSD)
EC_SMB05_DAT
V V
EC_SMB10_CLK MEC5105
EC_SMB10_DAT
V

Port Mapping USB 2.0 CLK Displayport

USB 2.0 PORT# DESTINATION DIFFERENTIAL DESTINATION DDI PORT# DESTINATION

1 Type-C Port-A CLKOUT_PCIE0 DDI 1 USB Type-C Port-B

2 Dock CLKOUT_PCIE1 NGFF (WLAN) 2 USB Type-C Port-A

3 Type-C Port-B CLKOUT_PCIE2 NGFF (WWAN)

4 WWAN CLK CLKOUT_PCIE3 SSD

5 IR CAM CLKOUT_PCIE5 Card Reader Symbol Note :

7 WLAN

9 USB Type-A
FLEX CLOCKS DESTINATION @ : means de-pop

CLKOUT_LPC_0 ESPI
10 USH : means Digital Ground
CLKOUT_LPC_1 ESPI
: means Analog Ground

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P04-Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 4 of 65
A
 5 4 3 2 1

+3VS

@ UCPU1A SKL-U
Functional Strap Definitions I2C0_IRQ_TS RC1942 1 100K_0201_5%
GPP_E19 (Internal Pull Down): DDPB_CTRLDATA E55 C47
37 DDI1_P2_TXN0 DDI1_TXN[0] EDP_TXN[0] eDP_TXN_P0 22
0 = Port B is not detected. 37 DDI1_P2_TXP0
F55
DDI1_TXP[0] EDP_TXP[0]
C46
eDP_TXP_P0 22 2Lane eDP
E58 D46 +3VS
1 = Port B is detected. 37 DDI1_P2_TXN1
F58 DDI1_TXN[1] EDP_TXN[1] C45 eDP_TXN_P1 22
GPP_E21 (Internal Pull Down): DDPC_CTRLDATA Type-C PortB 37 DDI1_P2_TXP1
F53
DDI1_TXP[1] EDP_TXP[1]
A45 eDP_TXP_P1 22
37 DDI1_P2_TXN2 DDI1_TXN[2] EDP_TXN[2]
0 = Port C is not detected. 37 DDI1_P2_TXP2
G53
DDI1_TXP[2] EDP_TXP[2]
B45
F56 A47
1 = Port C is detected. 37 DDI1_P2_TXN3
G56 DDI1_TXN[3] EDP_TXN[3] B47 WLAN_RST# RH5051 2 10K_0201_5%
37 DDI1_P2_TXP3 DDI1_TXP[3] EDP_TXP[3]
D C50 E45 D
37 PCH_DDI2_N0 DDI2_TXN[0] DDI EDP EDP_AUXN eDP_AUXN 22
D50 F45
37 PCH_DDI2_P0 DDI2_TXP[0] EDP_AUXP eDP_AUXP 22
C52
37 PCH_DDI2_N1 DDI2_TXN[1]
D52 B52
Type-C PortA 37
37
PCH_DDI2_P1
PCH_DDI2_N2
A50
DDI2_TXP[1] EDP_DISP_UTIL
B50 DDI2_TXN[2] G50
37 PCH_DDI2_P2 DDI2_TXP[2] DDI1_AUXN PCH_DDI1_AUXN 36,37
D51 F50
37 PCH_DDI2_N3 DDI2_TXN[3] DDI1_AUXP PCH_DDI1_AUXP 36,37
C51 E48
37 PCH_DDI2_P3 DDI2_TXP[3] DDI2_AUXN PCH_DDI2_AUXN 35,37
F48
DDI2_AUXP PCH_DDI2_AUXP 35,37
+3VS G46
DISPLAY SIDEBANDS DDI3_AUXN F46
PAD~D @ T6
CPU_DP1_CTRL_CLK L13 DDI3_AUXP PAD~D @ T5
CPU_DP1_CTRL_DATA GPP_E18/DDPB_CTRLCLK CPU_DP1_HPD
L12 L9
CPU_DP2_CTRL_CLK GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 CPU_DP2_HPD CPU_DP1_HPD 30,36,37 +1.8VA
2 1 L7
CPU_DP2_CTRL_CLK GPP_E14/DDPC_HPD1 I2C0_IRQ_TS CPU_DP2_HPD 30,35,37
RC43 2.2K_0402_5% N7 L6
2 1 CPU_DP2_CTRL_DATA CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 WLAN_RST# I2C0_IRQ_TS 22
RC45 2.2K_0402_5%
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD WLAN_RST# 24 GNSS_IRQ @ RH81 2 10K_0201_5%
CPU_DP1_CTRL_CLK GPP_E17/EDP_HPD EDP_HPD 22 USH_DET#
2 1 N11 RH71 2 100K_0201_5%
GPP_E22/DDPD_CTRLCLK GNSS_OFF# RH51
RC178 2.2K_0402_5% N12 R12 2 10K_0201_5%
CPU_DP1_CTRL_DATA GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PANEL_BKLEN 22
2 1 R11
EDP_COMP EDP_BKLTCTL EDP_BIA_PWM 22
RC179 2.2K_0402_5% +1.0VS_VCCIO RC108 1 2 24.9_0402_1% E52 U13
EDP_RCOMP 1 OF 20 EDP_VDDEN PCH_ENVDD 22
SKL-U_BGA1356
+3V_PRIM COMPENSATION PU FOR eDP EDP_HPD RC1262 1100K_0402_5%
CAD Note:Trace width=20 mils, Isolat i on Spaci ng=25 m
il, SKL-U Ballout Rev0.71 & INTEL symbol Rev1.0 CPU_DP1_HPD RC1242 1100K_0402_5%
Max length=100 mils.
1
RC199
2 MEDIACARD_IRQ#
10K_0402_5%
PVT-010
Add R3 CPN CPU
PVT-010
Add R3 CPN CPU
4+2 CPU Option PVT-010
Add R3 CPN CPU
2+2 CPU Option CPU_DP2_HPD RC46 2 1100K_0402_5%

UCPU1 SR3L9@ UCPU1 SR3LB@ UCPU1 QNEG@ UCPU1 QNBE@ UCPU1 QNEE@

C
R3 C
R3 R3 SR3JY@ QNB1@ SR343@ SR342@ SR340@ @SR33Z@
UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1
i3 NVPro i3 NVPro i3 NVPro i5 NVPro i5 Vpro i7 VPro
SA0000AWS2L SA0000AWB3L SA0000AWB1L SA0000AWR0L SA0000AWS0L SA0000B2Y1L SA0000B2Y0L SA0000A387L SA0000A377L SA0000ADO2L SA0000ADP2L
i5 vpro R i5 Nvpro R i5 Nvpro R i7 vpro R i5 vpro R
SKL_ULT
@ UCPU1I

CSI-2
X76 DRAM Option (R1) , R3 check P08 DRAM Config Option
(Resistor pop location)
A36 C37 UFCAM_CSI2_CLKN0 33
33 UFCAM_CSI2_DN0 CSI2_DN0 CSI2_CLKN0
B36 D37 UFCAM_CSI2_CLKP0 33 MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3
33 UFCAM_CSI2_DP0 CSI2_DP0 CSI2_CLKP0
C38 C32 WFCAM_CSI2_CLKN1 33
33
33
UFCAM_CSI2_DN1
UFCAM_CSI2_DP1
D38
CSI2_DN1 CSI2_CLKN1
D32 WFCAM_CSI2_CLKP1 33 Micron 8G/1866
C36 CSI2_DP1 CSI2_CLKP1 C29 MICRON_8G@ MICRON_8G@ MICRON_8G@ MICRON_8G@ X76_M8G@ X76_M8G@ X76_M8G@ X76_M8G@
D36
CSI2_DN2 CSI2_CLKN2
D29 X7669231L05 UD1 UD2 UD3 UD4 RH18 RH16 RH13 RH10
CSI2_DP2 CSI2_CLKP2 MT52L256M32D1PF-107WT MT52L256M32D1PF-107WT MT52L256M32D1PF-107WT
A38 B26 MT52L256M32D1PF-107WT 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
CSI2_DN3 CSI2_CLKN3
B38 A26 SA00009XU0L SA00009XU0L SA00009XU0L SA00009XU0L SD028100280 SD028100280 SD028100280 SD028100280
CSI2_DP3 CSI2_CLKP3

33 WFCAM_CSI2_DN4
C31 E13 CSI2_COMP RC114
1 2 100_0402_1% Micron 16G/1866
D31 CSI2_DN4 CSI2_COMP B7 @ RC197 1 2 MICRON_16G@ MICRON_16G@ MICRON_16G@ MICRON_16G@ X76_M16G@ X76_M16G@ X76_M16G@ X76_M16G@
33 WFCAM_CSI2_DP4
C33
CSI2_DP4 GPP_D4/FLASHTRIG
0_0402_5%
MEDIACARD_IRQ# 27 X7669231L07 UD1 UD2 UD3 UD4 RH17 RH16 RH13 RH10
33 WFCAM_CSI2_DN5 CSI2_DN5
D33 MT52L512M32D2PF-107WT MT52L512M32D2PF-107WT MT52L512M32D2PF-107WT MT52L512M32D2PF-107WT 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
33 WFCAM_CSI2_DP5 CSI2_DP5 EMMC
A31 SA00009U70L SA00009U70L SA00009U70L SA00009U70L SD028100280 SD028100280 SD028100280 SD028100280
33 WFCAM_CSI2_DN6 CSI2_DN6 MEM_CONFIG0
B31 AP2
33
33
WFCAM_CSI2_DP6
WFCAM_CSI2_DN7
A33
CSI2_DP6 GPP_F13/EMMC_DATA0
AP1 MEM_CONFIG1 Micron 32G/1866
CSI2_DN7 GPP_F14/EMMC_DATA1 MEM_CONFIG2
B33 AP3 MICRON_32G@ MICRON_32G@ MICRON_32G@ MICRON_32G@ X76_M32G@ X76_M32G@ X76_M32G@ X76_M32G@
33 WFCAM_CSI2_DP7 CSI2_DP7 GPP_F15/EMMC_DATA2
AN3 MEM_CONFIG3 X7669231L09 UD1 UD2 UD3 UD4 RH18 RH15 RH13 RH10
GPP_F16/EMMC_DATA3 MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT
A29 AN1 MT52L1G32D4PG-107WT 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2 GNSS_OFF#
GNSS_OFF# 25 SA00009XV0L SA00009XV0L SA00009XV0L SA00009XV0L SD028100280 SD028100280 SD028100280 SD028100280
CSI2_DP8 GPP_F18/EMMC_DATA5
C28 AM4
D28
CSI2_DN9 GPP_F19/EMMC_DATA6
AM1 Hynix 8G/1866 X76_H8G@ X76_H8G@ X76_H8G@ X76_H8G@
B A27 CSI2_DP9 GPP_F20/EMMC_DATA7 RH17 RH15 RH13 RH10 B
HYNIX_8G@ HYNIX_8G@ HYNIX_8G@ HYNIX_8G@
B27 CSI2_DN10 AM2 USH_DET# X7669231L06 UD1 UD2 UD3 UD4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
CSI2_DP10 GPP_F21/EMMC_RCLK GNSS_IRQ USH_DET# 41,43
C27 AM3 H9CCNNN8GTMLAR-NUD FBGA
H9CCNNN8GTMLAR-NUD FBGA
H9CCNNN8GTMLAR-NUD FBGA
H9CCNNN8GTMLAR-NUD FBGA SD028100280 SD028100280 SD028100280 SD028100280
CSI2_DN11 GPP_F22/EMMC_CLK WWAN_PWR_OFF# GNSS_IRQ 25
D27 AP4 SA00008G64L SA00008G64L SA00008G64L SA00008G64L
CSI2_DP11 GPP_F12/EMMC_CMD WWAN_PWR_OFF# 25
AT1 EMMC_RCOMP 1 2 Hynix 16G/1866 X76_H16G@ X76_H16G@ X76_H16G@ X76_H16G@
EMMC_RCOMP RC66 200_0402_1% RH18 RH16 RH12 RH10
HYNIX_16G@ HYNIX_16G@ HYNIX_16G@ HYNIX_16G@
SKL-U_BGA1356 9 OF 20 X7669231L08 UD1 UD2 UD3 UD4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
H9CCNNNBJTMLAR-NUD FBGA
H9CCNNNBJTMLAR-NUD FBGA
H9CCNNNBJTMLAR-NUD FBGA
H9CCNNNBJTMLAR-NUD FBGA SD028100280 SD028100280 SD028100280 SD028100280
SA00008FJ4L SA00008FJ4L SA00008FJ4L SA00008FJ4L
DDR Memory Conf i gur at i no Type St r ap pin Hynix 32G/1866 X76_H32G@ X76_H32G@ X76_H32G@ X76_H32G@
HYNIX_32G@ HYNIX_32G@ HYNIX_32G@ HYNIX_32G@ RH17 RH16 RH12 RH10
X7669231L10 UD1 UD2 UD3 UD4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
+1.8VA H9CCNNNCLTMLAR-NUD FBGA
H9CCNNNCLTMLAR-NUD FBGA
H9CCNNNCLTMLAR-NUD FBGA
H9CCNNNCLTMLAR-NUD FBGA SD028100280 SD028100280 SD028100280 SD028100280
SA0000AEN0L SA0000AEN0L SA0000AEN0L SA0000AEN0L
@ RH17 2 1 10K_0402_5% MEM_CONFIG0 @ RH18 2 1 10K_0402_5% X76_8G@
X768G Samsung 8G/1866 X76_S8G@ X76_S8G@ X76_S8G@ X76_S8G@
@ RH15 2 1 10K_0402_5% MEM_CONFIG1 @ RH16 2 1 10K_0402_5% X76 SAMSUNG_8G@ SAMSUNG_8G@ SAMSUNG_8G@ SAMSUNG_8G@ RH18 RH15 RH12 RH10
X7669231L01 UD1 UD2 UD3 UD4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ RH12 2 1 10K_0402_5% MEM_CONFIG2 @ RH13 2 1 10K_0402_5% K4E8E324EB-EGCF FBGA178PK4E8E324EB-EGCF FBGA178PK4E8E324EB-EGCF FBGA178PK4E8E324EB-EGCF FBGA178P SD028100280 SD028100280 SD028100280 SD028100280
X7669231L01 SA00009XY0L SA00009XY0L SA00009XY0L SA00009XY0L
@ RH9 2 1 10K_0402_5% MEM_CONFIG3 @ RH10 2 1 10K_0402_5% X76_16G@
X7616G Samsung 16G/1866 X76_S16G@ X76_S16G@ X76_S16G@ X76_S16G@
X76 SAMSUNG_16G@ SAMSUNG_16G@ SAMSUNG_16G@ SAMSUNG_16G@ RH17 RH15 RH12 RH10
X7669231L02 UD1 UD2 UD3 UD4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
K4E6E304EB-EGCF FBGA17 K4E6E304EB-EGCF FBGA17 K4E6E304EB-EGCF FBGA17 K4E6E304EB-EGCF FBGA17 SD028100280 SD028100280 SD028100280 SD028100280
X7669231L02 SA00008QV2L SA00008QV2L SA00008QV2L SA00008QV2L
X76_32G@
X7632G Samsung 32G/1866 X76_S32G@ X76_S32G@ X76_S32G@ X76_S32G@
GPIO Pin Pin Name Micron Micron Mircon Hynix Hynix Hynix SamsungSamsungSamsung
8G 16G 32G
Mircon Hynix SamsungMircon Hynix Samsung
32G
X76 SAMSUNG_32G@ SAMSUNG_32G@ SAMSUNG_32G@ SAMSUNG_32G@ RH18 RH16 RH13 RH9
8G 16G 32G 8G 16G 32G 32G 32G 16G 16G 16G X7669231L03 UD1 UD2 UD3 UD4 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
A 4EBE304EB-EGCF FBGA178 4EBE304EB-EGCF FBGA178 4EBE304EB-EGCF FBGA178 4EBE304EB-EGCF FBGA178 SD028100280 SD028100280 SD028100280 SD028100280 A
GPP_F13 MEM_CONFIG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X7669231L03 SA00008X10L SA00008X10L SA00008X10L SA00008X10L

GPP_F14 MEM_CONFIG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DELL CONFIDENTIAL/PROPRIETARY

2133Mbps
1866Mbps
GPP_F15 MEM_CONFIG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title
GPP_F16 MEM_CONFIG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P05-MCP(1/14)DDI,EDP,CSI2,EMMC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 5 of 65
5 4 3 2 1
 5 4 3 2 1

LPDDR3, Ballout for side by side(Non-Interleave)

19 DDR_A_DQS#[0..7] 20 DDR_B_DQS#[0..7]

19 DDR_A_DQS[0..7] 20 DDR_B_DQS[0..7]

19 DDR_A_D[0..63] 20 DDR_B_D[0..63]

19,21 DDR_A_CA1_[0..9] 20,21 DDR_B_CA1_[0..9]

19,21 DDR_A_CA2_[0..9] 20,21 DDR_B_CA2_[0..9]

D D
SKL-U
@ UCPU1B SKL-U @ UCPU1C

AU53 DDR_A_CLK#0
DDR_A_D0 AL71 DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 19,21 DDR_A_D16 AF65 AN45 DDR_B_CLK#0
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 19,21 DDR_A_D17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1 DDR_B_CLK#0 20,21
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 19,21 DDR_A_D18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDR_B_CLK0 DDR_B_CLK#1 20,21
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_A_CLK1 19,21 DDR_A_D19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1 DDR_B_CLK0 20,21
DDR_A_D4 AL70
DDR0_DQ[3]
BA56 DDR_A_CKE0 DDR_A_D20 AF66
DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 20,21
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 19,21 DDR_A_D21 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 19,21 DDR_A_D22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDR_B_CKE1 DDR_B_CKE0 20,21
DDR_A_D7 AN71
DDR0_DQ[6] DDR0_CKE[2]
AY56 DDR_A_CKE3 DDR_A_CKE2 19,21 DDR_A_D23 AK66
DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1]
AN55 DDR_B_CKE2 DDR_B_CKE1 20,21
DDR_A_D8 AR70
DDR0_DQ[7] DDR0_CKE[3] DDR_A_CKE3 19,21 DDR_A_D24 AF70
DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2]
AP53 DDR_B_CKE3 DDR_B_CKE2 20,21
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_A_D25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3] DDR_B_CKE3 20,21
DDR_A_D10 AU71 DDR0_DQ[9] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 19,21 DDR_A_D26 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42 DDR_B_CS#0
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 19,21 DDR_A_D27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1 DDR_B_CS#0 20,21
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDR_A_ODT0 19,21 DDR_A_D28 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDR_B_ODT0 DDR_B_CS#1 20,21
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_A_D29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42
DDR_B_ODT0 20,21
DDR_A_D14 DDR0_DQ[13] DDR_A_D30 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
AU70 BA51 AH70
DDR_A_D15 AU69
DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
BB54
DDR_A_CA1_0 19,21 DDR_A_D31 AH69
DDR1_DQ[14]/DDR0_DQ[30]
AY48
DDR_A_D32 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52
DDR_A_CA1_1 19,21 DDR_A_D48 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50
DDR_B_CA1_0 20,21
DDR_A_D33 AW65
DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
AY52
DDR_A_CA1_2 19,21 DDR_A_D49 AU66
DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
BA48
DDR_B_CA1_1 20,21
DDR_A_D34 AW63
DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
AW52
DDR_A_CA1_3 19,21 DDR_A_D50 AP65
DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
BB48
DDR_B_CA1_2 20,21
DDR_A_D35 AY63
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
AY55
DDR_A_CA1_4 19,21 DDR_A_D51 AN65
DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
AP48
DDR_B_CA1_3 20,21
DDR_A_D36 BA65
DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
AW54
DDR_A_CA1_5 19,21 DDR_A_D52 AN66
DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
AP52
DDR_B_CA1_4 20,21
DDR_A_D37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54
DDR_A_CA1_6 19,21 DDR_A_D53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50
DDR_B_CA1_5 20,21
DDR_A_D38 BA63
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
BA55
DDR_A_CA1_7 19,21 DDR_A_D54 AT65
DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
AN48
DDR_B_CA1_6 20,21
DDR_A_D39 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54
DDR_A_CA1_8 19,21 DDR_A_D55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53
DDR_B_CA1_7 20,21
DDR_A_D40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_CA1_9 19,21 DDR_A_D56 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDR_B_CA1_8 20,21
DDR_A_D41 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_D57 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR_B_CA1_9 20,21
DDR_A_D42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_CA2_0 19,21 DDR_A_D58 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
C DDR_A_D43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_CA2_1 19,21 DDR_A_D59 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CA2_0 20,21 C
DDR_A_D44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50
DDR_A_CA2_2 19,21 DDR_A_D60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
DDR_B_CA2_1 20,21
DDR_A_D45 AY61
DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
AU52
DDR_A_CA2_3 19,21 DDR_A_D61 AP61
DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AW44
DDR_B_CA2_2 20,21
DDR_A_D46 BA59
DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
AY51
DDR_A_CA2_4 19,21 DDR_A_D62 AT60
DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
BB44
DDR_B_CA2_3 20,21
DDR_A_D47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48
DDR_A_CA2_5 19,21 DDR_A_D63 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47
DDR_B_CA2_4 20,21
DDR_B_D0 AY39
DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
AT50
DDR_A_CA2_6 19,21 DDR_B_D16 AU40
DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
BA44
DDR_B_CA2_5 20,21
DDR_B_D1 AW39
DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
BB50
DDR_A_CA2_7 19,21 DDR_B_D17 AT40
DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
AW46
DDR_B_CA2_6 20,21
DDR_B_D2 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50
DDR_A_CA2_8 19,21 DDR_B_D18 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46
DDR_B_CA2_7 20,21
DDR_B_D3 AW37
DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
BA50
DDR_A_CA2_9 19,21 DDR_B_D19 AU37
DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
BA46
DDR_B_CA2_8 20,21
DDR_B_D4 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_B_D20 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46
DDR_B_CA2_9 20,21
DDR_B_D5 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D21 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3]
BA39 AP40 BA47
DDR_B_D6 DDR0_DQ[37]/DDR1_DQ[5] DDR_B_D22 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4]
BA37 AM70 AP37
DDR_B_D7 BB37
DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0]
AM69
DDR_A_DQS#0 19 DDR_B_D23 AR37
DDR1_DQ[38]/DDR1_DQ[22]
AH66
DDR_B_D8 AY35
DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0]
AT69
DDR_A_DQS0 19 DDR_B_D24 AT33
DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2]
AH65
DDR_A_DQS#2 19
DDR_B_D9 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70
DDR_A_DQS#1 19 DDR_B_D25 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69
DDR_A_DQS2 19
DDR_B_D10 AY33
DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1]
BA64
DDR_A_DQS1 19 DDR_B_D26 AU30
DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3]
AG70
DDR_A_DQS#3 19
DDR_B_D11 AW33
DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4]
AY64
DDR_A_DQS#4 19 DDR_B_D27 AT30
DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3]
AR66
DDR_A_DQS3 19
DDR_B_D12 BB35
DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4]
AY60
DDR_A_DQS4 19 DDR_B_D28 AR33
DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6]
AR65
DDR_A_DQS#6 19
DDR_B_D13 BA35
DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5]
BA60
DDR_A_DQS#5 19 DDR_B_D29 AP33
DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6]
AR61
DDR_A_DQS6 19
DDR_B_D14 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38
DDR_A_DQS5 19 DDR_B_D30 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
DDR_A_DQS#7 19
DDR_B_D15 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_B_DQS#0 20 DDR_B_D31 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_A_DQS7 19
DDR_B_D32 AY31
DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0]
AY34
DDR_B_DQS0 20 DDR_B_D48 AU27
DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2]
AR38
DDR_B_DQS#2 20
DDR_B_D33 AW31
DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1]
BA34
DDR_B_DQS#1 20 DDR_B_D49 AT27
DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2]
AT32
DDR_B_DQS2 20
DDR_B_D34 AY29
DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1]
BA30
DDR_B_DQS1 20 DDR_B_D50 AT25
DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3]
AR32
DDR_B_DQS#3 20
DDR_B_D35 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30
DDR_B_DQS#4 20 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25
DDR_B_DQS3 20
DDR_B_D36 BB31
DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4]
AY26
DDR_B_DQS4 20 DDR_B_D52 AP27
DDR1_DQ[51] DDR1_DQSN[6]
AR27
DDR_B_DQS#6 20
DDR_B_D37 BA31
DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5]
BA26
DDR_B_DQS#5 20 DDR_B_D53 AN27
DDR1_DQ[52] DDR1_DQSP[6]
AR22
DDR_B_DQS6 20
DDR_B_D38 BA29
DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_B_DQS5 20 DDR_B_D54 AN25
DDR1_DQ[53] DDR1_DQSN[7]
AR21
DDR_B_DQS#7 20
DDR_B_D39 BB29
DDR0_DQ[54]/DDR1_DQ[38]
AW50 DDR_B_D55 AP25
DDR1_DQ[54] DDR1_DQSP[7] DDR_B_DQS7 20
DDR_B_D40 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR_B_D41 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDR_B_D57 DDR1_DQ[56] DDR1_ALERT#
AW27 AU22 AP43
DDR_B_D42 DDR0_DQ[57]/DDR1_DQ[41] DDR_B_D58 DDR1_DQ[57] DDR1_PAR
AY25 AY67 AU21 AT13
B DDR_B_D43 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68
+V_DDR_REF_CA 21 DDR_B_D59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0 PAD~D @ T36 B
DDR_B_D44 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ BA67
+V_DDR_REFA_R 21 DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR CH - A
DDR_B_D45 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +V_DDR_REFB_R 21 DDR_B_D61 AP22 DDR1_DQ[60] DDR CH - B DDR_RCOMP[1] AU18 SM_RCOMP2
DDR_B_D46 DDR0_DQ[61]/DDR1_DQ[45] DDR_VTT_CNTL DDR_B_D62 DDR1_DQ[61] DDR_RCOMP[2]
BA25 AW67 AP21
DDR_B_D47 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 DDR1_DQ[62]
BB25 AN21
DDR0_DQ[63]/DDR1_DQ[47] DDR1_DQ[63]

SKL-U_BGA1356 2 OF 20 SKL-U_BGA1356 3 OF 20

+1.2V_DDR

UC1
1 5
NC VCC
DDR_VTT_CNTL 2
A
4
1
+3VS
LPDDR3 COMPENSATION SIGNALS
Y CC15
3
GND SM_RCOMP0
0.1U_0402_10V7K RC1641 2 200_0402_1%
1

2
74AUP1G07GW_TSSOP5
R32 SM_RCOMP1 RC1661 2 80.6_0402_1%
Use SA00005U600 100K_0402_5%
SM_RCOMP2 RC1651 2 162_0402_1%
2

SM_PG_CTRL 53 CAD Note:

Trace width=12~15 mil, Spacing=20 mils
A Max trace length= 500 mil A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P06-MCP(2/14)LPDDR3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 6 of 65
5 4 3 2 1
 5 4 3 2 1

PVT-023
Change 0 ohm to short pad

+1.8VA +1.8V_ESPI
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236 SKL-U
R513 1 @ 2 @ UCPU1E
SPI - FLASH
0_0201_5% SMBUS, SMLINK
PVT-048 PCH_SPI_CLK AV2
De-pop debug XDP related compoments PCH_SPI_SO SPI0_CLK DDR_XDP_SMBCLK
AW3 R7
@XDP@ RC67 1 2 1K_0402_5% PCH_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 DDR_XDP_SMBDAT DDR_XDP_SMBCLK 13
13 PCH_SPI_DO_XDP @XDP@ RC69 1 2 1K_0402_5% PCH_SPI_IO2 AW2
SPI0_MOSI GPP_C1/SMBDATA
R10 PCH_SMB_ALERT# DDR_XDP_SMBDAT 13 ESPI_CLK 2 1
13 PCH_SPI_DO2_XDP PCH_SPI_IO3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
12P_0402_50V8J EMC@
PCH_SPI_CS0# AU3 SPI0_IO3 R9 CC78
D PCH_SPI_CS1# AU2 SPI0_CS0# GPP_C3/SML0CLK W2 D

31 PCH_SPI_CS2# AU1 SPI0_CS1# GPP_C4/SML0DATA W1 GPP_C5 Reserve for RF

+1.8V_ESPI SPI0_CS2# GPP_C5/SML0ALERT#
W3 SML1_SMBCLK
SPI - TOUCH GPP_C6/SML1CLK
V3 SML1_SMBDAT SML1_SMBCLK 30
ESPI_ALERT# GPP_C7/SML1DATA GPP_B23 SML1_SMBDAT 30
RC83 1 2 10K_0402_5% M2 AM7
M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
J4 GPP_D2/SPI1_MISO
+3VS
V1 GPP_D3/SPI1_MOSI
TC1 GPP_D21/SPI1_IO2
@ RC1981 2 0_0201_5% V2 RFQ-034
8,31 TPM_PIRQ# GPP_D22/SPI1_IO3 change LPC to ESPI mode DDR_XDP_SMBDAT
M1 LPC 2 1
GPP_D0/SPI1_CS# AY13 ESPI_IO0_R RC3831 2 15_0402_5% 2.2K_0402_5% RN1
GPP_A1/LAD0/ESPI_IO0
BA13 ESPI_IO1_R RC3841 2 15_0402_5% ESPI_IO0 30,43 DDR_XDP_SMBCLK 2 1
C LINK GPP_A2/LAD1/ESPI_IO1
BB13 ESPI_IO2_R RC3851 2 15_0402_5%
ESPI_IO1 30,43 2.2K_0402_5% RN2
G3 GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3861 2 15_0402_5%
ESPI_IO2 30,43 CLKRUN# 2 1
24 CL_CLK G2 CL_CLK GPP_A4/LAD3/ESPI_IO3 BA12
ESPI_IO3 30,43 @ RC82
8.2K_0402_5%
24 CL_DATA G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# 30,43
24 CL_RST# CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# 30
+1.8V_PGPP
SIO_RCIN# AW13 AW9 PCI_CLK_LPC0 RC71 1 2 15_0402_5%
@ RC73 1 SIO_RCIN# GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 @ RC70 1 ESPI_CLK 30,43
2 10K_0402_5% AY9 2 22_0402_5%
ESPI_ALERT#AY11 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN#
30 ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/CLKRUN#
+3V_PRIM
SKL-U_BGA1356 5 OF 20 RP2
SPI_SI_VROM1 1 8 PCH_SPI_SI
SPI_CLK_VROM1 2 7 PCH_SPI_CLK SML1_SMBCLK 1 2
+3.3V_SPI 3 6 RC55 1K_0402_5%
31 PCH_SPI_CLK_TPM SML1_SMBDAT
31 PCH_SPI_SI_TPM 4 5 1 2
CC90 SPI_CLK_VROM1 RC51 1K_0402_5%
1 2 33_0804_8P4R_5%

128Mb Flash ROM

2
33_0402_5%
C 0.1U_0402_25V6 RP3 C
PCH_SPI_SO

@ RC169 33P_0402_50V8J
UH1 1 8
PCH_SPI_CS0# 31 PCH_SPI_SO_TPM SPI_SO_VROM1 2
1 8 7 change RC49 to 2.2k
SPI_SO_VROM1 CS# VCC SPI_IO3_VROM1 SPI_IO2_VROM1 3 PCH_SPI_IO2
2 7 6
SPI_IO2_VROM1 3 DO HOLD#_RESET# 6 SPI_CLK_VROM1 SPI_IO3_VROM1 4 5 PCH_SPI_IO3 +3V_PRIM

1
WP# CLK SPI_SI_VROM1
4 5
GND DI 33_0804_8P4R_5%
9
ThemalPad

2
PCH_SMB_ALERT#

@ CC91
W25Q128JVEIQ_WSON8_8X6 1 2
RC49 2.2K_0402_5%

1
TLS CONFIDENTIALITY
HIGH ENABLE
LOW(DEFAULT) DISABLE

+3V_PRIM

GPP_C5 1 2
RC58 4.7K_0201_5%

+3V_PRIM
EC interface
@ RH19 1 2 1K_0402_5%~D PCH_SPI_IO2 HIGH ESPI
B LOW(DEFAULT) LPC B

@ RH20 1 2 1K_0402_5%~D PCH_SPI_IO3

+3V_PRIM
SPI debug conn @ RH21 1 2 1K_0402_5%~D PCH_SPI_IO3

JSPI2 GPP_B23 1 2
PCH_SPI_CS1# 1 @ RC64 150K_0201_1%
PCH_SPI_SI 1
2
PCH_SPI_SO 3
2 9/5 MOW
PCH_SPI_CLK 4 3 Opt i on 1: I mpl e ment a 1 k Oh m pull- do wn r esi st or on t he si gnal and de- popul at e
PCH_SPI_CS0# 5
4
the EXI BOOT STALL BYPASS
PCH_SPI_IO2 5
PCH_SPI_IO3
6
6 required 1 kOhm pull-up resistor(MOW WW5). HIGH ENABLE
7
8
7 In this case, customers must ensure that the SPI LOW(DEFAULT) DISABLE
+3.3V_SPI 8 f l as h devi ce on t he pl a t fo r m has HOLD f unc t i onal i t y di sabl ed by defaut.l
9
+3V_PRIM 9
10
10
Note that the pull down resistor on SPI0_IO3 is only needed for SKL U/Y plat f or ms
11
with ES and SKL S/H plat f or ms wit h pr e- ES1/ ES1 sa mpl es( MO W WW9).
12 GND1
GND2

ACES_50521-01041-P01
CONN@ PVT-023
Change 0 ohm to short pad
+3V_PRIM +3.3V_SPI

RC170
A PCH SPI 2 @ 1 A

0_0402_1%

TPM
DELL CONFIDENTIAL/PROPRIETARY
JSPI Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P07-MCP(3/14)SPI,SMB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 7 of 65
5 4 3 2 1
 5 4 3 2 1

+3VS

@ UCPU1F SKL-U DDR_CHA_EN RH30 1 2 100K_0402_5%~D

+3VS
LPSS ISH DDR_CHB_EN RH29 1 2 100K_0402_5%~D

1 2 HOST_SD_WP# AN8
RC56 EDP_CAB_DET# GPP_B15/GSPI0_CS# DDR_CHB_EN DDR_CHA_EN
10K_0402_5% 22 EDP_CAB_DET#
AP7 P2 @ RH31 1 2 SHORT PADS
RC398 1 2 TPM_PIRQ#_R AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 DDR_CHA_EN
0_0201_5%
GPP_B17/GSPI0_MISO GPP_D10
1 2 UART2_TXD NRB_BIT AR7 P4 AR_DET# DDR_CHB_EN @ RH28 1 2 SHORT PADS
RH3 49.9K_0201_1% GPP_B18/GSPI0_MOSI GPP_D11 P1 CPU_DET#
AM5 GPP_D12
D 1 2 UART2_RXD RC399 1 @ 2 SIO_EXT_SCI# GPP_B19/GSPI1_CS# D
0_0201_5% AN7 M4
ISH_I2C0_SDA 31
RH4 49.9K_0201_1% AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3
44 PCH_3.3V_TS_EN GPP_B22 AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL 31
1 2 UART2_RTS# GPP_B22/GSPI1_MOSI N1
WWAN_RST# GPP_D7/ISH_I2C1_SDA ALS_I2C1_SDA 33
RC190 49.9K_0402_1% AB1 N2
AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL ALS_I2C1_SCL 33 +1.8V_PGPP
1 2 UART2_CTS# 30 DEBUG_UART0_TX W4 GPP_C9/UART0_TXD
GPP_C10/UART0_RTS#
GPP F group GPP_F10/I2C5_SDA/ISH_I2C2_SDA
AD11
RC191 49.9K_0402_1% HOST_SD_WP# AB3 AD12
27 HOST_SD_WP# GPP_C11/UART0_CTS#
1.8V only GPP_F11/I2C5_SCL/ISH_I2C2_SCL ACCEL_INT1# RC182 1 2 10K_0201_5%
UART2_RXD AD1
43 UART2_RXD UART2_TXD GPP_C20/UART2_RXD ACCEL_INT2#
AD2 U1 RC183 1 2 10K_0201_5%
43 UART2_TXD UART2_RTS# GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
AD3 U2
43 UART2_RTS# UART2_CTS# GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL TS_ID0
AD4 U3 RC192 1 2 100K_0201_5%
43 UART2_CTS# GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS#
7,31 TPM_PIRQ#
RC196 1 @ 2 0_0201_5% UART2_RTS# U4
GPP_D16/ISH_UART0_CTS#/SML0BALERT# KICKSTD_SW_DET#_PCH RC391 1 2 220K_0201_5%
TS_RST# U7 AC1
22 TS_RST# GPP_C17 U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 ALS_I2C1_ALERT#_PCH RC392 1 2 100K_0201_5%
+3V_PRIM GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
I2C1_SDA_TS U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
PAD~D @ T15
22 I2C1_SDA_TS I2C1_SCK_TS U9
GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
1 2 EDP_CAB_DET# 22 I2C1_SCK_TS GPP_C19/I2C1_SCL ACCEL_INT1#
10K_0201_5% AY8
RC180 SKYCAM_I2C_DATA AH9 GPP_A18/ISH_GP0 BA8 ACCEL_INT2#
1 2 WWAN_RST# 34 SKYCAM_I2C_DATA SKYCAM_I2C_CLK AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 TS_ID0
10K_0201_5% BB7
RC181
34 SKYCAM_I2C_CLK GPP_F5/I2C2_SCL GPP_A20/ISH_GP2
BA7
100K_0201_5% PCH_3.3V_TS_EN GPP_A21/ISH_GP3
1 2 AH11 AY7
@ RC396 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 3.3V_CAM_EN 34 KICKSTD_SW_DET#_PCH
AH12
GPP_F7/I2C3_SCL
GPP F group GPP_A23/ISH_GP5
AW7
1 2 10K_0402_5% SIO_EXT_SCI# AP13 ALS_I2C1_ALERT#_PCH
1.8V only GPP_A12/BM_BUSY#/ISH_GP6
RC149 UF_I2C_DATA AF11
33 UF_I2C_DATA UF_I2C_CLK AF12 GPP_F8/I2C4_SDA
33 UF_I2C_CLK GPP_F9/I2C4_SCL
+3V_PRIM
+3VS_TS SKL-U_BGA1356 6 OF 20
C C

TS_RST# RC205 1 2 10K_0201_5%

GPP_C17 RC206 1 2 10K_0201_5%
1 2 I2C1_SDA_TS
RC48 4.7K_0402_5%
I2C1_SDA_TS
1 2 I2C1_SCK_TS I2C1_SCK_TS
RC50 4.7K_0402_5% SKYCAM_I2C_DATA
SKYCAM_I2C_CLK +3V_PRIM
UF_I2C_DATA
UF_I2C_CLK
X76 DRAM Option (R3)
1 1 1 1
Micron 8G/1866
1

1
33P_0402_50V8J
@EMC@ CC98

33P_0402_50V8J
@EMC@ CC99

33P_0201_50V8J
@EMC@ CC13

33P_0201_50V8J
@EMC@ CC11

33P_0201_50V8J
@EMC@ CC7

33P_0201_50V8J
@EMC@ CC8
MICRON_8G_R3@ MICRON_8G_R3@ MICRON_8G_R3@ MICRON_8G_R3@ R5771
X7669231L56 UD1 UD2 UD3 UD4 10K_0201_5%
2

2 2 2 2 MT52L256M32D1PF-107WT MT52L256M32D1PF-107WT MT52L256M32D1PF-107WT

MT52L256M32D1PF-107WT
SA00009XU1L SA00009XU1L SA00009XU1L SA00009XU1L

2
+3V_PRIM Micron 16G/1866 AR_DET#
MICRON_16G_R3@ MICRON_16G_R3@ MICRON_16G_R3@ MICRON_16G_R3@
X7669231L52 UD1 UD2 UD3 UD4

1
1 2 NRB_BIT MT52L512M32D2PF-107WT MT52L512M32D2PF-107WT MT52L512M32D2PF-107WT MT52L512M32D2PF-107WT
@ RC63 2.2K_0201_5% SA00009U71L SA00009U71L SA00009U71L SA00009U71L R5772
@ 10K_0201_5%
Micron 32G/1866
MICRON_32G_R3@ MICRON_32G_R3@ MICRON_32G_R3@ MICRON_32G_R3@
NO REBOOT STRAP X7669231L54

2
UD1 UD2 UD3 UD4
MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT
HIGH No REBOOT SA00009XV1L SA00009XV1L SA00009XV1L SA00009XV1L
B LOW(DEFAULT) REBOOT ENABLE B

Weak IPD
Hynix 8G/1866
HYNIX_8G_R3@ HYNIX_8G_R3@ HYNIX_8G_R3@ HYNIX_8G_R3@
X7669231L51 UD1 UD2 UD3 UD4
H9CCNNN8GTMLAR-NUD FBGA
H9CCNNN8GTMLAR-NUD FBGA
H9CCNNN8GTMLAR-NUD FBGA
H9CCNNN8GTMLAR-NUD FBGA
ACCEL_INT1# 2 1 SA00008G65L SA00008G65L SA00008G65L SA00008G65L
ACCEL_INT1#_D 31

D107 PCB footprint Hynix 16G/1866 +3V_PRIM

RB751S40T1G_SOD523-2 RB520SM-30T2R_EMD2-2 HYNIX_16G_R3@ HYNIX_16G_R3@ HYNIX_16G_R3@ HYNIX_16G_R3@
X7669231L53 UD1 UD2 UD3 UD4
ACCEL_INT2# 2 1 H9CCNNNBJTMLAR-NUD FBGA
H9CCNNNBJTMLAR-NUD FBGA
H9CCNNNBJTMLAR-NUD FBGA
H9CCNNNBJTMLAR-NUD FBGA
ACCEL_INT2#_D 31
+3V_PRIM SA00008FJ5L SA00008FJ5L SA00008FJ5L SA00008FJ5L

1
D108 PCB footprint @U22@
RB751S40T1G_SOD523-2 RB520SM-30T2R_EMD2-2 Hynix 32G/1866 R5775
HYNIX_32G_R3@ HYNIX_32G_R3@ HYNIX_32G_R3@ HYNIX_32G_R3@ 10K_0201_5%
X7669231L55
1

KICKSTD_SW_DET#_PCH
2 1 UD1 UD2 UD3 UD4
KICKSTD_SW_DET# 30,42
@RC65 H9CCNNNCLTMLAR-NUD FBGA
H9CCNNNCLTMLAR-NUD FBGA
H9CCNNNCLTMLAR-NUD FBGA
H9CCNNNCLTMLAR-NUD FBGA

2
2.2K_0201_5% D109 PCB footprint SA0000AEN1L SA0000AEN1L SA0000AEN1L SA0000AEN1L
RB520SM-30T2R_EMD2-2 CPU_DET#
RB751S40T1G_SOD523-2 X76_8G_R3@
X768G3 Samsung 8G/1866
2

ALS_I2C1_ALERT#_PCH 2 1 X76 SAMSUNG_8G_R3@ SAMSUNG_8G_R3@ SAMSUNG_8G_R3@ SAMSUNG_8G_R3@

ALS_I2C1_ALERT# 33

1
GPP_B22 X7669231L57 UD1 UD2 UD3 UD4 @U42@
D110 PCB footprint K4E8E324EB-EGCF FBGA178PK4E8E324EB-EGCF FBGA178PK4E8E324EB-EGCF FBGA178PK4E8E324EB-EGCF FBGA178P R5776
RB751S40T1G_SOD523-2 RB520SM-30T2R_EMD2-2 X7669231L57 SA00009XY1L SA00009XY1L SA00009XY1L SA00009XY1L 10K_0201_5%
BOOT BIOS Destination(Bit 6) X76_16G_R3@
X7616G3 Samsung 16G/1866

2
X76 SAMSUNG_16G_R3@ SAMSUNG_16G_R3@ SAMSUNG_16G_R3@ SAMSUNG_16G_R3@
HIGH LPC UD1 UD2 UD3 UD4
X7669231L58
LOW(DEFAULT) SPI K4E6E304EB-EGCF FBGA17 K4E6E304EB-EGCF FBGA17 K4E6E304EB-EGCF FBGA17 K4E6E304EB-EGCF FBGA17
Internal PD 20K +3VS_TS +3VS_TS X7669231L58 SA00008QV3L SA00008QV3L SA00008QV3L SA00008QV3L
X76_32G_R3@
X7632G3 Samsung 32G/1866
1

A X76 SAMSUNG_32G_R3@ SAMSUNG_32G_R3@ SAMSUNG_32G_R3@ SAMSUNG_32G_R3@ A

RC393 X7669231L59 UD1 UD2 UD3 UD4
100K_0201_5% 4EBE304EB-EGCF FBGA178 4EBE304EB-EGCF FBGA178 4EBE304EB-EGCF FBGA178 4EBE304EB-EGCF FBGA178
X7669231L59
2

SA00008X11L SA00008X11L SA00008X11L SA00008X11L

G

TS_ID0 2 1 TS_ID0_M 1 3
TS_ID0_D 22
DELL CONFIDENTIAL/PROPRIETARY
D

D112
RB751S40T1G_SOD523-2
Q351
Security Classification Compal Secret Data Compal Electronics, Inc.
PCB footprint 2015/10/22 2013/10/28 Title
RB520SM-30T2R_EMD2-2 DII-DMN65D8LW-7 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P08-MCP(4/14)GSPI,I2C,UART,ISH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 8 of 65
5 4 3 2 1
 5 4 3 2 1

@ UCPU1H SKL-U

SSIC / USB3
PCIE/USB3/SATA
H8
USB3_1_RXN USB3RN1 37
G8 USB3RP1 37
H13 USB3_1_RXP C13
D G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
USB3TN1 37 Type-C PortA D
PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3TP1 37
B17
A17 PCIE1_TXN/USB3_5_TXN J6
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3RN2 25
H6 USB3RP2 25
USB3_2_RXP/SSIC_1_RXP
G11 B13
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
USB3TN2 25 WWAN
PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3TP2 25
D16
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN USB3RN3 39
H10 USB3RP3 39
USB3_3_RXP/SSIC_2_RXP
H16 B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
USB3TN3 39 USB3.0 Type-A
PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3TP3 39
D17
PCIE3_TXN
C17 E10
PCIE3_TXP USB3_4_RXN USB3RN4 37
F10 USB3RP4 37
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
USB3TN4 37 Type-C PortB
PCIE4_RXP USB3_4_TXP USB3TP4 37
B19
A19 PCIE4_TXN AB9
PCIE4_TXP USB2N_1 USB20_N1 35
AB10
F16
USB2P_1 USB20_P1 35 Type-C PortA
24 PCIE_PRX_WLANTX_N5 PCIE5_RXN
E16 AD6
WLAN 24 PCIE_PRX_WLANTX_P5
C19 PCIE5_RXP USB2N_2 AD7
USB20_N2 43
PCIe Gen2 x 1 24 PCIE_PTX_WLANRX_N5
D19
PCIE5_TXN USB2P_2 USB20_P2 43 Dock
24 PCIE_PTX_WLANRX_P5 PCIE5_TXP
AH3 USB20_N3 36
USB2N_3
G18 AJ3
F18
PCIE6_RXN USB2P_3 USB20_P3 36 Type-C PortB
D20 PCIE6_RXP AD9
PCIE6_TXN USB2N_4 USB20_N4 25
C20 AD10
PCIE6_TXP USB2P_4 USB20_P4 25 NGFF (WWAN)
23 PCIE_PRX_SSDTX_N7 F20 AJ1 USB20_N5 43
E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2
23 PCIE_PRX_SSDTX_P7
B21 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 43 IR Camera
23 PCIE_PTX_SSDRX_N7 USB2
C A21 PCIE7_TXN/SATA0_TXN AF6 C
23 PCIE_PTX_SSDRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
PCIe SSD G21
USB2P_6
23 SATA_PRX_SSDTX_N8 PCIE8_RXN/SATA1A_RXN
23 SATA_PRX_SSDTX_P8 F21 AH1
PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_N7 24
D21 AH2
SATA SSD 23 SATA_PTX_SSDRX_N8
C21
PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 24 NGFF (WLAN)
23 SATA_PTX_SSDRX_P8 PCIE8_TXP/SATA1A_TXP
AF8
E22 USB2N_8 AF9
27 PCIE_PRX_CARDTX_N9 PCIE9_RXN USB2P_8
E23
Cardreader 27 PCIE_PRX_CARDTX_P9
B23 PCIE9_RXP AG1
27 PCIE_PTX_CARDRX_N9
PCIe Gen2 x 1 27 PCIE_PTX_CARDRX_P9
A23
PCIE9_TXN USB2N_9
AG2
USB20_N9 39
USB Type-A
PCIE9_TXP USB2P_9 USB20_P9 39
F25 AH7 USB20_N10 43
PCIE10_RXN USB2N_10
E25 AH8
D23 PCIE10_RXP USB2P_10 USB20_P10 43 USH
PCIE10_TXN RC137 1 113_0402_1%
C23 AB6 USBCOMP 2
PCIE10_TXP USB2_COMP OTG_ID RC62 1
AG3 2 0_0201_5% PD1_OTG_ID 35
PCIE_RCOMPN USB2_ID
F5 AG4 VBUSSENSE @ RC61 1 2 1K_0201_5%
PCIE_RCOMPN USB2_VBUSSENSE PD1_VBUS_SENSE 35 Type-C PortA
RC113 1 2 100_0402_1% PCIE_RCOMPP E5
+1.8V_PGPP PCIE_RCOMPP A9 USB_OC0#
D56 GPP_E9/USB2_OC0# C9 USB_OC1#
13 CPU_XDP_PRDY# D61
PROC_PRDY# GPP_E10/USB2_OC1#
D9 USB_OC2#
@ RC72 1 2 10K_0402_5%
13 CPU_XDP_PREQ# BB11
PROC_PREQ# GPP_E11/USB2_OC2#
B9 PRIM_CORE_OPT_DIS USB_OC2# 39
GPP_A7/PIRQA# GPP_E12/USB2_OC3# +3V_PRIM
E28 J1
25 PCIE_PRX_WWANTX_N11 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 SIO_EXT_WAKE# SSD_DEVSLP 23
25 PCIE_PRX_WWANTX_P11 E27 J2
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SIO_EXT_WAKE# 30
D24 J3
M.2 2242 25 PCIE_PTX_WWANRX_N11
C24
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 WWAN_DEVSLP 25
25 PCIE_PTX_WWANRX_P11
WWAN 2nd 25 PCIE_PRX_WWANTX_N12 E30
PCIE11_TXP/SATA1B_TXP
H2 SIO_EXT_WAKE#
RC59 2 110K_0402_5%
PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0
SSD SATA/PCIe 2 Lane ony 4/14 25 PCIE_PRX_WWANTX_P12
F30
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1
H3 GPP_E1 1 2
m2280_PCIE_SATA# 23
A25 G4 RC41 0_0201_5% USB_OC0# 1 2
25 PCIE_PTX_WWANRX_N12 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 m3042_PCIE#_SATA 30
25 PCIE_PTX_WWANRX_P12 B25 RC13 10K_0402_5%
B PCIE12_TXP/SATA2_TXP H1 USB_OC1# 1 2 B
GPP_E8/SATALED#
RC11 10K_0402_5%
USB_OC2# 1 2
SKL-U_BGA1356 8 OF 20 RC14 10K_0402_5%
PRIM_CORE_OPT_DIS1 @ 2
RC12 10K_0402_5%

+3V_PRIM m2280_PCIE_SATA# 1 2
RC195 10K_0201_5%

U4252

5
MC74VHC1G32DFT2G_SC70-5
PRIM_CORE_OPT_DIS 1

P
INB VR_LPM_R# GPP_E1 @ RC2042
4 1
SIO_SLP_S0# O VR_LPM_R# 56
10,31,45,56,57 SIO_SLP_S0# 2 10K_0402_5%
INA

G
3
OTG_ID @ RH90 1 2 0_0201_5%
VBUSSENSE RH91 1 2 1K_0201_5%

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P09-MCP(5/14)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 9 of 65
5 4 3 2 1
 5 4 3 2 1

RC380 U22@ CC2 U22@

1 2 1 2
SUSCLK 1 2
@ RC74 1K_0402_5% 15P_0201_50V8J
33_0201_1%

2
1M_0201_5%

3
4
RC35 U22@
@ UCPU1J SKL_ULT
YC1 U22@
CLOCK SIGNALS 24MHZ_12PF_7M24090001

1
2
D42
C42 CLKOUT_PCIE_N0 XTAL24_IN RC381 U22@ CC1 U22@
CLKOUT_PCIE_P0 XTAL24_OUT
AR10 1 2 1 2
GPP_B5/SRCCLKREQ0#
B42 15P_0201_50V8J
D 24 CLK1_PCIE_WLAN# A42 CLKOUT_PCIE_N1 F43 CLK_ITPXDP_N_R RC33 1 2 0_0402_5% 33_0201_1% D
WLAN---> 24 CLK1_PCIE_WLAN AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_ITPXDP_P_R RC32 1 2 0_0402_5% CLK_ITPXDP_N 13
24 CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P 13
+3VS RC157 1 2 10K_0402_5%
25 CLK2_PCIE_WWAN# D41 BA17 SUSCLK
C41
CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 23,24,25 CC23
WWAN---> 25 CLK2_PCIE_WWAN
AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN PCH_RTCX1 1 2
25 CLKREQ_PCIE#2 GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT PCH_RTCX2
RC153 1 2 10K_0402_5% E35
+3VS XTAL24_OUT
D40 6.8P_0402_50V8J
23 CLK_PCIE_SSD# CLKOUT_PCIE_N3 XCLK_BIASREF
C40 E42 1 2
SSD---> 23 CLK_PCIE_SSD CLKOUT_PCIE_P3 XCLK_BIASREF +1.0V_CLK

1
AT10 RC31 2.7K_0402_1%
23 CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3#
RC159 1 2 10K_0402_5% AM18 PCH_RTCX1 RC86 YC2
+3VS RTCX1 PCH_RTCX2
B40 AM20 10M_0402_5% 9PF 20PPM 9H03280012
CLKOUT_PCIE_N4 RTCX2
A40 ESR MAX=50k ohm

2
CLKOUT_PCIE_P4
@ RC168 1 2 10K_0402_5% AU8 AN18 SRTCRST#
+3VS

1
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST# CC24
E40 RTCRST# RTC_RST# 30 1 2 PCH_RTCX2_R 1 2
27 CLK_PCIE_MMI# E38 CLKOUT_PCIE_N5 RC87 0_0402_5%
Card Reader ---> 27 CLK_PCIE_MMI
AU7 CLKOUT_PCIE_P5 6.8P_0402_50V8J
27 CLKREQ_PCIE#5 GPP_B10/SRCCLKREQ5#
+3VS RC161 1 2 10K_0402_5%
CMOS1

SKL-U_BGA1356 10 OF 20 1 2
1 2

1
@
CMOS1 must take care
1
+RTCVCC CLRP1 SHORT PADS~D short & touch risk on layout placement
CC25 10K_0201_5% @
+3.3V_ALW_DSW 1U_0402_6.3V6K

2
2
1 2 1 2 RTC_RST#
1 2 PCH_PCIE_WAKE# @ RC150 0_0402_5% RC89 20K_0201_5%
C RC90 1K_0402_5% 1 2 SRTCRST# C
RC85 20K_0201_5%
LAN_WAKE# 1
1 2 +3VS
RC143 10K_0402_5% CC22 PDG_An RC delay circuit with a t i me del ay i n t he
1 2 BATLOW# 1U_0402_6.3V6K range of 18– 25 ms s houl d be pr ovi ded.
2
RC84 8.2K_0402_5% The circuit should be connected to VCCRTC.

5
+3VS 1 PCH_PLTRST#

P
B
4
22,23,24,25,27,30,31,32,34,43 PLT_RST# O 2
A

G
1

1 2 ME_RESET# UC4

2
@ RC97 8.2K_0402_5% RC152 TC7SH08FU_SSOP5

3
100K_0402_5% RC154@ +RTCVCC
10K_0402_5%
+1.0V_VCCST
2

RC88 1
INTRUDER# 2 1M_0402_5%

1
1 2 H_VCCST_PWRGD_P
RC25 1K_0402_5%
+3.3V_ALW_DSW +3V_PRIM
+3V_PRIM

1 2 ME_SUS_PWR_ACK VRALERT# RC60 1 2 10K_0201_5%

@ RC162 10K_0402_5%
AC_PRESENT 1 2
RC91 10K_0402_5%
@ UCPU1K SKL-U
1 2 PCH_RSMRST#_R
RC189 10K_0402_5% SYSTEM POWER MANAGEMENT
AT11 SIO_SLP_S0# SLP_S0# for support connect stand by mode
1 2 PCH_PWROK GPP_B12/SLP_S0# AP15 SIO_SLP_S3# SIO_SLP_S0# 9,31,45,56,57
@ RC397 10K_0201_1% PCH_PLTRST# AN10
GPD4/SLP_S3#
BA16 SIO_SLP_S4# SIO_SLP_S3# 30,32
SYS_RESET# B5
GPP_B13/PLTRST# GPD5/SLP_S4#
AY16 SIO_SLP_S5# SIO_SLP_S4# 30,32
B PCH_RSMRST#_RAY17 SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# 30 B
8/21 CRB1.0 change to 0603 1/10W
13,30 PCH_RSMRST#_R RSMRST# AN15
H_CPUPWRGD_R @ RC39 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# 30,32,44,54,55,56
T7 @ PAD~D H_VCCST_PWRGD_P PROCPWRGD SLP_LAN# PAD~D @ T26
RC26 1 2 60.4_0402_1% VCCST_PWRGD_CPU
B65 BB17
13,32 H_VCCST_PWRGD_P VCCST_PWRGD GPD9/SLP_WLAN#
AN16 SIO_SLP_WLAN# 44
GPD6/SLP_A# SIO_SLP_A# 30
B6
13,30
57
SYS_PWROK
PCH_PWROK
BA20
SYS_PWROK
PCH_PWROK GPD3/PWRBTN#
BA15
SIO_PWRBTN# 10,13,30
APS CONN JAPS1
PCH_DPWROK_P BB20 AY15 AC_PRESENT 20
H_CPUPWRGD H_VCCST_PWRGD_P 30 PCH_DPWROK_P DSW_PWROK GPD1/ACPRESENT AC_PRESENT 30 GND
AU13 BATLOW# 19
ME_SUS_PWR_ACK GPD0/BATLOW# GND
AR13 18
30 ME_SUS_PWR_ACK GPP_A13/SUSWARN#/SUSPWRDNACK +3V_PRIM SIO_SLP_S3# 18
100P_0402_50V8J~D

100P_0402_50V8J~D

AP11 17
30 SUSACK# GPP_A15/SUSACK#
AU11 16
17
PME#
PCH_PCIE_WAKE#BB15 GPP_A11/PME# AP16 INTRUDER#
PAD~D @ T38 +3VALW SIO_SLP_S5# 15 16
1 1 30 PCH_PCIE_WAKE# WAKE# INTRUDER# 15
LAN_WAKE# SIO_SLP_S4#
CA4

CA3

AM15 14
30 LAN_WAKE# AW17 GPD2/LAN_WAKE# AM10 SIO_SLP_A# 13 14
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11 12 13
VRALERT#
2 2 43 3.3V_IRCAM_EN# GPD7/RSVD GPP_B2/VRALERT# +3VALW 12
11
RTC_RST# 10 11
SKL-U_BGA1356 11 OF 20 10
9
9
8
10,13,30 SIO_PWRBTN# 7
8
+3VS SYS_RESET# 7
ESD Request:place near CPU side 1 2 6
6
RC34 0_0402_5% 5
SIO_SLP_S0# 5
10K_0402_5%
4
4
1

3
+3VS 3
@ RC38

2
RC78 1
2
1
POP NO Support Deep sleep
5

ACES_50506-01841-P01
DE-POP Support Deep sleep
2

XDP_DBRESET# 1 @CONN@
P

13 XDP_DBRESET# B SYS_RESET#_R 1 SYS_RESET#

4 2
PCH_DPWROK_P1 PCH_RSMRST#_R ME_RESET# O RC36 1K_0402_5%
2 2 1 2
G

A A A
@ RC78 0_0402_5% @ RC96 8.2K_0402_5% @ UC3
74AHC1G09GW_TSSOP5
3
1
0.01U_0402_16V7K

100K_0402_5%~D

1
CC16

RC80

2 if pop UC12, RC291 also need pop(74AHC1G09GW is OD output) DELL CONFIDENTIAL/PROPRIETARY

2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P10-MCP(6/14)CLK,PM,RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 10 of 65
5 4 3 2 1
 5 4 3 2 1

+1.0V_VCCST

1 2 H_CATERR#
@ RC7 49.9_0402_1% +1.0V_VCCSTG
1 2 H_THERMTRIP#_R
RC20 1K_0402_5%
+1.0V_VCCSTG @ UCPU1D SKL-U TDI_XDP 2 1
RC2 51_0402_5%
1 2 H_PROCHOT# D63 H_CATERR# TDO_XDP 2 1
RC28 1K_0402_5% A54 CATERR# RC19 100_0402_5%
30 H_PECI H_PROCHOT# 1 2 H_PROCHOT#_R C65 PECI TMS_XDP 2 1
30,50,53,57 H_PROCHOT# PROCHOT# JTA G
RC27 1 2499_0402_1% H_THERMTRIP#_R C63 RC18 51_0402_5%
30 H_THERMTRIP# RC389 60.4_0402_1% A65 THERMTRIP# B61 TCLK_XDP PCH_JTAG_TCLK 2 1
D SKTOCC# PROC_TCK TDI_XDP TCLK_XDP 13 D
CPU MISC D60 @ RC17 51_0402_5%
+3VS PVT-001 C55 PROC_TDI A61 TDO_XDP TDI_XDP 13
Due to touch control baord with internal PU 35K, so depop RC9 13 XDP_OBS0_R D55 BPM#[0] PROC_TDO C60 TMS_XDP TDO_XDP 13
13 XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TMS B59 TRST#_XDP TMS_XDP 13
T9 @ PAD~D BPM#[2] PROC_TRST# TRST#_XDP 13
1 2 TOUCH_SCREEN_PD# XDP_OBS3_R C56
T10 @ PAD~D BPM#[3] PCH_JTAG_TCLK
@ RC9 10K_0402_5% B56
1 2 EC_SLP_S0IX# SIO_EXT_SMI# A6 PCH_JTAG_TCK D59 TDI_XDP PCH_JTAG_TCLK 13
TOUCH_SCREEN_PD# A7 GPP_E3/CPU_GP0 PCH_JTAG_TDI TDO_XDP
@ RC163 10K_0402_5% A56
22 TOUCH_SCREEN_PD# NFC_DET# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 TMS_XDP
EC_SLP_S0IX# GPP_B3/CPU_GP2 PCH_JTAG_TMS TRST#_XDP
AY5 C61
+3V_PRIM 30 EC_SLP_S0IX# GPP_B4/CPU_GP3 PCH_TRST# A59 TCLK_XDP 1 2
CPU_POPIRCOMP AT16 JTAGX +1.0V_VCCSTG
@ RC3 1K_0402_5%
SIO_EXT_SMI# PCH_POPIRCOMP AU16 PROC_POPIRCOMP
1 2
EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
RC8 10K_0402_5%
1 2 NFC_DET# EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
RC68 10K_0402_5%

1
49.9_0402_1%

49.9_0402_1%

49.9_0402_1%

49.9_0402_1%
RC160

RC167

RC122

RC123
SKL-U_BGA1356 4 OF 20

2
+5VALW HDA_SDO
Strap pin ME debug mode , this signal

2
RC188 has a weak internal PD
1M_0201_5% @ L=>security measures def i ned
C
in the Flash Descriptor will be C
From EC, for in ef f ect ( def ault)

1
enable
ME code H=>Flash Descriptor Security

3
programing will be overridden

2
@Q25B
DMN2400UV-7_SOT-563-6 RC92
5 6 1 1 2 HDA_SDOUT
30 ME_FWP +DVDDIO

4
Q25A 1K_0402_5%
DMN2400UV-7_SOT-563-6
Low = Disabled
R5774 1 2 * High = Enabled
0_0201_5%

@ UCPU1G SKL-U

AUDIO

RC75 1 2 33_0402_5% HDA_SYNC_R BA22

28 HDA_SYNC HDA_BLK_R HDA_SYNC/I2S0_SFRM
RC77 1 2 33_0402_5% AY22
28 HDA_BLK HDA_SDOUT RC76 1 2 HDA_SDOUT_R HDA_BLK/I2S0_SCLK
33_0402_5% BB22 SDIO/SDXC
28 HDA_SDOUT HDA_SDI0 BA21
HDA_SDO/I2S0_TXD
28 HDA_SDI0 AY21
HDA_SDI0/I2S0_RXD
AB11 CAM_CBL_DET#
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD CAM_CBL_DET# 43
AW22 AB13 +3VS
J5
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
AB12
SPK_ID 29
44 NGFF_WWAN_PWREN AY20
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
W12 CAM_CBL_DET# 1 2
HDA_BLK AW20
I2S1_SFRM GPP_G3/SD_DATA2
W11 CONTACTLESS_DET# SSD_PWR_EN 44 RC53 100K_0402_5%~D
I2S1_TXD GPP_G4/SD_DATA3
W10
CONTACTLESS_DET# 43 WWAN_OFF# 1 2
AK7 GPP_G5/SD_CD# W8
WWAN_OFF# 25
1 RC202 10K_0402_5%
AK6
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
W7 EDP_ID0 PCH_AUD_PWR_EN 30 CONTACTLESS_DET# 1 2
@ CC17 AK9
GPP_F0/I2S2_SCLK GPP_G7/SD_WP EDP_ID0 22 RC200 100K_0402_5%~D
B AK10 GPP_F2/I2S2_TXD BA9 B
22P_0402_50V8J
2 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
SD_PWR_EN 44
GPP_A16/SD_1P8_SEL +3V_PRIM
TPM_DET H5 AB7 SD_RCOMPRC140 1 2 200_0402_1%
GPP_D19/DMIC_CLK0 SD_RCOMP
Close to RC77 D7
GPP_D20/DMIC_DATA0 EDP_ID0 1 2100K_0201_5%
D8 AF13 RC193
C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
SPKR AW5
HDA_SDOUT 28 SPKR GPP_B14/SPKR

HDA_SDI0
SKL-U_BGA1356 7 OF 20
RF@CC93

RF@CC94
1

1
2P_0201_25V8B

2P_0201_25V8B

+3V_PRIM
2

TPM@
TPM_DET 100K_0201_5% 2 1 RH11

TPM_DET 100K_0201_5% 1 2 RH14

TPM BOM Optional

+3V_PRIM +3V_PRIM TPM_DET
A 1 2 SPKR 1 2 HDA_SDOUT TPM 1 = W/TPM A
@ RC158 8.2K_0402_5% @ RC81 4.7K_0402_5%
0 = W/O TPM

TOP SWAP STRAP Flash Descriptor Security DELL CONFIDENTIAL/PROPRIETARY

ENABLE
override
HIGH HIGH DISABLE Security Classification Compal Secret Data Compal Electronics, Inc.
LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P11-MCP(7/14)MISC,JTAG,HDA,SDIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 11 of 65
5 4 3 2 1
 5 4 3 2 1

13 CFG[0..15]
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
D CFG14 D
CFG15

@ UCPU1S SKL-U
@ UCPU1T SKL-U
RESERVED SIGNALS-1
1 2 CFG0 SPARE
@ RC29 10K_0402_1% CFG0 E68 BB68
1 2 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
PAD~D @ T27 AW69 F6
CFG[1] RSVD_TP_BB69 PAD~D @ T30 RSVD_AW69 RSVD_F6 XTAL24_IN_RU
@ RC37 10K_0402_1% CFG2 D65 AW68 E3
CFG[2] RSVD_AW68 RSVD_E3
1 2 CFG3 D67 AK13 AU56 C11
CFG4 CFG[3] RSVD_TP_AK13 PAD~D @ T33 RSVD_AU56 RSVD_C11
@ RC30 10K_0402_1% E70 AK12 AW48 B11
C68 CFG[4] RSVD_TP_AK12 PAD~D @ T34 XTAL24_OUT_RU C7 RSVD_AW48 RSVD_B11 A11
CFG5
CFG6 D68 CFG[5] BB2 U12 RSVD_C7 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 U11 RSVD_U12 RSVD_D12 C12
F71 CFG[7] RSVD_BA3 H11 RSVD_U11 RSVD_C12 F52
CFG8
HIGH(DEFAULT) No stall(Normal Operat i on) CFG9 G69
CFG[8] RSVD_H11 RSVD_F52
LOW stall CFG10 F70
CFG[9]
AU5
CFG11 G68 CFG[10] TP5 AT5
PAD~D @ T22
CFG12 H70
CFG[11] TP6 PAD~D @ T37 SKL-U_BGA1356 20 OF 20
PVT-024 CFG[12]
CFG13 G71
Change 0 ohm to short pad CFG[13]
CFG14 H69 D5
CFG[14] RSVD_D5
CFG15 G70 D4
+1.0VA +1.0VA_XDP1 CFG[15] RSVD_D4 B2
RSVD_B2
E63 C2
13 CFG16 CFG[16] RSVD_C2
1 @ 2 F63
13 CFG17 CFG[17]
R5770 0_0201_5%
RSVD_B3
B3 Support for KBL-R U4+2
13 CFG18 E66 A3
F66 CFG[18] RSVD_A3
C
13 CFG19 CFG[19] C
1 2 CFG4 AW1 U42@
RC40 10K_0402_1% 2 1 CFG_RCOMP E60 RSVD_AW1 XTAL24_IN_RU RC377 2 1 33_0201_1%
CFG_RCOMP
RC112 49.9_0402_1% E1
ITP_PMODE RSVD_E1 U42@ U42@
2 1 E8 E2
+1.0VA_XDP1 ITP_PMODE RSVD_E2 XTAL24_OUT_RU
RC10 1.5K_0402_5% RC378 2 1 33_0201_1% RC3741 2 1M_0201_1%
AY2 BA4
RSVD_AY2 RSVD_BA4
AY1 BB4
13 ITP_PMODE RSVD_AY1 RSVD_BB4 YC3 U42@
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4 1 3
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4 1 3
LOW Enabled K46 BB5 NC NC
K45
RSVD_K46 TP4 PAD~D @ T39
RSVD_K45 2 4

27P_0201_25V8
CC96 U42@

27P_0201_25V8
CC97 U42@
A69 2 2
AL25 RSVD_A69 B69 24MHZ_18PF_XRCGB24M000F2P51R0
RSVD_AL25 RSVD_B69
AL27
RSVD_AL27
AY3
RSVD_AY3 1 1
C71
RSVD_C71
B70 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60
C54
RSVD_C54
A52 D54
RSVD_A52 RSVD_D54
BA70 AY4
T31 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T40
BA68 BB3
T28 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T41
J71 AY71
J68
RSVD_J71 VSS_AY71
AR56
ZVM# for SKYLAKE-U 2+3e
RSVD_J68 ZVM# Pebble Creek use 2+2e
F65 AW71
G65
VSS_F65 RSVD_TP_AW71
AW70
PAD~D @ T23
B VSS_G65 RSVD_TP_AW70 PAD~D @ T29 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
MSM# for SKYLAKE-U 2+3e
RSVD_E61 PROC_SELECT# +1.0V_VCCST
RC24 100K_0402_5%

SKL-U_BGA1356 19 OF 20

X76 32Gb 2133 DRAM Option (R1) , (R3) DRAM Config Option
(Resistor pop location)
MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3

Micron 32G/2133
Micron 32G_R3@ Micron 32G_R3@ Micron 32G_R3@ Micron 32G_R3@ X76_M32G@ X76_M32G@ X76_M32G@ X76_M32G@
X7669231L60 UD1 UD2 UD3 UD4 RH17 RH16 RH13 RH9
MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT MT52L1G32D4PG-107WT 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA00009ZN1L SA00009ZN1L SA00009ZN1L SA00009ZN1L SD028100280 SD028100280 SD028100280 SD028100280
Hynix 32G/2133
HYNIX_32G_@ HYNIX_32G_@ HYNIX_32G_@ HYNIX_32G_@ X76_H32G@ X76_H32G@ X76_H32G@ X76_H32G@
X7669231L62 UD1 UD2 UD3 UD4 RH18 RH15 RH13 RH9
H9CCNNNCLGALAR-NVD FBGA H9CCNNNCLGALAR-NVD FBGA
H9CCNNNCLGALAR-NVD FBGA H9CCNNNCLGALAR-NVD FBGA 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
SA00009ZL0L SA00009ZL0L SA00009ZL0L SA00009ZL0L SD028100280 SD028100280 SD028100280 SD028100280
Samsung 32G/2133
SAMSUNG_32G@ SAMSUNG_32G@ SAMSUNG_32G@ SAMSUNG_32G@ X76_S32G@ X76_S32G@ X76_S32G@ X76_S32G@
X7669231L61 UD1 UD2 UD3 UD4 RH17 RH15 RH13 RH9
A K4EBE304EB-EGCG FBGA178 K4EBE304EB-EGCG FBGA178 K4EBE304EB-EGCG FBGA178 K4EBE304EB-EGCG FBGA178 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% A
SA00008VV0L SA00008VV0L SA00008VV0L SA00008VV0L SD028100280 SD028100280 SD028100280 SD028100280

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P12-MCP(8/14)CFG,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 12 of 65
5 4 3 2 1
 5 4 3 2 1

PVT-025
Change 0.01 ohm to short pad
+1.0VA +1.0VA_XDP
+1.0VS_VCCIO
D 1 @ 2 +3V_PRIM +3.3V_ALW_DSW D
RC130 0_0603_5% 1 2 FIVR_EN_R +3VS
@ RC119 150_0402_5%

1.5K_0402_5%
RC107

1
1K_0402_5%

1.5K_0402_5%
+1.0VA_XDP +1.0V_VCCST

RC120

RC127
Place 1 2 FIVR_EN
near

2
@ RC109 150_0402_5%

2
JXDP1
0.1U_0402_10V7K

0.1U_0402_10V7K
1 1
FIVR_EN PCH_SPI_DO_XDP XDP_DBRESET# SIO_PWRBTN#
@ CC33

@ CC37
1 2 PVT-048
De-pop debug XDP related compoments
@ RC111 10K_0402_5%

0.1U_0402_25V6
@XDP@ CC95

0.1U_0402_25V6
1
2 2

@ CC36
1
TRST#_XDP 2 1 @ RC106
51_0402_5%
Place near Place near

2
TCLK_XDP 2 1 RC102
JXDP1.48 JXDP1.41

2
+1.0VA_XDP 51_0402_5%

1 2 CPU_XDP_PREQ#
12 CFG[0..15] @ RC151 51_0402_5%
CFG0
CFG1
CFG2 2 1 RESET_OUT#_R
CFG3 @ CC26 0.1U_0402_25V6
CFG4 +1.0VA_XDP
CFG5
CFG6
Place near CPU XDP
CFG7 JXDP1.47 +1.0VA_XDP
CFG8
CFG9 JXDP1
C CFG10 XDP_PRSNT_PIN1 1 2 C
CPU_XDP_PREQ# 1 2
CFG11 PVT-048 3 4 CFG17 CFG17 12
CFG12 De-pop debug XDP related compoments 9 CPU_XDP_PREQ# 5
3 4
6 CFG16
9 CPU_XDP_PRDY# 5 6 CFG16 12
CFG13 CFG3 @XDP@
RC141 2 1 1K_0402_5% XDP_PRSNT_PIN1 7 8
7 8
CFG14 CFG0 9 10 CFG8 CFG8 12
9 10
CFG15 @ RC142 2 1 0_0402_5% CFG1 11 12 CFG9 CFG9 12
11 12
13 14
13 14
CFG2 15 16 CFG10 CFG10 12
15 16
CFG3 17 18 CFG11 CFG11 12
PVT-048 19 17 18 20
De-pop debug XDP related compoments XDP_OBS0 19 20
21 22 CFG19 CFG19 12
XDP_OBS0 XDP_OBS1 21 22
@XDP@ RC138 1 2 0_0402_5% 23 24 CFG18 CFG18 12
11 XDP_OBS0_R XDP_OBS1 23 24
@XDP@ RC136 1 2 0_0402_5% 25 26
11 XDP_OBS1_R CFG4 27
25 26
28 CFG12
27 28 CFG12 12
CFG5 29 30 CFG13 CFG13 12
29 30
31 32
31 32
@ RC132 1 2 1K_0402_5% CFG6 33 34 CFG14 CFG14 12
10,32 H_VCCST_PWRGD_P 33 34
CFG7 35 36 CFG15 CFG15 12
H_VCCST_PWRGD_XDP 35 36
10,30 PCH_RSMRST#_R @XDP@ RC131 1 2 37 38
H_VCCST_PWRGD_XDP 39 37 38 40
1K_0402_5%
PVT-048 SIO_PWRBTN# 41 39 40 42 CLK_ITPXDP_P 10
De-pop debug XDP related compoments 10,30 SIO_PWRBTN# 43
41 42
44
CLK_ITPXDP_N 10
FIVR_EN FIVR_EN_R 43 44
@ RC121 1 2 0_0402_5% 45 46
1K_0402_5% FIVR_EN_R RESET_OUT#_R 45 46 XDP_DBRESET# ITP_PMODE 12
CFG0 @ RC144 1 2 47 48 XDP_DBRESET# 10
PCH_SPI_DO_XDP @XDP@ RC100 1 2 0_0402_5% RESET_OUT#_R 49 47 48 50
7 PCH_SPI_DO_XDP 49 50 TDO_XDP
@ RC99 1 2 0_0402_5% 51 52 TDO_XDP 11
10,30 SYS_PWROK PVT-048 7 DDR_XDP_SMBDAT 53
51 52
54 TRST#_XDP
De-pop debug XDP related compoments 7 DDR_XDP_SMBCLK 53 54 TDI_XDP TRST#_XDP 11
55 56 TDI_XDP 11
@XDP@ RC1871 2 33_0201_1% XDP_PRSENT# 11 PCH_JTAG_TCLK TCLK_XDP 57
55 56
58 TMS_XDP
7 PCH_SPI_DO2_XDP 11 TCLK_XDP 57 58 XDP_PRSENT# TMS_XDP 11
59 60
59 60
61
61
B B
62 63
+3V_PRIM GND GND

JXT_FP270H-061G1AM
CONN@
5

U44
1 @XDP@
P

XDP_PRSENT# NC
2 4
A Y XDP_PRSENT 45
G

NL17SZ14DFT2G_SOT353-5
3

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P13-MCP(9/14)XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 13 of 65
5 4 3 2 1
 5 4 3 2 1

PSC(Primary side cap) : Place as close to the package as possible +VCC_CORE +VCC_CORE
BSC(Backside cap) : Place on secondary side, underneath the package
@ UCPU1L SKL-U
CPU POWER 1 OF 4
Component placement order: A30 G32
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source A34 VCC_A30 VCC_G32 G33
VCC_A34 VCC_G33
A39 G35
A44 VCC_A39 VCC_G35 G37
VCC_A44 VCC_G37
AK33 G38
+VCC_CORE: 0.55~1.5V, 29A AK35 VCC_AK33
VCC_AK35
VCC_G38
VCC_G40
G40
AK37 G42
D +VCC_EDRAM: 1V, 2.5A AK38 VCC_AK37
VCC_AK38
VCC_G42
VCC_J30
J30 D
AK40 J33
+V1.8S_EDRAM: 1.8V, 50mA AL33 VCC_AK40
VCC_AL33
1.5V@29A VCC_J33
VCC_J37
J37

+VCC_EOPIO: 0.8~1V, 2A AL37

AL40
VCC_AL37 VCC_J40
J40
K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
VCC_AM32 VCC_K35

100_0402_1%
AM33 K37
VCC_AM33 VCC_K37

1
AM35 K38
VCC_AM35 VCC_K38
AM37 K40 Close CPU

RC5
VCC_AM37 VCC_K40
AM38 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43

2
+VCC_CORE_G0 K32 E32 VCCSENSE
T8 @ PAD~D RSVD_K32 VCC_SENSE VCCSENSE 57
E33 VSSSENSE
VSS_SENSE VSSSENSE 57

100_0402_1%
+VCC_CORE_G1 AK32
T18 @ PAD~D RSVD_AK32

1
B63 H_CPU_SVIDALRT#
AB62 VIDALERT# A63 VIDSCLK_R
VCCOPC_AB62 VIDSCK

RC6
P62 D64 VIDSOUT_R
V62 VCCOPC_P62 1V@2.5A VIDSOUT
VCCOPC_V62
G20

2
VCCSTG_G20
H63
VCC_OPC_1P8_H63
1V@0.05A
G61
VCC_OPC_1P8_G61 PVT-026
AC63 Change 0 ohm to short pad
VCCOPC_SENSE
AE63
VSSOPC_SENSE +1.0V_VCCSTG_R RC1 1 2
@ 0_0402_1% +1.0V_VCCSTG
AE62
AG62 VCCEOPIO
VCCEOPIO 1V@2A
AL63
AJ62 VCCEOPIO_SENSE
C VSSEOPIO_SENSE C

SKL-U_BGA1356 12 OF 20

VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e

(w/ on package cache)

+1.0V_VCCST
SVID ALERT

1
56_0402_1%
RC94
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils

2
2 1 H_CPU_SVIDALRT#
57 VIDALERT_N 220_0402_5% RC22

+1.0V_VCCST
SVID DATA

100_0402_1%
1
CAD Note: Place the PU resistors close to CPU

RC93
B B
RC208close to CPU 300 - 1500mils

2
2 1 VIDSOUT_R
57 VIDSOUT 0_0402_5%~D RC23

+1.0V_VCCST
SVID CLK

100_0402_1%
1

@ RC95
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils

2
2 1 VIDSCLK_R
57 VIDSCLK 0_0402_5%~D RC21

CDI#61280
10.2.7 SVID Topology
Table 10-9. SVID Bus Routing Guidelines
A
need double pull high A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P14-MCP(10/14)PWR-VCC CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 14 of 65
5 4 3 2 1
 5 4 3 2 1

+VCCGT: 0.55~1.5V, 54A

+VCCGTX : 0.55~1.5V, 7A
+VCC_GT +VCC_GT

D @ UCPU1M SKL-U D

+VCCIA_GT CPU POWER 2 OF 4

N70
VCCGT
A48 N71
A53 VCCGT VCCGT R63
A58 VCCGT VCCGT R64
A62 VCCGT VCCGT R65
A66 VCCGT VCCGT R66
VCCGT VCCGT
AA63 R67
AA64 VCCGT VCCGT R68
AA66 VCCGT VCCGT R69
AA67
VCCGT
VCCGT
1.5V@54A VCCGT
VCCGT
R70
AA69 R71 +VCC_CORE +VCCIA_GT +VCC_GT
VCCGT VCCGT
AA70 T62 U42@ R275 U22@ R276
AA71 VCCGT VCCGT U65 0.0002_0805_5% 0.0002_0805_5%
AC64 VCCGT VCCGT U68 1 2 1 2
AC65 VCCGT VCCGT U71
AC66 VCCGT VCCGT W63
VCCGT VCCGT
AC67 W64
VCCGT VCCGT
AC68 W65
AC69 VCCGT VCCGT W66
VCCGT VCCGT
AC70 W67
VCCGT VCCGT
AC71 W68
VCCGT VCCGT
J43 W69 U42@ R277 U22@ R278
VCCGT VCCGT +VCCIA_GT
J45 W70 0.0002_0805_5% 0.0002_0805_5%
J46 VCCGT VCCGT W71 1 2 1 2
J48
VCCGT
VCCGT
1.5V@7A VCCGT
VCCGT
Y62
J50
J52 VCCGT
J53 VCCGT AK42 +VCC_GT
J55 VCCGT VCCGTX_AK42 AK43
C J56 VCCGT VCCGTX_AK43 AK45 C
J58 VCCGT VCCGTX_AK45 AK46
VCCGT VCCGTX_AK46
J60 AK48
VCCGT VCCGTX_AK48 +VCCIA_GT
K48 AK50
K50 VCCGT VCCGTX_AK50 AK52 AK52 @
VCCGT VCCGTX_AK52
K52 K52 AK53 AK52 R279 1 2 0_0402_5%
VCCGT VCCGTX_AK53
K53 AK55
K55 VCCGT VCCGTX_AK55 AK56 +VCC_GT
VCCGT VCCGTX_AK56
K56 AK58 @
K58 VCCGT VCCGTX_AK58 AK60 R280 1 2 0_0402_5%
K52
VCCGT VCCGTX_AK60
K60 AK70
VCCGT VCCGTX_AK70
L62 AL43
VCCGT VCCGTX_AL43
L63 AL46
VCCGT VCCGTX_AL46
L64 AL50
L65 VCCGT VCCGTX_AL50 AL53
VCCGT VCCGTX_AL53
L66 AL56
VCCGT VCCGTX_AL56
L67 AL60
VCCGT VCCGTX_AL60
L68 AM48
+VCC_GT VCCGT VCCGTX_AM48
L69 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
100_0402_1% VCCGT VCCGTX_AM53
M62 AM56
VCCGT VCCGTX_AM56
1

N63 AM58
VCCGT VCCGTX_AM58
N64 AU58
RC44

N66 VCCGT VCCGTX_AU58 AU63

Close CPU VCCGT VCCGTX_AU63
N67 BB57
VCCGT VCCGTX_BB57
N69 BB66
2

VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
57 VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
57 VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
100_0402_1%
1

B SKL-U_BGA1356 13 OF 20 B
RC42
2

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P15-MCP(11/14)PWR-VCCGT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 15 of 65
5 4 3 2 1
 5 4 3 2 1

+1.2V_DDR: 1.2V, 3.5A

+1.0V_VCCST: 1V, 120mA; VCCPLL: 1V, 120mA
+1.0V_VCCSTG: 1V, 40mA
+VCCPLL_OC: 1.2V, 260mA
+1.0VS_VCCIO: 0.85~0.95V, 3.1A +1.2V_DDR +1.0VS_VCCIO
+VCC_SA: 1.15V, 5.1A

@
UCPU1N SKL-U
CPU POWER 3 OF 4

AU23 AK28
VDDQ_AU23
D AU28
VDDQ_AU28
0.95V@3.1AVCCIO
VCCIO
AK30 D
AU35 AL30
AU42 VDDQ_AU35 VCCIO AL42
BB23 VDDQ_AU42 VCCIO AM28
+1.2V_DDR +1.2V_MEM_CPUCLK VDDQ_BB23 VCCIO
BB32
VDDQ_BB32
1.2V@3.5A VCCIO
AM30
BB41 AM42 +VCC_SA
+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
1 VDDQ_BB47
@ 2 BB51 AK23
RC156 VDDQ_BB51 VCCSA
0_0402_1% AK25
VCCSA
G23
PVT-027 AM40 VCCSA G25
Change 0 ohm to short pad VDDQC VCCSA G27
+1.2V_MEM_CPUCLK VCCSA +1.0VS_VCCIO
1V@0.12A A18
VCCST
G28
1.15V@5.1A VCCSA
VCCSA
J22
PSC BSC 1V@0.04A A22
VCCSTG_A22 VCCSA
J23

100_0402_1%
J27
10U_0402_6.3V6M

1U_0201_6.3V6M

VCCSA

1
1.2V@0.26A AL23 K23

RC147
VCCPLL_OC VCCSA K25
+1.0V_VCCST VCCSA
1 1 1V@0.12A K20 K27 Close CPU
CC83

@ CC76

VCCPLL_K20 VCCSA
K21 K28
VCCPLL_K21 VCCSA
K30
PSC

2
VCCSA
2 2 close to package AM23 VCCIO_SENSE

1U_0402_6.3V6K
VCCIO_SENSE
AM22 VSSIO_SENSE VCCIO_SENSE 56
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE 56
1
H21

CC35
VSSSA_SENSE

100_0402_1%

100_0402_1%
+1.2V_MEM_CPUCLK (VDDQC) Place on CPU H20
BSC VCCSA_SENSE

1
Back Side (underneath the package): 2 underneath the package
1U_0201*1 pcs (@)

RC115

RC155
1U_0402_6.3V6K
SKL-U_BGA1356 14 OF 20
Primary Side (close to package):
1 2
10U_0402 * 1 pcs 1 +VCC_SA

CC4
+VCCPLL_OC +1.0V_VCCST RC116 100_0402_1%

2
C C

2 PSC PSC

1U_0402_6.3V6K
1U_0201_6.3V6M
close to package close to package

1 1 VSA_SEN- 57

CC68
VSA_SEN+ 57

CC3
2 2

+1.0VS_VCCIO Decoupling Requirment

+1.2_DDR Decoupling Requirment Back Side (underneath the package):
Back Side (underneath the package): 10U_0402*2 pcs + 1U_0201*4 pcs (@)
10U_0402*2 pcs + 1U_0201*4 pcs (@) Primary Side (close to package):
Primary Side (close to package): 1U_0402*4 pcs
10U_0402*4 pcs + 22U_0603*3 pcs

+1.0VS_VCCIO
B +1.2V_DDR B

PSC
PSC
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1
1 1 1 1 1 1 1
CC88

CC87

CC86

CC19

CC82

CC84

CC20

CC60

CC69

CC63

CC61
2 2 2 2
2 2 2 2 2 2 2

BSC BSC
10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1
@ CC85

@ CC18

@ CC77

@ CC80

@ CC75

@ CC74

CC67

@ CC62

@ CC71

@ CC65

@ CC72

@ CC66
2 2 2 2 2 2 2 2 2 2 2 2
@

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P16-MCP(12/14)PWR-VCCIO,MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 16 of 65
5 4 3 2 1
 5 4 3 2 1

PVT-028
Change 0 ohm to short pad

+3V_PRIM +3.3V_PGPP

1 @ 2 close UC1.AG15 and <120mil

close UC1.Y16 and <400mil
close UC1.T16 and <400mil
RC134 0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1

CC58

CC50

CC45
D
+3.3V_ALW_DSW +1.8VA +1.0VA +1.0V_PRIM_CORE
PCH PWR 2@ 2@ 2@
D
47U_0805_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M

47U_0805_6.3V6M
PVT-028
1 1 1 1
CC73

CC47

CC29

CC52
@ +1.0V_MPHYAON +1.0V_PRIM_CORE +1.0VA Change 0 ohm to short pad

+1.8VA +1.8V_PGPP
2 2 2 2
close UC1.AB19 and <400mil
1 @ 2
RC139 0_0603_5%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1

CC54

CC51
CC32

CC14
@ UCPU1O SKL-U
2 2 2@ 2@ +1.8V_PGPP +3.3V_PGPP +3V_PRIM +1.8VA
CPU POWER 4 OF 4

1.0V@0.696A AB19
VCCPRIM_1P0
AB20 AK15
VCCPRIM_1P0 VCCPGPPA
P18 AG15

1U_0402_6.3V6K
4.7P_0402_50V8C
VCCPRIM_1P0 VCCPGPPB Y16 1

1
PVT-028 VCCPGPPC
close UC1.AF18 and <400mil 1.0V@2.57A AF18 Y15

CC46
VCCPRIM_CORE VCCPGPPD

CC48
Change 0 ohm to short pad AF19 T16
VCCPRIM_CORE VCCPGPPE
V20 AF16 1.8V@0.161A +1.8V_PGPP

2
+1.0VA +1.0V_MPHYAON V21 VCCPRIM_CORE VCCPGPPF AD15 2
VCCPRIM_CORE VCCPGPPG +3.3V_PGPP
close UC1.AL1 and <120mil AL1 V19 close UC1.V19 and <120mil
DCPDSW_1P0 VCCPRIM_3P3_V19
1 @ 2
RC125 0_0603_5% +1.0V_MPHYGT close UC1.K17 and <120mil 1.0V@0.022A K17 T1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS +3V_PRIM
+1.0V_DTS L1
+1.5VS_AUDIO +3V_PRIM VCCMPHYAON_1P0
VCCATS_1P8
AA1 1.8V@0.006A close UC1.AA1 and <400mil
1 @ 2 close UC1.N15 and CC210 <400mil, CC211 <120mil 1.0V@2.1A N15
RC47 VCCMPHYGT_1P0_N15
0_0402_1% 3.3V@0.001A

47U_0805_6.3V6M
N16 AK17

1U_0402_6.3V6K
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 close UC1.AK17 and <120mil
1 1 N17
VCCMPHYGT_1P0_N17

CC43
P15 AK19 3.0V@0.001A

1U_0402_6.3V6K
VCCMPHYGT_1P0_P15 VCCRTC_AK19
close UC1.AK19 and <120mil +RTCVCC

CC39
P16 BB14

1U_0402_6.3V6K
1 1

0.1U_0402_10V7K
1

VCCMPHYGT_1P0_P16 VCCRTC_BB14

CC57
1 1

0.1U_0402_10V7K

CC56
@RC185 RC186 2@ 2 1.0V@0.088A K15 BB10
C +1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
close UC1.BB10 and <120mil C

CC70

CC79
0_0603_5% 0_0603_5% L15
VCCAMPHYPLL_1P0 A14 2 2
+VCCCLK1 1

0.1U_0402_10V7K
VCCCLK1

CC81
2 2
+1.0V_APLL 1.0V@0.026A V15 1.0V@0.135A
2

VCCAPLL_1P0 K19 +VCCCLK2

VCCCLK2
AB17
+1.0VA VCCPRIM_1P0_AB17 2
L23 Y18 L21 +VCCCLK3
VCCPRIM_1P0_Y18 VCCCLK3
1 2
+3.3V_ALW_DSW 3.3V@0.118A AD17
VCCDSW_3P3_AD17 VCCCLK4
N20 +VCCCLK4
BLM18EG221SN1D_2P AD18
VCCDSW_3P3_AD18
AJ17 L19 +VCCCLK5
VCCDSW_3P3_AJ17 VCCCLK5

close UC1.AJ19 and <400mil 1.5V@0.068A AJ19 A10 +VCCCLK6

1

VCCHDA VCCCLK6
2P_0201_25V8B
CC53

2P_0201_25V8B
CC64

PVT-028 +1.0V_SRAM 3.3V@0.011A AJ16 AN11

Change 0 ohm to short pad +3.3V_SPI VCCSPI GPP_B0/CORE_VID0 CORE_VID0 56
AN13 CORE_VID1 56
2

GPP_B1/CORE_VID1
1.0V@0.642A AF20

1U_0402_6.3V6K
close UC1.AF20 and <400mil VCCSRAM_1P0
+1.0V_MPHYGT AF21
1 CC44
VCCSRAM_1P0
+1.0V_SRAM T19
T20 VCCSRAM_1P0
VCCSRAM_1P0
1 @ 2
RC133 0_0603_5% 2@
+3V_PRIM 3.3V@0.075A AJ21
VCCPRIM_3P3_AJ21
+1.0V_APLLEBB
+1.0V_APLLEBB AK20
CDI#561280
+1.0VA VCCPRIM_1P0_AK20
3/23 follow PDG 5.76GHz
1 @ 2 An EMI Filter Implementation to Isolate close UC1.N18 and <120mil 1.0V@0.033A N18
RC128 VCCAPLLEBB
0_0402_1% 5.76 GHz Noise Coming From VccHDA 1U_0402_6.3V6K
1
PVT-028 SKL-U_BGA1356 15 OF 20
CC38

Change 0 ohm to short pad

+1.0VA +1.0V_CLK 2

1 @ 2
RC103 0_0603_5%
1U_0402_6.3V6K

1 close UC1.A10 and <120mil

CC28

+1.0V_CLK +1.0V_CLK
B B
2
@ RC16 RC118
+3VALW 1 2 +VCCCLK1 1 2 +VCCCLK4
PVT-028 +3.3V_ALW_DSW
Change 0 ohm to short pad 0_0603_5%
0_0402_5% 1 1
CC5 CC40
+1.0V_MPHYGT +1.0V_AMPHYPLL
0.1U_0201_10V6K 0.1U_0201_10V6K
@ RC394 1 2 0_0402_5% 2 2
1 @ 2
RC129 0_0402_1% Q352
1U_0402_6.3V6K

close UC1.K15 and <120mil Close to Pin A14 Close to Pin N20
DMG2301U-7_SOT23-3
1
CC34

1 2 +3.3V_ALW_DSW_Q352 1 3
D

RC395 0_0402_5% RC117 RC105

1

2 1 2 +VCCCLK2 1 2 +VCCCLK5
@ +3.3V_ALW_DSW
G
2

R234 0_0603_5% 0_0603_5%

1 1
499K_0402_1%
CC42 CC41
0.1U_0201_10V6K 0.1U_0201_10V6K
2

2 2
22U_0603_6.3V6M

22U_0603_6.3V6M

@ @ R235
1 1
+1.0VA +1.0V_APLL
CC55

CC59

close UC1.V15 and <100mil 100K_0402_5% Close to Pin K19 Close to Pin L19
1

L30 1
1 2 @ C1134
1

2 2 0.1U_0201_10V6K R233 RC104 RC15

BLM18EG221SN1D_2P 49.9K_0402_1% 1 2 +VCCCLK3 1 2 +VCCCLK6
2
2
1

1 0_0603_5% 1 0_0402_5%
R121
CC27 CC30
1

0_0201_5% D
22U_0603_6.3V6M 22U_0603_6.3V6M
1

2P_0201_25V8B
CC92

Q353 2
VCCDSW_EN_GPIO 30 2 2
place near AD17,AD18,AJ17 DII-DMN65D8LW-7 G
2

S
2

3
1

A A
CC49
2P_0201_25V8B
2

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P17-MCP(13/14)PCH PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 17 of 65
5 4 3 2 1
 5 4 3 2 1

Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on

@ UCPU1P SKL-U @ UCPU1Q SKL-U R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
@ UCPU1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
VSS VSS VSS VSS VSS VSS
A70 AM13 AT71 BA57 G22 L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
D AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10 D
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
VSS VSS VSS VSS VSS VSS
AB18 AM55 AV68 BB30 G58 N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
VSS VSS VSS VSS VSS VSS
AD19 AM8 AW12 BB6 H15 P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
VSS VSS VSS VSS VSS VSS
AD62 AN28 AW18 BB67 J11 R6
VSS VSS VSS VSS VSS VSS
AD8 AN30 AW21 BB70 J13 T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
VSS VSS VSS VSS VSS VSS
AE69 AN40 AW34 D14 J42 U10
VSS VSS VSS VSS VSS VSS
AF1 AN42 AW36 D18 J8 U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
VSS VSS VSS VSS VSS VSS
AF15 AN63 AW41 D25 K18 U66
VSS VSS VSS VSS VSS VSS
AF17 AP10 AW43 D26 K22 U67
VSS VSS VSS VSS VSS VSS
AF2 AP18 AW45 D30 K61 U69
VSS VSS VSS VSS VSS VSS
AF4 AP20 AW47 D34 K63 U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
VSS VSS VSS VSS VSS VSS
AG16 AP28 AW51 D44 K65 V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
C AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17 C
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
VSS VSS VSS VSS VSS VSS
AH13 AP68 AW64 D62 L16 Y20
VSS VSS VSS VSS VSS VSS
AH6 AP70 AW66 D66 L17 Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
VSS VSS VSS VSS
AH64 AR15 AY66 E11
VSS VSS VSS VSS
AH67 AR16 B10 E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
VSS VSS VSS VSS SKL-U_BGA1356 18 OF 20
AJ18 AR23 B18 E21
AJ20 VSS VSS AR28 B22 VSS VSS E46
VSS VSS VSS VSS
AJ4 AR35 B30 E50
VSS VSS VSS VSS
AK11 AR42 B34 E53
VSS VSS VSS VSS
AK16 AR43 B39 E56
VSS VSS VSS VSS
AK18 AR45 B44 E6
AK21 VSS VSS AR46 B48 VSS VSS E65
VSS VSS VSS VSS
AK22 AR48 B53 E71
VSS VSS VSS VSS
AK27 AR5 B58 F1
VSS VSS VSS VSS
AK63 AR50 B62 F13
VSS VSS VSS VSS
AK68 AR52 B66 F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
VSS VSS VSS VSS
AL2 AR58 BA10 F27
VSS VSS VSS VSS
AL28 AR63 BA14 F28
VSS VSS VSS VSS
AL32 AR8 BA18 F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
VSS VSS VSS VSS
AL38 AT20 BA23 F35
VSS VSS VSS VSS
AL4 AT23 BA28 F37
VSS VSS VSS VSS
AL45 AT28 BA32 F38
VSS VSS VSS VSS
AL48 AT35 BA36 F4
AL52 VSS VSS AT4 F68 VSS VSS F40
VSS VSS VSS VSS
AL55 AT42 BA45 F42
VSS VSS VSS VSS
AL58 AT56 BA41
B AL64 VSS VSS AT58 VSS B
VSS VSS

SKL-U_BGA1356 16 OF 20 SKL-U_BGA1356 17 OF 20

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P18-MCP(14/14)VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 18 of 65
5 4 3 2 1
 5 4 3 2 1

+1.8VU +1.8VU +1.8VU +1.8VU

+1.8VU UD4 @ +1.8VU UD2 @

DDR_A_D27 DDR_A_D12

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
A3 P9 A3 P9
VDD1 DQ0 DDR_A_D29 VDD1 DQ0 DDR_A_D8
6 DDR_A_DQS#[0..7] 1 1 A4 N9 1 1 A4 N9

1
VDD1 DQ1 DDR_A_D25 VDD1 DQ1 DDR_A_D10

CD40

CD83

CD36

CD50

CD84

CD54
A5 N10 A5 N10
A6 VDD1 DQ2 N11 DDR_A_D31 A6 VDD1 DQ2 N11 DDR_A_D14
6 DDR_A_DQS[0..7] VDD1 DQ3 VDD1 DQ3
A10 M8 DDR_A_D28 A10 M8 DDR_A_D13

2
2 2 U3 VDD1 DQ4 M9 DDR_A_D24 2 2 U3 VDD1 DQ4 M9 DDR_A_D9
6 DDR_A_D[0..63] VDD1 DQ5 VDD1 DQ5
U4 M10 DDR_A_D30 U4 M10 DDR_A_D15
U5 VDD1 DQ6 M11 DDR_A_D26 U5 VDD1 DQ6 M11 DDR_A_D11
6,21 DDR_A_CA1_[0..9] VDD1 DQ7 DDR_A_D20 VDD1 DQ7 DDR_A_D7
U6 F11 U6 F11
U10 VDD1 DQ8 F10 DDR_A_D17 U10 VDD1 DQ8 F10 DDR_A_D1
6,21 DDR_A_CA2_[0..9] VDD1 DQ9 VDD1 DQ9
+1.2V_DDR F9 DDR_A_D22 +1.2V_DDR F9 DDR_A_D0
DQ10 DDR_A_D18 DQ10 DDR_A_D5
F8 F8
D
A8 DQ11 E11 DDR_A_D21 A8 DQ11 E11 DDR_A_D3 D
A9 VDD2 DQ12 E10 DDR_A_D16 A9 VDD2 DQ12 E10 DDR_A_D6
VDD2 DQ13 DDR_A_D23 +1.2V_DDR +1.2V_DDR VDD2 DQ13 DDR_A_D4
D4 E9 D4 E9
+1.2V_DDR +1.2V_DDR D5 VDD2 DQ14 D9 DDR_A_D19 D5 VDD2 DQ14 D9 DDR_A_D2
VDD2 DQ15 DDR_A_D51 VDD2 DQ15 DDR_A_D40
D6 T8 D6 T8
G5 VDD2 DQ16 T9 DDR_A_D55 G5 VDD2 DQ16 T9 DDR_A_D45
VDD2 DQ17 DDR_A_D49 VDD2 DQ17 DDR_A_D43

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
H5 T10 H5 T10
VDD2 DQ18 DDR_A_D53 VDD2 DQ18 DDR_A_D47
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
H6 T11 1 1 1 H6 T11

1
VDD2 DQ19 DDR_A_D50 VDD2 DQ19 DDR_A_D44

CD12

CD61

CD60

CD77
1 1 1 H12 R8 H12 R8
1

VDD2 DQ20 DDR_A_D54 VDD2 DQ20 DDR_A_D41

CD2

CD23

CD24

CD18
J5 R9 J5 R9
J6 VDD2 DQ21 R10 DDR_A_D48 J6 VDD2 DQ21 R10 DDR_A_D46

2
K5 VDD2 DQ22 R11 DDR_A_D52 2 2 2 K5 VDD2 DQ22 R11 DDR_A_D42
2

2 2 2 VDD2 DQ23 DDR_A_D56 VDD2 DQ23 DDR_A_D33

K6 C11 K6 C11
K12 VDD2 DQ24 C10 DDR_A_D61 K12 VDD2 DQ24 C10 DDR_A_D37
L5 VDD2 DQ25 C9 DDR_A_D62 L5 VDD2 DQ25 C9 DDR_A_D34
P4 VDD2 DQ26 C8 DDR_A_D59 P4 VDD2 DQ26 C8 DDR_A_D39
P5 VDD2 DQ27 B11 DDR_A_D60 P5 VDD2 DQ27 B11 DDR_A_D36
VDD2 DQ28 DDR_A_D57 VDD2 DQ28 DDR_A_D32
P6 B10 P6 B10
U8 VDD2 DQ29 B9 DDR_A_D63 U8 VDD2 DQ29 B9 DDR_A_D35
VDD2 DQ30 DDR_A_D58 VDD2 DQ30 DDR_A_D38
U9 B8 U9 B8
+1.2V_DDR VDD2 DQ31 +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31

+1.2V_DDR +1.2V_DDR +1.2V_DDR DDR_A_CA1_0 DDR_A_CA2_0

A11
VDDQ CA0
R2
DDR_A_CA1_1
Closed to UD20 A11
VDDQ CA0
R2
DDR_A_CA2_1
C12 P2 C12 P2
VDDQ CA1 DDR_A_CA1_2 VDDQ CA1 DDR_A_CA2_2

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
Closed to UD19 E8
VDDQ CA2
N2
DDR_A_CA1_3
E8
VDDQ CA2
N2
DDR_A_CA2_3
E12 N3 1 1 1 1 1 1 E12 N3

1
VDDQ CA3 DDR_A_CA1_4 VDDQ CA3 DDR_A_CA2_4
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

CD80

CD79

CD63

CD39

CD65
G12 M3 G12 M3
VDDQ CA4 DDR_A_CA1_5 VDDQ CA4 DDR_A_CA2_5

CD74

CD57
1 1 1 1 1 1 H8 F3 H8 F3
1

VDDQ CA5 DDR_A_CA1_6 VDDQ CA5 DDR_A_CA2_6

CD59

CD38

CD9

CD37

CD11

CD16

H9 E3 H9 E3

2
VDDQ CA6 DDR_A_CA1_7 2 2 2 2 2 2 VDDQ CA6 DDR_A_CA2_7
CD27

H11 E2 H11 E2
J9 VDDQ CA7 D2 DDR_A_CA1_8 J9 VDDQ CA7 D2 DDR_A_CA2_8
2

2 2 2 2 2 2 J10 VDDQ CA8 C2 DDR_A_CA1_9 J10 VDDQ CA8 C2 DDR_A_CA2_9

VDDQ CA9 VDDQ CA9
K8 K8
K11 VDDQ K11 VDDQ
VDDQ DDR_A_DQS3 VDDQ DDR_A_DQS1
L12 L10 L12 L10
N8 VDDQ DQS0 G10 DDR_A_DQS2 N8 VDDQ DQS0 G10 DDR_A_DQS0
N12 VDDQ DQS1 P10 DDR_A_DQS6 N12 VDDQ DQS1 P10 DDR_A_DQS5
R12 VDDQ DQS2 D10 DDR_A_DQS7 R12 VDDQ DQS2 D10 DDR_A_DQS4
C C
U11 VDDQ DQS3 U11 VDDQ DQS3
+1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
L11 DDR_A_DQS#3 L11 DDR_A_DQS#1
F2 DQS0# G11 DDR_A_DQS#2 F2 DQS0# G11 DDR_A_DQS#0
+1.2V_DDR +1.2V_DDR VDDCA DQS1# DDR_A_DQS#6 VDDCA DQS1# DDR_A_DQS#5
G2 P11 G2 P11
VDDCA DQS2# DDR_A_DQS#7 VDDCA DQS2# DDR_A_DQS#4

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
H3 D11 H3 D11
VDDCA DQS3# VDDCA DQS3#
L2 1 1 L2

1
VDDCA VDDCA

CD3

CD58

CD56
M2 M2
VDDCA VDDCA
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

L8 L8
DM0 DM0
1 1 G8 G8

2
1

DM1 2 2 DM1
CD31

CD14

CD10

A1 P8 A1 P8
A2 NC DM2 D8 A2 NC DM2 D8
A12 NC DM3 A12 NC DM3
2

2 2 A13 NC A13 NC
NC DDR_A0_ZQ0 RD20 1 NC DDR_A1_ZQ0
B1 B3 2 240_0402_1% B1 B3 RD1 1 2 240_0402_1%
B13 NC ZQ0 B4 DDR_A0_ZQ1 RD19 1 2 240_0402_1% B13 NC ZQ0 B4 DDR_A1_ZQ1 RD2 1 2 240_0402_1%
NC ZQ1 NC ZQ1
C4 C4
K9 NC K9 NC
R3 NC K3 R3 NC K3
NC CKE0 DDR_A_CKE0 6,21 NC CKE0 DDR_A_CKE2 6,21
T1 K4 DDR_A_CKE1 6,21 T1 K4 DDR_A_CKE3 6,21
T13 NC CKE1 T13 NC CKE1
U1 NC U1 NC
U2 NC L3 DDR_A_CS#0 U2 NC L3 DDR_A_CS#0
NC CS0# DDR_A_CS#1 DDR_A_CS#0 6,21 NC CS0# DDR_A_CS#1
U12 L4 DDR_A_CS#1 6,21 U12 L4
NC CS1# NC CS1#
U13 U13
NC NC
J3 DDR_A_CLK0 6,21 J3 DDR_A_CLK1 6,21
CK CK
P3
VSSCA CK#
J2 DDR_A_CLK#0 6,21 All VREF traces should P3
VSSCA CK#
J2 DDR_A_CLK#1 6,21
M4 have 10 mil trace width M4
VSSCA VSSCA
J4 J4
G4 VSSCA J8 DDR_A_ODT0 G4 VSSCA J8 DDR_A_ODT0
VSSCA ODT DDR_A_ODT0 6,21 VSSCA ODT
G3 G3
F4 VSSCA F4 VSSCA
D3 VSSCA J11 D3 VSSCA J11
VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA

B B
T12 B2 T12 B2
VSSQ VSS VSSQ VSS
T6
VSSQ VSS
B5 Closed to DRAM T6
VSSQ VSS
B5 Closed to DRAM
R6 C5 R6 C5
P12 VSSQ VSS E4 +VREFDQ_A +VREFCA P12 VSSQ VSS E4 +VREFDQ_A +VREFCA
VSSQ VSS VSSQ VSS
N6 E5 N6 E5
M12 VSSQ VSS F5 M12 VSSQ VSS F5
VSSQ VSS VSSQ VSS
0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D
M6 H2 M6 H2
VSSQ VSS VSSQ VSS
L9 J12 L9 J12
K10 VSSQ VSS K2 K10 VSSQ VSS K2
VSSQ VSS 1 1 VSSQ VSS 1 1
CD21

CD22

CD71

CD69
H10 L6 H10 L6
G9 VSSQ VSS M5 G9 VSSQ VSS M5
G6 VSSQ VSS N4 G6 VSSQ VSS N4
VSSQ VSS 2 2 VSSQ VSS 2 2
F12 N5 F12 N5
F6 VSSQ VSS R4 F6 VSSQ VSS R4
VSSQ VSS VSSQ VSS
E6 R5 E6 R5
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 VSSQ VSS T3 C6 VSSQ VSS T3
VSSQ VSS VSSQ VSS
B12 T4 B12 T4
B6 VSSQ VSS T5 B6 VSSQ VSS T5
VSSQ VSS VSSQ VSS

H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D

Decoupling per DRAM device

VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF +1.2V_DDR +1.8VU
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

intel uesd 0201 for 0.1uF

1

1
CD32

CD41
2

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P19-DDRIII Channel A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 19 of 65
5 4 3 2 1
 5 4 3 2 1

6 DDR_B_DQS#[0..7]
+1.8VU +1.8VU +1.8VU +1.8VU
6 DDR_B_DQS[0..7]
+1.8VU UD3 @ +1.8VU UD1 @
6 DDR_B_D[0..63]
DDR_B_D30 DDR_B_D9

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
A3 P9 A3 P9
VDD1 DQ0 DDR_B_D28 VDD1 DQ0 DDR_B_D15
6,21 DDR_B_CA1_[0..9] 1 1 A4 N9 1 1 A4 N9

1
VDD1 DQ1 DDR_B_D26 VDD1 DQ1 DDR_B_D13

CD49

CD35

CD7

CD48

CD55

CD34
A5 N10 A5 N10
A6 VDD1 DQ2 N11 DDR_B_D27 A6 VDD1 DQ2 N11 DDR_B_D12
6,21 DDR_B_CA2_[0..9] VDD1 DQ3 VDD1 DQ3
A10 M8 DDR_B_D29 A10 M8 DDR_B_D14

2
2 2 U3 VDD1 DQ4 M9 DDR_B_D24 2 2 U3 VDD1 DQ4 M9 DDR_B_D10
VDD1 DQ5 DDR_B_D25 VDD1 DQ5 DDR_B_D8
U4 M10 U4 M10
U5 VDD1 DQ6 M11 DDR_B_D31 U5 VDD1 DQ6 M11 DDR_B_D11
U6 VDD1 DQ7 F11 DDR_B_D48 U6 VDD1 DQ7 F11 DDR_B_D39
U10 VDD1 DQ8 F10 DDR_B_D51 U10 VDD1 DQ8 F10 DDR_B_D38
+1.2V_DDR VDD1 DQ9 F9 DDR_B_D50 +1.2V_DDR VDD1 DQ9 F9 DDR_B_D37
DQ10 DDR_B_D54 DQ10 DDR_B_D33
F8 F8
D
A8 DQ11 E11 DDR_B_D52 A8 DQ11 E11 DDR_B_D34 D
A9 VDD2 DQ12 E10 DDR_B_D49 A9 VDD2 DQ12 E10 DDR_B_D35
+1.2V_DDR +1.2V_DDR VDD2 DQ13 DDR_B_D55 +1.2V_DDR +1.2V_DDR VDD2 DQ13 DDR_B_D32
D4 E9 D4 E9
D5 VDD2 DQ14 D9 DDR_B_D53 D5 VDD2 DQ14 D9 DDR_B_D36
VDD2 DQ15 DDR_B_D62 VDD2 DQ15 DDR_B_D1
D6 T8 D6 T8
G5 VDD2 DQ16 T9 DDR_B_D58 G5 VDD2 DQ16 T9 DDR_B_D5
VDD2 DQ17 DDR_B_D61 VDD2 DQ17 DDR_B_D7
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
H5 T10 H5 T10
H6 VDD2 DQ18 T11 DDR_B_D56 H6 VDD2 DQ18 T11 DDR_B_D2
1 1 1 1 1 1
1

1
VDD2 DQ19 DDR_B_D63 VDD2 DQ19 DDR_B_D0
CD17

CD51

CD76

CD33

CD81

CD78

CD53

CD68
H12 R8 H12 R8
J5 VDD2 DQ20 R9 DDR_B_D59 J5 VDD2 DQ20 R9 DDR_B_D4
J6 VDD2 DQ21 R10 DDR_B_D57 J6 VDD2 DQ21 R10 DDR_B_D3
2

2
2 2 2 K5 VDD2 DQ22 R11 DDR_B_D60 2 2 2 K5 VDD2 DQ22 R11 DDR_B_D6
VDD2 DQ23 DDR_B_D19 VDD2 DQ23 DDR_B_D41
K6 C11 K6 C11
K12 VDD2 DQ24 C10 DDR_B_D18 K12 VDD2 DQ24 C10 DDR_B_D45
L5 VDD2 DQ25 C9 DDR_B_D16 L5 VDD2 DQ25 C9 DDR_B_D42
P4 VDD2 DQ26 C8 DDR_B_D17 P4 VDD2 DQ26 C8 DDR_B_D47
P5 VDD2 DQ27 B11 DDR_B_D23 P5 VDD2 DQ27 B11 DDR_B_D44
VDD2 DQ28 DDR_B_D22 VDD2 DQ28 DDR_B_D40
P6 B10 P6 B10
U8 VDD2 DQ29 B9 DDR_B_D21 U8 VDD2 DQ29 B9 DDR_B_D43
VDD2 DQ30 DDR_B_D20 VDD2 DQ30 DDR_B_D46
U9 B8 U9 B8
+1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31 +1.2V_DDR VDD2 DQ31
+1.2V_DDR +1.2V_DDR +1.2V_DDR
DDR_B_CA1_0 DDR_B_CA2_0
Closed to UD21 A11
VDDQ CA0
R2
DDR_B_CA1_1
A11
VDDQ CA0
R2
DDR_B_CA2_1
C12
VDDQ CA1
P2
DDR_B_CA1_2
Closed to UD22 C12
VDDQ CA1
P2
DDR_B_CA2_2
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

E8 N2 E8 N2
VDDQ CA2 DDR_B_CA1_3 VDDQ CA2 DDR_B_CA2_3

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
1 1 1 1 1 1 E12 N3 E12 N3
1

VDDQ CA3 DDR_B_CA1_4 VDDQ CA3 DDR_B_CA2_4

CD1

CD13

CD30

CD82

CD15

G12 M3 1 1 1 1 1 1 G12 M3

1
VDDQ CA4 DDR_B_CA1_5 VDDQ CA4 DDR_B_CA2_5
CD28

CD6

CD64

CD25

CD52

CD85

CD75
H8 F3 H8 F3
VDDQ CA5 DDR_B_CA1_6 VDDQ CA5 DDR_B_CA2_6

CD26

CD4
H9 E3 H9 E3
2

2 2 2 2 2 2 VDDQ CA6 DDR_B_CA1_7 VDDQ CA6 DDR_B_CA2_7

H11 E2 H11 E2

2
J9 VDDQ CA7 D2 DDR_B_CA1_8 2 2 2 2 2 2 J9 VDDQ CA7 D2 DDR_B_CA2_8
J10 VDDQ CA8 C2 DDR_B_CA1_9 J10 VDDQ CA8 C2 DDR_B_CA2_9
VDDQ CA9 VDDQ CA9
K8 K8
K11 VDDQ K11 VDDQ
VDDQ DDR_B_DQS3 VDDQ DDR_B_DQS1
L12 L10 L12 L10
N8 VDDQ DQS0 G10 DDR_B_DQS6 N8 VDDQ DQS0 G10 DDR_B_DQS4
N12 VDDQ DQS1 P10 DDR_B_DQS7 N12 VDDQ DQS1 P10 DDR_B_DQS0
R12 VDDQ DQS2 D10 DDR_B_DQS2 R12 VDDQ DQS2 D10 DDR_B_DQS5
C C
U11 VDDQ DQS3 U11 VDDQ DQS3
+1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
+1.2V_DDR +1.2V_DDR L11 DDR_B_DQS#3 L11 DDR_B_DQS#1
F2 DQS0# G11 DDR_B_DQS#6 F2 DQS0# G11 DDR_B_DQS#4
VDDCA DQS1# DDR_B_DQS#7 VDDCA DQS1# DDR_B_DQS#0
G2 P11 G2 P11
VDDCA DQS2# DDR_B_DQS#2 VDDCA DQS2# DDR_B_DQS#5

10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
H3 D11 H3 D11
VDDCA DQS3# VDDCA DQS3#
10U_0603_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

L2 1 1 L2

1
VDDCA VDDCA

CD62

CD8

CD66
1 1 M2 M2
1

VDDCA VDDCA
CD73

CD29

CD5

L8 L8
DM0 DM0
G8 G8

2
A1 DM1 P8 2 2 A1 DM1 P8
2

2 2 A2 NC DM2 D8 A2 NC DM2 D8
A12 NC DM3 A12 NC DM3
A13 NC A13 NC
NC DDR_B0_ZQ0 RD13 1 NC DDR_B1_ZQ0
B1 B3 2 240_0402_1% B1 B3 RD8 1 2 240_0402_1%
B13 NC ZQ0 B4 DDR_B0_ZQ1 RD14 1 2 240_0402_1% B13 NC ZQ0 B4 DDR_B1_ZQ1 RD7 1 2 240_0402_1%
NC ZQ1 NC ZQ1
C4 C4
K9 NC K9 NC
R3 NC K3 R3 NC K3
NC CKE0 DDR_B_CKE0 6,21 NC CKE0 DDR_B_CKE2 6,21
T1 K4 DDR_B_CKE1 6,21 T1 K4 DDR_B_CKE3 6,21
T13 NC CKE1 T13 NC CKE1
U1 NC U1 NC
U2 NC L3 DDR_B_CS#0 U2 NC L3 DDR_B_CS#0
NC CS0# DDR_B_CS#1 DDR_B_CS#0 6,21 NC CS0# DDR_B_CS#1
U12 L4 DDR_B_CS#1 6,21 U12 L4
NC CS1# NC CS1#
U13 U13
NC NC
J3 DDR_B_CLK0 6,21 J3 DDR_B_CLK1 6,21
CK CK
P3
VSSCA CK#
J2 DDR_B_CLK#0 6,21 All VREF traces should P3
VSSCA CK#
J2 DDR_B_CLK#1 6,21
M4 have 10 mil trace width M4
VSSCA VSSCA
J4 J4
G4 VSSCA J8 DDR_B_ODT0 G4 VSSCA J8 DDR_B_ODT0
VSSCA ODT DDR_B_ODT0 6,21 VSSCA ODT
G3 G3
F4 VSSCA F4 VSSCA
D3 VSSCA J11 D3 VSSCA J11
VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA

B B
T12 B2 T12 B2
VSSQ VSS VSSQ VSS
T6
VSSQ VSS
B5 Closed to DRAM T6
VSSQ VSS
B5 Closed to DRAM
R6 C5 R6 C5
P12 VSSQ VSS E4 +VREFDQ_B +VREFCA P12 VSSQ VSS E4 +VREFDQ_B +VREFCA
VSSQ VSS VSSQ VSS
N6 E5 N6 E5
M12 VSSQ VSS F5 M12 VSSQ VSS F5
VSSQ VSS VSSQ VSS
0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D

0.047U_0402_10V7K~D
M6 H2 M6 H2
VSSQ VSS VSSQ VSS
L9 J12 L9 J12
K10 VSSQ VSS K2 K10 VSSQ VSS K2
VSSQ VSS 1 1 VSSQ VSS 1 1
CD19

CD47

CD70

CD72
H10 L6 H10 L6
G9 VSSQ VSS M5 G9 VSSQ VSS M5
G6 VSSQ VSS N4 G6 VSSQ VSS N4
VSSQ VSS 2 2 VSSQ VSS 2 2
F12 N5 F12 N5
F6 VSSQ VSS R4 F6 VSSQ VSS R4
VSSQ VSS VSSQ VSS
E6 R5 E6 R5
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 VSSQ VSS T3 C6 VSSQ VSS T3
VSSQ VSS VSSQ VSS
B12 T4 B12 T4
B6 VSSQ VSS T5 B6 VSSQ VSS T5
VSSQ VSS VSSQ VSS

H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D

Decoupling per DRAM device

VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF

intel uesd 0201 for 0.1uF

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P20-DDRIII Channel B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 20 of 65
5 4 3 2 1
 5 4 3 2 1

+1.2V_DDR

M3 M1

1
VREF traces should be at least 20 mils wide
with 20 mils spacing to other signals/planes.
RD12
8.2K_0402_1%

2
RD10
6 +V_DDR_REF_CA 1 2 +VREFCA
1
4.99_0402_1%~D
CD46
0.022U_0402_16V7K~D

1
D 2 D

RD11

1
8.2K_0402_1%
RD9

2
24.9_0402_1%

2
+1.2V_DDR +1.2V_DDR

M3 M1 M3 M1

1
RD18 RD6
8.2K_0402_1% 8.2K_0402_1%

2
RD15 RD5
6 +V_DDR_REFA_R 1 2 +VREFDQ_A 6 +V_DDR_REFB_R 1 2 +VREFDQ_B

10_0402_1%~D 10_0402_1%~D
1 1

CD67 CD20

1
0.022U_0402_16V7K~D 0.022U_0402_16V7K~D
2 2
RD16 RD4

1
8.2K_0402_1% 8.2K_0402_1%
1

RD3

2
RD17 24.9_0402_1%
24.9_0402_1%
C C

2
2

+0.6VS +0.6VS

RD21 1 2 68_0201_1% RD22 1 2 68_0201_1%

6,19 DDR_A_CA1_0 6,20 DDR_B_CA1_0
RD23 1 2 68_0201_1% RD24 1 2 68_0201_1%
6,19 DDR_A_CA1_1 6,20 DDR_B_CA1_1
RD25 1 2 68_0201_1% RD26 1 2 68_0201_1%
6,19 DDR_A_CA1_2 6,20 DDR_B_CA1_2
RD27 1 2 68_0201_1% RD28 1 2 68_0201_1%
6,19 DDR_A_CA1_3 6,20 DDR_B_CA1_3
RD29 1 2 68_0201_1% RD30 1 2 68_0201_1%
6,19 DDR_A_CA1_4 6,20 DDR_B_CA1_4
RD31 1 2 68_0201_1% RD32 1 2 68_0201_1%
6,19 DDR_A_CA1_5 6,20 DDR_B_CA1_5
RD33 1 2 68_0201_1% RD34 1 2 68_0201_1%
6,19 DDR_A_CA1_6 6,20 DDR_B_CA1_6
RD35 1 2 68_0201_1% RD36 1 2 68_0201_1%
6,19 DDR_A_CA1_7 6,20 DDR_B_CA1_7
RD37 1 2 68_0201_1% RD38 1 2 68_0201_1%
6,19 DDR_A_CA1_8 6,20 DDR_B_CA1_8
RD39 1 2 68_0201_1% RD40 1 2 68_0201_1%
6,19 DDR_A_CA1_9 6,20 DDR_B_CA1_9
+0.6VS

RD41 1 2 68_0201_1% RD42 1 2 68_0201_1%

6,19 DDR_A_CA2_0 6,20 DDR_B_CA2_0

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0402_6.3V6M
RD43 1 2 68_0201_1% RD44 1 2 68_0201_1%
6,19 DDR_A_CA2_1 6,20 DDR_B_CA2_1 1 1 1 1 1

CD100

CD101

CD102

CD103

CD104
RD45 1 2 68_0201_1% RD46 1 2 68_0201_1%
6,19 DDR_A_CA2_2 6,20 DDR_B_CA2_2
RD47 1 2 68_0201_1% RD48 1 2 68_0201_1%
6,19 DDR_A_CA2_3 6,20 DDR_B_CA2_3
RD49 1 2 68_0201_1% RD50 1 2 68_0201_1%
6,19 DDR_A_CA2_4 6,20 DDR_B_CA2_4 2 2 2 2 2
RD51 1 2 68_0201_1% RD52 1 2 68_0201_1%
6,19 DDR_A_CA2_5 6,20 DDR_B_CA2_5
RD53 1 2 68_0201_1% RD54 1 2 68_0201_1%
B 6,19 DDR_A_CA2_6 6,20 DDR_B_CA2_6 B
RD55 1 2 68_0201_1% RD56 1 2 68_0201_1%
6,19 DDR_A_CA2_7 6,20 DDR_B_CA2_7
RD57 1 2 68_0201_1% RD58 1 2 68_0201_1%
6,19 DDR_A_CA2_8 6,20 DDR_B_CA2_8
RD59 1 2 68_0201_1% RD60 1 2 68_0201_1%
6,19 DDR_A_CA2_9 6,20 DDR_B_CA2_9

RD61 1 2 80.6_0201_1%~D RD62 1 2 80.6_0201_1%~D

6,19 DDR_A_CS#0 6,20 DDR_B_CS#0
RD63 1 2 80.6_0201_1%~D RD64 1 2 80.6_0201_1%~D
6,19 DDR_A_CS#1 6,20 DDR_B_CS#1

RD65 1 2 80.6_0201_1%~D RD66 1 2 80.6_0201_1%~D

6,19 DDR_A_CKE0 6,20 DDR_B_CKE0
RD67 1 2 80.6_0201_1%~D RD68 1 2 80.6_0201_1%~D +0.6VS
6,19 DDR_A_CKE1 6,20 DDR_B_CKE1
RD69 1 2 80.6_0201_1%~D RD70 1 2 80.6_0201_1%~D
6,19 DDR_A_CKE2 6,20 DDR_B_CKE2
RD71 1 2 80.6_0201_1%~D RD72 1 2 80.6_0201_1%~D
6,19 DDR_A_CKE3 6,20 DDR_B_CKE3

RD73 1 2 80.6_0201_1%~D RD74 1 2 80.6_0201_1%~D

6,19 DDR_A_ODT0 6,20 DDR_B_ODT0

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0402_6.3V6M
1 1 1 1 1

CD105

CD106

CD107

CD108

CD109
2 2 2 2 2

+0.6VS +0.6VS

RD75 1 2 37.4_0201_1%~D RD76 1 2 37.4_0201_1%~D

6,19 DDR_A_CLK0 6,20 DDR_B_CLK0

RD77 1 2 37.4_0201_1%~D RD78 1 2 37.4_0201_1%~D

6,19 DDR_A_CLK#0 6,20 DDR_B_CLK#0

A A
+0.6VS +0.6VS

RD79 1 2 37.4_0201_1%~D RD80 1 2 37.4_0201_1%~D

6,19 DDR_A_CLK1 6,20 DDR_B_CLK1

RD81 1 2 37.4_0201_1%~D RD82 1 2 37.4_0201_1%~D

6,19 DDR_A_CLK#1 6,20 DDR_B_CLK#1

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P21-DDRIII Vref & Termination
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 21 of 65
5 4 3 2 1
 5 4 3 2 1
PVT-012
PVT-029 Remove co-lay L26, L27, L28

+3VALW
+3VALW
Change 0.01 ohm to short pad
Change 0 ohm to short pad
+LCDVDD +LCDVDD
eDP Conn PVT-029
+LCDVDD Change 0.01 ohm to short pad
Change 0 ohm to short pad
U8
1
eDP_TXN_P1_R eDP_TXN_P1_CONN

10U_0402_6.3V6M

10U_0402_6.3V6M

0.1U_0402_10V7K
5 1 1 @ 2 @ C180 1 2 0.1U_0201_10V6K 1 @ 2
1 5 eDP_TXN_P1

1
IN OUT

C40

C41

C169
C42 R75 0_0603_5% R412 0_0402_1%
0.1U_0402_10V7K 2
2 GND C179 2 0.1U_0201_10V6K eDP_TXP_P1_R eDP_TXP_P1_CONN
5 eDP_TXP_P1 1 1 @ 2

2
ENVDD 4 3 2 R413 0_0402_1%
EN OC
SY6288C20AAC_SOT23-5

D60 PVT-029
2 Change 0.01 ohm to short pad
D 5 PCH_ENVDD Change 0 ohm to short pad D
1 ENVDD C177 1 2 0.1U_0201_10V6K eDP_TXN_P0_R 1 @ 2 eDP_TXN_P0_CONN
5 eDP_TXN_P0
R414 0_0402_1%
LCD_VCC_TEST_EN 3
30 LCD_VCC_TEST_EN
C178 1 2 0.1U_0201_10V6K eDP_TXP_P0_R 1 @ 2 eDP_TXP_P0_CONN
5 eDP_TXP_P0
BAT54CW-7-F_SOT323-3 R415 0_0402_1%

R76 2 1 220K_0201_5% ENVDD

CONN@
PVT-029 ACES_50398-05071-001
Change 0.01 ohm to short pad 50 55
Change 0 ohm to short pad eDP_TXN_P1_CONN 50 G5
49 54
C175 2 0.1U_0201_10V6K eDP_AUXP_R eDP_AUXP_CONN eDP_TXP_P1_CONN 49 G4 53
5 eDP_AUXP 1 1 @ 2 48
R416 48 G3 52
0_0402_1% 47
eDP_TXN_P0_CONN 46 47 G2 51
LCD_POWER_20V C176 2 0.1U_0201_10V6K eDP_AUXN_R eDP_AUXN_CONN eDP_TXP_P0_CONN 46 G1
5 eDP_AUXN 1 1 @ 2 45

eDP BackLight Power 1 @ 2

R417 0_0402_1%
eDP_AUXP_CONN
eDP_AUXN_CONN
44
43
42
45
44
43
+INV_PWR_SRC 42
B+ R501 0_0603_5%~D 41
40 41
40
+LCDVDD 39
39
1 2 @ R484 1 2 0_0603_5%~D 38
R502 0_0603_5%~D 37 38
36 37
30 LCD_TST 36
+LCDVDD 35
Q33 5 EDP_HPD 35
34
SI3457BDV-T1-E3_TSOP6~D 34
11 EDP_ID0
1 @ 2 33
PVT-029 R433 33
0_0402_1% 32
D
Change 0.01 ohm to short pad 32

0.1U_0402_10V7K

33P_0402_50V8J
RF@C172
6 31
60mil 60mil
S

Change 0 ohm to short pad 31

10U_0402_6.3V6M

10U_0402_6.3V6M
4 5 @ @ 30
2 1 BL voltage : 33V. 51 LED_IFB8

1
30

C174

C182
2 29
Panel BL Power max : 3.6W 51 LED_IFB7 29

C167
1 51 LED_IFB6 28
1

28
per pin AWG36 0.75A
G

1 51 LED_IFB5 27

2
C231 R485 1 2 26 27
51 LED_IFB4
3

0.1U_0402_25V6K~D 0.1U_0402_25V6K~D 25 26
1M_0402_5%~D 51 LED_IFB3 25
24

10U_0603_25V6M
C 51 LED_IFB2 C
2 23 24
1 51 LED_IFB1
2

1 22 23
C232

C233

EN_INVPWR_R 21 22
+LED_AN 21
20
37.2V
2
1

2 20
19
19
@

18
R486 +LED_AN 18
17
+3VS_TS 17
100K_0402_5%~D 16
37.2V @ R464 1 2 0_0402_5% 15 16
2

@ R465 15
1 2 0_0402_5% 14
13 14
1

D 13

@EMC@ C190
@ R466 1 2 0_0402_5% 12
+3VS 12
2 Q32 11
30 EN_INVPWR 11

1U_1206_50V7

0.1U_0402_50V7K

0.1U_0402_50V7K

0.1U_0402_50V7K
G DII-DMN65D8LW-7 @ R467 1 2 0_0402_5% 10
1 1 1 1 10
S @ R468 1 2 0_0402_5% 9
3

C1038

C189

C188
8
R418 @ 0_0402_5% TS_RST#R 8
EN_INVPWR Pull down resistor on p.30 2 2 2 2 10,23,24,25,27,30,31,32,34,43PLT_RST#
1 2
TOUCH_SCREEN_PD#_R
7
7
R419 1 @ 2 0_0402_1% 6
11 TOUCH_SCREEN_PD# 6
R420 1 @ 2 0_0402_1% 5
8 I2C1_SDA_TS 5
R421 1 @ 2 0_0402_1% 4
8 I2C1_SCK_TS 4
3
5 I2C0_IRQ_TS 3
8 EDP_CAB_DET# 2
R432 TS_ID0_R 2
8 TS_ID0_D
1 @ 2 0_0402_1% 1
1
PVT-029 JEDP1
Change 0.01 ohm to short pad
Change 0 ohm to short pad

R495 1 2 0_0402_5% TS_RST#R

8 TS_RST#
BackLight PWM Control
Truth Table for EDP_ID/TS_ID0
D39
B
2 TS_RST#R B
5 PANEL_BKLEN
+3VS_TS
1
Touch EDP_ID0 TS_ID0
DISPOFF# 51 Controller Panel
1

30 PANEL_BKEN_EC 3
R61
TPK SHARP LOW LOW

EMC@ C191

EMC@ C196

0.1U_0402_10V7K
@EMC@ C193

TVNST52302AB0_SOT523-3
BAT54CW-7-F_SOT323-3 220K_0201_5%

0.1U_0201_10V6K
1 1 2

2
15P_0402_50V8J
Laibao SHARP LOW High
2

DI1 EMC@
2 2 1
HH BOE High LOW
D40

1
2
30 BIA_PWM_EC Reserved High High
1 INV_PWM 51
1

5 EDP_BIA_PWM 3 1
R67 @EMC@
BAT54CW-7-F_SOT323-3 4.7K_0201_5% MC1
680P_0402_50V7K
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P22-eDP, TS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 22 of 65
5 4 3 2 1
 5 4 3 2 1

D D

PVT-013
Remove co-lay L11 NGFF(SATA) +3.3VDX_SSD +3.3VDX_SSD

33P_0402_50V8J

4.7U_0402_6.3V6M

0.1U_0402_10V7K

4.7U_0402_6.3V6M

47P_0402_50V8J
C140
PVT-030
Change 0 ohm to short pad 1 1 2 1 1

C139

C143

C141

C142
JNGFF2
R60 1 @ 2 0_0402_1% CLK_PCIE_SSD_R 1 2 @
10 CLK_PCIE_SSD GND 3.3V 2 2 1 2 2
3 4
5 GND 3.3V 6
R59 CLK_PCIE_SSD#_R PERn3 NC
10 CLK_PCIE_SSD#
1 @ 2 0_0402_1% 7 8 T60 @
PERp3 NC
9 10 RF@
11 GND DAS/DSS#/LED# 12
13 PETn3 3.3V 14
PETp3 3.3V
15 16
GND 3.3V
17 18
PERn2 3.3V
C 19 20 If system didn't support DEVSLP, set Device Sleep C
PERp2 NC
21 22
23
GND NC
24
Signal high and keep (from power on), device will ignore.
25 PETn2 NC 26 If system support DEVSLP, set Device Sleep Signal low
PETp2 NC (from power on) device, device will support DEVSLP
27 28
GND NC
9 PCIE_PRX_SSDTX_N7
29
PERn1 NC
30 function as below:
31 32 Device Sleep Signal H: SSD enter sleep model.
9 PCIE_PRX_SSDTX_P7 PERp1 NC
33 34 T32 @
CD42 1 2 0.22U_0402_10V6K PCIE_PTX_SSDRX_N7_C 35
GND NC
36
Device Sleep Signal L: SSD exit sleep model.
9 PCIE_PTX_SSDRX_N7 PCIE_PTX_SSDRX_P7_C PETn1 NC
CD43 1 2 0.22U_0402_10V6K 37 38
PCIe SSD 9 PCIE_PTX_SSDRX_P7
39
PETp1 DEVSLP
40
SSD_DEVSLP 9
GND NC
41 42
9 SATA_PRX_SSDTX_P8 PERn0/SATA-B+ NC
43 44
9 SATA_PRX_SSDTX_N8 PERp0/SATA-B- NC
45 46
SATA SSD CD44 1 2 0.22U_0402_10V6K SATA_PTX_SSDRX_N8_C 47 GND NC 48
9 SATA_PTX_SSDRX_N8 SATA_PTX_SSDRX_P8_C PETn0/SATA-A- NC
CD45 1 2 0.22U_0402_10V6K 49 50
9 SATA_PTX_SSDRX_P8 PETp0/SATA-A+ PERST#/NC PLT_RST# 10,22,24,25,27,30,31,32,34,43
51 52 CLKREQ_PCIE#3 10
CLK_PCIE_SSD#_R GND CLKREQ#/NC
53 54 PEW ake# R57 1 @ 2 0_0402_5% PCIE_WAKE# 24,25,30
CLK_PCIE_SSD_R REFCLKn PEWAKE#/NC R64
55 56 1 2 10K_0402_5% +3.3VDX_SSD
57 REFCLKp NC 58
GND NC

Solt M & Key M

PVT-030
Change 0 ohm to short pad Platform Pin-out
67 68 R65 1 @ 2 0_0402_5%
SSD_PEDET NC SUSCLK SUSCLK 10,24,25
R66 1 @ 2 0_0402_1% 69 70
9 m2280_PCIE_SATA# PEDET (NC-PCIe/GND-SATA) 3.3V
71 72 +3.3VDX_SSD
GND 3.3V
73 74
B 75 GND 3.3V B
m2280_PCIE_SATA# : GND
1
SATA - Low 77
GND GND
76
C32
PCIe - High 0.1U_0402_10V7K
LOTES_APCI0146-P004A 2 @EMC@
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P23-SATA / PCIE SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 23 of 65
5 4 3 2 1
 A B C D E

Wireless LAN

JNGFF1
0R
WWAN closed to pin 2, 4 closed to pin 72, 74
1 WWAN_WAKE#_R 1
+3VS_WLAN +3VS_WLAN

PCIE_WAKE#

10U_0402_6.3V6M
PCIE_WAKE#

WWAN_WAKE#

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

0.1U_0201_10V6K
C156

15P_0402_50V8J

10U_0402_6.3V6M

10U_0402_6.3V6M

0.1U_0201_10V6K
C150

15P_0402_50V8J
+3VALW
1 1 1 1

1
C148

C154

C153

C155

C147

C146
PCH

C152

C149
+3V_5105

2
PH 2 2 2 2
1k

PH RF@ RF@
100k
JNGFF2
PCH_PCIE_WAKE# EC SSD
@0R
PCIE_WAKE#
PCIE_WAKE# PCIE_WAKE#
+3VS_WLAN
JNGFF3
1 2
USB20_P7_R 3 GND 3.3VAUX 4
USB20_N7_R 5 USB_D+ 3.3VAUX 6
7 USB_D- LED1#
GND

Solt A & Key A

Platform Pin-out
JNGFF3 17
19 MLDIR Sense LED2#
16
18
WLAN 21
23
DP_ML3N
DP_ML3P
GND
DP_AUXN
20
22
25 GND DP_AUXP 24
27 DP_ML2N GND 26
2 2
PCIE_WAKE# PCIE_WAKE# 29 DP_ML2P DP_ML1N 28
31 GND DP_ML1P 30
33 DP_HPD GND 32
CV9 1 2 .1U_0402_16V7K PCIE_PTX_WLANRX_P5_C 35 GND DP_ML0N 34
9 PCIE_PTX_WLANRX_P5 PCIE_PTX_WLANRX_N5_C PETP0 DP_ML0P
CV10 1 2 .1U_0402_16V7K 37 36
9 PCIE_PTX_WLANRX_N5 PETN0 GND
39 38 CL_RST# 7
GND CLink RESET
41 40 CL_DATA 7
9 PCIE_PRX_WLANTX_P5 PERP0 CLink DATA
43 42 CL_CLK 7
9 PCIE_PRX_WLANTX_N5 PERN0 CLink CLK
45 44 PVT-031
GND COEX3 Change 0 ohm to short pad NGFF_COEX3 25
CLK1_PCIE_WLAN_R 47 46
REFCLKP0 COEX2 NGFF_COEX2 25
CLK1_PCIE_WLAN#_R 49 48
REFCLKN0 COEX1 NGFF_COEX1 25
51 50 R161 1 @ 2 0_0402_1%
GND SUSCLK WLAN_RST#_Q SUSCLK 10,23,25
10 CLKREQ_PCIE#1 53 52
55 CLKQ0# PERST0# 54 BT_OFF#_R C151 1 2 0.1U_0201_10V6K
23,25,30 PCIE_WAKE# PEWAKE0# W_DISABLE2# WL_OFF#_R
57 56 @EMC@
59 GND W_DISABLE1# 58
PVT-014 PETP1 I2C_DATA
61 60
Remove co-lay R166, R165, R164, R163 63 PETN1 I2C_CLK 62
65 GND I2C IRQ 64
67 PERP1 GPIO0 NFC RESET# 66 WLAN_RST#_Q
69 PERN1 PERST1# 68
HCM1012GH900BP_4P 71 GND CLKREQ1# 70 PCIE_WAKE#
4 3 USB20_P7_R 73 REFCLKP1 PEWAKE1# 72
9 USB20_P7 REFCLKN1 3.3VAUX +3VS_WLAN
75 74
GND 3.3VAUX
1 2 USB20_N7_R 77 76
9 USB20_N7 GND GND
ML8 EMC@
LOTES_APCI0145-P004A
CONN@

+3VS_WLAN

+3VS_WLAN

1
@ R156
3 3
100K_0402_5%

PCB footprint

2
5

U23 D91 RB520SM-30T2R_EMD2-2

1 BT_OFF#_R 2 1
P

10,22,23,25,27,30,31,32,34,43PLT_RST# B BT_RADIO_DIS# 30
4 WLAN_RST#_Q
2 Y RB751S40T1G_SOD523-2
5 WLAN_RST#
1

1
A
G

@
TC7SH08FU_SSOP5 R160 R158
3

100K_0201_5% 220K_0201_5%
2

2
PVT-014
Remove co-lay R166, R165, R164, R163
+3VS_WLAN

1
HCM1012GH900BP_4P
4 3 CLK1_PCIE_WLAN_R @ R157
10 CLK1_PCIE_WLAN
100K_0402_5%

1 2 CLK1_PCIE_WLAN#_R
10 CLK1_PCIE_WLAN#

2
PCB footprint
L24 EMC@ D92 RB520SM-30T2R_EMD2-2
WL_OFF#_R 2 1 WLAN_WIGIG60GHZ_DIS# 30

RB751S40T1G_SOD523-2

1
@
R159
220K_0201_5%

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P24-WLAN / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 24 of 65
A B C D E
 5 4 3 2 1

PVT-032
Change 0 ohm to short pad

+1.8VS_AUDIO +1.8VS

R455 1 @ 2 0_0402_1%

+1.8VS +1.8VS
+3VS_WWAN +3VS_WWAN +3VS_WWAN +3VS_WWAN
USB3#2
U4 Common PCIe/USB3.0

1
D D

PCIe#12 USB3/PCIe MUX Choke R35

@RF@ C100

100U_A1_6.3VM_R70M

100U_A1_6.3VM_R70M
10K_0201_1%
1 1

2
(SATA2)

22U_0603_6.3V6M

0.1U_0201_10V6K
C105

33P_0201_50V8J
RF@C106

@RF@ C104

22U_0603_6.3V6M

0.1U_0201_10V6K
C101

33P_0201_50V8J
RF@C102

47P_0402_50V8J

G
Q29
1 1 1 1 1 1 1 1

C103

47P_0402_50V8J

C99

C97

C98
+ +

2
GNSS_OFF#_R 3 1 GNSS_OFF# 5

D
PCH JNGFF1 2 2 2 2 2 2 2 2 2 2 DII-DMN65D8LW-7

PCIe#11 PCIe/SATA
closed to pin 64,
closed to pin 2, 66
4
USB3#2 Common USB2.0
Choke D94
2 1 WWAN_RADIO_DIS# 30
+1.8VS
WWAN_RADIO_DIS#_R RB751S40T1G_SOD523-2
D95 PCB footprint

1
2 1 RB520SM-30T2R_EMD2-2
WWAN_OFF# 11
R33
10K_0201_1% RB751S40T1G_SOD523-2
PVT-032 +3VS PCB footprint
Change 0 ohm to short pad D111 RB520SM-30T2R_EMD2-2
module with internal PU

2
R456 1 2 SAR_DPR_R
30 SAR_DPR#

PCIe/USB 3.0 Mux +3VS_U4 1 @ 2

RB751S40T1G_SOD523-2
UIM_DET# R122 1 @ 2 0_0402_1%
UIM_DET 26

0.1U_0201_10V6K

10U_0402_6.3V6M

10U_0402_6.3V6M
@ 0_0402_1% PCB footprint PVT-032
1

1
RB520SM-30T2R_EMD2-2 Change 0 ohm to short pad

C28

C227

C228
+3VS_WWAN +1.8VS

2
2

U4

1
C
+3VS_WWAN C
USB3TP2 C217 1 2 0.1U_0201_10V6K USB3TP2_C 19 1 R123 @ R479
9 USB3TP2 B0+ VDD
USB3TN2 C215 1 2 0.1U_0201_10V6K USB3TN2_C 18 6 JNGFF1 47K_0402_5%
USB 3.0 #2 9 USB3TN2
USB3RP2 17 B0- VDD 10 1 2
100K_0402_5%
9 USB3RP2 B1+ VDD 30 NGFF_CONFIG_3 CONFIG_3 3.3V
9 USB3RN2 USB3RN2 16 3 4 @ R125

2
B1- GND 3.3V WWAN_PWR_OFF#_R
5 6 1 2
USB20_P4_CONN GND 1.8V FULL_CARD_PWR_OFF# WWAN_RADIO_DIS#_R WWAN_PWR_OFF# 5
9 PCIE_PTX_WWANRX_P12
C31 1 2 0.22U_0402_10V6KPCIE_PTX_WWANRX_P12_C15 3 PCIE_PTX_WRX_UT_P12_SW 7 8
C0+ A0+ USB_D+ 3.3V W_DISABLE#
C30 1 2 0.22U_0402_10V6KPCIE_PTX_WWANRX_N12_C14 4 PCIE_PTX_WRX_UT_N12_SW USB20_N4_CONN 9 10 0_0201_5%
9 PCIE_PTX_WWANRX_N12 C0- A0- PCIE_PRX_WTX_UR_P12_SW USB_D- 3.3V GPIO_9/DAS/DSS#/LED#1 1
13 7 11 C108
PCIE #12 9 PCIE_PRX_WWANTX_P12
12 C1+ A1+ 8 PCIE_PRX_WTX_UR_N12_SW GND 0.1U_0201_10V6K
9 PCIE_PRX_WWANTX_N12 C1- A1-
9 5 PVT-032
Solt B & Key B 2
25,30 NGFF_CONFIG_1 SEL GND Change 0 ohm to short pad
11 20 FULL_CARD_PWR_OFF#
GND 1.8V GPIO_5
2 20 21 22 GPIO control pop R125 R479 depop R123
PD GND 30 NGFF_CONFIG_0 CONFIG_0 1.8V GPIO_6
R38 1 @ 2 0_0402_1% WWAN_WAKE#_R 23 24 no use depop R125 R479 pop R123
SEL=0 A to B 21
30 WWAN_WAKE#
SAR_DPR_R 25
GPIO_11 1.8V 1.8V GPIO_7
26 GNSS_OFF#_R
SEL=1 A to C PGND 27 DPR 1.8V 1.8V GPIO_10
28
PI3PCIE3212ZBEX_TQFN20_2P5X4P5 PCIE_PRX_WTX_UR_N12_SW_CONN GND 1.8V GPIO_8
29 30 UIM_RESET 26
PCIE_PRX_WTX_UR_P12_SW_CONN 31 PERN1/USB3RXN/SSIC-RXN UIM-RESET 32
PERp1/USB3RxP/SSIC-RxP UIM-CLK UIM_CLK 26
33 34 UIM_DATA 26
PCIE_PTX_WRX_UT_N12_SW_CONN 35 GND UIM-DATA1.8V/3.3V

36 PVT-032
PETn1/USB3TxN/SSIC-TxN UIM-PWR +SIM_PWR Change 0 ohm to short pad
PCIE_PTX_WRX_UT_P12_SW_CONN 37 38 R489 1 2 0_0201_5%
PETp1/USB3TxP/SSIC-TxP DEVSLP GNSS_SCL WWAN_DEVSLP 9
PVT-015 39 40 @ R219 1 @ 2 0_0402_1%
Remove co-lay R39, R40, R41, R42, R43, R44, R45, R46 41 GND 1.8V GPIO_0
42
9 PCIE_PRX_WWANTX_N11 PERn0/SATA_B+ 1.8V GPIO_1 GNSS_IRQ
9 PCIE_PRX_WWANTX_P11 43 44
PERp0/SATA_B- 1.8V GPIO_2 GNSS_IRQ 5
45 46
PCIE_PTX_WWANRX_N11_C GND 1.8V (26MHZ) GPIO_3
CV2 1 2 0.22U_0402_10V6K 47 48
9 PCIE_PTX_WWANRX_N11 PETn0/SATA_A- 1.8V GPIO_4
USB3TP ML1 EMC@ CV1 1 2 0.22U_0402_10V6K PCIE_PTX_WWANRX_P11_C 49 50
9 PCIE_PTX_WWANRX_P11 PETp0/SATA_A+ PERST# PLT_RST# 10,22,23,24,27,30,31,32,34,43
PCIE_PTX_WRX_UT_P12_SW 4 3 PCIE_PTX_WRX_UT_P12_SW_CONN 51 52
CLK2_PCIE_WWAN#_R GND CLKREQ# CLKREQ_PCIE#2 10
53 54
CLK2_PCIE_WWAN_R REFCLKN PEWAKE# PCIE_WAKE# 23,24,30
USB3TN 55 56
PCIE_PTX_WRX_UT_N12_SW 1 2 PCIE_PTX_WRX_UT_N12_SW_CONN 57 REFCLKP NC 58
GND NC R492
59 60 1 2 0_0201_5% NGFF_COEX3 24
41
ANTCTRL0 ANTCTL0 1.8V 1.8V COEX3
CMMI21T-670Y-N_4P 61 62 R493 1 @ 2 0_0201_5%
41
ANTCTRL1 ANTCTL1 1.8V 1.8V COEX2 NGFF_COEX2 24
63 64 R494 1 @ 2 0_0201_5%
T25 @ ANTCTL2 1.8V 1.8V COEX1 NGFF_COEX1 24
65 66 UIM_DET# @
T24 @ ANTCTL3 1.8V PU.1.8V SIM DETECT
SUSCLK_L
67 (low active) 68 R124 1 2 0_0201_5%
T20 @ RESET# 1.8V SUSCLK SUSCLK 10,23,24
25,30 NGFF_CONFIG_1 69 70 @
B
71 CONFIG_1 3.3V 72 B
GND 3.3V +3VS_WWAN 1
PVT-015 73 74
Remove co-lay R39, R40, R41, R42, R43, R44, R45, R46 GND 3.3V C107
30 NGFF_CONFIG_2 75
CONFIG_2
0.1U_0402_10V7K
2 @EMC@
77 76
USB3RP CMMI21T-670Y-N_4P GND GND
PCIE_PRX_WTX_UR_P12_SW 4 3 PCIE_PRX_WTX_UR_P12_SW_CONN
LOTES_APCI0144-P007A
USB3RN CONN@
PCIE_PRX_WTX_UR_N12_SW 1 2 PCIE_PRX_WTX_UR_N12_SW_CONN

ML2 EMC@

PVT-015
Remove co-lay R39, R40, R41, R42, R43, R44, R45, R46

DLW21HN900HQ2L_4P
4 3 CLK2_PCIE_WWAN_R
10 CLK2_PCIE_WWAN 4 3

1 2 CLK2_PCIE_WWAN#_R
10 CLK2_PCIE_WWAN# 1 2
EMC@
L9

A PVT-015 A
Remove co-lay R39, R40, R41, R42, R43, R44, R45, R46

DLW21HN900HQ2L_4P
1 2 USB20_P4_CONN
9 USB20_P4 1 2 Enable PCIe and USB 3.1 Gen1 on M.2 Card Key B
4 3 USB20_N4_CONN
spec. ECN updated on 2017/02/10
9 USB20_N4 4 3
L10 EMC@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P25-WWAN / 2nd SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 25 of 65
5 4 3 2 1
 5 4 3 2 1

D D

uSIM CONN +SIM_PWR

+SIM_PWR ESD
JSIM1 UIM_RESET UIM_DATA
UIM_CLK

@RF@ R154
7 1
UIM_DET 8 GND VCC 2 UIM_RESET
25 UIM_DET DETECT RESET UIM_RESET 25
UIM_CLK

15K_0402_1%
3
CLOCK UIM_CLK 25

1
9 UIM_CLK UIM_DET
10 GND1 4 RF@C137
GND2 GND

ESD207-B1-02EL_TSLP-2-19-2

ESD207-B1-02EL_TSLP-2-19-2

ESD207-B1-02EL_TSLP-2-19-2

ESD207-B1-02EL_TSLP-2-19-2
11 5 47P_0402_50V8J~D

1
GND3 VPP

2
UIM_DATA

2.2P_0402_50V8C~D
C136 EMC@

D64

D65

D63

D62
6 1
IO UIM_DATA 25

2
4.7U_0402_6.3V6M

0.1U_0402_10V7K
@RF@ C144

2.2P_0402_50V8C~D
C138 EMC@

2.2P_0402_50V8C~D
C134 EMC@
1 1
UIM_DATA

33P_0402_50V8J
1 1 2

RF@C135

EMC@

EMC@

EMC@

EMC@

2.2P_0402_50V8C~D
C133 EMC@
JAE_SF56S006V4A
1

2
C145
CONN@

1
RF@ R155 2 2
2 2 51_0402_5%

1
2

2
C C

Normal Close

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P26-SIM Card CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 26 of 65
5 4 3 2 1
 5 4 3 2 1

PVT-051

Card Reader For verify card reader sequence to add load switch

+1.8V_PGPP
1)Placing the RTS5242 chip and flash card socket locate to suit trace routing for SI / EMI / ESD.
+1.8V_PGPP +1.8VS_CR
2)Keep bulk and de-coupling capacitors as close as possible to the RTS5242 chip and flash card socket.
■ Bulk capacitor for Card_3V3 place closed to flash card socket. PVT-053
Layout request change short to 0 ohm
■ Bulk capacitor for 3V3_IN / 3V3aux / DV12S place closed to RTS5242 chip. U4255
3)Keep damping resistor (ex, for SD CLK / MS CLK) as close as possible to the RTS5242 chip. 1 7 +1.8VS_CR_R 1 @ 2
4)Keep these capacitors for SD card / MS card signals as close as possible to flash card socket. 2 VIN VOUT 8 R5781 0_0603_5%
VIN VOUT C1137
D D
RUN_ON_P 3 6 1 2
30,32,44,45,55,56 RUN_ON_P ON CT
+3VS_CR +3VS_CR 2200P_0402_25V7K~D
4 +1.8VS_CR
+5VALW VBIAS
5
C1136 GND 9
GND 1

10U_0402_6.3V6M
2 1

0.1U_0402_10V7K

4.7U_0402_6.3V6M

0.1U_0402_10V7K
C1138
2 1 2 1U_0402_6.3V6K~D TPS22967DSGR_SON8_2X2 0.1U_0402_10V7K

1
2

CR7
RUN_ON_P

CR20

CR21

CR8
@ R5780 1 2 100K_0402_5%~D

2
1 2 1

27
11
UR1
+SD_VDD1

3V3aux
3V3_IN
1 12
10,22,23,24,25,30,31,32,34,43PLT_RST# PERST# CARD_3V3 DV33_18
2 18 1U_0402_6.3V6K 2 1EMC@ CR15
10 CLKREQ_PCIE#5 CLK_REQ# DV33_18
CLK_PCIE_MMI_R 5
CLK_PCIE_MMI#_R REFCLKP SD_RCLK_M_L RR2 SD_RCLK_M
6 15 1 2 0_0402_5%
REFCLKN SP1 SD_RCLK_P_L RR3 SD_RCLK_P

2.2P_0402_50V8C~D
16 1 2 0_0402_5%
CR22 PCIE_PTX_CARDRX_P9_C RTS5242 SP2 SD_CLK_L SD_CLK
9 PCIE_PTX_CARDRX_P9 1 2 0.1U_0402_10V7K 3 17 RR4 1 2 0_0402_5%
CR23 PCIE_PTX_CARDRX_N9_C HSIP SP3 SD_CMD_L SD_CMD
9 PCIE_PTX_CARDRX_N9 1 2 0.1U_0402_10V7K 4 19 RR6 1 2 0_0402_5% 1
PCIE_PRX_CARDTX_P9_C HSIN SP4 SD_D3_L SD_D3

CR13 EMC@
C CR14 1 2 0.1U_0402_10V7K 7 20 RR8 1 2 0_0402_5% C
9 PCIE_PRX_CARDTX_P9 HSOP SP5
CR12 1 2 0.1U_0402_10V7K PCIE_PRX_CARDTX_N9_C 8 21 SD_D2_L RR9 1 2 0_0402_5% SD_D2
9 PCIE_PRX_CARDTX_N9 HSON SP6
29 SP7_SDWP
SP7 2

2.2P_0402_50V8C~D

2.2P_0402_50V8C~D

2.2P_0402_50V8C~D

2.2P_0402_50V8C~D

2.2P_0402_50V8C~D
@ RR12 1 2 0_0402_5% PVT-033
5 MEDIACARD_IRQ# Change 0 ohm to short pad 1 1 1 1 1
CD_WAKE#

CR18 @EMC@

CR17 @EMC@

CR16 @EMC@

CR11 @EMC@

CR10 @EMC@
+3VS_CR 2 1 32
WAKE# PVT-052
RR11 10K_0402_5% 31 Reserve 0 ohm for debug
SD_CD# MS_INS#
Support Runtime D3 mode => DE-POP RR11 Close to UR1 30
SD_CD# 2 2 2 2 2
No Support Runtime D3 mode => POP RR11 (pull high) 22 SD_LN1_P
SD_LN1_P 23 SD_LN1_M
CR9 SD_LN1_M
1 2 0.1U_0402_10V7K DV12S 10
AV12 SD_LN0_P
14 26
DV12S SD_LN0_P 25 SD_LN0_M
SD_LN0_M
0.1U_0402_10V7K

4.7U_0402_6.3V6M

+SD_VDD2 13
SD_VDD2 24 SD_REG2
2 1

E-PAD
SDREG2
CR5

1 2 RREF 9 28 10K_0402_5% 2 1 RR10 +3VS_CR

RREF GPIO
CR6

RR1 6.2K_0402_1%

2
1 2 Close to UR1 RTS5242-GR_QFN32_4X4-S EMC@ CR19

33
1U_0402_6.3V6K

1
If GPIO not use for LED function,
must be pull-high (Layout guide)

B B
PVT-016
Remove co-lay L29
CONN@ JCR1

PVT-033 +SD_VDD1 Close to JCR1 SD_D2 1

Change 0 ohm to short pad SD_D3 DAT2
2
SD_CMD CD/DAT3
3
RR7 CLK_PCIE_MMI_R CMD
10 CLK_PCIE_MMI 1 @ 2 0_0402_1% 4
SD_CLK VDD1
5
CLK

10U_0402_6.3V6M

0.1U_0402_10V7K
6
RR5 CLK_PCIE_MMI#_R SD_RCLK_P VSS
10 CLK_PCIE_MMI# 1 @ 2 0_0402_1% 2 7
DAT0/RCLK+

1
+SD_VDD2 SD_RCLK_M

CR1
8
SD_CD# DAT1/RCLK-

CR2
9
CD
13

2
1 14 VDD2
SWIO

4.7U_0402_6.3V6M

0.1U_0402_10V7K
15
SD_LN0_P VSS
For GPIO control SD_WP QR1 1 1
SD_LN0_M
16
D0+

CR4
17
DMN2400UFB4-7_DFN1006H4-3 D0-

CR3
18 10
SD_LN1_M 19 VSS GND 11
SP7_SDW P 1 3 2 2 SD_LN1_P 20 D1- GND 12
D

D1+ GND
21 22
VSS GND
23
GND
G
2

T-SOL_158-1000902614
8 HOST_SD_WP#
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P27-Card Reader(RT5242)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 27 of 65
5 4 3 2 1
 5 4 3 2 1

RA8 RA27 RA28 CA14

1 2 1 2 1 2 1 2 MONO_IN
30 BEEP

0.22U_0402_16V7K

0.22U_0402_16V7K

0.22U_0402_16V7K
0_0201_5% 0.1U_0201_10V6K
+AVDD1 +5VS_AUDIO 1K_0201_5% 1K_0201_5%
@
1 1 1

CA46

CA47

CA48
LA1 1 2 BLM21PG600SN1D_2P
2 2 2

1 LINE1-L 29
CA19
RA9 LINE1-R 29
2 10U_0603_6.3V6M 1 2
11 SPKR

1
D AGND D
1K_0201_5% 1
AGND RA30 @
1K_0201_5% CA13

CA15 10U_0603_6.3V6M
SLEEVE 29
100P_0201_25V7K
2
Beep sound Close to UA1 Pin32 RING2 29

MONO_IN
MIC2-VREFO-R 29
DMIC_CLK12 2 Place near UA1 pin25/26
MIC2-VREFO-L 29
DMIC_DATA12
DMIC_DATA34 HPOUT-L HPOUT-R HPOUT-L
1 15mil HPOUT-L 29
+AVDD1
15mil HPOUT-R HPOUT-R 29
22P_0201_25V8

22P_0201_25V8

22P_0201_25V8

330P_0402_50V8J

330P_0402_50V8J
1 1 1 1 1
CA41 @EMC@

CA34 @EMC@

CA35 @EMC@

CA41 close @ @

CA9

CA11
with UA1 Pin6
150 mA UA1

36

35

34

33

32

31

30

29

28

27

26

25
2 2 2 CA16 2 1 2 2
AGND

LINE2-L

LINE1-L

RING2

MIC2-VREFO-L

HP-OUT-L
LINE2-R

LINE1-R

MIC2-VREFO-R

HP-OUT-R
PCBEEP

MIC2-CAP

SLEEVE
10U_0603_6.3V6M
0.1U_0201_10V6K

0.1U_0201_10V6K
CA23
1 1 CA17 2 1
AGND

CA22
CA34 close with DMIC12 AGND AGND
2.2U_0402_6.3V6M
CA35 close with DMIC34
2 2 37 24 CA18 1 2 1U_0603_10V6K
AGND AVSS1 CPVEE AGND
RA10 1 2
100K_0201_5% 38 23 PVT-034 +1.8VS_AUDIO
VREF CBN Change 0 ohm to short pad
CA20 2 1 39 22 CA21 1 2 1U_0603_10V6K
AGND LDO1-CAP CBP RA11
AGND 150 mA
10U_0603_6.3V6M 40 21 2 @ 1
Analog AVDD1 CPVDD

10U_0603_6.3V6M
LA2 1 2 0_0603_5% 41 20 0_0402_1%
Digital +5VS_AUDIO PVDD1 HP-OUT2-R

0.1U_0201_10V6K
CA24
30mil AGND 1 1

10U_0603_6.3V6M

CA29
42 19
29 SPK_-OUT-L+ SPK-L+ HP-OUT2-L

0.1U_0201_10V6K
CA26
1 1 CA27 1 2 0.1U_0201_10V6K

CA25
43 18
29 SPK_-OUT-L- SPK-L- AVSS2 2 2
C C
44 17 CA28 1 2 10U_0402_6.3V6M
2 2 29 SPK_-OUT-R- SPK-R- LDO2-CAP AGND
45 16
29 SPK_-OUT-R+ SPK-R+ AVDD2

SPDIFO/GPIO2-DMIC-DATA-34
CA25, CA26 close to UA1 pin41 46 15 4/19 AGND
PVDD2 LINE1-VREFO-R-E/MONO update CA28 from 0603 to 0402
30mil 47 14
5VSTB/AUX MODE LINE1-VREFO-L-E Analog
LA3 1 2 0_0603_5% HP2 48 13 Digital

GPIO0/DMIC-DATA
+5VS_AUDIO

2
HP2/LINE2 JD LDO3-CAP

@ CA30

GPIO1/DMIC-CLK
0.1U_0201_10V6K
@ RA31

DC DET/EAPD
2 1

HP1/LINE1 JD
2

10U_0603_6.3V6M
0_0402_5%

SDATA-OUT
PVT-034 CA31 RA12

SDATA-IN
1

DVDD-IO
Change 0 ohm to short pad

CA32
10U_0603_10V6M 0_0402_5%
Codec
1
1 2

DVDD

SYNC
RA23 1

BCLK
@ 2 0_0402_1% 49

PDB
PGND

1
2
CA31,CA30 close to UA1 pin46
+5VS_AUDIO Analog

10

11

12
RA22 1 @ 2 0_0402_1% ALC3253-VA3-CG_MQFN48_6X6
+DVDD Pin14~40

DMIC_CLK_R
+RTCBATT
+DVDD +DVDDIO

RA25 1 RA19 1 2 100K_0201_5%

Add Moat between Analog and Digital shape
@ 2 0_0402_1% 1 2 HP2
RA40 100K_0201_5% RA15 2 1 100K_0201_5%
Moat
RA13 2 100K_0402_1% JACK_PLUG# Digital

HDA_BLK_L

HDA_SDI0_L
+DVDD 1
1 Pin1~13, 41~48
RA14 1 2 200K_0402_1% CA40
29 HP_PLUG#
0.1U_0402_10V7K
GND AGND check divided voltage meet HP1 2
DMIC_DATA34 HDA_SDOUT 11
33 DMIC_DATA34 DMIC_DATA12 RA17 1 2 33_0402_5% HDA_SDI0 11
CODEC_MUTE#
RA29 1 2 DMIC_CLK12 RA24 1 2 22_0402_5%
+3VS_AUDIO HDA_SYNC 11
B DMIC_CLK34 RA32 1 B
2 22_0402_5% RA16 1 2 0_0402_5%
0_0402_5% 33 DMIC_CLK34 HDA_BLK 11

DMIC_DATA34
1
DMIC_DATA12
@ RA36 DMIC_CLK34 @ CA37 +DVDD
1 2
20mA 10mil 22P_0402_50V8G
+1.8VS_AUDIO +DVDD
1

1
2
33P_0402_50V8J
@EMC@ C73

33P_0402_50V8J
@EMC@ C74

33P_0402_50V8J
@EMC@ C83
2.2U_0402_6.3V6M

0.1U_0201_10V6K

0_0402_5% 1 1

1
+3V_5105
CA39

CA33

2 RA33
10K_0402_5%
2 2

2
G
Q22
For EMI +DVDD +DVDD +DVDD
+DVDD PVT-034 PVT-034 CODEC_MUTE# 3 1
Change 0 ohm to short pad Change 0 ohm to short pad NB_MUTE# 30

D
MIC1 MIC2
CA5 DII-DMN65D8LW-7
1 1

1
RA26 1 2 RA41 1 @ 2 0_0402_1% 1 5 RA43 1 2 0_0402_1%
1 @ 5 0.1U_0201_10V6K
+3VS_AUDIO VDD GND
CA39,CA33 close 2 6 2 VDD GND 6 @
DMIC_CLK12 3 LRSEL GND 7 CA1 DMIC_CLK12 3 LRSEL GND 7 RA21
0_0402_5% with UA1 Pin4 TC3
DMIC_DATA12 4 CLK GND 8 2 0.1U_0201_10V6K DMIC_DATA12 4 CLK GND 8 2 1K_0201_5%
TC2 DAT GND DAT GND

2
SPK0641HT4H-1-7_8P SPK0641HT4H-1-7_8P
DMIC@ DMIC@
@ RA18
1 2
10mA 10mil
+1.5VS_AUDIO +DVDDIO
2.2U_0402_6.3V6M

0.1U_0201_10V6K

0_0402_5% 1 1
CA38

CA36

+DVDD +DVDD +DVDD

PVT-034
Change 0 ohm to short pad
2 2 MIC3
CA2 CA6
1 1
RA42 1 @ 2 0_0402_1% 1 5 0.1U_0201_10V6K 0.1U_0201_10V6K
2 VDD GND 6
DMIC_CLK34 LRSEL GND
place near JWFC1
3 7
A
DMIC_DATA34 4 CLK GND 8 2 MIC4 on WF-CAM Module 2
A

DAT GND
For EMI SPK0641HT4H-1-7_8P
DMIC@

CA36,CA38 close
with UA1 Pin12

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P28-Audio Codec ALC3253
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 28 of 65
5 4 3 2 1
 5 4 3 2 1

Int. Speaker Conn.

40mil = For 4ohm 3W Speaker
+3V_PRIM

D D

RA39
EMC@ LA8 1 2 BLM15PX181SN1D_2P SPK_L+ SPK_L+ SPK_ID 2 1
28 SPK_-OUT-L+ SPK_L- SPK_L-
28 SPK_-OUT-L- EMC@ LA7 1 2 BLM15PX181SN1D_2P
10K_0402_5%

TVNST52302AB0_SOT523-3
3

2
1000P_0402_50V7K~D
CA44

1000P_0402_50V7K~D
CA45

DA9
1 1

JSPK

@EMC@

@EMC@

EMC@
2 2 SPK_L+ 1

1
SPK_L- 2 1
SPK_R+ 3 2
SPK_R- 4 3
RA38 2 4
11 SPK_ID
@ 1 0_0402_1% 5 7
6 5 G1 8
PVT-035 6 G2

Int. Speaker Conn. Change 0 ohm to short pad

ACES_50376-00601-001
CONN@

40mil = For 4ohm 3W Speaker

EMC@ LA6 1 2 BLM15PX181SN1D_2P SPK_R+ SPK_R+
28 SPK_-OUT-R+ SPK_R- SPK_R-
28 SPK_-OUT-R-
EMC@ LA5 1 2 BLM15PX181SN1D_2P

TVNST52302AB0_SOT523-3
SPK_ID Speaker

2
1000P_0402_50V7K~D
CA42

1000P_0402_50V7K~D
CA43

DA8
1 1 High Main Soure

@EMC@

@EMC@

EMC@
2 2 Low 2nd Soure

1
C C

Universal Audio Jack Universal Audio Jack CONN

EMC@ JP1
RA6 1 2 16.2_0402_1% HPOUT-L_L L19 1 2 BLM15AX700SN1D_2P HPOL_CONN PVT-035 RING2_CONN 3
28 HPOUT-L Change 0 ohm to short pad HPOL_CONN 1
RA3 1 2 16.2_0402_1% HPOUT-R_L L18 1 2 BLM15AX700SN1D_2P HPOR_CONN
28 HPOUT-R
EMC@ RA7 5
HP_PLUG#_R

ESD207-B1-02EL_TSLP-2-19-2

ESD207-B1-02EL_TSLP-2-19-2
28 HP_PLUG# 1 @ 2 6
HPOR_CONN
1000P_0201_50V7K

1000P_0201_50V7K
CA12 1 2 10U_0402_6.3V6M 2
28 LINE1-L

1
0_0201_5% SLEEVE_CONN 4
1

1
CA49

CA50
CA10 1 2 10U_0402_6.3V6M EMC@ EMC@ 7
28 LINE1-R GND

DA4

DA5

ESD207-B1-02EL_TSLP-2-19-2
8
use X5R for better performance GND
2

1
SINGA_2SJ3157-001111F

DA6
CONN@

EMC@
RA2 1 2 2.2K_0201_5%
28 MIC2-VREFO-L

2
B B
AGND AGND
RA1 1 2 2.2K_0201_5%
28 MIC2-VREFO-R
AGND

EMC@
40mil L12 1 2 BLM15PX330SN1D_2P SLEEVE_CONN
28 SLEEVE
EMC@
L15 1 2 BLM15PX330SN1D_2P RING2_CONN
28 RING2

ESD207-B1-02EL_TSLP-2-19-2

ESD207-B1-02EL_TSLP-2-19-2
40mil 1

1
1000P_0201_50V7K

1000P_0201_50V7K
1

1
CA8

CA7

DA3

DA1
2

EMC@

EMC@
2

AGND AGND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P29-SPK CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 29 of 65
5 4 3 2 1
 5 4 3 2 1

PVT-036
+LCDVDD Change 0 ohm to short pad
Change 0.01 ohm to short pad

PVT-011 +1.8VAPVT-047 +3V_5105

R C REV
Depop R411, LED4, Q16, R5766, LED5, Q356, SW3 for PVT build Layout request change short pad to 0 ohm PVT-002

1
RE195 Change Board ID to PVT
@ R411 1 2
+1.8VA_EC
240K 4700p

1
100_0402_5%
1
0_0603_5% RE50 1 2 75_0402_5% RE15 130K 4700p Pre-EVT1
CE54 +3VALW +3V_5105 H_PROCHOT# 11,50,53,57
4.3K_0402_5% R 62K 4700p EVT1

2
0.1U_0201_10V6K CE55 PVT-036
1

1
2 0.1U_0201_10V6K RE11 +RTCVCC_VBAT Change 0 ohm to short pad D
Change 0.01 ohm to short pad
33K 4700p DVT1

2
2
@ 1 @ 2 PROCHOT# 2 Q12
LED4 G DII-DMN65D8LW-7
BOARD_ID
2 RE19 +RTCVCC_EC 8.2K 4700p DVT2

10U_0603_6.3V6M

0.1U_0201_10V6K

1U_0402_6.3V6K

0.1U_0201_10V6K
HT-191UD5_AMBER Close to pin N5 0_0603_5% S

3
1
PVT-036 2 @ 1
1 1
4.3K 4700p PVT

1
Change 0 ohm to short pad

CE46

CE8

CE14

CE10
A
Change 0.01 ohm to short pad 1
0_0402_1%
1
C 2K 4700p

2
CE9
for Debug

2
2 2 CE18 4700P_0402_25V7K
2 1K 4700p
1
D@ +3V_5105 0.1U_0201_10V6K2
DII-DMN65D8LW-7
10,22,23,24,25,27,31,32,34,43
PLT_RST#
2
G Q16
+LCDVDD RE194 2 1 100_0402_1% UE3
S
BOARD_ID rise t i me i s meas ur ed fr o m5 %~68 %.
3

D PVT-011 F2 D
Depop R411, LED4, Q16, R5766, LED5, Q356, SW3 for PVT build +VSS_PLL GPIO033/RC_ID0 TYPEC_ID 32

@
CE47 2 1 22U_0603_6.3V6M A2 J10
VBAT GPIO034/RC_ID1/SPI0_CLK BOARD_ID CPU_ID 32

1
J13
@ R5766 2 1 B7 GPIO036/RC_ID2/SPI0_MISO E7 +3V_5105
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_USH_SMBDAT 36,37,43
100_0402_5% CE48 0.1U_0201_10V6K D7
GPIO004/SMB00_CLK/SPI0_MOSI UPD2_USH_SMBCLK 36,37,43 IMVP_SMBCLK
K2 RE270 1 2 2.2K_0201_5%
+3V_5105 VREF_ADC T58 IMVP_SMBDAT
G3 RUNPWROK @ PAD~D RE269 1 2 2.2K_0201_5%

2
+3.3V_EC_PLL
F1 GPIO057/VCC_PWRGD H5
PVT-036 VTR_PLL GPIO060/KBRST/48MHZ_OUT G11 HOST_DEBUG_TX PBAT_SMBCLK RE38 1 2 2.2K_0201_5%
GPIO104/UART0_TX PBAT_SMBDAT

2
Change 0 ohm to short pad @ H1 G12 RE35 1 2 2.2K_0201_5%
Change 0.01 ohm to short pad VTR_REG GPIO105/UART0_RX ME_FWP 11
LED5 B13
GPIO127/A20M/UART0_CTS# ME_SUS_PWR_ACK 10 UPD1_SMBINT#

0.1U_0201_10V6K
HT-191UD5_AMBER G8 F10 RE20 1 2 100K_0201_5%
PCH_DPWROK_P PCH_DPWROK 1 +3V_5105 VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# 35 UPD2_SMBINT#
10 PCH_DPWROK_P
1 @ 2 1 2 M9 RE52 1 2 100K_0201_5%
VTR2

CE49
RE248 0_0402_1% CE88 0.1U_0201_10V6K N5 N13

A
+1.8VA_EC VTR3 VTR3 +1.8V GPIO025/TIN0/nEM_INT/UART_CLK PCIE_WAKE# 23,24,25 CHG_MCP23008_SMBCLK
N12 RE110 1 2 2.2K_0201_5%
2 PCH_DPWROK GPIO026/TIN1 SIO_SLP_S4# 10,32 CHG_MCP23008_SMBDAT
F8 M11 RE111 1 2 2.2K_0201_5%

1
RUN_ON GPIO020 GPIO027/TIN2 SIO_SLP_A# 10
E8 H9
GPIO045 GPIO030/TIN3 T59
HOME_KEY# 43
9 SIO_EXT_WAKE#
M12 @ PAD~D
GPIO120

1
D@ C2 L9
IMVP_U42_U22#_LED DII-DMN65D8LW-7 24 BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5 UPD1_PS_SMBDAT
2 F9 M10 PVT-036 RE30 1 2 1K_0201_5%
+3V_5105 Q356 43,48 DET_L# GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 25 Change 0 ohm to short pad UPD1_PS_SMBCLK
G RE265 1 2 43K_0402_1% N4 N9 RE32 1 2 1K_0201_5%
10,32,44,54,55,56 SIO_SLP_SUS# GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 25 Change 0.01 ohm to short pad UPD2_USH_SMBDAT
3 S M8 RE68 1 2 1K_0201_5%
RESET_IN# 44 PCH_PWR_EN GPIO231 EC_SLP_S0IX#_EC
RE250 1 2 100K_0201_5% K8 C11 R5749 2 @ 1 EC_SLP_S0IX# UPD2_USH_SMBCLK RE70 1 2 1K_0201_5%
NGFF_CONFIG_0 10 AC_PRESENT GPIO233 GPIO156/LED0 EC_SLP_S0IX# 11
RE56 1 2 100K_0201_5% D10 0_0402_1% BAT1_LED# 43
NGFF_CONFIG_1 GPIO157/LED1 BCM5882_ALERT#
RE53 1 2 100K_0201_5% E11 D11 BAT2_LED# 43
RE116 1 2 10K_0201_5%
RE63 100K_0201_5% NGFF_CONFIG_2 7 SML1_SMBDAT GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BASE_SMB_ALERT# RE33
1 2 D8 E1 LCD_VCC_TEST_EN 22 1 2 10K_0201_5%
NGFF_CONFIG_3 7 SML1_SMBCLK GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 PCIE_WAKE#
RE40 1 2 100K_0201_5% M13 RE67 1 2 100K_0201_5%
LID_CL_SIO# 25 WWAN_WAKE# GPIO110/PS2_CLK2 WWAN_WAKE#
RE115 1 2 100K_0201_5%
10 SUSACK#
K12 E5 IMVP_SMBDAT 57 RH6 1 2 10K_0402_5%
L13 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 B3
+RTCVCC_EC 24 WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 IMVP_SMBCLK 57 VOL_DOWN#
PVT-011 K11 M7 VCCDSW_EN_GPIO 17
RE65 1 2 10K_0201_5%
Depop R411, LED4, Q16, R5766, LED5, Q356, SW3 for PVT build 10,13 SIO_PWRBTN# GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 HOME_KEY#
K10 M4 RE62 1 2 10K_0201_5%
POA_WAKE# 44 SLP_WLAN#_GATE GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 SAR_DPR# 25 VOL_UP#
RE117 1 2 100K_0201_5% 43 LID_CL_SIO# N11 M3 PBAT_SMBDAT 48 RE64 1 2 10K_0201_5%
SW3 GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PCH_PCIE_WAKE#
@ E10 N2 PBAT_SMBCLK 48
@ RE55 1 2 10K_0201_5%
POWER_SW_IN# 1 POWER_SW_IN#_R 50 CHG_MCP23008_SMBDAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 WLAN_WIGIG60GHZ_DIS#
2 1 2 C12 N10 RE251 1 2 100K_0201_5%
43,49 POWER_SW_IN# 50 CHG_MCP23008_SMBCLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA IMVP_U42_U22#_LED NGFF_CONFIG_2 25 WWAN_RADIO_DIS#
RE113 10K_0201_5% A12 RE266 1 2 100K_0201_5%
3 4 JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 BASE_SMBCLK RE46 1 2 1K_0201_5%
JTAG_TDO GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# BASE_SMBDAT 43 BASE_SMBDAT
F6 F7 BASE_SMBCLK 43 RE45 1 2 1K_0201_5%
JTAG_CLK C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 PVT-005
SKSFABE010_4P JTAG_TMS C5 GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# C3
UPD1_PS_SMBDAT 31,35,37 Change RE124 from 0201 0ohm to 0402 300ohm
IMVP_VR_ON JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_PS_SMBCLK 31,35,37 BT_RADIO_DIS#
RE247 1 2 100K_0402_5% G13 RE262 1 2 100K_0201_5%
RE69 1 2 220K_0201_5% EN_INVPWR JTAG_RST# J4 I_BATT RE124 1 2 300_0402_5%
LCD_TST GPIO200/ADC00 I_SYS I_ADP 50
@ RE51 1 2 100K_0201_5% PVT-036 E3 J5 RE125 1 2 300_0402_5%
P_SYS_R 50,57
@ RE24 1 2 100K_0201_5% VBUS1_ECOK Change 0 ohm to short pad 43 TACH_FAN1
D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6 SYS_PWROK
RE157 1 2 10K_0402_5%
for Debug Change 0.01 ohm to short pad 42 VOL_UP#
M2 GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 G2 PVT-004
VOL_DOWN# 42 USH_PWR_STATE# RE122 2 1 1M_0201_5%
22 LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 Change EN_PD_HV1 to I_ADP and pop RE124 for BPCC function (sync with KWMLK) SUS_ON_EC_R
L10 H2 USH_PWR_STATE# 43 RE112 1 2 100K_0201_5%
RE119 43
PWM_FAN1 GPIO053/PWM0/GPWM0 GPIO204/ADC04
1 @ 2 0_0201_5% KICKSTD_SW_DET#_R L11 J2
8,42 KICKSTD_SW_DET# USB_POWERSHARE_VBUS_EN39
0_0201_5% 1 @ 2 RE245 PCH_RSMRST# M5 GPIO054/PWM1/GPWM1 GPIO205/ADC05 J3
10,13 PCH_RSMRST#_R SHD_CLK GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 3VALW_PG_EC RE121 USB_POWERSHARE_EN#39
T57 @ PAD~D
J8 K3 1 @ 2 0_0201_5%
3VALW_PG 48,52
PVT-022
N1 GPIO056/PWM3/SHD_CLK GPIO207/ADC07 D3 Change CE19 from 0.1u to 2200p, and depop CE15
22 BIA_PWM_EC GPIO001/PWM4 GPIO210/ADC08 SUS_ON_EC_R AUX_EN_WOWL 44 PVT-036
L8 D2
N6 GPIO002/PWM5 GPIO211/ADC09 E2 Change 0 ohm to short pad I_BATT CE19 1 2 2200P_0201_16V7K
+RTCVCC_EC 31 P_SENSOR_ACT# GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 Change 0.01 ohm to short pad
22 PANEL_BKEN_EC
J9 G5
C GPIO015/PWM7 GPIO213/ADC11 DET_R# 48 I_SYS C
28 BEEP H11 F5
UPD2_SMBINT# 36
CE13 1 2 2200P_0402_50V7K
RE27 1 2 100K_0201_5%
POWER_SW_IN# D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4
GPIO133/PWM9 GPIO215/ADC13 DCIN1_EN 48 I_ADP
RE25 1 2 100K_0201_5% ALWON H12 L1 @ CE15 1 2 0.1U_0201_10V6K
DCIN1_EN 50 AC_DIS GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# 10
RE31 1 2 100K_0201_5% G10 L3
RUN_ON 43 BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# 10
RE17 1 2 100K_0201_5% MSCLK H10 PVT-036
RE2 1 2 10K_0201_5% G9 GPIO170/TFDP_CLK/UART1_TX H8 Change 0 ohm to short pad
MSDATA MSDATA
+3V_5105 GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ DOCK_PWR_EN 45 Change 0.01 ohm to short pad
J7
GPIO223/SHD_IO0 USH_RST#_L 3.3V_TS_EN 44
A4 L6 RE47 2 @ 1 0_0402_1%
28 NB_MUTE# GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 SHD_IO2 USH_RST# 43
B2 L7
POWER_SW_IN# 22 EN_INVPWR RESET_IN#
C1 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 M6
GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS1_ECOK 48
1

N7 +1.8VA_EC
32 IMVP_VR_ON GPIO031/GPTP-OUT1
1 RE61 K9 D6
10,30,32 SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN 43 UPD1_HPD
N8 C7 RE258 1 2 1M_0201_5%
10 SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN 50 UPD2_HPD
CE21 10K_0201_5% A5 ALWON RE26 2 1 2.2K_0201_5% RE259 1 2 1M_0201_5%
2.2U_0402_6.3V6K F13 VCI_OUT D5 POWER_SW_IN# ALWON_PWR 52
2

2 E13 GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 VCI_IN1#

ME_FWP 48 AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# VCI_IN2#
C13 D4
41 USH_DET GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2#
R471 1 @ 2 0_0402_5% E12 E4
36 PD2_HWRST GPIO126/PVT_IO3 GPIO000/VCI_IN3# POA_WAKE# 43
1

F11
42 RTCRST_ON
F12 GPIO122/BCM0_DAT/PVT_IO1 C6 PECI_EC_R RE49 1 2 43_0201_5%
25 WWAN_RADIO_DIS# GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN 44 H_PECI 11
@

RE54 D12
43 BASE_SMB_ALERT# GPIO046/BCM1_DAT 32KHZ_OUT
10K_0201_5% R470 1 @ 2 0_0402_5% D13 F3 @ CE57 1 2 10P_0402_50V8J
35 PD1_HWRST GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
PVT-036
2

Change 0 ohm to short pad F4

Change 0.01 ohm to short
25 padNGFF_CONFIG_3 SYSPWR_PRES GPIO041/SYS_SHDN# +PECI_VREF
+3VLP RE152 2 @ 1 B1 J11
UPD1_HPD_R 1 2 UPD1_HPD K7 SYSPWR_PRES GPIO044/VREF_VTT K13 PECI_EC_R
1K_0402_5% R475 @ 0_0402_1%
2 1 N3 GPIO011/nSMI VTR3 +1.8V GPIO042/PECI_DAT/SB-TSI_DAT J12 SIO_SLP_S4#
RE97 1 2
RE154 48 VBUS2_ECOK m3042_PCIE#_SATA 9
0_0402_5% SUS_ON_EC 32,43,45,53
100K_0402_5% K6 GPIO021/LPCPD# GPIO043/SB-TSI_CLK A8 REM_DIODE1_N CE27 1 2 2200P_0402_50V7K
7 ESPI_RESET# H7 GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A A7 REM_DIODE1_P SUS_ON_EC_R
@ RE98 1 2 0_0402_5%
7 ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# VTR3 +1.8V DP1_DN1A REM_DIODE2_N
32 PCH_PLTRST#_EC
K1 A10 CE29 1 2 2200P_0402_50V7K
G7 GPIO064/LRESET# VTR3 +1.8V DN2_DP2A A9 REM_DIODE2_P
7,43
ESPI_CLK H6 GPIO065/PCI_CLK/ESPI_CLK VTR3 +1.8V DP2_DN2A B9 REM_DIODE3_N CE28 1 2 2200P_0402_50V7K
7,43 ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# VTR3 +1.8V DN3_DP3A B8 REM_DIODE3_P SIO_SLP_S3# @ RE99 1 2 0_0402_5% RUN_ON_EC
7,43 ESPI_IO0 GPIO070/LAD0/ESPI_IO0 VTR3 +1.8V DP3_DN3A RUN_ON_EC 32,53
TRIP temperature setting is 99 Celsius degree L4 A11
7,43 ESPI_IO1 GPIO071/LAD1/ESPI_IO1 VTR3 +1.8V DN4_DP4A RUN_ON
PVT-036 G6 B10 RE100 1 2 0_0402_5%
VSET_5105 Change 0 ohm to short pad 7,43 ESPI_IO2 L5 GPIO072/LAD2/ESPI_IO2 VTR3 +1.8V DP4_DN4A C10 +VR_CAP
Change 0.01 ohm to short pad 7,43 ESPI_IO3 GPIO073/LAD3/ESPI_IO3 VTR3 +1.8V VIN VSET_5105 RUN_ON
0.1U_0402_10V7K

L2 C9 @ RE114 1 2 0_0402_5%
1 32 KHz Clock UPD2_HPD_RR476
1 @ 2 0_0402_1% UPD2_HPD M1 GPIO067/CLKRUN# VTR3 +1.8V
GPIO100/nEC_SCI VTR3 +1.8V
VSET
VCP
B11 I_ADP AUD_PWR_EN 44
1
CE30

G4 H3 THERMATRIP2# RE120 1 2 0_0402_5%

VSS_ANALOG
10,13 SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# 11 PCH_AUD_PWR_EN
RE58 Y2 L12 B12 THERMATRIP1#
1.96K_0402_1% MEC_XTAL1 1 2 MEC_XTAL2 48 DCIN2_EN GPIO107/nSMI THERMTRIP1# H13 PROCHOT#

VSS_ADC
MEC_XTAL1

VSS_PLL
2 GPIO160/PWM11/PROCHOT#

VR_CAP
A1
32.768KHZ_9.0PF_9H03200033 MEC_XTAL2 A3 XTAL1 +RTCVCC_EC

VSS1

VSS2

VSS3
2

XTAL2
1

VCI_IN2#
CE12 CE11 MEC5105_WFBGA169_11X11 RE142 1 2 100K_0402_5%

A6

A13

E6

H4

J1

C4

G1
VCI_IN1#
10P_0402_50V8J 12P_0402_50V8J RE141 1 2 100K_0402_5%
2

1U_0402_6.3V6K
+3V_5105
PCB footprint

1 +VR_CAP
+VSS_PLL RB520SM-30T2R_EMD 2- 2
B CPU_DP1_HPD UPD1_HPD_R B
RE12 1 @ 2 0_0402_5% 1 2
10 RTC_RST# 5,36,37 CPU_DP1_HPD
100K_0201_5%
1

D105
@D
1

+3V_5105
RE42

RB751S40T1G_SOD523-2
Q10 2 RTCRST_ON

CE64
DII-DMN65D8LW-7 G

2
CPU_DP2_HPD UPD2_HPD_R
100K_0201_5%

S 1 2
2

5,35,37 CPU_DP2_HPD
1

+3V_PRIM
RE16

D106 THERMATRIP1# 1 2
JTAG_RST# @ RB751S40T1G_SOD523-2 RE246 10K_0402_5%
PCB footprint PVT-036
RB520SM-30T2R_EMD 2- 2 Change 0 ohm to short pad
2

Change 0.01 ohm to short pad

RE253 1 2 100K_0402_5%
SHORT PADS

1U_0402_6.3V4Z

SHD_IO2
RE41

1 RE252 1 @ 2 0_0402_1%
1.8VA_PG 55
1

CE24

RE215

0.1U_0402_25V6
1 2 THERMATRIP2#
+3VALW
2

2 +1.0VS_VCCIO
@

MMBT3904WH_SOT323-3
SIO_SLP_S3# 10,30,32 8.2K_0402_5%

CE86
PVT-036
2

Change 0 ohm to short pad +1.0V_VCCST

QE16
@ QE15
G

Change 0.01 ohm to short pad

1

2
1 3 1 2 2
B +PECI_VREF RE261 1 2
RE219 2.2K_0402_5% @ 0_0201_5%
D

+1.0V_VCCST

0.1U_0201_10V6K
E
3

DII-DMN65D8LW-7
1

CE25
RE222 1 2 0_0402_5%
Different with X6 project 11 H_THERMTRIP#
2

+3V_5105

+3VS
RE9

RE8
RE7
RE6
RE5

10K_0402_5%
2
+3VALW

RE168
1

1
1
1
1

REM_DIODE2_P OTP thermal diode REM_DIODE1_P

For EMI request

100K_0402_5%

1
ESPI_CLK

2
Q7 Q11 PVT-003 RUNPWROK
1

C C Due to SB00000DH00 will EOL, change to SB00000PV00

1 1
2

2
2
2
2

RE174
+3V_5105
49.9_0402_1%

2 2
Thermal diode mapping SSD CPU
33_0402_5%
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%

DMN66D0LDW-7_SOT363-6
CE3 B CE2 B
EMC@

100P_0402_50V8J E MMBT3904WH_SOT323-3 100P_0402_50V8J E MMBT3904WH_SOT323-3

RE172
3

1
2 2 SB00000PV00
1641 Channel Locat i on REM_DIODE2_N REM_DIODE1_N
1

6
A A
RUN_ON# 2
10K_0201_5%
RE4

10K_0201_5%
RE3

10K_0201_5%
RE1

QE14B
D
JDEG3 G
2

1
1 JTAG_TDI DP1/DN1 CPU REM_DIODE2_N REM_DIODE1_N
S
33P_0402_50V8J

DMN66D0LDW-7_SOT363-6
2

1
2 JTAG_TMS
@

3
EMC@
2

3 JTAG_CLK
1

4 Q8 Q6 SB00000PV00
4 JTAG_TDO DP2/DN2 SSD
1

CE65

5 C C
5 1 1 Charger

3
@

6 MSCLK 2 2
LCD
2

QE14A
7 MSDATA 5
D
CE4 B CE26 B
DP3/DN3 WLAN
G
7 8 HOST_DEBUG_TX 100P_0402_50V8J E MMBT3904WH_SOT323-3 100P_0402_50V8J E MMBT3904WH_SOT323-3 27,32,44,45,55,56 RUN_ON_P S
3

8 9 2 2
DEBUG_UART0_TX 8

4
9 10 REM_DIODE2_P REM_DIODE1_P
10 DP4/DN4 Charger
REM_DIODE3_P
11
GND1 12 DP5/DN5 LCD REM_DIODE3_P 43
GND2 Q2
1

C
move to USH board DP6/DN6 USH 1 Security Classification Compal Secret Data Compal Electronics, Inc.
@

ACES_50521-01041-P01 2
CONN@ CE1 B WWAN on USH board Issued Date 2015/10/22 2013/10/28 Title
100P_0402_50V8J E MMBT3904WH_SOT323-3
Deciphered Date
P30-EC SMSC MEC5105
3

2
REM_DIODE3_N THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
REM_DIODE3_N 43
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 30 of 65
5 4 3 2 1
 5 4 3 2 1

Gyro + Accelerometer
+3VS PVT-037
+3VS Change 0 ohm to short pad
Change 0.01 ohm to short pad

check PH resistor

1
Jayton 1k
RS18 2 1 2.2K_0201_5% ISH_I2C0_SDA RS20
RS19 2 1 2.2K_0201_5% ISH_I2C0_SCL @ 0_0402_1%

RS10 2 1 10K_0201_5% ACCEL_INT1#_C

2
D RS9 ACCEL_INT2#_C +3VS_gyro D
2 1 10K_0201_5%

@ RS11 2 1 10K_0201_5% ACCEL_INT1#_C LGA1 PVT-037

@ RS6 2 1 10K_0201_5% ACCEL_INT2#_C Change 0 ohm to short pad
Change 0.01 ohm to short pad
5 8
VDDIO VDD
1 9 ACCEL_INT2#_C RS7 1 @ 2 ACCEL_INT2#_D
SDO/SA0 INT2 ACCEL_INT2#_D 8
0_0201_5%
2 10
PVT-037 SDx CS_Aux
Change 0 ohm to short pad 3 11

TPM
Change 0.01 ohm to short padv SCx NC

8 ACCEL_INT1#_D
ACCEL_INT1#_D RS8 1 @ 2 0_0201_5% ACCEL_INT1#_C 4
INT1 CS
12 +3VS_gyro Place close to LGA1 PIN1,3,22 and 23
ISH_I2C0_SCL +3VS_gyro
SCL
13 Pop De-pop
6 1 1 1
7 GND1 14 ISH_I2C0_SDA
GND2 SDA NPCT65x R153, R451, R460 R5750, R450
CS4 CS3 CS5
10U_0402_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K
2 2 2 * NPCT75x R5750, R450 R153, R451, R460
LSM6DS3USTR_LGA14_2P5X3 PVT-037
+3VS Change 0 ohm to short pad +3VS_TPM
Change 0.01 ohm to short pad

@TPM@
1 2
R5750 0_0603_5%
+3V_PRIM

@TPM@ 1 2 0.01_0603_1%

E-Compass R153

+3VALW_TPM +3VS_TPM

+TPM_LPM
close to U20.8
C +3VS PVT-037 C229 C230 C130 C128 C125 C224 C225 C
Change 0 ohm to short pad TPM@ TPM@ TPM@ TPM@ TPM@
Change 0.01 ohm to short pad 1 1 1 1 1 1 TPM@ 1 TPM@

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

10U_0402_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
1

PVT-037
RS17 +3VALW Change 0 ohm to short pad +3VALW_TPM 2 2 2 2 2 2 2
Change 0.01 ohm to short pad
@ 0_0402_1%
@TPM@
1 2
2

R457 0_0603_5%
+3VS_ecom
U3
Place close to LGA2 PIN1,3,22 and 23 +3VS_TPM
PVT-037 +3VS_ecom
6 2 Change 0 ohm to short pad
GND RES Change 0.01 ohm to short pad 1 1 1 TPM_PIRQ#
CS8 1 2 0.22U_0402_10V6K 5 12 @TPM@ 1 2 NOTE:
C1 RES CS6 CS7 CS9 R439 10K_0402_5%
RS15 1 @ 2 0_0201_5% 1 4 RS16 2 @ 1 0_0201_5% 10U_0402_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K +3V_PRIM Place 0.1 uF capacitors as close as
8 ISH_I2C0_SCL ISH_I2C0_SDA 8
9
SCL/SPC SDA/SDI/SDO
8 2 2 2 possible to the device power pins
PVT-037 11 VDD GND TPM@ 1 2
Change 0 ohm to short pad RES R5777
Change 0.01 ohm to short pad
10 10K_0402_5%
VDD_IO PVT-037
+3VS_ecom 3 7 Change 0 ohm to short pad
CS INT/DRDY Change 0.01 ohm to short pad
@TPM@ C226
2 1 PCH_SPI_CLK_TPM +TPM_LPM @TPM@ R453 1 2 0_0603_5% +3VS_TPM
LIS2MDLTR_LGA12_2X2
add slave address 0.1U_0201_10V6K
Reserve for EMI please close to U15 1 @ 2 +3VS
R454 0_0603_5%

PVT-037 +3VALW_TPM
Change 0 ohm to short pad
Change 0.01 ohm to short pad

U4246
@TPM@ 1

SAR Proximity Sensor R450 1 2 0_0402_1% 29 VSB

9,10,45,56,57 SIO_SLP_S0# GPIO0/SDA/XOR_OUT
30 8 +TPM_LPM
@TPM@ TPM_LPM GPIO1/SCL VDD
1 2 3 14 +3VS_TPM
B R460 0_0402_5% 6 GPIO2/GPX VDD 22 B
GPIO3/BADD VDD
24 2
+3VS +1.8VU +3VS 7 PCH_SPI_SO_TPM LAD0/MISO NC
7 PCH_SPI_SI_TPM 21 7
PVT-037 PVT-037 TPM_PIRQ# LAD1/MOSI NC
18 10
Change 0 ohm to short pad Change 0 ohm to short pad 7,8 TPM_PIRQ# LAD2/SPI_IRQ# NC
Change 0.01 ohm to short pad Change 0.01 ohm to short pad
15 11
LAD3 NC 25
+3VS PCH_SPI_CLK_TPM NC
1 1 7 PCH_SPI_CLK_TPM 19 26
1

CS2 PCH_SPI_CS2# 20 LCKL/SCLK NC 31

7 PCH_SPI_CS2# LFRAME#/SCS# NC
CS1 RS2 RS1 17
10,22,23,24,25,27,30,32,34,43PLT_RST#
1

LRESET#/SPI_RST#/SRESET#
0.1U_0201_10V6K

0.1U_0201_10V6K @ 0_0402_1% @ 0_0402_1% @TPM@ R451 2 1 10K_0402_5% 27 9

2 2 SERIRQ GND
RS5 RS3 RS4 13 16
2

CLKRUN#/GPIO4/SINT# GND
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 28 23
2

LPCPD# GND 32
U1 GND
1 6 UPD1_PS_SMBCLK 30,35,37
4 33
2

C2 5 PP PGND 12
VDD EVT use NPCT650VBBYX TEST Reserved
Q1A
JANT1
C1
SVDD NIRQ
A2
P_SENSOR_ACT# 30 DMN2400UV-7_SOT-563-6 CPN SA00008EL90 NPCT750JAAYX QFN 32P TPM
TPM@
ME - ANT 1
1 ANT_CS0 LS1 1 2 SX9306_CS0 A3
CS0 SCL
B1 PS_SMBCLK DVT1 use NPCT750JAAYX
QP-48G EMI_Spring 10NH_LQG15HS10NJ02D_5%_0402 B3 A1 PS_SMBDAT CPN SA0000AQ200
CS1 SDA
CONN@ PVT use NPCT750JAAYX PVT-006
5

C3 B2 TPM chip turn MP, change CPN from SA0000AQ200 to SA0000AQ220

CS2 GND CPN SA0000AQ220
4 3
UPD1_PS_SMBDAT 30,35,37
SX9310ICSTRT_WLCSP9
PAD~D @ T4
PAD~D @ T1 Q1B
DMN2400UV-7_SOT-563-6
PAD~D @ T2 PAD~D @ T3 1

C8
0.1U_0201_10V6K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P31-Sensor / TPM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 31 of 65
5 4 3 2 1
 5 4 3 2 1

+1.8VA

+3VALW

2
UE5 RE183
1 5 10K_0402_5%
NC VCC
2
10,22,23,24,25,27,30,31,34,43PLT_RST#

1
A 4
Y PCH_PLTRST#_EC 30
3
GND
D D
74AUP1G07GW _TSSOP5

Use SA00005U600

+3VALW
+3VALW

+3VALW

5
UE7

5
1 5 SIO_SLP_S3# 1

P
NC VCC 10,30,32 SIO_SLP_S3# B
1 4

P
10,30,32 SIO_SLP_S3# B O RUN_ON_P 27,30,44,45,55,56
4 IMVP_VR_ON_P 2 2
O A 30,53 RUN_ON_EC A

G
30 IMVP_VR_ON
2 4 H_VCCST_PWRGD_P 10,13 UC5
A Y

1
U15 3

3
GND
TC7SH08FU_SSOP5 RE14

3
TC7SH08FU_SSOP5 74AUP1G07GW _TSSOP5 100K_0402_5%

2
2 1
Use SA00005U600 @ RE13 0_0402_5%~D
2 1
@ RE10 0_0402_5%~D IMVP_VR_ON_P 57

1
RE29
100K_0402_5%
C C
+3VALW

5
1

P
10,30,44,54,55,56 SIO_SLP_SUS# B
4 VCCST_EN 45
2 O
A

G
UC8

1
3
TC7SH08FU_SSOP5 RE48
100K_0402_5%

2
+3VALW
5

1
P

10,30 SIO_SLP_S4# B
4 SUS_ON_P 55
2 O
30,43,45,53 SUS_ON_EC A
G

UC7
1
3

TC7SH08FU_SSOP5 RE44
100K_0402_5%
B B
2

2 1
@ RE36 0_0402_5%~D

+3VALW +3VALW
RE196 CE78 REV RE264 CE87 REV
2

2
U22@ U2+2 Single Port ACE w/o AR
RE196
240K_0402_5%
240K 4700p RE264 240K 4700p
62K_0402_1% Single Port ACE w/ AR
130K 4700p 130K 4700p
U4+2 Dual Port ACE w/o AR
62K 4700p * 62K 4700p
1

1
CPU_ID TYPEC_ID
30 CPU_ID 30 TYPEC_ID
Dual Port ACE w/ AR
RE196 U42@ 33K 4700p 33K 4700p
1

1
Dual Port ACE (w/AR +w/o AR)
CE78 8.2K 4700p CE87 8.2K 4700p
4700P_0402_25V7K
4.3K 4700p 4700P_0402_25V7K
4.3K 4700p
2

2
SD028620280 2K 4700p 2K 4700p
62K_0402_5%
1K 4700p 1K 4700p
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P32-PWRGD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 32 of 65
5 4 3 2 1
 5 4 3 2 1

8M Rear Camera (WF)

PVT-017
Remove co-lay L8, L7, L6, L5, L4, L3, L2, L1

Bypass cap close to CONN

PVT-038 JAE_WP7B-S034VA1
Change 0 ohm to short pad
WFCAM_CSI2_CLKN1_L R20 2 @ 1 0_0402_1% +2.8V_VCM_OUT +2.8V_WF_AVDD +1.8V_WF_DOVDD 37 38
WFCAM_CSI2_CLKN1 5
GND GND
35 36 PVT-038
WFCAM_CSI2_CLKP1_L R19 DMIC4 LRSEL to GND on Module GND GND Change 0 ohm to short pad
2 @ 1 0_0402_1% WFCAM_CSI2_CLKP1 5

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
17 34 0_0201_5% 2 @ 1 RA44
34 WFCAM_LED# 17 34 +DVDD
16 33 @ R435 1 2 0_0201_5%
1 1 1 16 33 +5VS

C14

C15

C16
WFCAM_CSI2_DP7_L 15 32
D WFCAM_CSI2_DN7_L 15 32 DMIC_CLK34 28 D
14 31
14 31 DMIC_DATA34 28
13 30 R11 1 @ 2
2 2 2 WFCAM_CSI2_DP6_L 13 30 WF_VSYNC 34
12 29
WFCAM_CSI2_DN6_L 12 29 WF_SENSOR_RST# 34
11 28 0_0201_5%
11 28 PVT-038
10 27
WFCAM_CSI2_CLKP1_L 10 27 WF_HCLK 34 Change 0 ohm to short pad
PVT-038 9 26 1
Change 0 ohm to short pad WFCAM_CSI2_CLKN1_L 9 26
8 25
WF_I2C_CLK 34 @RF@ C11
WFCAM_CSI2_DN4_L R16 8 25 47P_0201_25V8J
2 @ 1 0_0402_1% WFCAM_CSI2_DN4 5 7 24
WF_I2C_DATA 34
WFCAM_CSI2_DP4_L 6 7 24 23
+1.2V_WF_DVDD +2.8V_WF_AVDD WFCAM_CSI2_DN4_L 5 6 23 22 2
WFCAM_CSI2_DP4_L R13 5 22
2 @ 1 0_0402_1% WFCAM_CSI2_DP4 5 4 21
+1.2V_WF_DVDD
WFCAM_CSI2_DP5_L 3 4 21 20
WFCAM_CSI2_DN5_L 3 20 +1.8V_WF_DOVDD

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
2 19

0.1U_0201_10V6K

2.2U_0402_6.3V6M
2 19 +2.8V_WF_AVDD
1 18
1 18 +2.8V_VCM_OUT
1 1

1
C10
C7

C210

C211

C212
CONN@ JWFC1

2
2 2
PVT-038 WFCAM_CSI2_DN5_L
Change 0 ohm to short pad WFCAM_CSI2_DP5_L
WFCAM_CSI2_DN5_L R12 2 @ 1 0_0402_1% WFCAM_CSI2_DN5 5
WFCAM_CSI2_DN4_L
WFCAM_CSI2_DP4_L
WFCAM_CSI2_DP5_L R9 2 @ 1 0_0402_1% WFCAM_CSI2_DP5 5
WFCAM_CSI2_CLKN1_L
WFCAM_CSI2_CLKP1_L

WFCAM_CSI2_DN6_L
PVT-017 WFCAM_CSI2_DP6_L
Remove co-lay L8, L7, L6, L5, L4, L3, L2, L1
WFCAM_CSI2_DN7_L
WFCAM_CSI2_DP7_L
PVT-038 PVT-038
Change 0 ohm to short pad Change 0 ohm to short pad
WFCAM_CSI2_DN6_L R18 2 @ 1 0_0402_1% WFCAM_CSI2_DN6 5
WFCAM_CSI2_DN7_L R22 2 @ 1 0_0402_1% WFCAM_CSI2_DN7 5

ESD8011MUT5G X3DFN2
EMC@ D18

ESD8011MUT5G X3DFN2
EMC@ D19

ESD8011MUT5G X3DFN2
EMC@ D14

ESD8011MUT5G X3DFN2
EMC@ D15

ESD8011MUT5G X3DFN2
EMC@ D16

ESD8011MUT5G X3DFN2
EMC@ D17

ESD8011MUT5G X3DFN2
EMC@ D12

ESD8011MUT5G X3DFN2
EMC@ D13

ESD8011MUT5G X3DFN2
EMC@ D10

ESD8011MUT5G X3DFN2
EMC@ D11
1

1
C C
WFCAM_CSI2_DP6_L R17 2 @ 1 0_0402_1% WFCAM_CSI2_DP6 5
WFCAM_CSI2_DP7_L R21 2 @ 1 0_0402_1% WFCAM_CSI2_DP7 5
+2.8V_VCM_OUT

@ R15 1 2 100K_0201_5% WF_SENSOR_RST#

R14 1 2 100K_0201_5% WF_SENSOR_RST#

2
+2.8V_UF_AVDD
+1.8VA

2.2K_0201_5% RH2 UF_I2C_DATA

Bypass cap close to CONN 2 1
UF_I2C_CLK +3VS +3VS
2.2K_0201_5% 2 1 RH1

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1

1
+2.8V_VCM_OUT +1.8V_UF_VDD +2.8V_UF_AVDD +1.2V_UF_DVDD +3VS_AUDIO +5VS

C4

C208

C209
+2.8V_VCM_OUT ALS_I2C1_SCL RS22 2 1 1K_0201_5% CS10
ALS_I2C1_SDA RS23 2 1 1K_0201_5% 1U_0201_6.3V6K

2
ALS_I2C1_ALERT# RS24 2 1 1K_0201_5% 2
0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
2.2U_0402_6.3V6M

@ R5 1 2 100K_0201_5% UF_SENSOR_RST#

1 1 1 1 1 1 1
C17

C18
C1

C2

C3

C5

C6

R3 1 2 100K_0201_5% UF_SENSOR_RST#

B 2 2 2 2 2 2 2 B

5M Front Camera (UF)

DF37NC-30DS-0.4V(51)
PVT-017 CONN@ JUFC1
Remove co-lay L8, L7, L6, L5, L4, L3, L2, L1 1 2
+1.2V_UF_DVDD 1 2 UFCAM_CSI2_DP1_L UF_SENSOR_RST#
+2.8V_UF_AVDD 3 4
PVT-038 3 4 UFCAM_CSI2_DN1_L UF_I2C_DATA
+1.8V_UF_VDD 5 6
Change 0 ohm to short pad 7 5 6 8 UF_I2C_CLK
UFCAM_CSI2_CLKN0_L R6 7 8 UFCAM_CSI2_CLKP0_L
2 @ 1 0_0402_1% UFCAM_CSI2_CLKN0 5 9 10
11 9 10 12 UFCAM_CSI2_CLKN0_L UFCAM_CSI2_DP1_L
34 UF_HCLK 11 12 UFCAM_CSI2_DN1_L
13 14
UFCAM_CSI2_CLKP0_L R4 UF_SENSOR_RST# 13 14 UFCAM_CSI2_DP0_L
2 @ 1 0_0402_1% UFCAM_CSI2_CLKP0 5 34 UF_SENSOR_RST#
15 16
UF_I2C_DATA 17 15 16 18 UFCAM_CSI2_DN0_L PVT-038 UFCAM_CSI2_CLKP0_L
8 UF_I2C_DATA UF_I2C_CLK 17 18 Change 0 ohm to short pad UFCAM_CSI2_CLKN0_L
19 20
8 UF_I2C_CLK 19 20
21 22 RS25 1 @ 2 0_0201_5%
21 22 RS27 1 ALS_I2C1_SCL 8 UFCAM_CSI2_DP0_L
23 24 @ 2 0_0201_5%
23 24 ALS_I2C1_SDA 8 UFCAM_CSI2_DN0_L
25 26 RS26 1 @ 2 0_0201_5%
25 26 ALS_I2C1_ALERT# 8
27 28
+5VS 27 28
1 2 29 30
34 UFCAM_LED# 29 30 +3VS
R487 5.1K_0201_1%

ESD8011MUT5G X3DFN2
EMC@ D2

ESD8011MUT5G X3DFN2
EMC@ D4

ESD8011MUT5G X3DFN2
EMC@ D6

ESD8011MUT5G X3DFN2
EMC@ D7

ESD8011MUT5G X3DFN2
EMC@ D8

ESD8011MUT5G X3DFN2
EMC@ D9

ESD8011MUT5G X3DFN2
EMC@ D1

ESD8011MUT5G X3DFN2
EMC@ D3

ESD8011MUT5G X3DFN2
EMC@ D5
PVT-038 HRS_DF37NC-30DS-0P4V(51)

1
Change 0 ohm to short pad
UFCAM_CSI2_DN0_L R1 2 @ 1 0_0402_1% UFCAM_CSI2_DN0 5

UFCAM_CSI2_DP0_L R2 2 @ 1 0_0402_1% UFCAM_CSI2_DP0 5

2
A A

PVT-038
Change 0 ohm to short pad
UFCAM_CSI2_DN1_L R8 2 @ 1 0_0402_1% UFCAM_CSI2_DN1 5

UFCAM_CSI2_DP1_L R7 2 @ 1 0_0402_1% UFCAM_CSI2_DP1 5

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P33-World/User Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 33 of 65
5 4 3 2 1
 5 4 3 2 1

+1.8V_WF_DOVDD +1.2V_UF_DVDD +1.8V_UF_VDD +1.8V_IO_OUT +2.8V_VCM_OUT +2.8V_WF_AVDD

47P_0201_25V8J

47P_0201_25V8J

47P_0201_25V8J

47P_0201_25V8J

47P_0201_25V8J

47P_0201_25V8J
1 1 1 1 1 1
@RF@ @RF@ @RF@ @RF@ @RF@ @RF@
C75 C69 C53 C77 C86 C66

2 2 2 2 2 2

D D

PVT-039
+3VS_CAM Change 0 ohm to short pad +3V_SKYCAM
Change 0.01 ohm to short pad
+1.8V_IO_OUT 1 @ 2 +1.8V_WF_DOVDD +1.2V_UF_DVDD +1.8V_UF_VDD
R90 0_0603_5%
2.2K_0201_5% 2 1 RH24 WF_I2C_DATA
WF_I2C_CLK

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
2.2K_0201_5% 2 1 RH27 C55 C76 C61 C65 C80 C79

0.1U_0201_10V6K

0.1U_0201_10V6K

0.1U_0201_10V6K
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
1 1 1 1 1 1 1 1 1

C72

C70

C54
SKY CAM PMIC

10U_0603_6.3V6M
+1.8VA

2.2K_0201_5% 2 1 RH26 SKYCAM_I2C_DATA 2 2 2 2 2 2 PVT-039 2 2 2

2.2K_0201_5% 2 1 RH25 SKYCAM_I2C_CLK +3V_PRIM U12 Change 0 ohm to short pad
Change 0.01 ohm to short pad

H5 H4 1 @ 2 +2.8V_VCM_OUT
3V3_VDD1 VCM_OUT R113 2 0_0603_5%
G6 B7 1 @ +2.8V_WF_AVDD
3V3_VDD2 ANA_OUT R102 0_0603_5%
D1
R95 B6 3V3_VDD3
2 1 PLL_COMP1 A7 3V3_VDD4 E7 +1.8V_IO_OUT +2.8V_VCM_OUT +2.8V_WF_AVDD
3V3_VDD5 IO_OUT +1.8V_IO_OUT
B5 D7 1 @ 2 +1.8V_WF_DOVDD
0.01UF_0402_25V7K

C64 PLL_VDD 3V3_SUS S_IO_OUT R106 0_0603_5%

8.2K_0201_5% 1 2 1U_0402_6.3V6K A5 F7
2200P_0402_50V7K

PLL_VDD IO_GND

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
PLL_GND
1 1 CAP close to PINA5 D3
CPIO0 AUX1_OUT
C7 1 @ 2 +1.2V_UF_DVDD 1 1 1
C52

WF_I2C_DATA

C78

C87

C68
D6 A6 R105 1 @ 2 0_0603_5% PVT-039
33 WF_I2C_DATA CPIO1 AUX2_OUT +1.8V_UF_VDD Change 0 ohm to short pad
C56

PVT-039 WF_I2C_CLK F6 R98 0_0603_5%

33 to WF_I2C_CLK
Change 0 ohm short pad CPIO2 CORE_SW Change 0.01 ohm to short pad
C3 G7 L22 1 2 R116
2 2 Change 0.01 ohm to short pad ANA2_EN CPIO3 CORE_SW CORE_FB 2 2 2
C4 H6 1UH_1269AS-H-1R0M-P2_2.5A_20% 1 @ 2 +1.2V_WF_DVDD
R101 1 UF_SENSOR_RST#_R CPIO4 CORE_FB
@ 2 0_0402_1% C6 H7
PLL_GND 33 UF_SENSOR_RST# CPIO5 CORE_GND
E6 0_0603_5%
1
0.01UF_0402_25V7K

CPIO6
F1
2200P_0402_50V7K

R115 1 WF_SENSOR_RST#_R WLED_SW1 C88

@ 2 0_0402_1% E4 F2
33 WF_SENSOR_RST# S_RESETN WLED_SW2
1 1 E5 F3 4.7U_0402_6.3V6M
S_ENABLE WLED_SW3
C62

D4 2
S_IDLE
C63

33 WF_VSYNC @ R107 1 2 0_0402_5% C1 E1

H2 S_VSYNC WLED_OUT1 E2
C 10,22,23,24,25,27,30,31,32,43PLT_RST# C
2 2 @ R108 1 2 0_0402_5% STROBE_IN D2 RESET_IN WLED_OUT2 E3
S_STROBE WLED_OUT3 +3V_SKYCAM +3V_SKYCAM
OSC_IN B1 G1
R100 OSC_OUT A1 OSC_IN WLED_GND1 G2
PLL_COMP2 BLM15HD601SN1D_2P OSC-OUT WLED_GND2
2 1 G3

1
WF_HCLK_R WLED_GND3
EMC@ L20 1 2 D5
33 WF_HCLK UF_HCLK_R HCLK_A UFCAM_LED# 33
8.2K_0201_5% EMC@ L21 1 2 C5 C2 R93 R91
33 UF_HCLK HCLK_B WLED_NTC
1 1 BLM15HD601SN1D_2P 1 1 H1 100K_0201_5% 100K_0201_5%

3
EMC@ EMC@ @EMC@ @EMC@ PLL_COMP1 A3 DRV_WLED1 H3
C50 C49 C58 C57 PLL_COMP2 PLL_COMP1 DRV_WLED2
@ A4

2
OSC_IN R104 OSC_OUT PLL_COMP2
1 2 1M_0402_5% 47P_0201_25V8J 47P_0201_25V8J 68P_0201_25V8 68P_0201_25V8 B2 ILEDA @ R92 Q9B
2 2 2 2 ILEDA B3 R99 1 2 0_0201_5% 1 2 5 DMN2400UV-7_SOT-563-6
ILEDB ILEDA
Y1 G4 ILEDB
PVT-039 I2C_ICA
0_0201_5%

4
1
1 3 Change 0 ohm to short pad F4 B4 PLL_GND R447 1 2 0_0201_5%
Change 0.01 ohm to short pad
ILEDB
2 4 I2C_ICB PLL_GND A2 R97
SKYCAM_I2C_DATA R477 GND
1@ 1@ 8 SKYCAM_I2C_DATA 1 @ 2 0_0201_5% F5 0_0201_5%
18P_0402_50V8J

18P_0402_50V8J

20MHZ_12PF_7V20000015 SDA
C71

C67

SKYCAM_I2C_CLK R478 1 @ 2 0_0201_5% G5

8 SKYCAM_I2C_CLK

6 2
SCL
2 2
to GPP_F I2C2 1.8V TPS68470YFFR_DSBGA56

2 DMN2400UV-7_SOT-563-6
Q9A

1
@ R448
1 2 PVT-039
Change 0 ohm to short pad +3V_SKYCAM +3V_SKYCAM
+3V_PRIM Change 0.01 ohm to short pad
0_0603_5% +3VS_CAM
R94 +2.8V_UF_AVDD
U11 0_0603_5%
1

1
47P_0201_25V8J
1 @ 2
+3VS_CAM
B WFCAM_LED# 33 B
1 7 C59 1 @ R431 @ R430
VIN VOUT C51
2 8 0.1U_0402_10V7K @RF@ 100K_0201_5% 100K_0201_5%

3
VIN VOUT 2200P_0402_25V7K~D 2 C45

1
3.3V_CAM_EN 3 6 1 2

2
8 3.3V_CAM_EN ON CT 2 @ R429 @ Q26B R434
ILEDB @ R96 1 2 0_0201_5% 1 2 5 DMN2400UV-7_SOT-563-6 0_0201_5%
+5VALW 4
C60 VBIAS
5 0_0201_5%

2
1
GND PVT-039 +2.8V_UF_AVDD
1U_0402_6.3V6K~D 9
2 1 GND +3V_SKYCAM U9 Change 0 ohm to short pad +2.8V_UF_AVDD @ R428
Change 0.01 ohm to short pad
0_0201_5%
TPS22967DSGR_SON8_2X2 8 1 R79 1 @ 2 0_0603_5% R434 pop for EVT

2.2U_0402_6.3V6M
IN OUT R434 de-pop for WF module with LED feature

6 2
1
47P_0201_25V8J

7 2 1 1
NC SENSE/FB R78
1 C1

C44
@RF@ 6 3 C43
C46 NC NC
560K_0402_5%
R2 100P_0402_50V8J
R442 2 1 3.3V_CAM_EN ANA2_EN 5 4 2 2 2 DMN2400UV-7_SOT-563-6
2

2 EN GND @ Q26A
100K_0402_5%~D
TP

1
1

TPS79801QDGNRQ1_MSOP8
9

R77
do not leave floating for U11 pin3 470K_0402_5%
R1
2

VOUT = 1.275 V (1 + R2 / R1) + IFB* R2

VFB = 1.275 V
IFB= 0.53μ A at 25°C
Output Range = 1.275 V to 28 V
A A 100-pF capacitor (C1) placed in parallel A

with R2 of the output divider is necessary

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P34-Camera PMIC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 34 of 65
5 4 3 2 1
 5 4 3 2 1

+3.3V_LDO_PD1 +5VALW +5VALW_PD1 +5VALW_PD1 +VBUS1_PD_20V

+3VALW_PD1 +3VALW_PD1 +BMC_LDO_PD1 +1.8VA_LDO_PD1 +1.8VD_LDO_PD1 +3.3V_VOUT_PD1 +3.3V_LDO_PD1

@ RT29 1 2 10K_0402_5% I2C1_DAT_PD1 RT41 1 2 0_1206_5%
@ RT25 1 2 10K_0402_5% I2C1_CLK_PD1
@ RT32 1 2 10K_0402_5% I2C1_INT#_PD1
1 1 1 1 1 1 1 1 1 1 1

@ RT44 1 2 10K_0402_5% I2C2_DAT_PD1 CT16 CT17 CT11 CT19 CT18 CT14 CT15 CT10 CT12 CT13 CT9
@ RT43 1 2 10K_0402_5% I2C2_CLK_PD1 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 1U_0402_25V6K 1U_0402_25V6K 1U_0201_6.3V6K
10U_0402_6.3V6M 1U_0201_6.3V6K 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
@ RT42 1 2 10K_0402_5% I2C2_INT#_PD1 2 2 2 2 2 2 2 2 2 2 2
+3VALW +3VALW_PD1
@ RT6 1 2 4.7K_0201_5% PD1_DEBUG1
@ RT7 1 2 4.7K_0201_5% PD1_DEBUG2
D @ RT50 1 D
2 0_0402_5%
RT35 1 2 4.7K_0201_5% PD1_DEBUG_CTL1
RT36 1 2 4.7K_0201_5% PD1_DEBUG_CTL2 +3V_LDO

RT125 1 2 10K_0201_5% PD1_DEBUG4

RT37 1 2 0_0402_5%
PVT-040 EVT use 65982DB
Change 0 ohm to short pad
RT107
UT1
CPN SA0000AP500
+3.3V_LDO_PD1 1 @ 2 A6
PP_HV SENSEP
B10 DVT1 use 65982DC
A7 A10
0_0603_5% A8 PP_HV SENSEN CPN SA0000AX700
RT47 4.7K_0201_5% PD_EE_CS# PP_HV
1 2 B7
RT48 1 2 4.7K_0201_5% PD_EE_MISO PP_HV B9
RT10 1 2 4.7K_0201_5% PD_HOLD# A11 HV_GATE1 A9
+5VALW_PD1 PP_5V0 HV_GATE2
RT49 1 2 4.7K_0201_5% PD_EE_WP# C11
B11 PP_5V0
PP_5V0
D11 H11
PP_5V0 VBUS +VBUS1_PD_20V
+3.3V_LDO_PD1 J10
VBUS
H10 J11
PP_CABLE VBUS K11
@ RT119 1 2 100K_0402_5% PD1_AUX_N B1 VBUS
+3VALW_PD1 VDDIO
H1 H2 +3.3V_VOUT_PD1
@ RT120 1 2 100K_0402_5% PD1_AUX_P VIN_3V3 VOUT_3V3 G1
LDO_3V3 +3.3V_LDO_PD1
K1 +1.8VA_LDO_PD1
I2C1_DAT_PD1 LDO_1V8A
@ RT30 1 2 0_0201_5% D1 A2 +1.8VD_LDO_PD1
I2C1_CLK_PD1 I2C_SDA1 LDO_1V8D
@ RT26 1 2 0_0201_5% D2 E1 +BMC_LDO_PD1
I2C1_INT#_PD1 I2C_SCL1 LDO_BMC
@ RT33 1 2 0_0201_5% C1
I2C_IRQ1_N
UPD1_PS_SMBDAT RT40 1 @ 2 0_0201_5% I2C2_DAT_PD1 A5
30,31,37 UPD1_PS_SMBDAT UPD1_PS_SMBCLK I2C2_CLK_PD1 I2C_SDA2
RT39 1 @ 2 0_0201_5% B5
30,31,37 UPD1_PS_SMBCLK UPD1_SMBINT# I2C2_INT#_PD1 I2C_SCL2 PD1_CC1
RT38 1 @ 2 0_0201_5% B6 L9 RT113 1 2 0_0402_5%
30 UPD1_SMBINT# I2C_IRQ2_N C_CC1 USBC1_CC1 40
L10 PD1_CC2 RT114 1 2 0_0402_5%
C_CC2 USBC1_CC2 40
PVT-040
PVT-018 Change 0 ohm to short pad PD_EE_CLK CT8 2 220P_0201_25V7K
Remove co-lay R522, R523, R524, R525 TC4 PD_EE_MOSI
A3
B4 SPI_CLK RPD_G1
K9
K10 CT7
1
1 2 220P_0201_25V7K
Dead batery support
TC5 SPI_MOSI RPD_G2
C
PD_EE_MISO A4 C
TC11 SPI_MISO
PD_EE_CS# B3
TC10 SPI_SS_N
HCM1012GH900BP_4P K6
USB20_P1_R C_USB_TP USBC1_TP1_L 40
9 USB20_P1 4 3 L6
USB20_P1_R C_USB_TN USBC1_TN1_L 40
L5
USB20_N1_R USB_RP_P
K5
1 2 USB20_N1_R @ CT34 1 2 0.1U_0201_10V6K USB_RP_N K7
9 USB20_N1 5,37 PCH_DDI2_AUXP C_USB_BP USBC1_BP2_L 40
L7 USBC1_BN2_L 40
ML7 EMC@ RT14 1 2 1K_0201_5% PD1_AUX_P J1 C_USB_BN
RT13 1 2 1K_0201_5% PD1_AUX_N J2 AUX_P
AUX_N PD1_SBU1 RT117 1 @
K8 2 0_0402_5%
C_SBU1 PD1_SBU2 USBC1_SBU1 37,40
@ CT35 1 2 0.1U_0201_10V6K L8 RT118 1 @ 2 0_0402_5%
5,37 PCH_DDI2_AUXN C_SBU2 USBC1_SBU2 37,40
G4 PVT-040
TC8 SWD_CLK Change 0 ohm to short pad
TC9 F4
SWD_DATA PD1_GPIO0 RT45
B2 1 @ 2 0_0402_1% PD1_USBC_POL 37
RT15 UART_MISO GPIO0 PD1_GPIO1 RT46
1 2 1M_0402_5% C2 1 @ 2 0_0402_1%
UART_MOSI GPIO1 PD1_GPIO2 EN_PD_HV1 48
RT18 1 2 1M_0402_5% E2 D10 RT28 1 @ 2 0_0402_1%
36 UART_MOSI UART_TX GPIO2 PD1_GPIO3 TC20
F2 G11 RT20 1 @ 2 0_0402_1%
36 UART_MISO UART_RX GPIO3 PCH_DP2_HPD_UT1 AC1_DISC# 48,50
C10 RT34 1 @ 2 0_0402_1%
PD1_LSTX GPIO4 PD1_GPIO5 CPU_DP2_HPD 5,30,37
L4 E10 RT31 1 @ 2 0_0402_1%
PD1_LSRX LSTX/R2P GPIO5 PD1_GPIO6 PD1_OTG_ID 9
K4 G10 RT17 1 @ 2 0_0402_1%
TC7 LSRX/P2R GPIO6 TC6
D7 PD1_GPIO7 RT97 1 @ 2 0_0402_1%
PD1_DEBUG_CTL1 GPIO7 PD1_GPIO8 TC17
PD1_GPIO8_EXT
E4 H6 RT11 1 @ 2 0_0402_1%
PD1_DEBUG_CTL2 DEBUG_CTL1 GPIO8 TC19
D5
+3.3V_LDO_PD1 +3.3V_LDO_PD1 DEBUG_CTL2 PD1_GPIO5 RT27 1 @ 2 0_0402_5%
UPD1_PS_SMBCLK PD1_DEBUG1 PD1_VBUS_SENSE 9
RT5 1 2 0_0201_5% L2
U22 UPD1_PS_SMBDAT RT8 1 2 0_0201_5% PD1_DEBUG2 K2 DEBUG1 E11 RT24 1 2 10K_0402_5%
PD_EE_CS# 1 8
DEBUG2 MRESET power side pull down 1M
CS# VCC PD_HOLD#
PD_EE_MISO
PD_EE_WP#
2
DO(IO1) HOLD#(IO3)
7
PD_EE_CLK
1 37 PD1_USBC_AMSEL
RT3
RT4
1 2 0_0201_5% PD1_DEBUG3
PD1_DEBUG4
L3
DEBUG3 RESET_N
F11 RT99 non-mount
3 6 1 2 0_0201_5% K3 @ RT16 1 2 0_0402_5% +3.3V_LDO_PD1
WP#(IO2) CLK PD_EE_MOSI 37 PD1_USBC_EN DEBUG4 PD1_GPIO1
4 5 CT5 F10 @ RT19 1 2 0_0402_5% @ RT99 1 2 1M_0201_5%
GND DI(IO0) BUSPOWER_N +1.8VD_LDO_PD1
9 0.1U_0201_10V6K F1 RT23 1 2 0_0402_5%
thermal pad 2 I2C_ADDR PD1_GPIO2 RT100 1
G2 2 1M_0201_5%
W25Q80DVZPIG_WSON8 R_OSC
2

H7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SS

0.22U_0402_16V7K

15K_0402_1%
RT22

1
RT2 1 2 1K_0201_5% PD1_LSTX 0_0402_5%
1

CT6

RT21
TPS65982DCZQZR BGA 96P

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H8
L1
L11
B B
1

2
+3.3V_LDO_PD1
SPI ROM
8Mb 30 PD1_HWRST
1

1
10K_0402_1%
RT103
SPI I/F
RT110 @ RT109
100K_0402_5% 0_0402_5%

UPD1_PS_SMBDAT
2

2
PD1_GPIO8_EXT
UPD1_PS_SMBCLK
UT1
TPS65982

1
100K_0402_1%
RT104
UPD1_SMBINT# TX/RX USB2.0 #1

JUSBC1
UE1

2
MEC5105
UV1 For "-D" version only
UART Share ROM

SS Signal
PS8743A Factory Set Device Configurations 7
Infinite boot retry from Flash to Host I/F cycles.
DIV=RT104/(RT103+RT104)
between 0.7~1.0

UPD2_USH_SMBDAT

UPD2_USH_SMBCLK
UT2 USB2.0 #3
A A
TPS65982
UPD2_SMBINT# TX/RX
JUSBC2

UV2
PS8743A
SS Signal Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P35-PD Controller TI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F371P
Date: Tuesday, November 07, 2017 Sheet 35 of 65
5 4 3 2 1
 5 4 3 2 1

+5VALW +5VALW_PD2 +5VALW_PD2 +VBUS2_PD_20V +BMC_LDO_PD2 +1.8VA_LDO_PD2 +1.8VD_LDO_PD2 +3.3V_VOUT_PD2 +3.3V_LDO_PD2

RT56 1 2 0_1206_5% 1 1 1 1 1 1 1

CT23 CT24 CT30 CT32 CT20 CT28 CT31

1 1
1U_0402_25V6K 1U_0402_25V6K 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 1U_0201_6.3V6K 10U_0402_6.3V6M
CT22 CT21 2 2 2 2 2 2 2
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
2 2
+3VALW +3VALW_PD2

D D
RT84 1 2 0_0402_5%

+3V_LDO

@ RT85 1 2 0_0402_5% +3VALW_PD2 +3VALW_PD2

1 1

CT29 CT33
10U_0402_6.3V6M 1U_0201_6.3V6K
2 2

EVT use 65982DB

PVT-041
CPN SA0000AP500
Change 0 ohm to short pad UT2 DVT1 use 65982DC
RT108
1 @ 2 A6 B10
CPN SA0000AX700
A7 PP_HV SENSEP A10
0_0603_5% A8 PP_HV SENSEN
+3.3V_LDO_PD2 B7 PP_HV
PP_HV
B9
A11 HV_GATE1 A9
+5VALW_PD2 PP_5V0 HV_GATE2
@ RT87 1 2 10K_0402_5% I2C1_DAT_PD2_C C11
I2C1_CLK_PD2_C PP_5V0
@ RT86 1 2 10K_0402_5% B11
I2C1_INT#_PD2_C PP_5V0
@ RT94 1 2 10K_0402_5% D11 H11
+VBUS2_PD_20V
PP_5V0 VBUS
J10
@ RT67 1 2 10K_0402_5% I2C2_DAT_PD2 H10 VBUS J11
@ RT64 I2C2_CLK_PD2 PP_CABLE VBUS
1 2 10K_0402_5% K11
I2C2_INT#_PD2 VBUS
@ RT62 1 2 10K_0402_5% +3VALW_PD2 B1
VDDIO
C @ RT81 1 2 4.7K_0201_5% PD2_DEBUG1 H1 H2 C
VIN_3V3 VOUT_3V3 +3.3V_VOUT_PD2
@ RT90 1 2 4.7K_0201_5% PD2_DEBUG2 G1
LDO_3V3 +3.3V_LDO_PD2
K1 +1.8VA_LDO_PD2
RT83 2 4.7K_0201_5% PD2_DEBUG_CTL1 I2C1_DAT_PD2_C LDO_1V8A
1 @ RT93 1 2 0_0201_5% D1 A2 +1.8VD_LDO_PD2
RT79 2 4.7K_0201_5% PD2_DEBUG_CTL2 I2C1_CLK_PD2_C I2C_SDA1 LDO_1V8D
1 @ RT92 1 2 0_0201_5% D2 E1 +BMC_LDO_PD2
PVT-041 I2C1_INT#_PD2_C I2C_SCL1 LDO_BMC
@ RT95 1 2 0_0201_5% C1
RT126 1 2 10K_0201_5% PD2_DEBUG4 Change 0 ohm to short pad I2C_IRQ1_N
UPD2_USH_SMBDAT RT66 1 @ 2 0_0201_5% I2C2_DAT_PD2 A5
30,37,43 UPD2_USH_SMBDAT UPD2_USH_SMBCLK I2C2_CLK_PD2 I2C_SDA2
PVT-018 RT63 1 @ 2 0_0201_5% B5
Remove co-lay R522, R523, R524, R525 30,37,43 UPD2_USH_SMBCLK UPD2_SMBINT# I2C2_INT#_PD2 I2C_SCL2 PD2_CC1
RT61 1 @ 2 0_0201_5% B6 L9 RT115 1 2 0_0402_5%
30 UPD2_SMBINT# I2C_IRQ2_N C_CC1 USBC2_CC1 40
L10 PD2_CC2 RT116 1 2 0_0402_5%
C_CC2 USBC2_CC2 40

HCM1012GH900BP_4P RT73 100K_0402_5% PD2_EE_CLK CT26 1 2 220P_0201_25V7K

4 3 USB20_P3_R RT70
1
1
2
2 100K_0402_5% PD2_EE_MOSI
A3
B4 SPI_CLK RPD_G1
K9
K10 CT25 1 2 220P_0201_25V7K
Dead batery support
9 USB20_P3 PD2_EE_MISO SPI_MOSI RPD_G2
RT69 1 2 100K_0402_5% A4
RT72 3.3K_0402_1% PD2_EE_CS# SPI_MISO
1 2 B3
USB20_N3_R +3.3V_LDO_PD2 SPI_SS_N
9 USB20_N3 1 2 K6
C_USB_TP USBC2_TP1_L 40
L6
EMC@ USB20_P3_R C_USB_TN USBC2_TN1_L 40
ML14 L5
USB20_N3_R K5 USB_RP_P
@ CT36 1 2 0.1U_0201_10V6K USB_RP_N K7
5,37 PCH_DDI1_AUXP C_USB_BP USBC2_BP2_L 40
L7
PD2_AUX_P C_USB_BN USBC2_BN2_L 40
RT82 1 2 1K_0201_5% J1
RT91 1 2 1K_0201_5% PD2_AUX_N J2 AUX_P
AUX_N K8 PD2_SBU1 RT121 1 @ 2 0_0402_5%
C_SBU1 PD2_SBU2 USBC2_SBU1 37,40
+3.3V_LDO_PD2 @ CT37 1 2 0.1U_0201_10V6K L8 RT122 1 @ 2 0_0402_5%
5,37 PCH_DDI1_AUXN C_SBU2 USBC2_SBU2 37,40
G4 PVT-041
TC15 SWD_CLK Change 0 ohm to short pad
TC14 F4
@ RT123 2 100K_0402_5% PD2_AUX_N SWD_DATA PD2_GPIO0 RT76
1 B2 1 @ 2 0_0402_1%
GPIO0 PD2_GPIO1 PD2_USBC_POL 37
C2 RT75 1 @ 2 0_0402_1%
GPIO1 PD2_GPIO2 EN_PD_HV2 48
E2 D10 RT57 1 @ 2 0_0402_1%
PD2_AUX_P 35 UART_MISO UART_TX GPIO2 PD2_GPIO3 TC21
@ RT124 1 2 100K_0402_5% F2 G11 RT59 1 @ 2 0_0402_1%
35 UART_MOSI UART_RX GPIO3 PCH_DP1_HPD_UT2 AC2_DISC# 48,50
C10 RT51 1 @ 2 0_0402_1%
PD2_LSTX GPIO4 PD2_GPIO5 CPU_DP1_HPD 5,30,37
L4 E10 RT52 1 @ 2 0_0402_1%
PD2_LSRX LSTX/R2P GPIO5 PD2_GPIO6 TC16
K4 G10 RT60 1 @ 2 0_0402_1%
TC13 LSRX/P2R GPIO6 TC12
D7 PD2_GPIO7 RT98 1 @ 2 0_0402_1%
PD2_DEBUG_CTL1 GPIO7 PD2_GPIO8 TC18
PD2_GPIO8_EXT
E4 H6 RT65 1 @ 2 0_0402_1%
PD2_DEBUG_CTL2 DEBUG_CTL1 GPIO8 TC22
D5
B DEBUG_CTL2 B
UPD2_USH_SMBCLK RT80 1 2 0_0402_5% PD2_DEBUG1 L2
UPD2_USH_SMBDAT RT89 1 2 0_0402_5% PD2_DEBUG2 K2
DEBUG1
E11 RT58 1 2 10K_0402_5% power side pull down 1M
DEBUG2 MRESET
RT77 1 PD2_DEBUG3
5/9
modify from RT55 to RT53
RT101 non-mount
2 0_0402_5% L3 F11
37 PD2_USBC_AMSEL PD2_DEBUG4 DEBUG3 RESET_N PD2_GPIO1 @ RT101 1
RT78 1 2 0_0402_5% K3 @ RT55 1 2 0_0402_5% 2 1M_0201_5%
37 PD2_USBC_EN DEBUG4 +3.3V_LDO_PD2
F10 @ RT54 1 2 0_0402_5%
BUSPOWER_N +1.8VD_LDO_PD2
F1 RT53 1 2 0_0402_5% PD2_GPIO2 RT102 1 2 1M_0201_5%
I2C_ADDR G2
R_OSC
1

H7

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SS

0.22U_0402_16V7K

15K_0402_1%
@ RT96

1
RT74 1 2 1K_0201_5% PD2_LSTX 0_0402_5%
1

CT27

RT88
TPS65982DCZQZR BGA 96P

A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H8
L1
L11
2

+3.3V_LDO_PD2
2

1
10K_0402_1%
RT105
30 PD2_HWRST
1

1
RT112 @ RT111
100K_0402_5% 0_0402_5%

2
PD2_GPIO8_EXT
2

1
100K_0402_1%
RT106
2
A For "-D" version only A

Factory Set Device Configurations 7

Infinite boot retry from Flash to Host I/F cycles.
DIV=RT106/(RT105+RT106)
between 0.7~1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P36-PD Controller TI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F371P
Date: Tuesday, November 07, 2017 Sheet 36 of 65
5 4 3 2 1
 5 4 3 2 1

USB-C Port-A USB-C Port-A

PCH DDI2
MUX+Redriver USB-C
UV1 RECEPTACLE

+3VS_MUX +3VS_MUX
PCH
+3VS_MUX +3VS_MUX
USB-C Port-B USB-C Port-B
PVT-003
MUX+Redriver USB-C

1
Due to SB00000DH00 will EOL, change to SB00000PV00
PARADE@ RV57 PARADE@ RV58 PVT-003
Due to SB00000DH00 will EOL, change to SB00000PV00
PARADE@ RV59 PARADE@ RV60
PCH DDI1 UV2 RECEPTACLE

2
1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%

2
MUX1_CSCL 1 6
UPD1_PS_SMBCLK MUX2_CSCL 1 6
UPD2_USH_SMBCLK
D UPD1_PS_SMBCLK 30,31,35 UPD2_USH_SMBCLK 30,36,43 D
+3VS PVT-042 +3VS_MUX +1.2V_MUX PARADE@ QC2A DMN66D0LDW-7_SOT363-6 PARADE@ QC3A DMN66D0LDW-7_SOT363-6
+1.2V_DDR +1.2V_MUX Change 0 ohm to short pad
SB00000PV00 SB00000PV00
PVT-042 RV2 @ RV91 1 2 0_0201_5% @ RV93 1 2 0_0201_5%
Change 0 ohm to short pad 1 @ 2
RV26 pop and RV14 de-pop for PS8743A
@PARADE@ RV26
RV26 de-pop and RV14 pop for PS8743B

5
0.1U_0201_10V6K

0.1U_0201_10V6K
1 2 0_0603_5%

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 MUX1_CSDA UPD1_PS_SMBDAT MUX2_CSDA UPD2_USH_SMBDAT

1
CV17

CV18

CV19

CV39
0_0603_5% 4 3 4 3
UPD1_PS_SMBDAT 30,31,35 UPD2_USH_SMBDAT 30,36,43
+3VS_MUX PARADE@ QC2B DMN66D0LDW-7_SOT363-6 PARADE@ QC3B DMN66D0LDW-7_SOT363-6

2
2 2
SB00000PV00 SB00000PV00
@ RV92 1 2 0_0201_5% @ RV94 1 2 0_0201_5%
+1.2V_MUX

1
PARADE@
RV73 +3VS_MUX
0_0402_5% close to UV1

1
+3VS_MUX PARADE@
dePOP RV73 RV61

2
pop RV74 forTUSB546 0_0402_5%
+1.2V_MUX
@TI@ RV14 1 2 0_0402_5% USBC1 MUX default H/W setting

0.1U_0201_10V6K
CV36
1 Parade : pop RV61

2
+3VS_MUX_UV1 MUX1_CEXT TI : pop RV19 CE_DP CE_USB FLIP TUSB456 Configuration VESA DisplayPot Alt Mode
MUX1_CEXT

1
@TI@ 1 2 0_0402_5% DFP_D Configuration
RV74 @TI@ RV19 L L L Power Down
0_0402_5% 2 L L H Power Down
1 2 2.2U_0402_6.3V6M L H L One Port USB 3.1 - No Flip
close to UV1 pin17 PARADE@ @TI@ CV61 L H H One Port USB 3.1 - With Flip

17

28
20
2

6
UV1 H L L 4 Lane DP - No Flip C and E
H L H 4 Lane DP - With Flip C and E

VDD33
VDD_DCI

VDD
VDD
VDD
H H L One Port USB 3.1 + 2Lane DP -No Flip D and F
CV24 0.1U_0201_10V6K DDI2_P1_TXP0_C H H H One Port USB 3.1 + 2Lane DP -With Flip D and F
5 PCH_DDI2_P0 1 2 9 30
CV25 0.1U_0201_10V6K DDI2_P1_TXN0_C ML0p RX1p USBC1_RX1P 40
1 2 10 31
5 PCH_DDI2_N0 ML0n RX1n USBC1_RX1N 40
CV26 0.1U_0201_10V6K DDI2_P1_TXP1_C USBC1_TX1P_C CV33 0.1U_0201_10V6K
1 2 12 33 1 2 USBC1_TX1P 40
5 PCH_DDI2_P1 DDI2_P1_TXN1_C ML1p TX1p USBC1_TX1N_C
CV28 1 2 0.1U_0201_10V6K 13 34 CV31 1 2 0.1U_0201_10V6K
5 PCH_DDI2_N1

CV30 1 2 0.1U_0201_10V6K DDI2_P1_TXP2_C

15
ML1n TX1n USBC1_TX1N 40
+3VS_MUX USB 3.0 AC Coupling Capacitor Topology
5 PCH_DDI2_P2 DDI2_P1_TXN2_C ML2p
CV32 1 2 0.1U_0201_10V6K 16 40
5 PCH_DDI2_N2 ML2n RX2p USBC1_RX2P 40 MUX1_ADDR PARADE@ RV6
39 1 2 4.7K_0402_5% USB
DDI2_P1_TXP3_C RX2n USBC1_RX2N 40 CABLE
CV34 1 2 0.1U_0201_10V6K 18 TUSB_MUX1_SSEQ1 USB3RP1 0.1u SSRXp USBC1_RX1P USBC1_RX1P
5
5
PCH_DDI2_P3
PCH_DDI2_N3
CV35 1 2 0.1U_0201_10V6K DDI2_P1_TXN3_C
19 ML3p 37
USBC1_TX2P_C CV27 1 2 0.1U_0201_10V6K
USBC1_TX2P 40
@TI@RV5 1 2 4.7K_0402_5% UV1 JUSBC1
ML3n TX2p USBC1_TX2N_C
36 CV29 1 2 0.1U_0201_10V6K USB3RN1 0.1u SSRXn
PS8743A USBC1_RX1N USBC1_RX1N

CV63 1 2 0.1U_0201_10V6K DDI2_P1_AUXP_C

24
TX2n
PVT-042
USBC1_TX2N 40
+3VS_MUX USB3TP1 0.1u SSTXp USBC1_TX1P 0.1u USBC1_TX1P
BME dock
5,35 PCH_DDI2_AUXP DDI2_P1_AUXN_C AUXp UV1_SBU1
CV64 1 2 0.1U_0201_10V6K 25 27 RV95 1 @ 2 0_0201_5% Change 0 ohm to short pad
5,35 PCH_DDI2_AUXN AUXn SBU1 UV1_SBU2 USBC1_SBU1 35,40
26 RV96 1 @ 2 0_0201_5% USB3TN1 0.1u SSTXn USBC1_TX1N 0.1u USBC1_TX1N
SBU2 USBC1_SBU2 35,40 TUSB1_USB_EQ0
@ RV27 1 2 1K_0402_5%

CV22 1 2 0.1U_0201_10V6K USB3RP1_C

5
@TI@ RV67
@TI@ RV68
1
1
2 0_0201_5%
2 0_0201_5%
TUSB1_USB_EQ0 TUSB1_USB_EQ0
TUSB1_USB_EQ1 TUSB1_USB_EQ1
TUSB1_USB_EQ0
@TI@
RV20 1 2 1K_0402_5%
PCH
9 USB3RP1 USB3RN1_C SSRXp
C CV23 1 2 0.1U_0201_10V6K 4 38 PARADE@ RV87 1 2 0_0201_5% USB3RP3 0.1u C
9 USB3RN1 SSRXn FLIP PD1_USBC_POL 35
35 PARADE@ RV88 1 2 0_0201_5% SSRXp USBC1_RX1P USBC2_RX1P
CE_USB
23
PD1_USBC_EN
PD1_USBC_AMSEL
35
35
+3VS_MUX USB3RN4 0.1u UV2 JUSBC2
USB3TP1_C CE_DP
9 USB3TP1
CV20
CV21
1
1
2
2
0.1U_0201_10V6K
0.1U_0201_10V6K USB3TN1_C
8
7
SSTXp
dePOP RV87,RV88 USB3TP4 0.1u
SSRXn
PS8743A USBC1_RX1N USBC2_RX1N
9 USB3TN1 SSTXn pop RV67,RV68 forTUSB546 TUSB1_USB_EQ1 0.1u
@ RV28 1 2 1K_0402_5% SSTXp USBC1_TX1P USBC2_TX1P
PVT-042 MUX1_I2C_EN TUSB1_USB_EQ1 USB3TN4 0.1u 0.1u
29
Change 0 ohm to short pad I2C_EN MUX1_ADDR SSTXn USBC1_TX1N USBC2_TX1N
3 @TI@
RV21 1 2 1K_0402_5%
RV11 SW_DP2_HPD_UV1 DCICFG/ADDR
1 @ 2 0_0201_5% 32
5,30,35 CPU_DP2_HPD IN_HPD
CDE/DCI_CLK
14
11
MUX1_TUSB_DPEQ0
MUX1_TUSB_SSEQ0
ADDR=High
SSDE/DCI_DATA
MUX1_REXT MUX1_CSCL @TI@ RV65 PD1_USBC_POL UV1_SBU1
2 21 1 2 0_0201_5% TUSB1_FLIP RV18 1 2 2M_0201_5%
REXT DPEQ/CSCL MUX1_CSDA @TI@ RV66 PD1_USBC_EN
22 1 2 0_0201_5% TUSB1_USB/AMSL
CEQ/CSDA UV1_SBU2 RV17
41 1 2 2M_0201_5%
Thermal pad
1

PARADE@ PH
RV16 DDI2_P1_AUXN_C 100k
1 2 100K_0201_5% RV7 PS8743AQFN40GTR-B1_QFN40_4X6
+3VS_MUX
4.99K_0402_1% +3VS_MUX
+3VS_MUX +3VS_MUX +3VS_MUX
RV15 1 2 100K_0201_5%
DDI2_P1_AUXP_C EVT use PS8743A_B0
2

MUX1_I2C_EN
CPN SA00009YO00 PARADE@ RV13 1 2 4.7K_0402_5%
POP RV75 POP RV77 POP RV79
DVT1 use PS8743A_B1

2
@ RV12 1 2 4.7K_0402_5% forTUSB546 forTUSB546 forTUSB546 0R
@ RV75 @ RV77 @ RV79 DDI2_AUXP PCH_DDI2_AUXP 0.1u DDI2_P1_AUXP_C AUXp SBU1 UV1_SBU1 USBC1_SBU1 USBC1_SBU1
CPN SA00009YO10 1K_0201_5% 1K_0201_5% 1K_0201_5%
UV1 0R
Deafult use I2C DDI2_AUXN PCH_DDI2_AUXN 0.1u DDI2_P1_AUXN_C
PS8743A UV1_SBU2 USBC1_SBU2 JUSBC1

1
MUX1_REXT MUX1_TUSB_DPEQ0 MUX1_TUSB_SSEQ0 AUXn SBU2 USBC1_SBU2
TUSB_MUX1_DPEQ1 TUSB_MUX1_DPEQ0 TUSB_MUX1_SSEQ0 0R
DDPC_HPD1 CPU_DP2_HPD SW_DP2_HPD_UV1

2
PH PD IN_HPD
@TI@ RV76 @TI@ RV78 @TI@ RV80 @100k 100k 2M 2M
1K_0201_5% 1K_0201_5% 1K_0201_5%
ESD ESD

1
+3VS_MUX @0R
@0.1u PD1_AUX_P AUXp SBU1 PD1_SBU1
+3VS_MUX +1.2V_MUX UT1
@0.1u PD1_AUX_N
TPS65982 PD1_SBU2
@0R
1

PARADE@ AUXn SBU2

0.1U_0201_10V6K
RV71 0R

0.1U_0201_10V6K
0_0402_5% +1.2V_MUX PCH_DP2_HPD_UT1
RV43 de-pop for 8743A 1

CV60
PD PD1_GPIO4
1
RV42 pop for PS8743B

CV42
@100k
2

dePOP RV71 +1.2V_MUX +3VS_MUX

B
pop RV72 forTUSB546 +3VS_MUX
2
2
USBC2 MUX default H/W setting PH
1M to +1.8VA_EC B
1

@TI@ RV42 1 2 0_0402_5% PARADE@ CE_DP CE_USB FLIP TUSB456 Configuration VESA DisplayPot Alt Mode
1

DFP_D Configuration
0.1U_0201_10V6K
CV57

@TI@ RV62 PD PH
RV72
0_0402_5%
1 +3VS_MUX_UV2 MUX2_CEXT 0_0402_5%
Parade : pop RV62 depop-RV43
close to UV2 L
L
L
L
L
H
Power Down
Power Down
100k 1M to +1.8VA_EC

TI : pop RV43 de-pop RV62 L H L One Port USB 3.1 - No Flip

2

2 MUX2_CEXT
1 2 0_0402_5% L H H One Port USB 3.1 - With Flip
2

@TI@ RV43 H L L 4 Lane DP - No Flip C and E

close to UV2 pin17 PARADE@ H L H 4 Lane DP - With Flip C and E
17

28
20
1

UV2 @TI@ CV62 1 2 2.2U_0402_6.3V6M H H L One Port USB 3.1 + 2Lane DP -No Flip D and F 0R
H H H One Port USB 3.1 + 2Lane DP -With Flip D and F PCH CPU_DP1_HPD UPD1_HPD_R UPD1_HPD
VDD33
VDD_DCI

VDD
VDD
VDD

CV45 0.1U_0201_10V6K DDI1_P2_TXP0_C +3VS_MUX

1 2 9 30
5 DDI1_P2_TXP0 DDI1_P2_TXN0_C ML0p RX1p USBC2_RX1P 40
CV47 1 2 0.1U_0201_10V6K 10 31
5 DDI1_P2_TXN0 ML0n RX1n USBC2_RX1N 40 MEC5105
CV49 0.1U_0201_10V6K DDI1_P2_TXP1_C USBC2_TX1P_C CV56 0.1U_0201_10V6K MUX2_ADDR @ RV32 0R
1 2 12 33 1 2 USBC2_TX1P 40 1 2 4.7K_0402_5%
5 DDI1_P2_TXP1 DDI1_P2_TXN1_C ML1p TX1p USBC2_TX1N_C
CV50 1 2 0.1U_0201_10V6K 13 34 CV54 1 2 0.1U_0201_10V6K USBC2_TX1N 40 TUSB_MUX2_SSEQ1 CPU_DP2_HPD UPD2_HPD_R UPD2_HPD
5 DDI1_P2_TXN1 ML1n TX1n RV31 1 2 4.7K_0402_5%
CV51 0.1U_0201_10V6K DDI1_P2_TXP2_C
1 2 15
5 DDI1_P2_TXP2 CV52 0.1U_0201_10V6K DDI1_P2_TXN2_C ML2p
1 2 16 40
5 DDI1_P2_TXN2 ML2n RX2p USBC2_RX2P 40
39
DDI1_P2_TXP3_C RX2n USBC2_RX2N 40
CV53 1 2 0.1U_0201_10V6K 18 +3VS_MUX
5 DDI1_P2_TXP3 CV55 0.1U_0201_10V6K DDI1_P2_TXN3_C ML3p USBC2_TX2P_C CV46 0.1U_0201_10V6K PH
1 2 19 37 1 2
5 DDI1_P2_TXN3 ML3n TX2p USBC2_TX2N_C USBC2_TX2P 40 100k
36 CV48 1 2 0.1U_0201_10V6K
TX2n USBC2_TX2N 40 TUSB2_USB_EQ0
@ RV34 1 2 1K_0402_5%
CV58 0.1U_0201_10V6K PCH_DDI1_AUXP_C TUSB2_USB_EQ0
1 2 24
5,36 PCH_DDI1_AUXP PCH_DDI1_AUXN_C AUXp UV2_SBU1
CV59 1 2 0.1U_0201_10V6K 25 27 RV97 1 @ 2 0_0201_5% RV35 1
@TI@ 2 1K_0402_5%
5,36 PCH_DDI1_AUXN AUXn SBU1 UV2_SBU2 USBC2_SBU1 36,40
26 RV98 1 @ 2 0_0201_5%
SBU2 USBC2_SBU2 36,40
PVT-042 +3VS_MUX 0R
CV43 0.1U_0201_10V6K USB3RP4_C Change 0 ohm to short pad DDI1_AUXP PCH_DDI1_AUXP 0.1u PCH_DDI1_AUXP_C AUXp SBU1 UV2_SBU1 USBC2_SBU1 USBC2_SBU1
9 USB3RP4 1 2 5
CV44 0.1U_0201_10V6K USB3RN4_C SSRXp TUSB2_USB_EQ0 PARADE@ RV90 0_0201_5%
1 2 4 38 1 2
9 USB3RN4 SSRXn FLIP
35
TUSB2_USB_EQ1 PARADE@ RV89 1 2 0_0201_5%
PD2_USBC_POL 36 TUSB2_USB_EQ1
@ RV37 1 2 1K_0402_5% UV2 0R
CE_USB 23
PD2_USBC_EN
PD2_USBC_AMSEL 36
36
TUSB2_USB_EQ1 DDI1_AUXN PCH_DDI1_AUXN 0.1u PCH_DDI1_AUXN_C
PS8743A UV2_SBU2 USBC2_SBU2 JUSBC2
CV40 0.1U_0201_10V6K USB3TP4_C CE_DP AUXn SBU2 USBC2_SBU2
9 USB3TP4 1 2 8 @TI@
RV38 1 2 1K_0402_5%
CV41 0.1U_0201_10V6K USB3TN4_C SSTXp 0R
9 USB3TN4 1 2 7
SSTXn DDPB_HPD0 CPU_DP1_HPD PCH_DP1_HPD_UV2
dePOP RV89,RV90
PVT-042 MUX2_I2C_EN forTUSB546 +3VS_MUX PH IN_HPD
29 PD
Change 0 ohm to short pad I2C_EN MUX2_ADDR @100k 2M 2M
3 100k
RV39 PCH_DP1_HPD_UV2 DCICFG/ADDR
1 @ 2 0_0201_5% 32
5,30,36 CPU_DP1_HPD IN_HPD
CDE/DCI_CLK
14
11
MUX2_TUSB_DPEQ0
MUX2_TUSB_SSEQ0
ADDR=Low PD2_USBC_AMSEL
@ RV53 1 2 1K_0402_5% ESD ESD

SSDE/DCI_DATA
@TI@
RV50 1 2 1K_0402_5%
MUX2_REXT MUX2_CSCL @TI@ RV69 PD2_USBC_POL
2 21 1 2 0_0201_5% TUSB2_FLIP
REXT DPEQ/CSCL MUX2_CSDA @TI@ RV70 PD2_USBC_EN
22 1 2 0_0201_5% TUSB2_USB/AMSL @0R
CEQ/CSDA @0.1u PD2_AUX_P AUXp SBU1 PD2_SBU1
41
Thermal pad
POP RV69,RV70
UV2_SBU1 RV47 1 2 2M_0201_5% UT2
1

PARADE@
RV30 PS8743AQFN40GTR-B1_QFN40_4X6
forTUSB546
UV2_SBU2 RV46 1 2 2M_0201_5% @0.1u PD2_AUX_N
TPS65982 PD2_SBU2
@0R

RV45 PCH_DDI1_AUXN_C
1 2 100K_0201_5% 4.99K_0402_1% AUXn SBU2
+3VS_MUX
A 0R A
EVT use PS8743A_B0 PCH_DP1_HPD_UT2
2

PCH_DDI1_AUXP_C
RV44 1 2 100K_0201_5% CPN SA00009YO00 +3VS_MUX
+3VS_MUX +3VS_MUX +3VS_MUX
PD
@100k
PD2_GPIO4

DVT1 use PS8743A_B1 MUX2_I2C_EN PARADE@ RV41

CPN SA00009YO10 1 2 4.7K_0402_5%
POP RV81 POP RV83 POP RV85
2

@ RV40 1 2 4.7K_0402_5% forTUSB546 forTUSB546 forTUSB546

@ RV81 @ RV83 @ RV85 PD
1K_0201_5% 1K_0201_5% 1K_0201_5% 100k
Deafult use I2C
1

MUX2_REXT MUX2_TUSB_DPEQ0 MUX2_TUSB_SSEQ0

TUSB_MUX2_DPEQ1 TUSB_MUX2_DPEQ0 TUSB_MUX2_SSEQ0
2

@TI@ RV82 @TI@ RV84 @TI@ RV86

1K_0201_5% 1K_0201_5% 1K_0201_5% Security Classification
2015/10/22
Compal Secret Data
2013/10/28 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
P37-MUX Re-Driver
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F371P
Date: Tuesday, November 07, 2017 Sheet 37 of 65
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P38-DDI WiGig MUX
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F371P
Date: Tuesday, November 07, 2017 Sheet 38 of 65
5 4 3 2 1
 5 4 3 2 1

PVT-019
D Remove co-lay R134, R135, R133, R131, R129, R128 D

ML6 EMC@
USB20_P9_PS 4 3 USB20_P9_CONN
4 3

USB20_N9_PS 1 2 USB20_N9_CONN
1 2
DLW21HN900HQ2L_4P close to CONN

close to JUSB1
ML5
C111 1 2 0.1U_0201_10V6K USB3TP3_C 1 2 USB3TP3_CONN
9 USB3TP3
2.0A
C110 1 2 0.1U_0201_10V6K USB3TN3_C 4 3 USB3TN3_CONN
9 USB3TN3
+5V_USB_P1
CMMI21T-670Y-N_4P
EMC@

47U_0805_6.3V6M

47U_0805_6.3V6M

0.1U_0201_10V6K
1 1 1

C114

C113

C115
2 2 2

ML4 EMC@
1 2 USB3RP3_CONN
9 USB3RP3
C C

4 3 USB3RN3_CONN
9 USB3RN3

CMMI21T-670Y-N_4P

+3V_5105

+5VALW USB_DET# @ R449 1 2 100K_0402_5%

1U_0402_6.3V6K

2.1A / Channel
10U_0402_6.3V6M

1
1

C29

C27
2

USB Power Share USB TYPE-A CONN

+5VALW +5V_USB_P1 +5V_USB_P1

US1 JUSB1
1 12 1
IN OUT USB20_P9_CONN 3 VBUS
USB20_N9_CONN D+
9 USB20_N9 2 2
3 DM_OUT USB3RP3_CONN 6 D-
9 USB20_P9 DP_OUT USB20_P9_PS USB3RN3_CONN SSRX+
10 5
13 DP_IN 11 USB20_N9_PS USB3TP3_CONN 9 SSRX-
9 USB_OC2# FAULT# DM_IN USB3TN3_CONN SSTX+
8 11
USB_ILIM_SEL1 USB_DET# SSTX- GND
+5VALW R54 1 2 10K_0402_5% 4
T42 @ PAD~D 10 12
B ILIM_SEL PVT-007 4 DP GND 13 B
5 15 Change R56 from 30k to 23.2k for current limit 7 GND GND 14
30 USB_POWERSHARE_VBUS_EN EN ILIM_LO GND GND
16
ILIM_HI
@ R51 1 2 1M_0402_5% TAIWI_USB036-10B7CRL-TW
1

30 USB_POWERSHARE_EN#
6 CONN@
7 CTL1 9 R56
R50 2 1 100K_0402_5% 8 CTL2 NC 14 23.2K_0402_1%
+5VALW CTL3 GND
17
GNDP
2

TPS2544RTER_WQFN16_3X3
+5V_USB_P1
For ESD request
MD1
USB3RN3_CONN 1 8
USB3RP3_CONN 2 R- VCC 7
USB3TN3_CONN 3 R+ GND 6 USB20_P9_CONN
CTL1 CTL2 CTL3 ILIM_SEL MODE USB3TP3_CONN 4
T- D-
5 USB20_N9_CONN
T+ D+
AZ1065-06Q.RDG_MSOP8
0 1 1 0 DCP_Auto EMC@
0 1 1 1 DCP_Auto
1 1 1 0 SDP
1 1 1 1 CDP

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P39-VUBS Provider-Type-A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F371P
Date: Tuesday, November 07, 2017 Sheet 39 of 65
5 4 3 2 1
 5 4 3 2 1

+VBUS1_PD_20V +VBUS1_PD_20V +VBUS2_PD_20V +VBUS2_PD_20V

ESD218-B1-02ELS TSSLP-2-4

ESD218-B1-02ELS TSSLP-2-4
10U_0603_25V6M

0.1U_0402_25V6

0.1U_0402_25V6

10U_0603_25V6M
1 1 1 1

1
D71
CT1

C165

C202

CT4

D82
turn part EVT only 2 2
turn part EVT only 2 2

EMC@
DX07SA24XJ2R1000 +VBUS2_PD_20V DX07SA24XJ2R1000 +VBUS2_PD_20V

EMC@
+VBUS1_PD_20V +VBUS1_PD_20V

2
D D

JUSBC2
JUSBC1 A1 B12
GND GND
A1 B12
GND GND USBC2_TX1P A2 B11 USBC2_RX1P
USBC1_TX1P USBC1_RX1P 37 USBC2_TX1P USBC2_TX1N SSTXP1 SSRXP1 USBC2_RX1N USBC2_RX1P 37
A2 B11 A3 B10
37 USBC1_TX1P USBC1_TX1N SSTXP1 SSRXP1 USBC1_RX1N USBC1_RX1P 37 37 USBC2_TX1N SSTXN1 SSRXN1 USBC2_RX1N 37
A3 B10
37 USBC1_TX1N SSTXN1 SSRXN1 USBC1_RX1N 37
C195 1 2 A4 B9 2 1 C199
C159 1 2 A4 B9 2 1 C160 0.01U_0201_25V6K VBUS VBUS 0.01U_0201_25V6K
0.01U_0201_25V6K VBUS VBUS 0.01U_0201_25V6K USBC2_CC1 A5 B8 USBC2_SBU2
USBC1_CC1 USBC1_SBU2 36 USBC2_CC1 CC1 RFU2 USBC2_SBU2 36,37
A5 B8
35 USBC1_CC1 CC1 RFU2 USBC1_SBU2 35,37 USBC2_TOP_DP1 USBC2_BOT_DN2
A6 B7
USBC1_TOP_DP1 A6 B7 USBC1_BOT_DN2 USBC2_TOP_DN1 A7 DP1 DN2 B6 USBC2_BOT_DP2
USBC1_TOP_DN1 DP1 DN2 USBC1_BOT_DP2 DN1 DP2

Bottom
A7 B6
DN1 DP2 USBC2_SBU1 USBC2_CC2

Bottom
A8 B5
USBC1_SBU1 USBC1_CC2 36,37 USBC2_SBU1 RFU1 CC2 USBC2_CC2 36

TOP
A8 B5
35,37 USBC1_SBU1 RFU1 CC2 USBC1_CC2 35

TOP
C192 1 2 A9 B4 2 1 C197
C163 1 2 A9 B4 2 1 C161 0.01U_0201_25V6K VBUS VBUS 0.01U_0201_25V6K
0.01U_0201_25V6K VBUS VBUS 0.01U_0201_25V6K USBC2_RX2N USBC2_TX2N
37 USBC2_RX2N A10 B3 USBC2_TX2N 37
USBC1_RX2N A10 B3 USBC1_TX2N USBC2_RX2P A11 SSRXN2 SSTXN2 B2 USBC2_TX2P
37 USBC1_RX2N USBC1_RX2P SSRXN2 SSTXN2 USBC1_TX2P USBC1_TX2N 37 37 USBC2_RX2P SSRXP2 SSTXP2 USBC2_TX2P 37
A11 B2
37 USBC1_RX2P SSRXP2 SSTXP2 USBC1_TX2P 37
A12 B1
A12 B1 GND GND
GND GND
JUSBC2_GND 1 4 JUSBC2_GND
JUSBC1_GND 1 4 JUSBC1_GND GND GND

1
GND GND
1 2 3
1

LT2 GND GND

1 2 3 EMC@
LT1 GND GND CT3 HCB2012KF-121T50_2P
EMC@ EMC@
EMC@ CT2 HCB2012KF-121T50_2P 0.1U_0402_25V6 JAE_DX07S024XJ2
0.1U_0402_25V6 JAE_DX07S024XJ2 2 CONN@
2 CONN@

2
2

D55 EMC@ D58 EMC@

C C
PVT-020 USBC2_TX1P 1 2 1 2 USBC2_RX2N
Remove co-lay R521, R520, R515, R514, R517, R516, R519, R518

D48 EMC@ D52 EMC@ ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

ML9 ML12
USBC1_TX1P 1 2 1 2 USBC1_RX2N 1 2 USBC1_BOT_DN2 1 2 USBC2_TOP_DP1 D56 EMC@ D59 EMC@
35 USBC1_BN2_L 36 USBC2_TP1_L
USBC2_TX1N 1 2 1 2 USBC2_RX2P
ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 4 3 USBC1_BOT_DP2 4 3 USBC2_TOP_DN1
35 USBC1_BP2_L 36 USBC2_TN1_L
D49 EMC@ D53 EMC@ MCM1012B900F06BP_4P MCM1012B900F06BP_4P ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2
EMC@ EMC@
USBC1_TX1N 1 2 1 2 USBC1_RX2P D80 EMC@ D87 EMC@
USBC2_RX1P 1 2 1 2 USBC2_TX2N
ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

D68 EMC@ D76 EMC@ ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

USBC1_RX1P 1 2 1 2 USBC1_TX2N D81 EMC@ D88 EMC@

ML10 ML11
1 2 USBC1_TOP_DP1 1 2 USBC2_BOT_DN2 USBC2_RX1N 1 2 1 2 USBC2_TX2P
35 USBC1_TP1_L 36 USBC2_BN2_L
ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

D70 EMC@ D78 EMC@ 4 3 USBC1_TOP_DN1 4 3 USBC2_BOT_DP2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2
35 USBC1_TN1_L 36 USBC2_BP2_L
USBC1_RX1N 1 2 1 2 USBC1_TX2P MCM1012B900F06BP_4P MCM1012B900F06BP_4P
EMC@ EMC@

ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

D50 EMC@ D69 EMC@ D54 EMC@ D79 EMC@

USBC1_CC1 1 2 1 2 USBC1_SBU2 USBC2_CC1 1 2 1 2 USBC2_SBU2

ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

B B
D74 EMC@ D72 EMC@ D85 EMC@ D83 EMC@
USBC1_TOP_DP1 1 2 1 2 USBC1_BOT_DN2 USBC2_TOP_DP1 1 2 1 2 USBC2_BOT_DN2

ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

D75 EMC@ D73 EMC@ D86 EMC@ D84 EMC@

USBC1_TOP_DN1 1 2 1 2 USBC1_BOT_DP2 USBC2_TOP_DN1 1 2 1 2 USBC2_BOT_DP2
Pin12
Pin1 USB Type-C Receptacle Interface (Front View)
ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

D51 EMC@ D77 EMC@ A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D57 EMC@ D89 EMC@
USBC1_SBU1 1 2 1 2 USBC1_CC2 USBC2_SBU1 1 2 1 2 USBC2_CC2
GND TX1+ TX1- VBUS CC1 D+ D- SBU1 VBUS RX2- RX2+ GND
ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2 ESD8011MUT5G X3DFN2

GND RX1+ RX1- VBUS SBU2 D- D+ CC2 VBUS TX2- TX2+ GND
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
Printed Circuit Board
Pin13
Pin24

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P40-TYPE-C USBC1/2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F371P
Date: Tuesday, November 07, 2017 Sheet 40 of 65
5 4 3 2 1
 5 4 3 2 1

Tunnable IC RF conn for WWAN

JANT7
EMI_Spring

D D
CONN@
+3VALW PVT-043 +3V_RF
Change 0 ohm to short pad L81 JANT2

1
JANT3
2 1 50OHM traces 1 2 50OHM traces 1

1
GND_2 1 1
3
R82 GND_3 1.8NH +-0.1NH LQP03TN1N8B02D
1 @ 2 0_0201_5% 4
GND_4 EMI_Spring
@ @

1
CONN@

2P_0201_25V8B
C9

2P_0201_25V8B
C1039
BELLW_10093-1021
CONN@

2
L80

10
U10
1 2 1.8NH +-0.1NH LQP03TN1N8B02D

COM
1 9 @ L13 1 2 22NH_LQG15HS22NJ02D_5%
+3V_RF C47 RF1 RF3
1 2 2 8 L14 1 2 22NH_LQG15HS22NJ02D_5%
RF2 RF4

4.3P_0402_50V8
3 7
GND_01 GND_02

GPIO0
R81 1 @ 2 0_0201_5% 4 6 L17 1 2 BLM15AG121SN1D_L0402_2P
VDD GPIO1
PVT-043
Change 0 ohm to short pad ANTCTRL1_L R87 1 2 0_0201_5%
1 ANTCTRL1 25

5
EC646_LGA10_1P1X1P5
C48
L16 1 2 BLM15AG121SN1D_L0402_2P ANTCTRL0_L R86 1 2 0_0201_5%
0.1U_0201_10V6K ANTCTRL0 25
2

+3V_RF +3V_RF

Truth Table
C GPIO0 GPIO0 RF1 RF2 RF3 RF4 C

1
@ R83 @ R88
0_0201_5% 0_0201_5%
L L ON OFF OFF OFF

2
L H OFF ON OFF OFF ANTCTRL1_L ANTCTRL0_L

H L OFF OFF ON OFF

1
@ R85 @ R84
H H OFF OFF OFF ON 0_0201_5% 0_0201_5%

2
B B

+3V_5105
1

R474
10K_0402_5%
1 2

USH_DET 30
R480 C
2 1 2 MMBT3904WH_SOT323-3
5,43 USH_DET#
B Q31
220K_0201_5% E USH_DET
3
1

@ R481 H = USH present

300K_0201_5% L = USH not present
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P41-RF Tunable IC / I/O Expander
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 41 of 65
5 4 3 2 1
 A B C D E

+3V_5105

+3V_5105

SCREW HOLE @ RE118 1 2 100K_0201_5% KICKSTD_SW_DET#

Kickstand detect SW

1
RE123
4.99K_0201_1%
FD1 FD3 FD2 FD4
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL H16 H17 CLIP1 CLIP2 CLIP13

2
@ @ 1 1 1
1 1 1
H_1P5N H_1P5N
EMI_Spring EMI_Spring EMI_Spring KICKSTD_SW_DET#
8,30 KICKSTD_SW_DET# Deafult Close High
1

1
CONN@ CONN@ CONN@ POP RE123,R488
de-pop RE118,R490
Open Low

4
1 1
H1 H2 H3 H4 H12 for cable routing SW5
BTE-PQR2_4P
@ @ @ @ @
H_2P3 H_2P3 H_2P3 H_2P3 H_3P6 Close Low
1

1
H14 H15
de-POP RE123,R488

3
@ @
High POP RE118,R490
R488 R490
H_6P0N H_6P0N Open
H6 H7 H8 H9 1 2 1 2

1
@ @ @ @
43K_0201_1% 100K_0201_5%
H_2P3 H_4P0 H_4P0 H_2P3
1

@
for WLAN/WWAN Volume Up But t on SW1
TAFG3-12WQR_3P
H10 H11 H5 H13 1
@ @ @ @ R23 1 2 1K_0201_5% VOLUME_UP# 2
30 VOL_UP#
H_3P3 H_3P3 H_3P3 H_3P3 3
1

1
0.1U_0201_10V6K

7
6
5
4
D20
1

C19
ESD207-B1-02EL_TSLP-2-19-2
EMC@
2

2
CLIP3 CLIP4 CLIP5 CLIP6 CLIP7
1 1 1 1 1
1 1 1 1 1
EMI_Spring EMI_Spring EMI_Spring EMI_Spring EMI_Spring
CONN@ CONN@ CONN@ CONN@ CONN@

CLIP8 CLIP9 CLIP10 CLIP11 CLIP12 CLIP14

PU 10K resistor locate on EC side
1 1 1 1 1 1
1 1 1 1 1 1
2 2
EMI_Spring EMI_Spring EMI_Spring EMI_Spring EMI_Spring EMI_Spring
CONN@ CONN@ CONN@ CONN@ CONN@ CONN@
Volume Down But t on SW2
TAFG3-12WQR_3P
1
R24 1 2 1K_0201_5% VOLUME_DOWN# 2
for M.2 SSD/WLAN/WWAN shielding clip 30 VOL_DOWN#
3

0.1U_0201_10V6K

1
1

7
6
5
4
C20
D21
ESD207-B1-02EL_TSLP-2-19-2
EMC@
2

2
+RTCVCC +RTCVCC_EC
@ R2751
0_0402_5%
1 2

Q349
DMG2301U-7_SOT23-3

1 3
D

PCB footprint
1

SATA LED
RB520SM-30T2R_EMD2-2
1U_0402_6.3V6K~D

G
2
1

D116
C1040

R5768 RB751S40T1G_SOD523-2
3 2 10K_0402_5% 3
2 1
2

R5779
1

D R5769
0_0201_5%
DII-DMN65D8LW-7 RTCRST_ON_R
2 1 2 1 2 RTCRST_ON 30
Q348 G
S
3

1M_0402_5%~D
0.1U_0402_25V6K~D
1
22P_0402_50V8J

100K_0201_1%

1
1

R2745

C1131
C1132
2

2
@
2

+3.3V_TBAT_LDO +3V_LDO +RTCBATT

RTC
BAT54HT1G_SOD323-2

BAT54HT1G_SOD323-2

W=20mils W=20mils W=20mils

2

RTCD2 RTCD1
RTCR1
1.2K_0402_5%
+RTCBATT
1

4 4
JRTC1
1
2 1
2

+RTCVCC_EC 3
W=20mils G1
1 4
C112 G2
1U_0402_6.3V6K ACES_50278-00201-001
CONN@
2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P42-RTC, VOL SW, SCREWH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 42 of 65
A B C D E
 5 4 3 2 1

+RTCVCC_EC +RTCVCC_EC

+3VALW

1
RE267 +3VALW
100K_0201_5% RE268
100K_0201_5%

2
1 6 1 2 BAT1_LED#_USH
30 BAT1_LED# 4 3 1 2 BAT2_LED#_USH
30 BAT2_LED#
D113
Q354A
RB751S40T1G_SOD523-2 D114

USH CONN
DMN2400UV-7_SOT-563-6 PCB footprint Q354B
RB751S40T1G_SOD523-2
RB520SM-30T2R_EMD2-2 DMN2400UV-7_SOT-563-6 PCB footprint
RB520SM-30T2R_EMD2-2

B+_USH +5VS_USH +5VD_USH +3VS_USH +3VALW_USH

Docking CONN FAN CONN D

PVT-044 PVT-044
JIO2 +3VS Change 0 ohm to short pad +3V_FAN +5VS Change 0 ohm to short pad +5V_FAN
Change 0.01 ohm to short pad Change 0.01 ohm to short pad
1
JIO1 1
2
1
1 2
2 4/15 add pin2 to GND 3 2
3
R443 1 @ 2 0_0402_1% R445 1 @ 2 0_0402_1%
3 4 4
5 3 4 6 DET_R 5 4 +3VALW +5VD
5 6 48 DET_R 5
7 8 6
7 8 BASE_SMBCLK 6
9 10 30 BASE_SMBCLK 7
11 9 10 12 BASE_SMBDAT 8 7 @ R444 1 2 0_0402_5% @ R446 1 2 0_0402_5%
11 12 30 BASE_SMBDAT 8
13 14 9
15 13 14 16 10 9
BCM5882_ALERT# 15 16 REM_DIODE3_N 30 9 USB20_N2 10
17 18 11
30 BCM5882_ALERT# USH_RST# 17 18 HOME_KEY# REM_DIODE3_P 30 9 USB20_P2 11 +3V_FAN +5V_FAN
19 20 12
30 USH_RST# USH_PWR_STATE# 19 20 POWER_SW_IN# HOME_KEY# 30 BASE_SMB_ALERT# 12
21 22 13 PVT-008 PVT-044
30 USH_PWR_STATE# CONTACTLESS_DET# 21 22 LID_CL_SIO# POWER_SW_IN# 30,49 30 BASE_SMB_ALERT# DET_L# 13 For PWM_FAN1 GPIO solution Change 0 ohm to short pad
11 CONTACTLESS_DET#
23 24 LID_CL_SIO# 30 30,48 DET_L# 14 Change 0.01 ohm to short pad
SUS_ON_EC 25 23 24 26 15 14
30,32,45,53 SUS_ON_EC POA_WAKE# 27 25 26 28 16 15

10K_0402_5%~D

10K_0402_5%~D
30 POA_WAKE# 27 28 USB20_P10 9 +5V_DOCK 16
EC_FPM_EN

10K_0402_5%~D
29 30 17
30 EC_FPM_EN USB20_N10 9

1
BAT1_LED#_USH 29 30 17

@ R29
31 32 18 C21
31 32
2A 18 2

R27

R28
BAT2_LED#_USH

0_0402_1%
33 34 19 0.1U_0402_25V6K~D
UPD2_USH_SMBCLK 33 34 19

R438
30,36,37 UPD2_USH_SMBCLK
35 36 20 @
UPD2_USH_SMBDAT 37 35 36 38 21 20 JFAN1
30,36,37 UPD2_USH_SMBDAT 37 38 21 1
39 40 22 6
USH_DET# 5,41

2
39 40 23 22 5 G2
23 PCB footprint G1
41 42 24 4
43 GND1 GND2 44 25 24 RB520SM-30T2R_EMD2-2
3 4
GND3 GND4 25 30 PWM_FAN1 3
26 2 1 2
26 30 TACH_FAN1 2
27 1
JAE_WP7B-S040VA1-R6000 27 1
28 D22
28 CONN@
CONN@ 29 31 RB751S40T1G_SOD523-2 1
30 29 GND 32 @ ACES_50224-00401-001
30 GND C1120
C ACES_51522-03001-P01 100P_0402_50V8J C
UPD2_USH_SMBCLK CONN@ 2
UPD2_USH_SMBDAT BASE_SMBCLK
HOME_KEY# BASE_SMBDAT
check current rating
10P_0201_25V8
@EMC@

10P_0201_25V8
@EMC@

10P_0201_25V8
@EMC@

10P_0201_25V8
@EMC@

10P_0201_25V8
@EMC@
1 1 1 0.3A per pin 1 1

follow 3/29 USH pin-define

C219

C220

C221

C222

C223
2 2 2 2 2

UART ESPI
BIOS debug BIOS debug
JUART RFQ-034
1 change LPC to ESPI mode +3VS
8 UART2_RTS# 1
2 JESPI1
8 UART2_TXD 2
3 1

IR CAM CONN
8 UART2_RXD 3 1
4 2
8 UART2_CTS# 4 2
3
5
7,30 ESPI_IO0 4 3
PVT-044 GND 7,30 ESPI_IO1 4
6 5
Change 0 ohm to short pad GND 7,30 ESPI_IO2 5
6
Change 0.01 ohm to short pad 7,30 ESPI_IO3 6
CVILU_CI1804M1VRA-NH 7
7,30 ESPI_CS# 7
+5VALW_IR @CONN@ @ RE193 1 20_0402_5% 8
10,22,23,24,25,27,30,31,32,34PLT_RST# 8
R266 9
+3VALW QZ9 0_0603_5% JIR1 9
7,30 ESPI_CLK 10
DMG2301U-7_SOT23-3 +3VS_IR_R +3VS_IR 10
+5VALW 1 @ 2 1
2 1
2
S

3 1 1 @ 2 3 11
R223 0_0603_5% 4 3 12 GND1
11 CAM_CBL_DET# 4 GND2
PVT-044 5
B 2 Change 0 ohm to short pad 5 B
6
G

Change 0.01 ohm to short pad

2

C236 7 6 ACES_50521-01041-P01
R5778 1 7
0.1U_0201_10V6K 2 0_0201_5% 3.3V_IRCAM_EN# 10 8 CONN@
1 USB20_P5_CONN 9 8
USB20_N5_CONN 9
1 10
@ C1133 11 10
+3VS_IR 11
0.1U_0201_10V6K 12
12
13
2 14 GND
GND
ACES_50208-01201-P01
CONN@
+3VS_IR

+5VS +5VS_USH +3VS +3VS_USH

10U_0402_6.3V6M

0.1U_0201_10V6K

0.1U_0201_10V6K

68P_0402_50V8J
EMC@ C1034

1 1 1
1

U4247 U4249
1U_0201_6.3V6M

1U_0201_6.3V6M
C1035

C1036

C1037

1U_0201_6.3V6M

1U_0201_6.3V6M
1 6 1 1 6 1
2

2 2 2 EMC@ IN OUT IN OUT

1 1
C1121

EMC@ C1126

C1123

EMC@ C1128
1 R5751 2 5 2 EMC@ 1 R5753 2 5 2
20K_0201_5% SET GND 20K_0201_5% SET GND
EMC@

2 EMC@ 1 R5755 2 4 3 2 1 R5757 2 4 3 PVT-009

EN(/EN) FLAG EN(/EN) FLAG

EMC@
10K_0201_5% 2 EMC@ 10K_0201_5% 2 Change USH board fingerprint power path from B+_USH to +3.3V_ALW

PVT-021 EMC@ G527ATP1U_TSOT23-6 EMC@ G527ATP1U_TSOT23-6 B+ B+_USH

Remove co-lay R49, R52 @EMC@ U4251
4 5

1U_0402_25V6K
+5VD +5VD_USH +3VALW +3VALW_USH C1125 1U_0402_25V6K IN OUT
ML3 EMC@ 2 1 3 6 1

@EMC@
1 2 USB20_P5_CONN @EMC@ IN OUT
9 USB20_P5

C1130
1 2 U4248 U4250 2 7
1U_0201_6.3V6M

1U_0201_6.3V6M

FLAG GND
1U_0201_6.3V6M

1U_0201_6.3V6M
4 3 USB20_N5_CONN 6 1 6 1 @EMC@ 1 2 1 8 2
9 USB20_N5 4 3 1 IN OUT 1 IN OUT B+ EN(#EN) OVTH
EMC@ 1 1 R5759 20K_0201_5%
C1122

EMC@ C1127

C1124

EMC@ C1129
DLW21HN900HQ2L_4P 1 R5752 2 5 2 EMC@ 1 R5754 2 5 2 @EMC@ 1 2 G516A1Y51U_TSOT23-8
20K_0201_5% SET GND 20K_0201_5% SET GND R5767
A A
EMC@

2 1 R5756 2 4 3 2 1 R5758 2 4 3 10K_0201_5%

EN(/EN) FLAG EN(/EN) FLAG
EMC@

EMC@ 10K_0201_5% 2 EMC@ 10K_0201_5% 2

EMC@ G527ATP1U_TSOT23-6 EMC@ G527ATP1U_TSOT23-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P43-IOB CONN/IR CAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 43 of 65
5 4 3 2 1
 5 4 3 2 1

+5V RUN Touch Screen Load Switch PVT-045

+5VS +3VALW Change 0.01 ohm to short pad +3VS_TS +3VS_TS
+5VD +5VS
Card Reader Load Switch
PVT-045 UZ4 R204 0_0603_5%
U2 Change 0.01 ohm to short pad C203 2 1 1U_0402_6.3V6K~D 1 14 +3VS_TS_R 1 @ 2
VIN1 VOUT1 1
0_0603_5% 2 13
+5VS_R R30 1 VIN1 VOUT1 2200P_0402_25V7K~D C194
1 7 @ 2 1 1 1
2 VIN VOUT 8 1 R5764
2 3.3V_TS_EN_R 3 12 C200 1 2
VIN VOUT 8 PCH_3.3V_TS_EN ON1 CT1 0.1U_0402_10V7K
C24 C23 C503 C504 0_0402_5% 2
RUN_ON_P 3 6 1 2 @1 R5765 2 4 11 C201

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
27,30,32,44,45,55,56RUN_ON_P ON CT 2 2 2 30 3.3V_TS_EN +5VALW VBIAS GND
0_0402_5% 2200P_0402_25V7K~D
D 2200P_0402_25V7K~D SD_PWR_EN D
5 10 1 2
11 SD_PWR_EN ON2 CT2
+5VALW 4
C22 VBIAS 5 6 9 +3VS_CR_R +3VS_CR
GND PVT-050 VIN2 VOUT2 R205 +3VS_CR
1U_0402_6.3V6K~D 9 7 8
GND Due to SD can't be detect during S4, change default PD to PU and change +1.8V_PGPP to +1.8VS_CR VIN2 VOUT2
2 1 1 @ 2
15
TPS22967DSGR_SON8_2X2 +1.8VS_CR GPAD 0_0603_5% 1
R210 2 1 100K_0402_5%~D SD_PWR_EN AOZ1331_DFN_14P PVT-045
@ R31 1 2 100K_0402_5%~D RUN_ON_P Change 0.01 ohm to short pad C198
R209 2 1 100K_0402_5%~D PCH_3.3V_TS_EN
0.1U_0402_10V7K
2
@ R211 2 1 100K_0402_5%~D SD_PWR_EN

PVT-045
Deeper Sleep, SSD Load Switch +5V Audio , 3V Run +5VALW Change 0.01 ohm to short pad +5VS_AUDIO +5VS_AUDIO
C90
+3VALW PVT-045 +3V_PRIM +3V_PRIM 1U_0402_6.3V6K~D U13 R114 0_0805_5%
C124 Change 0.01 ohm to short pad 2 1 1 14 +5VS_AUDIO_R 1 @ 2
VIN1 VOUT1 1
1U_0402_6.3V6K~D U21 R145 0_0805_5% 2 13
+3V_PRIM_R VIN1 VOUT1 C89
2 1 1 14 1 @ 2 1 220P_0402_50V8K
2 VIN1 VOUT1 13 AUD_PWR_EN 3 12 C91 1 2
VIN1 VOUT1 30 AUD_PWR_EN ON1 CT1 2
0.1U_0402_10V7K
C1271000P_0402_50V7K~D C126
PCH_PWR_EN_R 3 12 1 2 4 11 C92
ON1 CT1 0.1U_0402_10V7K +5VALW VBIAS GND
2 2200P_0402_25V7K~D
4 11 C129 RUN_ON_P 5 10 1 2
+5VALW VBIAS GND 27,30,32,44,45,55,56RUN_ON_P ON2 CT2
SSD_PWR_EN 1 2 0_0402_5% 2200P_0402_25V7K~D +3VS
11 SSD_PWR_EN +3VALW
C @ R150 5 10 1 2 6 9 C
RUN_ON_P 1 2 0_0402_5% ON2 CT2 +3.3VDX_SSD +3.3VDX_SSD C96 2 11U_0402_6.3V6K~D 7 VIN2 VOUT2 8 R119 0_0603_5% +3VS
R149 VIN2 VOUT2 +3VS_R
6 9 1 @ 2
VIN2 VOUT2 R152
2 1 7 8 0_0805_5% 15
C132 VIN2 VOUT2 +3.3VDX_SSD_R RUN_ON_P GPAD PVT-045
1U_0402_6.3V6K~D 1 @ 2 1 @ R117 1 2 100K_0402_5%~D 1
15 AOZ1331_DFN_14P Change 0.01 ohm to short pad
GPAD PVT-045 C131 C95
R146 1 2 100K_0402_5%~D PCH_PWR_EN AOZ1331_DFN_14P Change 0.01 ohm to short pad +3VS
0.1U_0402_10V7K 0.1U_0402_10V7K
R151 1 2 100K_0402_5%~D SSD_PWR_EN 2 2
R110 2 1 100K_0402_5%~D AUD_PWR_EN
@ R148 1 2 0_0402_5% PCH_PWR_EN_R @ R109 2 1 100K_0402_5%~D AUD_PWR_EN
30 PCH_PWR_EN
R147 1 2 0_0402_5%
10,30,32,44,54,55,56SIO_SLP_SUS#

R5773 1 2 10K_0201_1%
+3VALW

30 SLP_WLAN#_GATE
WLAN/WWAN Load Switch 3V_Audio, 1.8V_Audio Load Switch
+3VS_WLAN
2

+3VALW PVT-045 +3VS_AUDIO +3VS_AUDIO

G

Q357 D115 +3VALW PVT-045 +3VS_WLAN C93 Change 0.01 ohm to short pad
1 3 2 C117 Change 0.01 ohm to short pad 1U_0402_6.3V6K~D U14 R111 0_0603_5%
10 SIO_SLP_WLAN# 1
1U_0402_6.3V6K~D U17 R140 0_0805_5% 2 1 1 14 +3VS_AUDIO_R 1 @ 2
D

VIN1 VOUT1 1
1 2 1 1 14 +3VS_WLAN_R 1 @ 2 C120 2 13
DII-DMN65D8LW-7 VIN1 VOUT1 VIN1 VOUT1 C81
2 13 0.1U_0402_10V7K 1000P_0402_50V7K~D
3 VIN1 VOUT1 2200P_0402_25V7K~D 2 AUD_PWR_EN 3 12 C84 1 2
30 AUX_EN_WOWL ON1 CT1 2
0.1U_0402_10V7K
AUX_EN_WOWL_R 3 12 C119 1 2
BAT54CW-7-F_SOT323-3 D61 ON1 CT1
+5VALW 4 11 C85
C118 VBIAS GND
30 3.3V_WWAN_EN
2 +5VALW 4 11 4700P_0402_25V7K
VBIAS GND 2200P_0402_25V7K~D +3VS_WWAN AUD_PWR_EN 5 10 1 2
1 WWAN_EN 5 10 1 2 ON2 CT2 +1.8VS_AUDIO +1.8VS_AUDIO
B C121 ON2 CT2 +3VS_WWAN +1.8VA 6 9 B
+3VS_WWAN_R C94 VIN2 VOUT2 R112 0_0603_5%
11 NGFF_WWAN_PWREN
3 1U_0402_6.3V6K~D 6 9 1 7 8
VIN2 VOUT2 VIN2 VOUT2 +1.8VS_AUDIO_R 1
2 1 7 8 1U_0402_6.3V6K~D @ 2 1
BAT54CW-7-F_SOT323-3 VIN2 VOUT2 L31 1 2 C116 2 1 15
15 GPAD PVT-045 C82
GPAD 2
0.1U_0402_10V7K Change 0.01 ohm to short pad
R216 1 2 100K_0402_5%~D WWAN_EN BLM18SG221TN1D_2P AOZ1331_DFN_14P 0.1U_0402_10V7K
AOZ1331_DFN_14P L32 1 2 2
R139 1 2 100K_0402_5%~D AUX_EN_WOWL_R
BLM18SG221TN1D_2P

+1.8VA +1.8VA +3VALW +3VALW

@ R425 +1.5VS_AUDIO

+1.8VA Discharge 1
1
0.01_0603_1%
2
+1.5VS_AUDIO

4.7U_0402_6.3V6M
@ C205
1
1

1U_0402_6.3V6K~D @ C207
1 1 1

2
R472 2 @ U16
B+ C500 C501 C502
place close to 1 5 +1.5VS_AUDIO_R @ R214
80.6_0402_1%~D
U16 pin1 IN OUT 10K_0402_1% 2
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

PVT-003 2 2 2 2
2
1

Due to SB00000DH00 will EOL, change to SB00000PV00 @ R218 GND

1
R473 AUD_PWR_EN 1 2 3 4
SHDN SET
200K_0402_1%
3

1
DMN66D0LDW-7_SOT363-6

0_0402_5% 1 G916T1UF_SOT23-5
@ R215
1
2

QE13B

SB00000PV00 @ R217 49.9K_0402_1%

5 @ C206 100K_0402_5%~D
Vout = 1.25*(1+R214/R215)
A A
220P_0402_50V8K

2
2
4

2
6
DMN66D0LDW-7_SOT363-6

SB00000PV00

DELL CONFIDENTIAL/PROPRIETARY
QE13A

2
10,30,32,44,54,55,56SIO_SLP_SUS# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P44-DC/DC Interface 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 44 of 65
5 4 3 2 1
 A B C D E

+1.0V_VCCST source +1.0V_VCCST

+1.0V_VCCSTG source
+1.0VA +1.0V_VCCST
+1.0VA

0.1U_0402_10V7K
1
UZ3 PVT-046 +1.0V_VCCSTG

CZ5
1 Change 0.01 ohm to short pad UZ2
1 VIN1 Change 0 ohm to short pad 1
2 1 PVT-046
VIN2 2 2 VIN1 Change 0.01 ohm to short pad
+1.0V_VCCST_R 1 VIN2 Change 0 ohm to short pad
1 7 6 @ 2
VIN thermal VOUT +5VALW +1.0V_VCCSTG_R261
1U_0402_6.3V6K

R118 0_0603_5% 7 6 @ 2
VIN thermal VOUT
CZ8

3 R26 0_0402_1%
+5VALW VBIAS 3
2 4 5 VBIAS
32 VCCST_EN ON GND 1

1U_0402_6.3V6K

0.1U_0402_10V7K
1 4 5
ON GND +1.0V_VCCSTG

CZ6

CZ4
TPS22961DNYR_WSON8
2 TPS22961DNYR_WSON8
2

0.1U_0402_10V7K
BEAVER CREEK: 1
4.4mohm/6A BEAVER CREEK:

CZ1
TR=12.5us@Vin=1.05V 4.4mohm/6A
TR=12.5us@Vin=1.05V 2

+3V_PRIM
PVT-048
De-pop debug XDP related compoments VCCSTG_EN
U4245
5

@XDP@ +3VALW
SUS_ON_EC 1 @
P

30,32,43,53 SUS_ON_EC INB 4 R427 1 2 0_0402_5% VCCST_EN

O

5
XDP_PRSENT 2
13 XDP_PRSENT INA
G

P
MC74VHC1G32DFT2G_SC70-5
9,10,31,56,57 SIO_SLP_S0# B VCCSTG_EN
4
3

2 O
27,30,32,44,55,56 RUN_ON_P A

G
UC2

100K_0402_5%
2 TC7SH08FU_SSOP5 2

RZ2
+VCCPLL_OC source

2
+VCCPLL_OC
+VCCPLL_OC S0 S0Ix S3
+1.2V_DDR

0.1U_0402_10V7K
1
UZ1 PVT-046
SIO_SLP_S0# high low low

CZ2
1 Change 0.01 ohm to short pad
VIN1 Change 0 ohm to short pad
2
VIN2 2
7 6 +VCCPLL_OC_R 1 @ 2
1 VIN thermal VOUT RUN_ON_EC high high low
1U_0402_6.3V6K

R48 0_0603_5%
CZ3

+5VALW 3
VBIAS
2 4 5
PVT-046 ON GND
Change 0.01 ohm to short pad
Change 0 ohm to short pad
TPS22961DNYR_WSON8
RZ1
VCCSTG_EN 1 @ 2

0_0402_1% +5V_Dock source PVT-046

+5V_DOCK

+5VD Change 0.01 ohm to short pad

Change 0 ohm to short pad
3 U7 3
5 1 +5V_DOCK_R R72 1 @ 2 0_0805_5%
IN OUT
R74 1 2 100K_0201_5% 3
1 1 1
+1.0V_MPHYGT source FLAG

0.1U_0402_10V7K

22U_0805_10V6M
4 2
30 DOCK_PWR_EN EN(#EN) GND

C37

C38
C39
1U_0402_6.3V6K~D G517G1TO1U_TSOT23-5
2 2 2
+1.0V_MPHYGT +1.0V_MPHYGT

+1.0VA PVT-046
Change 0.01 ohm to short pad
0.1U_0402_10V7K

0.1U_0402_10V7K

Change 0 ohm to short pad 1 1

CZ10

CZ9

1 @ 2 R73 1 2 100K_0201_5% DOCK_PWR_EN

+1.0V_MPHYGT
R120 0_0603_5%
1U_0402_6.3V6K

2 2
@

1
CZ7

4 4

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P45-DC/DC Interface 2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 45 of 65
A B C D E
 5 4 3 2 1

Pebble Creek MLK Power Block - Tablet

D D

+3VALW
LCD driver INV_PW M IFB1~IFB8
2S/3S Battery B+ TPS61188

U8 ENVDD
EC SY6288 +LCDVDD

PCH_PW R_EN_R +3V_PRIM

U21
AOZ1331 RUN_ON_P
Type-C Port-A PD1 +3.3VDX_SSD
Controller Power Path AUX_EN_W OW L
U17 +3VS_WLAN
AOZ1331 WWAN_EN
Charger +3VS_WWAN
Type-C Port-B PD2 ISL88738
Controller (NVDC) 3.3V_TS_EN
+3VALW +3VS_TS
TDC: 5.21A UZ4
B+ AOZ1331 SD_PWR_EN
C
(NB680) +3VS_CR C

U21 AUD_PW R_EN

AOZ1331 +3VS_AUDIO

B+
B+ B+ B+
U11 3.3V_CAM_EN#
APE8937 +3VS_CAM

RUN_ON_P +3VS
U13
AOZ1331 AUD_PW R_EN
+5VS_AUDIO
U22: U42:
+VCC_CORE: 32A +VCC_CORE: 64A +5VALW
+VCC_GT: 31A +VCC_GT: 28A US1 USB3_PW R_SHR_VBUS_EN
TDC: 5.85A TPS2544 +5V_USB_P1
+VCC_SA: 4.5A +VCC_SA: 5A (NB679A)
(MP2949A)

B UZ3 3.3V_CAM_EN#
B

TPS22961 +1.0V_VCCST
+1.0VS_VCCIO TDC: 2.17A VCCSTG_EN +1.0VS_VCCIO
Vcore Power Rail (TPS62134A)
+5VD ALWON U2 RUN_ON_P
Audio Power Rail TDC 2.55A +5VD APE8937 +5VS
+1.0V_PRIM TDC: 1.79A SIO_SLP_SUS# +1.0V_PRIM_CORE (NB679)
Different from Pebble Creek (TPS62134D)
U7 DOCK_PWR_EN
G517G1 +5V_DOCK
+1.8VU TDC: 0.19A SUS_ON_P +1.8VU
(TLV62150)

+1.8VA TDC: 0.31A SIO_SLP_SUS# +1.8VA U21 AUD_PW R_EN

AOZ1331 +1.8VS_AUDIO
(TLV62150A)

+1.2V_DDR TDC: 3.2A SUS_ON_EC +1.2V_DDR UZ1 VCCSTG_EN

TPS22961 +VCCPLL_OC
(NB685)

A +1.0VA TDC: 2.87A SIO_SLP_SUS# +1.0VA UZ3 VCCST_EN A

TPS22961 +1.0V_VCCST
(SY8286RAC)

UZ2 VCCSTG_EN
TPS22961 +1.0V_VCCSTG

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/20 Deciphered Date 2015/08/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_POWER BLOCK DIAGRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 46 of 65
5 4 3 2 1
 5 4 3 2 1

Pebble Creek MLK Power Path Block

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/20 Deciphered Date 2015/08/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_POWER PATH DIAGRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 47 of 65
5 4 3 2 1
 5 4 3 2 1

Function feild
Power Path(37.1),
： EMC Part(47.1). 3VLDO(35.27/35.28)

Type C adapter input_1

+VBUS1_PD_20V
S1a S1b
PQ100 PQ101
+CHG_VIN_20V +CHG_VIN_20V @ PQ102
LCD_POWER_20V B+ @ PQ103
LCD_POWER_20V
@ PT101 +VBUS1_20V AON7405_DFN8-5 AON7405_DFN8-5 AON7405_DFN8-5 AON7405_DFN8-5
EMC@ PL100 1 1 @ PR268 1 @ PR116 1
HCB2012KF-121T50_0805 2 2 0_0603_5% 2 0_0603_5% 2
PD1_LPS2
1 2 3 5 5 3 1 2 5 3 1 2 5 3

1
330K_0201_1%

330K_0201_1%

330K_0201_1%
680P_0402_50V7K

499K_0402_1%
1

S TR AO7401 1P SC70-3
2200P_0402_50V7K

2200P_0402_50V7K

1000P_0201_50V7K

PR213

PR101

@ PR251
100P_0201_25V7K

100P_0201_25V7K
0.01U_0402_25V7K

S TR AO7401 1P SC70-3
1U_0603_25V6K

10U_0603_25V6M

4
1

1
0.1U_0402_25V6

0.1U_0402_25V6
EMC@ PC100

EMC@ PC103

EMC@ PC101

EMC@ PC108

EMC@ PC104

EMC@ PC106

EMC@ PC107

@ PR104
S TR AO7401 1P SC70-3

680P_0402_50V7K
@ PC112
1M_0402_1%

0.47U_0402_25V6K
EMC@ PC102

EMC@ PC105

499K_0402_1%
1

1
PC133

@ PR218

680P_0402_50V7K

499K_0402_1%
3

3
@ PR105
S S

499K_0402_1%

@ PC110
1

2
1

3
PQ133

@ PC111

PR103

@ PQ138
G S G
2 2

PR100

PQ104
2

2
PC109
G
D 2 D

2
D D

1
1
330K_0201_1%
2 D

1
PR214

49.9K_0402_1%
1

1
@ PR112

330K_0201_1%
SB000006O00

49.9K_0402_1%
2
+3V_LDO

1
330K_0201_1%
Use SB000004A0L footpin

@ PR250
49.9K_0402_1%
1
PD1_LPS1

PR107
PR109

@ PR110
2

DMN65D8LW-7_SOT323-3

2
49.9K_0402_1%
+3V_LDO

200K_0201_5%
1

1
@ PR137

DMN65D8LW-7_SOT323-3
2

2
1
PR106
PR215 0_0402_5% D @ PR266

2
6

1
@ PR252
D

@ PQ110
200K_0201_5% D 1 2 2 0_0402_5%

PQ134A

@ PQ112
1 2 2 @ PR114 48 LED_SOURCE 1 2 2
G
+3V_LDO

3
G D 0_0402_5% D 48 AC_IN
S G

2
200K_0201_5%

@ PQ139B
1
PQ108
2 1 2 5 S
VBUS1_ECOK 30,48

3
S G G

PR115
1
@ PR217 S @ PR253

3
3

6
0_0402_5% D PVT 0_0402_5% D S

DMN66D0LDW-7_SOT363-6

4
PQ134B

@ PQ139A
1 2 5 Due to SB00000DH00 will EOL, change to SB00000PV00 1 2 2
35,48 EN_PD_HV1 48 LED_SOURCE

6
G PR259 1 2 D G

PQ109A
1
200K_0201_5% D 2 PVT
PR178

PQ106
1 2 2 G Due to SB00000DH00 will EOL, change to SB00000PV00
S S
+3V_LDO 1M_0201_1%
4

1
G
1 2 S S

1M_0201_1%

1
1

DMN66D0LDW-7_SOT363-6
PR228

PR166
@ PR123
1M_0201_1% +3VALW

3
PR216 PR122 PQ141 0_0402_5% D

PQ109B
0_0402_5% 0_0402_5% 1 2 5
PD1_LPS1 35,48,50 AC1_DISC# PVT LDO_IN

D
1 2 1 2 3 1 G
30 DCIN1_EN

2
Due to SB00000DH00 will EOL, change to SB00000PV00
@ PR125 S
PR262

4
1

0_0402_5% D 1 2 PR176 @ PR119

0.01U_0402_50V7K
G

100K_0402_1%
2

1
PQ130

1 2 2 1M_0201_1% 1M_0402_1%
200K_0201_5% 16.7V

100K_0402_1%
48 AC2_OVP

1
@ PR267
G 1 2 1 2

1
@ PC286

@ PR249
S 1 2

330K_0402_1%
+3VALW
3

1
PR261

@ PR108
0_0402_5% @ PU105

2
5
AS331KTR-G1_SOT23-5

2
For MEC5105
2.2V

2
1
4
LED_SOURCE 48
3
48 AC_IN

0.1U_0402_10V7K
S2a S2b

1M_0201_1%
1
100P_0402_50V8J
Type C adapter input_2

10U_0402_6.3V6M

100K_0402_1%
49.9K_0402_1%
1

1
@ PC283

@ PR272
1

1
@ PR248

@ PC285

@ PR102

@ PC284
+VBUS2_PD_20V

2
PQ113 PQ114
+VBUS2_20V

2
@ PT102 AON7405_DFN8-5 AON7405_DFN8-5 +CHG_VIN_20V

2
EMC@ PL101 1 1
HCB2012KF-121T50_0805 2 2
PD2_LPS2
1 2 3 5 5 3
C C

1
330K_0201_1%
1
330K_0201_1%
2200P_0402_50V7K

2200P_0402_50V7K

1000P_0201_50V7K

PR129
100P_0201_25V7K

100P_0201_25V7K
0.01U_0402_25V7K

S TR AO7401 1P SC70-3
1U_0603_25V6K

10U_0603_25V6M

4
1
0.1U_0402_25V6

0.1U_0402_25V6
EMC@ PC120

EMC@ PC122

EMC@ PC116

EMC@ PC117

EMC@ PC119

EMC@ PC121

EMC@ PC115

1M_0402_1%

PR220
EMC@ PC114

EMC@ PC118

0.47U_0402_25V6K
S TR AO7401 1P SC70-3
1

1
PC134

@ PR219

680P_0402_50V7K

499K_0402_1%
1

1
499K_0402_1%

2
3

3
@ PC124

PR130
S S
PR128
2

+3VALW
PQ135

PQ115
PC123

G G
2 2
2

2
1
330K_0201_1%

D 2 D
1

1
PR221

200K_0201_5%
+3VALW

1
+3V_LDO

PR175
2

49.9K_0402_1%
1

1
330K_0201_1%

200K_0201_5%
1
PD2_LPS1

PR134

PR208

PR118
PR158

2
0_0402_5% From Charger 200K_0201_5%

PR174
1 2 AC_DISC_OUT# 50
1 2
+3V_LDO 30,43 DET_L#
49.9K_0402_1%
1

200K_0201_5%
2

1
PR133

PR222 PR230 PR202

2
6

6
200K_0201_5% D @ PR135 To EC 0_0402_5% 0_0402_5% D

PR160
PQ136A

PQ129A
1

D 0_0402_5% AC_DIS#
1 2 2 30 AC_DISC# 1 2 1 2 2
+3V_LDO

200K_0201_5%
1

1
PQ119

G 2 1 2 G PR161

0_0402_5%
VBUS2_ECOK 30,48
2

0_0402_5%

1000P_0402_50V7K
G

PR207
PR139

2
@ PC140
@ PR224 S S S PR209 1 2
To Charger 30 DET_R#
1

1
3

1
0_0402_5% D 0_0402_5%
PQ136B

1 2 5 PVT 1 2 CHG_PROCHOT# 50

DMN66D0LDW-7_SOT363-6
36,48 EN_PD_HV2

2
6
G Due to SB00000DH00 will EOL, change to SB00000PV00 1 2 D PR121

DMN65D8LW-7_SOT323-3
2
PQ121A
1

1
PR263 200K_0201_5% D 2 PR206 D 0_0402_5%

PQ111
PR179
PQ118

S 1 2 2 G D 0_0402_5% D 2 1 2
+3V_LDO
4

1M_0201_1% DET_R 43

PQ129B
G 5 1 2 5 G

1
1 2 S S G G S

390K_0402_1%
2.13V when
1M_0201_1%

3
1

PR162
PR229
PR172

1M_0201_1% S PQ122B S docked

4
PR225 PR132 PQ142 @ PR136 PVT

DMN66D0LDW-7_SOT363-6
3
0_0402_5% 0_0402_5% 0_0402_5% D Due to SB00000DH00 will EOL, change to SB00000PV00

2
PQ121B
PD2_LPS1
S

1 2 1 2 3 1 1 2 5
30 DCIN2_EN
2

36,48,50 AC2_DISC# G PVT

@ PR146 Due to SB00000DH00 will EOL, change to SB00000PV00
PR264
1

0_0402_5% D 1 2
G

S
2

4
PQ131

1 2 2 200K_0201_5%
48 AC1_OVP
G
S 1 2 1 2
+3VALW
3

PR200 PR192
PR265 PR177
0_0402_5% 0_0402_5% 0_0402_5%
1M_0201_1% AC_DIS# AC_DIS#
1 2 1 2
@ PR145 @ PR138
For MEC5105

6
0_0402_5% D 0_0402_5% D

PQ128A

PQ122A
1 2 2 1 2 2
30,48 VBUS2_ECOK 30,48 VBUS1_ECOK
G G
+3.3V_LDO_PD2 +3.3V_LDO_PD1
PR143 S PR142 S

1
200K_0201_5% 200K_0201_5%
1 2 1 2
+3VALW +3VALW
1
1

PC151
B B
PC150 0.01U_0402_50V7K PR127 PR124
2

3
0.01U_0402_50V7K PD111 200K_0201_5% D 200K_0201_5% D
2

PQ120B

PQ127B
PD110 RB520SM-30T2R_EMD2-2 1 2 5 1 2 5
RB520SM-30T2R_EMD2-2 1 2 +3VALW G +3VALW G
1 2
EN_PD_HV2 36,48 EN_PD_HV1 35,48
1
221K_0402_1%
PD1_LPS2

PD2_LPS2

@ PR144 S @ PR201 S

4
6

6
@ PR164 0_0402_5% D 0_0402_5% D
PR183

PQ120A

PQ127A
@ PR163 1 2 1 2 2 1 2 2
36,48,50 AC2_DISC# 35,48,50 AC1_DISC#
1 2 G G
1

1M_0402_1%
221K_0402_1%
47K_0402_1%

47K_0402_1%

PVT PVT
499K_0402_1%

499K_0402_1%

1M_0402_1%
2
1

Due to SB00000DH00 will EOL, change to SB00000PV00 Due to SB00000DH00 will EOL, change to SB00000PV00
PR182

PR184
PR185

S S

1
PR111

PR113

PU103 PU104
5

AS331KTR-G1_SOT23-5 AS331KTR-G1_SOT23-5 @ PR204 @ PR203

0_0402_5% 0_0402_5%
2

PR117 PR120 1 2 1 2
2

1 0_0402_5% 1 0_0402_5%
4 1 2 4 1 2
AC1_OVP 48 AC2_OVP 48
3 3
0.1U_0402_10V7K

0.1U_0402_10V7K
1M_0201_1%

1M_0201_1%
1

1
10U_0402_6.3V6M

10U_0402_6.3V6M
100P_0402_50V8J

100P_0402_50V8J
2.2U_0402_25V6M

2.2U_0402_25V6M
200K_0402_1%

200K_0402_1%

200K_0402_1%

200K_0402_1%
1

1
PC145

PR269

PC147

PR270
@ PC144

@ PC148
1

1
PC281

PC282
PR256

PR255

PR258

PR257
PC146

PC149
2

2
2

LDO_IN
PQ123
2

PD103 PR147
S TR AO7401 1P SC70-3
2

RB520SM-30T2R_EMD2-2 PU101 0_0805_5%

+3V_LDOP
2 1 1 5 1 2 1 3

S
+VBUS1_20V VCC OUT
2 PR148

1U_0402_16V6K
GND 1M_0201_1%

G
2
1
PR165 PR167 PD106 PC128 3 4 1 2

PC129
1

D 0_0402_5% D 0_0402_5% RB520SM-30T2R_EMD2-2 1U_0603_25V6K NC EN

10K_0402_1%
1
2 1 2 2 1 2 2 1 1 2 PC125
EN_PD_HV1 35,48 EN_PD_HV2 36,48 +VBUS2_20V

2
0.01U_0201_16V7

PR150
G G RT9069-33GB_SOT23-5
S PQ132 S PQ140 1 2
3

PR149
PQ124

2
300K_0402_5% PR231
S TR AO7401 1P SC70-3
1 2 0_0805_5%
1 3 1 2 +3V_LDO

S
+3VALW

1U_0402_16V6K

DMN65D8LW-7_SOT323-3
1
300K_0402_5%

1
PC131
+BAT_TABLET PR155

PR153
+BATT

G
2
1

3
@ PQ126
D D 100K_0201_1%

PQ125B
2 5 1 2

2
EMC@ PL102 G G

2
HCB2012KF-121T50_0805 S

1
1 2 S

0_0201_5%
4
1
0_0201_5%
RC delay 110ms

PR156
EMC@ PL103

@ PR271
HCB2012KF-121T50_0805
1 2

6 2
PR151
TVNST52302AB0_SOT523-3

TVNST52302AB0_SOT523-3

2
0.01U_0402_25V7K

0_0201_5% D
1000P_0402_50V7K

1M_0402_1%

PQ125A
1

1
@EMC@ PC127

@EMC@ PC132 1 2 2
@EMC@ PC126

A SM AR T 30,52 3VALW_PG A
1

PR126

EMC@ PD104

EMC@ PD105

2200P_0402_50V7K G
Batte ry : 1 2

0.1U_0201_10V6K
12:+BAT T S PVT
2

1
1
PC130
Due to SB00000DH00 will EOL, change to SB00000PV00
11:+BAT T JT100
2

14
10:+BAT T
2

13 GND
09:+BAT T

2
GND 12 For ISL88738
08:CL K_ S M B 12 11 PR152 100_0402_1%
11
07:D AT _ S M B 10
10 1 2
PBAT_SMBCLK 30
9
06:TBAT _ 3 V3 9 8
CLK_SMB PR154 100_0402_1%
05:SYS _ PR E S # 8 7 DAT_SMB
1 2
PBAT_SMBDAT 30
7 TBAT_3V3
04 : GN D 6
6
5 PR157 0_0402_5%
03 : GN D 5 SYS_PRES# 49
4 1 2
02 : GN D 4 3 +3.3V_TBAT_LDO
01 : GN D 3 2
2 1
Tablet battery 3.3V output
1
ACES_50278-01201-001 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@
Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_DCIN/Power Path
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date : Tuesday, November 07, 2017 Sheet 48 of 65
5 4 3 2 1
 5 4 3 2 1

D D

PD280
BAT54CW_SOT323-3
2
+3.3V_TBAT_LDO
1

3 Change from SCS00005400 to SCS00003800 for X1

+3V_LDO

B+

549K_0402_1%
1

PR282
1

1
PR280 PU280
PR281
100K_0402_5% SN74LVC1G123DCUR_VSSOP8
1

100K_0402_5% 1 8

2
A# VCC
PR283

2
C C
100K_0402_5% 2 7
B R/CEXT
3 6
2

CLR# CEXT
4 5 SYS_PRES# 48
1
D GND Q
2 PQ280

4.7U_0402_6.3V6M
G DMN65D8LW-7_SOT323-3
S
3
1

1
PC280
PR284 PR285
100K_0402_5% 1M_0402_1%

2
2

2
30,43 POWER_SW_IN#

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/08/20 Deciphered Date 2015/08/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_For bat ship mode
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 49 of 65
5 4 3 2 1
 A B C D

Charger controller(40.1), Support component(40.2)

@ PT100
+CHG_VIN_20V
+CHG_SRC_20V
1 1
EMC@ PL302 PR300
1UH_1277AS-H-1R0N-P2_3.3A_30% 0.01_1206_1%
1 2 CHG_VIN_20V 4 1

0.1U_0402_25V6
4.3V 3 2

2200P_0402_50V7K
SMF4L22A SOD123FL-2

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M
442K_0402_1%

@ PC301
1

@EMC@ PC306
@EMC@ PC303
0.1U_0402_25V6
PD906

PR305

@ PC302

PC307

PC308

PC309

PC304

PC305

PC310
1

1
2

3.3_0402_1%

3.3_0402_1%
1

1
2

2
PR302

PR301
CHG_ACIN

2
PC312
4.7U_0603_25V6K

0.1U_0402_25V6

1U_0402_25V6K

1U_0402_25V6K
100K_0402_1%
1 2

1
PC331

PR307
B+

1
PC313

PC314
2

2
2

2200P_0402_50V7K
10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

10U_0603_25V6M

@EMC@ PC321
0.1U_0402_25V6

@EMC@ PC329
PC315

PC316

PC317

PC318

PC319

PC320

@ PC324

@ PC325

@ PC326
1

1
0.22U_0603_25V7K
2.2_0603_5%
1

2
1
PC330
PR306
PR303

2
2_1206_5%
2
Change from AON6428L to AON6380 for X1 code 2

2
1 2
+CHG_VIN_20V

1U_0603_25V6K

5
PC332

AON6380_DFN5X6-8-5
1

CHG_ADP

CHG_CSIP

CHG_CSIN

CHG_BST1

CHG_UG1

CHG_LX1

CHG_LG1

5
PD300 PC333

AON6508_DFN8-5
DB2J31400L_SOD323-2 1U_0603_25V6K

2
2 1 1 2
Main: ML, 2nd: CLSN

PQ302
+CHG_VIN_20V PR308 CHG_UG1 4

PQ307
PD301 4.7_0402_5% Package: 11.5 x 10.3 x 2

16

15

14

13

12

11

10

33
PR309
Idc=10A, Isat=11A

9
DB2J31400L_SOD323-2 1 2 CHG_UG2 4
2_1206_5% VDD
2 1 1 2 5V Rdc=14mohm (Typ.)

CSIN

PAD
BOOT1

UGATE1

PHASE1

LGATE1
ADP

CSIP

ASGATE
B+ PC334
+BAT_TABLET

3
2
1
1U_0402_6.3V6K
PC335 CHG_DCIN 17 8 CHG_VDDP 1 2
1U_0402_6.3V6K VDD

3
2
1
DCIN VDDP PR310 PQ304
1 2 5V 18 7 CHG_LG2 PL301 0.005_1206_1% AON7405_DFN8-5
VDD LGATE2 2.2UH_MMD-10BZN2R2M-M1L_10A_20% 1 4 1
PR311 BATT+
@ PR3311 2 0_0402_5% CHG_ACIN 19 6 CHG_LX2 1 2 CHG_LX1 1 2 CHG_LX2 2
VDD ACIN PHASE2 2 3 3 5
2.2_0603_5%

10U_0603_25V6M

10U_0603_25V6M
PR3341 2 0_0402_5% CHG_CMIN 20 5 CHG_UG2

@EMC@ PR316
4.7_1206_5%

@EMC@ PR317
4.7_1206_5%
OTGEN/CMIN UGATE2

5
PC336

1
CHG_DAT 21 CHG_BST2

AON6508_DFN8-5

AON6508_DFN8-5
PR3131 2 0_0402_5% PU300 4 1 2

2200P_0402_50V7K
PC322

PC323
30 CHG_MCP23008_SMBDAT

4
SDA ISL88738HRTZ-T_TQFN32_4X4 BOOT2

4700P_0402_25V7K
PR3141 2 0_0402_5% CHG_CLK 22 Change part number to MP 3 0.22U_0603_25V7K

PQ305

PQ306
30 CHG_MCP23008_SMBCLK

2
SCL VSYS

1
PC340
SA00009VW0L

2
OTGPG/CMOUT
CHG_LG2 4

1
CHG_CSOP CHG_LG1 4

PC339
PR3151 2 75_0402_5% 23 2 PR318

CHG_BGATE
11,30,53,57 H_PROCHOT# PROCHOT# CSOP

AMON/BMON
0_0402_5%

1 SNUB_CHG1

1 SNUB_CHG2

2
BATGONE
24 1 1 2 B+

2
48 CHG_PROCHOT# ACOK CSON

CHG_CSON
PR341

BGATE
CMOP
PROG

PSYS

VBAT
PR319 0_0402_5%

3
2
1

3
2
1
0.1U_0402_25V6
1 2 1 2

680P_0402_50V7K
680P_0402_50V7K
VDD

2.2_0402_1%

2.2_0402_1%
@EMC@ PC343
@ PC341

@EMC@ PC342
100K_0402_1%

1
3V 25

26

27

28

29

30

31

32

PR323

PR324
50 ACAV_IN1

2
0_0402_5% CHG_VBAT1

CHG_BGATE
CHG_PSYS
CHG_AMON
154K_0402_1%

PR338 PR325

2
1

105K_0402_1%
3
0_0402_5% 1M_0402_1% 3
PQ308

2
1
PR312

1 2 2 1 2
30 AC_DIS
PR322
G
1M_0402_1%
1

S PR332
3
PR336

0_0402_5%
2

1
1 2 PC345 PC346 PC347
2

48 AC_DISC_OUT#
PR329
1U_0402_25V6K 4.7U_0603_25V6K 1U_0402_25V6K
1 2 1 2 1 2
2

3-CELL
2

CHG_COMP
For Battery 60% RSOC stop charging in Factory
1K_0402_1%
1
0.01U_0402_16V7K 499_0402_1%

PR328
1
PR327

560P_0402_50V7K

10K_0402_5%
1

@ PR333
@ PC348

+3V_LDO
1
2

0.1U_0402_25V6

PC352
2

0.1U_0402_25V6
PC349

PC350
1

1 2
PR345 PR330
0_0402_5% 100_0402_1%
2

2
5

1 2 1 2 +BAT_TABLET
P_SYS_R

30,57

50 ACAV_IN1
@ PT103 PR351
VCC

PR342 PD302 1 0_0402_5%

IN1
1

0_0402_5% RB520SM-30T2R_EMD2-2 4 1 2
OUT ACAV_IN 30 @ PC351
1 2 2 1 2
GND

I_ADP

IN2
30

35,48 AC1_DISC# 0.1U_0402_25V6

2
1

PR343 PD303 PU301

1M_0402_1%
1

0_0402_5% RB520SM-30T2R_EMD2-2 TC7SH08FU_SSOP5 PR346

@ PR347

1 2 2 1 100K_0402_1%
36,48 AC2_DISC#
PVT
2

Follow EE 2nd source list, change to SA007080120

2

4 4

When AC remove, AVAV_IN could inform EC fastly

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/24 Deciphered Date 2015/08/31 Title
PWR_Charger (ISL88738)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 50 of 65
A B C D
 5 4 3 2 1

LCD driver controller(35.31), Support component(35.32)

D D

Current: 11.1mA x 8 = 88.8mA

Max Voltage: 6.2V x 6 = 37.2V
PL400 PD400
10UH_MLPS-5020-100M-E_1.5A_20% DFLS160-7_POWERDI123-2
1 2 LED_SW 2 1
+INV_PWR_SRC +LED_AN

1
220P_0402_50V7K 10_0603_5%
PR400
0.1U_0603_50V7K

1U_0805_50V7K

2.2U_0603_50V6K

2.2U_0603_50V6K

2.2U_0603_50V6K

2.2U_0603_50V6K

0.1U_0603_50V7K
PC402 1 1 1 1

1
PC404

PC406
PC401

PC403

PC405

PC418
Open for PWM mode 0.1U_0402_25V6 No need EC control

PC400
@ PR401 1 2 @ PR402

2
0_0402_5% 0_0402_5%

2
1 2 1 2 2 2 2 2
@ PR403
@ PR404

1
PC407
1 2 1 2
0_0402_5%
LED_PWM 0_0402_5%
LED_IFB1 22

2
1

1
PU400
C C
@ PC408

SEL1

SEL2

SCL

IFB1
PWM

VDDIO

SDA
470P_0402_50V7K

2
PR406
43K_0201_1%
PR407 1 2 28 8 LED_IFB2 22
10K_0402_1% R_PWMIN IFB2
PR405

1
1 2 LED_SD 1 2 27 9
22 DISPOFF# FSLCT IFB3 LED_IFB3 22
@ PC409
523K_0402_1%

1
100P_0402_50V8J

26 10 470P_0402_50V7K
1M_0402_1%

2
VIN IFB4 LED_IFB4 22
1

@ PR409 @ PC410
PR408

@ PC411

1
LED_SD 1 2 25 11 470P_0402_50V7K

2
SD AGND
@ PC412
0_0402_5% LED_SW
24 12 470P_0402_50V7K
2

2
SW1 IFB5
2

PR410 23 13
SW2 IFB6
1M_0402_1% TPS61188ARUYR_QFN28_4X4
+LED_AN 3/28 Footprint change from -SS to -S LED_IFB5 22
1 2 22 14
OVP IFB7

1
R_FPWM
@ PR417 LED_IFB6 22 @ PC413

PGND1

PGND2

470P_0402_50V7K

1
ISETH
1 2
45.3K_0402_1%

PR411 470P_0402_50V7K

IFB8
LED_IFB7 22

2
1

@ PC414

NC

NC
0_0402_5%

TP

@ PC415
0_0402_5%

1
0_0402_5%
PR412

1 2 LED_PWM

@ PR418
22 INV_PWM 470P_0402_50V7K

2
1
21

20

19

18

17

16

15

29
100P_0402_50V8J

B B
1M_0402_1%
1

@ PC416

2
1
PR413

2
953K_0402_1%

118K_0402_1%
1

1
2

PR414
@

PR415
@ PR416
2

1 2 LED_IFB8 22

470P_0402_50V7K
0_0402_5%
2

1
0_0402_5%
PR420

@ PR419
@ PC417

1
0_0402_5%
1 2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_LCD driver (TPS61181A)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 51 of 65
5 4 3 2 1
 A B C D E

3V/5V controller(35.1), Support component(35.2)

SH000015A00
Main: ML, 2nd: CLSN
B+ Package: 5.7 x 5.4 x 1.8
EMC@ PL500 PU500 Idc=6.2A, Isat=8.4A
HCB2012KF-121T50_0805
1 2 3V_VIN 1 4 PR501 PC500 DCR=29mohm (Typ.)
VIN CLK
@ PR500 0_0402_5% 3.3_0603_1% 0.22U_0402_16V7K

2200P_0402_50V7K
1 2 12 8 1 2 1 2 PL501
ENCLK BST

0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
EMC@ PC502
EMC@ PC501
1 1.5UH_MMD-05AHN1R5M-M1L_6.2A_20% 1
PC505 3V_EN 11 7 1 2
+3VALWP

PC503
EN SW

1
PC504
4.7U_0402_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2 100mA output 6 5 +3VALWP

EMC@ PR502
4.7_0805_5%
LDO VOUT

PC506

PC507

PC508

PC509
2

1
PR519 3 2
1 2 PG PGND
+3VLP 9 10
0_0402_5%

2
RF DVT2 add VCC AGND

2
30,48 3VALW_PG
NB680GD-Z_QFN12_2X3

1
100K_0402_5%

680P_0603_50V7K
1
PC510

EMC@ PC511
PR503
1U_0402_16V6K

1
For Ultra-Sonic mode PR504

2
0_0402_5%
1 2 3V_EN
30,52 ALWON_PWR
+3VALW
2.2K_0402_1%

100K_0402_1%
1

EE side 2.2K @ PJP500

PR505

@ PR516

1 2
+3VALWP +3VALW
JUMP_43X118
2

3VALW
TDC 5.21A
Peak Current 7.45A

SH000015A00
Main: ML, 2nd: CLSN
2 CPU_B+ Package: 5.7 x 5.4 x 1.8 2
EMC@ PL502 PU501 Idc=6.2A, Isat=8.4A
HCB2012KF-121T50_0805
1 2 5VALW_VIN 1 4 PR507 PC513
DCR=29mohm (Typ.)
@ PR506 0_0402_5% VIN CLK
3.3_0603_1% 0.22U_0402_16V7K
@ PR1203 1 2 12 8 1 2 1 2 PL503
10U_0603_25V6M

10U_0603_25V6M
0.047U_0402_25V7K

0.47U_0402_25V6K

0_0805_5% ENCLK BST 1.5UH_MMD-05AHN1R5M-M1L_6.2A_20%

EMC@ PC515

EMC@ PC514

1 2 PC518 5VALW_EN 11 7 1 2
1 EN SW +5VALWP
1

1
PC517
PC516

4.7U_0402_6.3V6M

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2 +5VALW_LP 6 5 +5VALWP

@EMC@ PC1438

@EMC@ PC1439

@EMC@ PC1440
LDO VOUT

1
EMC@ PR508
4.7_0805_5%
RF DVT2 add

PC519

PC520

PC521

PC522
2

1
5VALW_PG 3 2
PG PGND
100K_0402_5%
1

9 10
PR509

2
VCC AGND

2
RF DVT2 add
NB679AGD-Z_QFN12_2X3

680P_0603_50V7K
2

EMC@ PC524

1
1

PC523
PR510 Ultra-Sonic mode 1U_0402_16V6K

2
0_0402_5%
2

1 2 5VALW_EN @ PJP501
30,52 ALWON_PWR
1 2
+5VALWP +5VALW
100K_0402_1%
1

JUMP_43X118
@ PR517

5VALW
TDC 5.85A
Peak Current 8.83A

3 3

SH000015A00
Main: ML, 2nd: CLSN
B+ Package: 5.7 x 5.4 x 1.8
EMC@ PL504 PU502 Idc=6.2A, Isat=8.4A
HCB2012KF-121T50_0805
1 2 5VD_VIN 1 4 PR512 PC526
DCR=29mohm (Typ.)
VIN CLK
@ PR511 0_0402_5% 3.3_0603_1% 0.22U_0402_16V7K
1 2 12 8 1 2 1 2 PL505
2200P_0402_50V7K

ENCLK BST
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
EMC@ PC528

1.5UH_MMD-05AHN1R5M-M1L_6.2A_20%
EMC@ PC527

PC531 5VD_EN 11 7 1 2
EN SW +5VDP
1

1
PC529

PC530

4.7U_0402_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1 2 +5VD_LP 6 5 +5VDP
EMC@ PR513
4.7_0805_5%

LDO VOUT
1

PC532

PC533

PC534

PC535
2

1
5VD_PG 3 2
PG PGND
100K_0402_5%
1

9 10
PR514

2
RF DVT2 add VCC AGND
2

NB679GD-Z_QFN12_2X3
680P_0603_50V7K
2

EMC@ PC537

1
1

PC536
1U_0402_16V6K
2

PR515 Ultra-Sonic mode

2

0_0402_5% @ PJP502
1 2 5VD_EN 1 2
30,52 ALWON_PWR
+5VDP +5VD
JUMP_43X118
100K_0402_1%
1
@ PR518

5VD
2

4
TDC 2.55A 4
Peak Current 3.62A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+3V(NB680)/+5V(NB679)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 52 of 65
A B C D E
 5 4 3 2 1

+1.2V_DDR controller(35.3), Support component(35.4)

SH00001BM00
Main: CLSN, 2nd: CYN
D Package: 5.2 x 5.4 x 1.3 D

Idc=6.5A, Isat=9A
DCR=21.3mohm (Typ.)
PR601
2.2_0603_5%
PC600
0.22U_0402_16V7K
EMC@ PR602
4.7_0805_5%
EMC@ PC601
680P_0402_50V7K
+1.2V_DDRP
1 2 1 2 1 2 1 2

PR600 PL600
75_0402_5% 1UH_MHCI05015B-1R0M-R8A_6.5A_20%
1 2 1.2V_DDR_OT 1 2
11,30,50,57 H_PROCHOT#

220P_0402_50V8J

100K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M
1
PC602

PR603

PC606
1

1
PC603

PC605
PC604
11

10

13
9
PU600

2
FB
BST
OTW

SW

2
EMC@ PL601
HCB2012KF-121T50_0805
1 2 1 6 +1.2V_DDRP
B+ VIN VDDQ

100K_0402_1%
2200P_0402_25V7K
10U_0603_25V6M

0.1U_0402_25V6

1
EMC@ PC608

EMC@ PC609

C C

PR604
PC607

EN_0.6V 16 5
EN1 VTT +0.6VSP
NB685GQ-Z_QFN16_3X3
2

2
EN_1.2V 15 8 +0.6VSP
EN2 VTTS

10U_0402_6.3V6M

10U_0402_6.3V6M
1.2V_DDR_PG
12 7

0.22U_0402_10V6K
PG VTTREF

1
PR605

PC610

PC611
MODE
AGND

PGND
100K_0402_5%
0_0402_5%

1
3V3

PC612
1 2

PR606
6 SM_PG_CTRL

2
0.1U_0402_10V7K

@ PR608
1M_0402_1%

14

2
1

0_0402_5%
@ PC613
PR607

1 2
30,32 RUN_ON_EC
2

150K_0402_1%
1
2

PR609
2

1U_0402_16V6K
+0.6VSP +0.6VS +1.2V_DDRP +1.2V_DDR

2
1
0_0402_5%

B B
@ PR610

1
PC614
PR611
0_0402_5% @ PJP601 @ PJP600
1 2 1 2 1 2
30,32,43,45 SUS_ON_EC
2
1 2 1 2
0.1U_0402_10V7K

JUMP_43X39 JUMP_43X79
1M_0402_1%
1

@ PC615

1
PR612

+3VALW
+1.2V_VDDR
2

0.6Volt +/- 5%
2

TDC 3.20A
Peak Current 4.58A

Mode EN1 EN2 VDDQ VTT

S0 H H on on
S3 L H on off
A S4/S5 L L off off A

Note: S3 - sleep ; S5 - power off

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/10 Deciphered Date 2014/05/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.2V_DDR(NB685)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 53 of 65
5 4 3 2 1
 5 4 3 2 1

Module Design

+1.0VA controller(35.5), Support component(35.6)

D D

SH00001BO00
Main: CLSN, 2nd: CYN
Package: 4.2 x 4.75 x 2
Idc=4.2A, Isat=5.2A
PR705 DCR=43mohm (Typ.)
100K_0402_5%

1.0VA_PG
1 2 EMC@ PR702 EMC@ PC701
EMC@ PL700 +3VALW 4.7_0603_5% 680P_0402_50V7K
PU700
HCB2012KF-121T50_0805 1 2 1 2
1 2 VIN_1.0VA 2 9 PR703 PC702
B+ IN PG 0_0603_5% 0.1U_0603_25V7K
2200P_0402_50V7K

10U_0603_25V6M

10U_0603_25V6M
0.1U_0402_25V6

@EMC@ PC705
3 1 1 2 1 2 PL701

EMC@ PC704
EMC@ PC703

IN BS 1UH_MHCI04012-1R0M-R8EQ_4.2A_20%

PC706
1

1
4 6 LX_1.0VA 1 2
IN LX +1.0VAP

22U_0603_6.3V6M
330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M
22U_0603_6.3V6M
C C

14K_0402_1%
5 19
2

2
IN LX

1
PC707

PC710

PC711
PR704

PC709
7 20

PC708
GND LX
8 14

2
GND FB

2.2U_0402_6.3V6M

2
PR700 18 17 LDO_1.0VA
75K_0402_1% GND VCC

PC712
1 2 EN_1.0VA 11 10
10,30,32,44,55,56 SIO_SLP_SUS# EN NC

20K_0402_1%
@ PR707
0.22U_0402_10V6K

1
1 2 ILMT_1.0VA 13 12
1M_0402_1%

+3VALW

2
ILMT NC
1

PR706
100K_0402_5%
PR701

PC700

15 16
PR708 2 BYP NC
1
0_0402_5% 21
2

2
PAD
Current limit set to 6A
2

SY8286RAC_QFN20_3X3

4.7U_0603_6.3V6K
1
@ PR709
2
+1.0VA
+3VALW TDC 2.87A
PC713
0_0402_5%
1

Peak Current 3.75A

2

B B

@ PJP700
+1.0VAP 1
1 2
2 +1.0VA
JUMP_43X79

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.0VA(SY8286RAC)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 54 of 65
5 4 3 2 1
 A B C D

Module Design

+1.8VS controller(35.13), Support component(35.14)

@ PR720
SH00000ME00
0_0402_5% Main: TOKO, 2nd: CLSN
32,55 SUS_ON_P
1 2
+1.8VAP Package: 2.5 x 2.0 x 1.2
PR721
Idc=1.3A, Isat=1.7A
1
0_0402_5% DCR=96mohm (Typ.) 1

1 2 EN_1.8VA
10,30,32,44,54,56 SIO_SLP_SUS#
EMC@ PR723 EMC@ PC727
@ PC720 4.7_0603_5% 680P_0402_50V7K
0.1U_0402_25V6 1 2 1 2

13

14

15

16

17
1 2

EN

PGND

PGND
VOS

TP
EMC@ PL720 PL721
HCB1608KF-121T30_0603 2.2UH_1239AS-H-2R2N-P2_1.3A_30%
VIN_1.8VA SW_1.8VA
B+ 1 2 12
PVIN SW
1 1 2
+1.8VAP

2200P_0402_50V7K

22P_0402_50V8J
0.1U_0402_25V6

10U_0603_25V6M

412K_0402_1%

22U_0603_6.3V6M
1
EMC@ PC723

EMC@ PC724

PC725

PR722
1

PC721
11 PU720 2

1
PVIN SW

PC722
TLV62150ARGTR_QFN16_3X3
For ME5105 power up sequence

2
2

2
10 3
AVIN SW
footprint
Tss=1.65mS TLV62150RGTR_QFN16_3X3-S

1
SS_1.8VA 9

324K_0402_1%
4

3300P_0402_50V7-K
SS/TR PG 1.8VA_PG 30

PR724
@ PJP720

AGND
+1.8VA

PC726
+1.8VAP 1 2

FSW
DEF

1
1 2

100K_0402_5%
FB

2
@ PR725
JUMP_43X39

5
Fsw=1.25MHz

2
+1.8VA

1
0_0402_5%
@ PR726
TDC 0.31A

FB_1.8VA
+3VALW Peak Current 0.45A

2
2 2

+1.8VAP

Module Design

+1.8VU controller(35.15), Support component(35.16)

PR727
SH00000ME00
0_0402_5% Main: TOKO, 2nd: CLSN
32,55 SUS_ON_P
1 2 Package: 2.5 x 2.0 x 1.2
+1.8VUP Idc=1.3A, Isat=1.7A
@ PR728
0_0402_5% DCR=96mohm (Typ.)
1 2 EN_1.8VU
27,30,32,44,45,56 RUN_ON_P
EMC@ PR730 EMC@ PC735
@ PC728 4.7_0805_5% 680P_0402_50V7K
0.1U_0402_25V6 1 2 1 2
13

14

15

16

17

3 3

1 2
EN

PGND

PGND
VOS

TP

EMC@ PL722 PL723

HCB1608KF-121T30_0603 2.2UH_1239AS-H-2R2N-P2_1.3A_30%
VIN_1.8VU SW_1.8VU
B+ 1 2 12
PVIN SW
1 1 2
+1.8VUP

22U_0603_6.3V6M

22U_0603_6.3V6M
2200P_0402_50V7K
0.1U_0402_25V6

22P_0402_50V8J
412K_0402_1%
10U_0603_25V6M

1
EMC@ PC731

EMC@ PC732

PR729
1

1
PC730

@ PC736
PC733

11 2

PC729
PVIN SW
PU721
2

2
TLV62150RGTR_QFN16_3X3

2
10 3
AVIN SW

Tss=1.65mS
324K_0402_1%
1

SS_1.8VU 9 4 1.8VU_PG
3300P_0402_50V7-K

PR731

SS/TR PG
1

AGND
PC734

FSW

100K_0402_5%
DEF

@ PJP721
FB

PR732

+1.8VUP 1 2
+1.8VU
2

1 2
8

JUMP_43X39
Fsw=1.25MHz

2
1
0_0402_5%
@ PR733

FB_1.8VU

+3VALW +1.8VU
TDC 0.19A
2

Peak Current 0.27A

+1.8VUP
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+1.8VA/+1.8VU(TLV62150)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 55 of 65
A B C D
 5 4 3 2 1

+1.0VS_VCCIO controller(35.11), Support component(35.12)

PR801 @ PR800
0_0402_5% 10K_0402_1%
1 2 1 2
9,10,31,45,57 SIO_SLP_S0# +3VALW
PR826
1 2 EN_VCCIO
27,30,32,44,45,55 RUN_ON_P
0_0402_5% SH00000Q300
Main: TOKO, 2nd: CLSN

0.1U_0402_25V6
1
D D

1M_0402_1%

1
Package: 3.2 x 2.5 x 1.2

@ PR803

@ PC800
Idc=3.3A, Isat=4.6A
+1.0VS_VCCIOP DCR=48mohm (Typ.)

13

14

15

16

17
2
PU800

EN

PGND

PGND

TP
LPM
EMC@ PL800 EMC@ PR806 EMC@ PC808
HCB1608KF-121T30_0603 4.7_0603_5% 680P_0402_50V7K
VIN_VCCIO
B+ 1 2 12
PVIN VOS
1 1 2 1 2

2200P_0402_50V7K
PL801

0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
EMC@ PC806

EMC@ PC807
1UH_1277AS-H-1R0N-P2_3.3A_30%

PC801

PC802
1

1
LX_VCCIO
11
PVIN SW
2 1 2
+1.0VS_VCCIOP
+3VALW

22U_0603_6.3V6M
22U_0603_6.3V6M

22U_0603_6.3V6M
2

2
TPS62134ARGT_QFN16_3X3

1
PC804

PC805
10 3

PC803
AVIN SW

2
10K_0402_1%
1

1
10K_0402_1%

VID0_VCCIO 9 4 +1.0VS_VCCIO_PG
@ PR804

VID0 PG
PR805

100K_0402_5%
1
AGND
VID1

FBS

PR734
SS
2

VID0_VCCIO

100_0402_1%
1
@ PR807
8

5
VID1_VCCIO

2
@ PJP800

SS_VCCIO
VID1_VCCIO 1 2
Vout=0.95V
10K_0402_1%

10K_0402_1%

+1.0VS_VCCIOP +1.0VS_VCCIO
1

1 2
@ PR808

2
@ PR810
PR809

JUMP_43X79
+3VALW 0_0402_5%
1 2

100P_0402_50V8J
VCCIO_SENSE 16
+1.0VS_VCCIO
2

PC809

1
C 1 2
VSSIO_SENSE 16
TDC 2.17A C

Peak Current 3.10A

2
@ PR811

1
100_0402_1%
0_0402_5%

@ PR812

2
+1.0V_PRIM_CORE controller(35.7), Support component(35.8)

DVT2-011
For RS3 WOV feature support, we need to add a OR gate on LPM.
PR814 @ PR813
0_0402_5% 10K_0402_1%
1 2 VR_LPM# 1 2
9 VR_LPM_R# +3VALW
PR815
1 2 EN_PRIM_COREP
10,30,32,44,54,55 SIO_SLP_SUS#
130K_0402_1% SH00000Q300
Main: TOKO, 2nd: CLSN
0.1U_0402_25V6
1
1M_0402_1%

Package: 3.2 x 2.5 x 1.2

PC810
@ PR816

Idc=3.3A, Isat=4.6A
DCR=48mohm (Typ.)
2

+1.0V_PRIM_COREP
13

14

15

16

17
2

PU801
B B
EN

PGND

PGND

TP
LPM

EMC@ PL802 EMC@ PR819 EMC@ PC818

HCB1608KF-121T30_0603 4.7_0603_5% 680P_0402_50V7K
VIN_PRIM
CPU_B+ 1 2 12
PVIN VOS
1 1 2 1 2
2200P_0402_50V7K

@ PR1204 PL803
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
EMC@ PC817
EMC@ PC816

0_0603_5% 1UH_1277AS-H-1R0N-P2_3.3A_30%
PC811

PC812
1

LX_PRIM
1 2 11
PVIN SW
2 1 2
+1.0V_PRIM_COREP
RF DVT2 add

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

TPS62134DRGT_QFN16_3X3

PC813

PC814

@ PC815
1

1
10 3
+3VALW AVIN SW

2
9 4 1.0V_PRIM_CORE_PG
VID0 PG
100K_0402_5%
VID0_PRIM_CORE

1
AGND

@ PJP801
VID1

FBS

PR735
1

1
10K_0402_1%

10K_0402_1%

1 2
SS

+1.0V_PRIM_COREP +1.0V_PRIM_CORE
PR817

1 2
PR818

JUMP_43X79
8

2
VID1_PRIM_CORE
2

VID0_PRIM_CORE
SS_PRIM

VID1_PRIM_CORE @ PR822
0_0402_5% +3VALW +1.0V_PRIM_CORE
TDC 1.79A
470P_0402_50V7K

1 2 1 2
Vout=1.0V 17 CORE_VID0
10K_0402_1%
1

1
10K_0402_1%

Peak Current 2.57A

@ PR820

@ PR821

PC819

@ PR824
1

@ PR823
1
100K_0402_1%

0_0402_5% 0_0402_5%
@ PR825

17 CORE_VID1 1 2
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VCCIO/PRIM(TPS62134*2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 56 of 65
5 4 3 2 1
 5 4 3 2 1

VCC_CORE controller(36.1), Drivers (36.2), Support component(36.3)

CPU_B+
VDD18_CORE +3VALW
U42@ PU900
1.8V_LDO

2M_0402_5%
1

0_0402_5%
PR943

1
4.7_0402_5%
D D

PR950
PR935
SA0000AG600

2
MP2949AGQKT-0021-Z_TQFN48_6X6

2
PWM_CORE1 58

0.01U_0402_50V7K

4.7U_0603_10V6K
1U_0603_10V6K
133K_0402_1%
+3VALW

PC911
PWM_CORE2 58

1
PR942

PC902
PC901
+1.0V_VCCST

2
PWM_GT 59

VRACPU_VINSEN
2

VRA_VDD18
PWM_SA 59

0.1U_0402_25V6
1.91K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
1

1
PC900

1
PR931

@ PR919

@ PR918

PR917

@ PR920
CS_CORE1 58

49

47

26

44

43

42

41

40

39

38
2

2
CS_CORE2 58

+1.0V_VCCST

AGND

VIN_SEN

VDD18

VDD33

PRM1

PWM2

PWM3

PWM4

PWM5

PWM6
CS_GT 59
PR916
0_0402_5%
1 2 37 34
32 IMVP_VR_ON_P EN STB SYNC 58,59 CS_SA 59
PR921
0_0402_5%
0.1U_0402_25V6
45.3_0402_1%

1 2 35 PR910
100_0402_1%
75_0402_1%
10K_0402_1%

9,10,31,45,56 SIO_SLP_S0# SLP_S0#

1

1.5K_0402_1%
1
@ PR901
PR900
PR934

PR925

PR922 5 1 2
PC903

CS1 CSSUMA 57
0_0402_5%
1 2 33 PR911
2

30 IMVP_SMBCLK SCL_P
1.5K_0402_1%
2

PR923 4 1 2
@ CS2
0_0402_5%
1 2 32
30 IMVP_SMBDAT SDA_P
PR933 3
75_0402_5% CS3

11,30,50,53 H_PROCHOT# 1 2 31
VRHOT#
PR932 2
C CS4 C
0_0402_5%
1 2 30 PR912
10 PCH_PWROK VRRDY
1.5K_0402_1%
PR924 PR927 1 1 2
CS5 CSSUMB 57
0_0402_5% 49.9_0402_1%
1 2 1 2 27 PR913
14 VIDSCLK SCLK
1.5K_0402_1%
PR930 PR926 48 1 2
CS6 CSSUMC 57
0_0402_5% 0_0402_5% PU900
1 2 1 2 29 U22@ MP2949AGQKT-0020
14 VIDALERT_N ALT#
Change MPS2949A
PR929 PR928 SA0000AG610
0_0402_5% 10_0402_1%
1 2 1 2 28 PR914
14 VIDSOUT SDIO
1.91K_0402_1%
PR936 6 1 2
VDIFFA
0_0402_5%
1 2 25
ADDR_P
@ PR937 @ PC1423 1 2 1U_0402_10V6K @ PR953 @ PC931
10K_0402_1% 100K_0402_1% 0.01U_0402_16V7K
1 2 1 2 46 7 1 2 1 2
VDD18_CORE PR938 5.23K_0402_1% PSYS VFBA
1 2 PR903
30,50 P_SYS_R
PR949 0_0402_5% 0_0402_5%
Pull high on EE side
PR939 36 8 1 2
PE VOSENA VCCSENSE 14
0_0402_5%
1 2 PR956 PR904
61.9K_0402_1% 0_0402_5%
@ PR940 1 2 24 9 1 2
IREF VORTNA VSSSENSE 14
10K_0402_1% Pull low on EE side
1 2
+3VALW
18
57 CSSUMA CS_SUMA

19 PR915
57 CSSUMB CS_SUMB
U42@ PR941 2.49K_0402_1%
10 1 2
VDIFFB
20
57 CSSUMC CS_SUMC
U22@ PR941 @ PR954 @ PC932
B
SD034590280 118K_0402_1% 100K_0402_1% 0.01U_0402_16V7K
B
59K_0402_1% 1 2 21 11 1 2 1 2
IMON set t i ng: IMONA VFBB

U22 (1+1+1) PC904

220P_0402_50V8J
PR906
0_0402_5%
PR941=118k 1 2 22
IMONB VOSENB
12 1 2
Pull high on EE side
VCC_GT_SENSE 15
PR944=121k PR944 PR907
121K_0402_1% 0_0402_5%
1 2 23 13 1 2
U42(2+1+1) IMONC VORTNB
Pull low on EE side
VSS_GT_SENSE 15

PR941=59k PC905

VOSENC
VORTNC
470P_0402_50V7K

VDIFFC
PR944=121K
TEMP

VFBC
1 2

PR945
620K_0402_1%
45

14

15

17

16
1 2
PR947
PC906 0_0402_5%
8.06K_0402_1%

33P_0402_50V8J 1 2
58,59 VRACPU_VTEMP
1

1 2 PR951
PR948

0_0402_5%
Pull high on EE side
1U_0603_10V6K

1 2
49.9K_0402_1%

VSA_SEN+ 16
1
PR946
1
PC907

PR952
2

0_0402_5%
1 2
2

VSA_SEN- 16
Pull low on EE side
2

0.01U_0402_16V7K 100K_0402_1%
1
@ PR955

2
@ PC933

2 1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/17 Deciphered Date 2014/12/05 Title
PWR_MP2949A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 57 of 65
5 4 3 2 1
 5 4 3 2 1

VCC_CORE Dr. MOS (36.2), Support component(36.3)

CPU_B+

D D

1000P_0402_50V7K

100P_0603_50V7
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
1U_0603_25V6K
EMC@ PC1106

EMC@ PC1007
PR1101 PU1005

PC1104

PC1105

EMC@ PC1103
1

1
PC1009
0_0402_5%
1 2 14 1
SH00001FL00
+3VALW VCC VIN 8 Main: ML, 2nd: CLSN

1U_0402_25V6K
2

2
VIN

1
Package: 11.5 x 10.3 x 2.4

PC327
PC1110 Idc=35A, Isat=40A
0.22U_0603_25V7K
DCR=0.95mohm (Typ.)

2
13
AGND BST
15 1 2 +VCC_CORE
RF DVT1 add PL1100
0.15UH_MMD-10BD-R15MEM2L_35A_20%
2 1 2
SW
9 3
57 PWM_CORE1 PWM SW 4

@EMC@ PR1106
SW

1
11

4.7_0805_5%
57,58,59 VRACPU_VTEMP VTEMP/FLT
10 5
57,58,59 SYNC SYNC PGND 6
12 PGND 7
57 CS_CORE1

2
CS PGND

680P_0603_50V7K
MP86901-CGLT-Z_TQFN21_3X4

@EMC@ PC1108
1
2
B+ CPU_B+
C C
EMC@ PL1000
HCB2012KF-121T50_0805
1 2
82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J
47U_D3_20VM_R45M

47U_D3_20VM_R45M

47U_D3_20VM_R45M

EMC@ PL1002

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
HCB2012KF-121T50_0805 1 1 1

@EMC@ PC1434

@EMC@ PC1435

@EMC@ PC1436

@EMC@ PC1437
1 2
PC1030

PC1028

PC1003

EMC@ PC1424

EMC@ PC1425

EMC@ PC1426

EMC@ PC1427

EMC@ PC1428

EMC@ PC1429

EMC@ PC1430

EMC@ PC1431

EMC@ PC1432

EMC@ PC1433
1

1
+ + +
2

2
2 2 2

RF DVT2 add TOP

CPU_B+
NC for U22 CPU
1000P_0402_50V7K

100P_0603_50V7
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
1U_0603_25V6K
EMC@ PC1112

EMC@ PC1011

EMC@ PC1107

U42@ PR1103 U42@ PU1006

PC1010

PC1109
1

1
PC1113

0_0402_5%
1 2 14 1
SH00001FL00
B +3VALW VCC VIN 8 Main: ML, 2nd: CLSN B
2

VIN
1U_0402_25V6K
1

Package: 11.5 x 10.3 x 2.4

U42@ PC328

U42@ PC1114 Idc=35A, Isat=40A

0.22U_0603_25V7K
DCR=0.95mohm (Typ.)
2

13
AGND BST
15 1 2
+VCC_CORE
RF DVT1 add U42@ PL1101
0.15UH_MMD-10BD-R15MEM2L_35A_20%
2 1 2
SW
9 3
57 PWM_CORE2 PWM SW
4

@EMC@ PR1108
SW

1
11

4.7_0805_5%
57,58,59 VRACPU_VTEMP VTEMP/FLT
10 5
57,58,59 SYNC SYNC PGND
6
12 PGND 7
57 CS_CORE2
2
CS PGND 680P_0603_50V7K

MP86901-CGLT-Z_TQFN21_3X4
@EMC@ PC1111
1
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VCORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 58 of 65
5 4 3 2 1
 5 4 3 2 1

VCC_GT/SA Dr. MOS (36.2), Support component(36.3)

D D

CPU_B+

100P_0603_50V7
1000P_0402_50V7K
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
1U_0603_25V6K
EMC@ PC1118

EMC@ PC1008

EMC@ PC1115
PR1118 PU1107

PC1119

PC1116
1

1
PC1013
0_0402_5%
1 2 14 1
SH00001FL00
+3VALW VCC VIN
8 Main: ML, 2nd: CLSN

1U_0402_25V6K
2

2
VIN

1
Package: 11.5 x 10.3 x 2.4

PC337
PC1120
0.22U_0603_25V7K
Idc=35A, Isat=40A
DCR=0.95mohm (Typ.)

2
13
AGND BST
15 1 2
+VCC_GT
RF DVT1 add PL1102
0.15UH_MMD-10BD-R15MEM2L_35A_20%
2 1 2
SW
9 3
57 PWM_GT PWM SW
4

@EMC@ PR1117
SW

1
11

4.7_0805_5%
57,58,59 VRACPU_VTEMP VTEMP/FLT
10 5
57,58,59 SYNC SYNC PGND
6
PGND
12 7
57 CS_GT

2
CS PGND

680P_0603_50V7K
MP86901-CGLT-Z_TQFN21_3X4

@EMC@ PC1117
1
C C

2
CPU_B+
1000P_0402_50V7K

43P_0603_50V8
0.1U_0402_25V6

10U_0603_25V6M

10U_0603_25V6M
1U_0603_25V6K
EMC@ PC1123

EMC@ PC1012

PR1126 PU1108
PC1121

PC1122

EMC@ PC1125
1

1
PC1014

0_0402_5%
1 2 12 1
SH000018O00
+3VALW VCC VIN 6 Main: ML, 2nd: CLSN
1U_0402_25V6K

B B
2

VIN
1

Package: 6.6 x 7.3 x 1.3

PC338

PC1126 Idc=10.8A, Isat=15.5A

0.22U_0603_25V7K
DCR=7.4mohm (Typ.)
2

11
AGND BST
13 1 2
+VCC_SA
RF DVT1 add PL1103
0.47UH_MHCI06015-R47MR8A7R45_10.8A_20%
2 1 2
SW
7 3
57 PWM_SA PWM SW

@EMC@ PR1125
1
9

4.7_0805_5%
57,58,59 VRACPU_VTEMP VTEMP/FLT
8 4
57,58,59 SYNC SYNC PGND
10 5
57 CS_SA

2
CS PGND

680P_0603_50V7K
MP86901-AGQT-Z_TQFN13_3X3
@EMC@ PC1124
1
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/02 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VCORE, +VCCSA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F371P
Date: Tuesday, November 07, 2017 Sheet 59 of 65
5 4 3 2 1
 4
3
2
1
2 1
2 1
PC1270
PC1360 1U_0201_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1

2
1
+
2 1

+VCC_SA
+VCC_CORE

2
1
+
PC1272 PC1297 PC1221 PC1233 PC1230 @ PC1200
PC1364 @ PC1217 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M
1U_0201_6.3V6M 220U_B2_2.5VM_R15M 2 1 2 1 2 1 2 1 2 1

2
1
+
2 1
PC1273 PC1298 PC1229 PC1222 PC1232 PC1202
PC1370 2 1 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M

A
A

1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1

2
1
+
2 1 PC1357
47U_0805_6.3V6M PC1274 PC1299 PC1225 PC1246 PC1248 @ PC1201
PC1365 2 1 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1
2
1
+

2 1 PC1358
47U_0805_6.3V6M PC1275 PC1300 PC1250 PC1237 PC1223 U42@ PC1203
PC1356 2 1 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1 2 1
2 1 PC1359
@ PR1200
47U_0805_6.3V6M PC1288 PC1301 PC1220 PC1224
1K_0402_1%
PC1362 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1 2 1
PC1289 PC1302 PC1234 PC1227
PC1355 PC1361 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
1U_0201_6.3V6M 47U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1290 PC1259 PC1247 @ PC1228
PC1322 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
47U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1291 PC1260 PC1251 @ PC1231
PC1363 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
47U_0603_6.3V6M 2 1 2 1 2 1
2 1
PC1292 PC1261 PC1252
@ PC1366 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M
47U_0603_6.3V6M 2 1 2 1 2 1
2 1
PC1293 PC1262 PC1256
@ PC1368 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M
47U_0603_6.3V6M 2 1 2 1
2 1
PC1294 PC1263
@ PC1369 1U_0201_6.3V6M 1U_0201_6.3V6M
47U_0603_6.3V6M 2 1 2 1
2 1
PC1295 PC1265
@ PR1202
1U_0201_6.3V6M 1U_0201_6.3V6M

B
B

1K_0402_1%
2 1 2 1

PC1296 PC1266
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1
1uF_0201 X 33
10uF_0402 X 4
+VCC_CORE_U42
1uF_0201 X 33
10uF_0402 X 4
+VCC_CORE_U22

PC1303 PC1267
47uF_0603 X 10
47uF_0603 X 10

1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1

PC1304 PC1268
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1

PC1305 PC1269
220uF_B2 X 3 (NC X 1)
220uF_B2 X 2 (NC X 2)

1U_0201_6.3V6M 1U_0201_6.3V6M
47uF_0805 X 6 (NC X 2)
47uF_0805 X 6 (NC X 2)

+VCC_SA_U42
+VCC_SA_U22

1uF_0201 X 7
1uF_0201 X 7

47uF_0805 X 3
47uF_0805 X 3
VCC_CORE output cap(36.4), VCC_GT output cap(36.5), VCC_SA output cap(36.6), VCCIA_GT out cap(36.7)

220uF_B2 X 0 (NC X 1)
220uF_B2 X 0 (NC X 1)

47uF_0603 X 3 (NC X 3)
47uF_0603 X 3 (NC X 3)

C
C

2 1 2 1

PC1411 PC1276
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
+VCC_GT

+VCCIA_GT
2
1
+

PC1412 PC1401 PC1374 PC1323 PC1210 @ PC1335 PC1385 PC1312 PC1209

1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0805_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+

PC1413 PC1402 @ PC1375 PC1278 PC1211 @ PC1336 PC1384 PC1314 @ PC1208

Issued Date
1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0805_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M
2 1 2 1 2 1 2 1 2 1 2 1 2 1
2
1
+

Security Classification
PC1414 PC1403 2 1 PC1309 PC1212 @ PC1331 PC1386 PC1319 @ PC1207
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M 220U_B2_2.5VM_R15M
2 1 2 1 PC1326 2 1 2 1 2 1 2 1 2 1 2 1
47U_0603_6.3V6M
PC1387 @ PR1201
PC1415 PC1404 2 1 PC1311 PC1213 @ PC1337 PC1316
1K_0402_1%
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1 PC1327 2 1 2 1 2 1 2 1 2 1
47U_0603_6.3V6M
PC1416 PC1405 2 1 PC1281 @ PC1214 @ PC1258 PC1388 PC1317
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1 PC1328 2 1 2 1 2 1 2 1 2 1

2011/06/02
47U_0603_6.3V6M
PC1417 PC1406 2 1 PC1282 @ PC1215 @ PC1306 PC1392 @ PC1315
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1 @ PC1329 2 1 2 1 2 1 2 1 2 1
47U_0603_6.3V6M
PC1418 PC1407 2 1 PC1287 @ PC1216 @ PC1279 @ PC1390 @ PC1320
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1 @ PC1330 2 1 2 1 2 1 2 1 2 1
47U_0603_6.3V6M
PC1419 PC1408 2 1 PC1339 @ PC1218 @ PC1254 @ PC1391 @ PC1321
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 10U_0402_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1 @ PC1376 2 1 2 1 2 1 2 1
47U_0603_6.3V6M
PC1420 PC1409 2 1 PC1340 @ PC1255 @ PC1421 @ PC1324

D
D

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M

2 1 @ PC1377 2 1 2 1 2 1 2 1

Compal Secret Data

47U_0603_6.3V6M

Deciphered Date
PC1410 PC1341 @ PC1389 @ PC1422 @ PC1325
1U_0201_6.3V6M 1U_0201_6.3V6M 47U_0603_6.3V6M 47U_0603_6.3V6M 47U_0805_6.3V6M
2 1 2 1

PC1283 @ PC1253
1U_0201_6.3V6M 47U_0603_6.3V6M
2 1 2 1

PC1284 @ PC1393

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1U_0201_6.3V6M 47U_0603_6.3V6M
2 1 2 1

2013/10/28

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
PC1285 @ PC1394
1U_0201_6.3V6M 47U_0603_6.3V6M

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 1

@ PC1395
47U_0603_6.3V6M
2 1

@ PC1313
+VCCIA_GT

47U_0603_6.3V6M
2 1

Size
Title

Date:
@ PC1318
+VCC_GT_U42
+VCC_GT_U22

47U_0603_6.3V6M
1uF_0201 X 20
Prepare footprint for audio noise modify
1uF_0201 X 14
1uF_0201 X 14

Document Number

LA-F371P
220uF_B2 X 2 (NC X 1)
220uF_B2 X 1 (NC X 2)

47uF_0603 X 3 (NC X 4)
47uF_0805 X 1 (NC X 1)

Tuesday, November 07, 2017

47uF_0805 X 5 (NC X 5)
47uF_0805 X 5 (NC X 5)

10uF_0402 X 4 (NC X 4)
10uF_0402 X 4 (NC X 4)

E
E

47uF_0603 X 6 (NC X 20)

47uF_0603 X 6 (NC X 20)

Sheet
60
Compal Electronics, Inc.

of
PWR-CPU DECOUPLING

65
Re v
1.0
4
3
2
1
 5 4 3 2 1

I2C

U6 I2C0_SCL
NC
I2C0 U7 I2C0_SDA
NC
+3VS_TS
D D

4.7K
4.7K
PH RES on PCH page
U9 I2C1_SCK_TS 0-ohm
I2C1 U8 I2C1_SDA_TS Touch Sensor

0-ohm
+1.8VA +1.8V_IO_OUT

2.2K 2.2K
PCH 2.2K 2.2K
PH RES on SkyCAM page
AH10 SKYCAM_I2C_CLK 0-ohm G5 F6 WF_I2C_CLK WF_I2C_CLK
I2C2 World Facing
AH9 SKYCAM_I2C_DATA F5 Skycam PMIC D6 WF_I2C_DATA WF_I2C_DATA Camera

0-ohm
C C

AH12 PMIC_I2C_SCL
NC
I2C3 AH11 PMIC_I2C_SDA
NC
+1.8VA

2.2K
2.2K
PH RES on UFCAM page
AF12 UF_I2C_CLK

I2C4 AF11 UF_I2C_DATA Front Camera

B +3VS B

2.2K
2.2K
PH RES on Sensor page
N3 ISH_I2C0_SCL 0-ohm
ISH_I2C0 M4 ISH_I2C0_SDA Gyro + Accelerometer
0-ohm
+3VS 0-ohm

Compass
0-ohm
1K
1K
PH RES on UFCAM page
N2 ALS_I2C1_SCL 0-ohm
ISH_I2C1 N1 ALS_I2C1_SDA ALS Sensor

A
0-ohm A

AD12 ISH_I2C2_SCL
NC
ISH_I2C2 AD11 ISH_I2C2_SDA
NC Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P61-PCH I2C Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 61 of 65
5 4 3 2 1
 A B C D E

+3VS

2.2k 2.2k
SMBUS Address [0x9a]
+3V_PRIM
R7 DDR_XDP_SMBCLK DDR_XDP_SMBCLK

R8 DDR_XDP_SMBDAT DDR_XDP_SMBDAT XDP

1K 1K

1 1
D8 SML1_SMBCLK SML1_SMBCLK W3
E11 SML1_SMBDAT SML1_SMBDAT V3 PCH

+3V_5105
R9 SML0CLK
NC
W2 SML0DATA
2.2K 2.2K NC

C3 UPD1_PS_SMBCLK 0-ohm

B4 UPD1_PS_SMBDAT 0-ohm PD1

[0x70]

0-ohm

0-ohm
P-Sensor
[0x28]
+3VS_MUX

1K 1K
+3V_5105

HEAD EC 0-ohm
2 2
5105 MOSFET
2.2K 2.2K
0-ohm
MUX1 [0x22]
MOSFET

N2 PBAT_SMBCLK 100-ohm
M3 PBAT_SMBDAT BATTERY [0x16]
100-ohm
+3V_5105

2.2K 2.2K

C12 CHG_MCP23008_SMBCLK 0-ohm

E10 CHG_MCP23008_SMBDAT Charger [0x12]
0-ohm
+3V_5105
0-ohm
I/O Expander [0x42]
0-ohm
1K 1K

F7 BASE_SMBCLK
3 3
B6 BASE_SMBDAT POGO conn

+3V_5105

2.2K 2.2K
USH [0x7E]

E7 UPD2_USH_SMBCLK 0-ohm

D7 UPD2_USH_SMBCLK 0-ohm PD2 [0x7E]

+3VS_MUX

1K 1K

0-ohm
MOSFET
0-ohm
MUX2 [0x20]
MOSFET

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P62-SMBus Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 62 of 65
A B C D E
 5 4 3 2 1

+RTCVCC

SRTCRST#
T200 Discrete Power On Sequence
[AC in] [Battery only, AC absent]
[AC in] for VBUS1/VBUS2 [Battery only, AC absent]
ITEM Measure Point Time ITEM Measure Point Time
+VBUS1_PD_20V Ta +VBUS_PD_20V To +3V_LDO To
Ta
Tb 3V_LDO To EN_PD_HV1 To
+3V_LDO B+
Tb Tc EN_PD_HV1 To AC1_DISC# Tc B+ To +3V_LDO
PD Output EN_PD_HV1
Tc POWER_SW_IN#
1ns < Th < 4s Td AC1_DISC# To DCIN1_EN Th POWER_SW_IN# Low pluse width
Te DCIN1_EN To VBUS1_ECOK Td POWER_SW_IN# To ALW ON
PD Output AC1_DISC#
Td EC Input ALWON Td Tf VBUS1_ECOK To +CHG_VIN_20V Te ALW ON To +3VALW
D EC Output DCIN1_EN Tg +CHG_VIN_20V To B+ Tf ALW ON To +5VALW D
Te EC Output +3VALW Te
Th B+ To ACAV_IN Tg +3VALW To 3VALW _PG
EC Output VBUS1_ECOK
Tf *Varies by different power path scenario +5VALW Tf Ti ACAV_IN To ALW ON
+CHG_VIN_20V Tj ALW ON To +3VALW
Tg 3VALW_PG Tg
Tk +3VALW To +5VALW
B+
Tl +5VALW To 3VALW _PG
Th
EC Input ACAV_IN
Ti
EC Output ALWON
Tj
+3VALW
ITEM Measure Point Time
Tk
+5VALW T1 DSW_ON To +3VALW _DSW
Tl T2 +3VALW _DSW To SUSCLK
3VALW_PG T3 +3VALW _DSW To PCH_DPWROK
T4 PCH_DPWROK To SIO_SLP_SUS#
T5 SIO_SLP_SUS# To PCH_PWR_EN
1ns < Th < 4s
EC Input POWER_SW_IN# T6 PCH_PWR_EN To +3V_PRIM
T7 PCH_PWR_EN To +1.8V_PRIM
T8 PCH_PWR_EN To +0.95V_PRIM
T9 PCH_PWR_EN To +1.0V_PRIM

update
T10 PCH_PWR_EN To EXT_PWR_GATE#
EC pay attention timing PCH_PWR_EN
T11 To SIO_SLP_S0#
T12 EXT_PWR_GATE# To +1.0VA_GATE
T1 T13 PCH_PWR_EN To SUSACK#
PCH Output SUSCLK T14 PCH_PWR_EN To PCH_RSMRST#
T2
T15 PCH_RSMRST# To SUSWARN#
EC Output PCH_DPWROK
T3 T16 PCH_RSMRST# To AC_PRESENT
C C
PCH Output SIO_SLP_SUS# T17 PCH_RSMRST# To SIO_SLP_S5#
T4
T18 SIO_SLP_S5# To SIO_SLP_A#
EC Output PCH_PWR_EN
T5 T19 SIO_SLP_S5# To SIO_SLP_W LAN#
+3V_PRIM (U21)
T6
T20 SIO_SLP_W LAN# To AUX_EN_WOWL
T21 AUX_EN_WOWL To +3VS_W LAN
+1.8VA (PU720)
T7 T22 SIO_PWRBTN# To SIO_SLP_S4#
+1.0V_PRIM_CORE (PU801) T23 SIO_SLP_S4# To SUS_ON_EC
T8
T24 SUS_ON_EC To +1.8V_MEM
+1.0VA (PU700)
T9 T25 SUS_ON_EC To +1.2V_DDR
PCH Output MPHYP_PWR_EN (EXT_PWR_GATE#) T26 SUS_ON_EC To +1.0V_VCCST
T10
T27 SIO_SLP_S4# To SIO_SLP_S3#
+1.0V_MPHYGT
T11 T28 SIO_SLP_S3# To RUN_ON_EC
PCH Output SIO_SLP_S0# T29 RUN_ON_EC To +0.85VS_VCCIO
T12
T30 RUN_ON_EC To +1.0V_VCCSTG
EC Output SUSACK#
T13 T31 RUN_ON_EC To +1.2VS
EC Output PCH_RSMRST# T32 RUN_ON_EC To +1.8VS
T14
T33 RUN_ON_EC To +3VS
PCH Output SUSWARN#
T15 T34 RUN_ON_EC To +5VS
EC Output AC_PRESENT T35 +3VS To RUNPWROK
T16
T36 RUNPWROK To VR_ON
PCH Output SIO_SLP_S5#
T17 T37 VR_ON To VCORE_PG
PCH Output SIO_SLP_A# T38 VCORE_PG To +VCC_SA
T18
T39 VR_ON To SYS_PW ROK
PCH Output SIO_SLP_WLAN#
T19 T40 SYS_PW ROK To PCH_PLTRST#
EC Output AUX_EN_WOWL T41 PCH_PLTRST# To +VCC_CORE
T20
T42 PCH_PLTRST# To +VCC_GT
+3VS_WLAN
B B

EC Output SIO_PWRBTN# 16ms < T < 4s

Minimum durat i on of P WRBT N # asser t i on = 1 6mS aft er SUSC

K
L
T21 sta b l e
PCH Output SIO_SLP_S4# (SUS_ON_EC)
T22
EC Output SUS_ON_EC (SUS_ON) Reserved
T23
+1.2V_DDR
T24
+1.0V_VCCST
T25
PCH Output SIO_SLP_S3# (RUN_ON_P) (AND with SIO_SLP_S0# o/p VCCSTG_EN)
T26
EC Output RUN_ON_EC (Reserved)
T27
+3.3VDX_SS
T28
+1.0V_VCCST (SIO_SLP_S0# AND SIO_SLPS4# o/p VCCST-EN)
T29
+1.8VA (SIO_SLP_SUS#)
T30
+3VS
T31
+5VS
T32
EC Input RUNPWROK (ALL_SYS_PWRGD)
T33
EC Output IMVP_VR_ON_P (IMVP_VR_ON AND with SIO_SLP_S3# o/p H_VCCST_PWRGD_P)
T34
VCORE_PG (PCH_PWROK,PU900)
T35
+VCC_SA
T36
A A
EC Output SYS_PWROK
T37
PCH Output PCH_PLTRST# (AND itself to PLT_RST#)
T38
+VCC_CORE
T39
+VCC_GT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P63-Power Up Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 63 of 65
5 4 3 2 1
 5 4 3 2 1

SUS_STAT#

PCH_PLTRST#

H_CPUPWRGD

SIO_SLP_S3#

D D
SYS_PWROK

IMVP_VR_ON (H_VCCST_PWRGD)

+VCC_CORE

+VCC_GT

+VCC_SA

VCORE_PG (PCH_PWROK)

RUN_ON_EC

+0.85VS_VCCIO

+1.0V_VCCSTG

+1.2VS
C C

+1.8VS

+3VS

+5VS

RUNPWROK (ALL_SYS_PWRGD)

SIO_SLP_S4#

SUS_ON_EC

+1.0V_VCCST

+1.2V_DDR

+1.8V_MEM
B B

SIO_SLP_S5#

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P64-Power Down Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 64 of 65
5 4 3 2 1
 5 4 3 2 1

(8) +3VALW
(2) +3V_LDO (8) +3VALW
LDO

+3V_PRIM
+3VALW
(11) SIO_SLP_SUS# EN (12) +3V_PRIM
EN
(1) VBUS1_20V (3) +CHG_VIN_20V 20V 8.9V (4) B+
LDO_1.0VA
D
MOS MOS CHARGER (8) +5VALW D

(2) +3V_LDO +1.0VA

ACOK
+5VALW
(1) VBUS1_20V (6) ACAV_IN EN (12) +1.0VA
EN

(4) B+
(2) +3V_LDO
PD1

VBUS2_20V +1.8VA PG (14) SHD_IO2

EN (12) +1.8VA
(8) +3VALW
PD2 (0) +RTC (8) +3VALW
(8) +3VALW

VCI_OVRD_IN
PRIM_CORE
VCI_OUT (7) ALWON
(9) RESET_IN#
EN (12) +1.0V_PRIM_CORE

(8) +3VALW VCC_DSW3P3 GPIO_020

DSW_PW ROK (10) PCH_DPWROK
(4) B+
C C

(11) SIO_SLP_SUS# GPIO_230

SLP_SUS#
(12) +3V_PRIM VCC_PRIM3P3 RSMRST# EC 5105 GPIO_227
RSMRST# (15) PCH_RSMRST# (13) SHD_IO2 +1.2V_DDR
(16) ESPI_RESET# (26) +1.2V_DDR
ESPI_RESET# EN

(17) ESPI_IO
ESPI_IO ESPI_IO (4) B+
ROM SPI
PCH (18) SUSWARN#

(19) AC_PRESENT
+1.8VU
(21) SUS_ON_EC
(20) SUSACK
(24) SUS_ON_P EN (26) +1.8VU
(23) SIO_SLP_S4#

(13) SIO_SLP_S0# (12) +1.0VA

SLP_S0#

SLP_S5# (22) SIO_SLP_S5# +1.0V_VCCST

SLP_S4# (23) SIO_SLP_S4#

(25) VCCST_EN EN (26) +1.0V_VCCST
(11) SIO_SLP_SUS#
(8) +5VALW
SLP_S3# (27) SIO_SLP_S3#
B B

(32) VCCST_PWRGD_CPU +5VS

(28) RUN_ON_EC
VCCST_PW RGD
(31) IMVP_VR_ON (29) RUN_ON_P EN (34) +5VS
(27) SIO_SLP_S3#
(8) +5VALW

PROCPWRGD
(35) H_VCCST_PWRGD_P +3.3VDX_SSD

PCH_PW ROK
(36) PCH_PWROK EN (34) +3.3VDX_SSD

SLP_S3# (37) SYS_PWROK (8) +5VALW

PLTRST# (38) PCH_PLTRST# (30) RUN_PWR_OK MOS

(ALL_SYS_PWRGD)
+3VS

MOS EN (34)+3VS

(12) +1.0VA

A A

+1.0V_VCCSTG

(33) VCCST_EN
EN (34) +1.0V_VCCSTG
(13) SIO_SLP_S0#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/10/22 Deciphered Date 2013/10/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P65-PWR Sequence Bolock Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, November 07, 2017 Sheet 65 of 65
5 4 3 2 1