Dell Latitude 7200 La-G661p r0.4 (x03)

A B C D E
MODEL NAME : APRDDB2000

PCB NO : LA-G661P
BOM P/N : 431ADH31L0*
ZZZ
MB_PCB
1 1
Dell/Compal Confidential
2 2
Schematic Document
Augusta Whiskey Lake U
BOM Structure
@ : Nopop Component
RF@ : RF Component
3
@RF@ : RF Nopop Component 2019-03-05 3
EMC@ : EMI Component

@EMC@ : EMI Nopop Component
Rev: 0.4 (X03)
PVT
ST@ : ST TPM
750@ : Nuvoton TPM
NRTD3@ : non RTD3 support NDS3@ : non Deep sleep Support
RTD3@ : RTD3 support DS@ : Support Deep sleep
XDP@ : XDP Component CPUI7@ : I7 CPU identify for BIOS
DB@ : Debug Component CPUI5@ : I5 CPU identify for BIOS
BreakDown@ : Breakdown Component CPUI7EC@ : I7 CPU identify for EC
U22@ : CPU U22 identify for BIOS CPUI5EC@ : I5 CPU identify for EC
4
U42@ : CPU U42 identify for BIOS TPS79801QDGNR@ : Camera sensor AVDD main LDO 4
U22EC@ : CPU U22 identify for EC TPS7A1601DGNR@ : Camera sensor AVDD 2nd LDO
U42EC@ : CPU U42 identify for EC GIGADEVICE@ : BIOS ROM Option
5105@ : Option for MEC5105 WINBOND@ : BIOS ROM Option Security Classification
2018/05/08
Compal Secret Data
2018/05/08 Titl e
Compal Electronics, Inc.
Issued Date Deciphered Date
5106@ : Option for MEC5106 MXIC@ : BIOS ROM Option THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P001 - Cover
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G661P
D a te : Tuesday, March 05, 2019 She e t 1 of 100
A B C D E
A B C D E
Channel A
Sharp FHD+ eDP x2 lanes Memory Bus Channel A
12.3" eD P LPDDR3
Channel A 32Gb x 32 QDP VCC_EC
1920(H)x1280(V) p.38 p.23
VSW_3V3
I2C
Touch Cntrl I2C Channel B
Wacom W9015A p.38
Memory Bus Channel B
Channel B LPDDR3 RGB+IR module
32Gb x 32 QDP
Gyro + Accelerometer p.24
I2C or 3.3V LDO Boost
ST LSM6DS3TR p.66 I2C (iSH) RGB only module TPS61200
conn p.42
SPI ROM 32 MByte (Main) SPI USB2#5 USB 2.0 CSIx1 IR LED
E-Compass SPI#1 DSP Realtek 5849 I2C
ST LIS2MDLTR p.9 SPI ROM
p.66 2M bit 1.8V IR sensor
p.41
TPM2. 0 IMX488
1 1
ST33TPHF2XSP I IR discrete LDO*2 1.2V, 2.8V,

p.41 IR and CAM LED
p.66
USB 2.0 CSIx2 CAM LED
USB2#6
DSP Realtek 5876 I2C
UF sensor
Finger Print Module SPI ROM p.41 1.8V
USB 2.0 USB2#9 2M bit OV 5675
Synaptics FM-3472
UF discrete LDO*2 1.2V, 2.8V VSW_3V3 VC C
Connect with Power BTN board conn p.77 p.41
I2C I2C ALS
AMS-TAOS TSL25911
Smart Card Smart Card Reader USB 2.0
A/D TX/RX Pi-Matching i-pex conn
CONN NXP TDA8034HN USH Control Vault USB2#8
conn p.40 A/D
CV3
RDIF/NFC Broadcom 58202 CSIx4
USB 3.0
Antenna USB3#2 DSP Realtek 5880 I2C
SPI ROM 1.8V
2M bit p.39 WF sensor
SPI ROM OV8856
32M-bi t
on USH board conn p.73 WHL U IR discrete LDO*3
p.39
1.2V, 2.8V, 2.8(VCM)
I2C_CLK I2C_CLK
1x DMIC I2C_DAT I2C_DAT
SSD M.2 2230
PCIe x 2lanes SPK0838HT 4H-1
Slot 3-Key-M PCIe#15,16 I2C SPI ROM 2MB SPI I2C_I N T I2C_I N T
2230
p.68 SPI
DMI C CSR1021 GPIO PTP_MODE #

PTP_SLP#
PTP_MODE # USB_D+ USB 2.0 D+
PCIe x 2lanes 2x DMIC GPIO EN USB_D- USB 2.0 D-
WWAN 4G LTE PCIe/USB 3.0 PCIe#11/PCIe#1 2 p.56
M.2 3042 Slot 2-Key-B Mux p.53 USB 3.0 5V 5V
USB3#4 Audio Codec
3042
HDA
USB 2.0 ALC3254 Universal
T77W968. 00 USB2#7
p.53 Headset Jack p.57 GND GND CLK Charge/Low_BAT#
p.56 2x DAT
nano LTE Coex Speaker p.57 INT
SIM p.54 Dock_Detect
I/O ExpanderKB_LED
GPIO _PW M
DET_L DET_L KB_BL_DET#
TI TCA6416 MASK_LED#
CNVi
WLAN / BT 4.1 CNVi MUTE_LED#
M.2 2230 Slot 1-Key-E BT_LED#
PCIe x 1lane PCIe#10 I2C1 I2C1 I2C_CLK
CL K CL K
2230
USB2.0
CNVi Jefferson Peak 2 USB2#1 0 I2C_DAT
2 2
UART
RFFEM 802.11abgn+ac BT5.0 UART I2C_I N T I2C_CLK
CLINK I2C1 I2C1
p.52 CLINK I2C_DAT Accelermeter
DAT DAT ST LNG2DMTR
I2C_I N T
SD4.0/SDXC
RealTek PCIe x 1lane
I2C_I N T
uSD Connector SD_WP PCIe#9 I2C1 I2C1
RTS5242 PCIe to SD p.70
p.70 INT INT
GPIO
GPIO
(BIOS Controlled)
5V/2 A 5V 5V KSO/KSI
GPIO
USB2#4
D+ D+ USB 2.0 D+
USB 2.0 D-
Keyboard Matrix
USB2.0 BC1. 2 USB2.0
USB2#3
TI TPS2544
USB TypeA Connector D- D-
USB3.0 Re-redriver USB3.0 USB3#3
PS8811QFN36GT R2A
W/O
on USB board conn p.73 WC WC
Wireless
Charging
Function
HEAD_DET# GPIO GPIO BT ON/OFF Button
USB3.0 / DP x 2lanes or DP x 4 lanes DET _R DET _R
DP1.2 x 4lanes DDI#1
VBUS CHRG_IN DP1.2 x 4lanes DDI#2

MOSFE T
GND GND VR_OUT
PCIE 4 lane ( Gen3 ) PCIe#5/PCIe#6
From EC
PCIe#7/PCIe#8
Port-A VBUS PP_5V0 5V_AL W conn p.49
USB Type-C CC 2 CC
ALT mode WCFW _EN
with PD I2C to EC
TI-ACE 65982-DD +VCC_EC
USB (Top) From PD Port A
PD controller WC_OUT
3
USB (Bottom) USB2.0 USB2.0 3
USB2#1
p.43
p.44 Alpine Ridge
SPI ROM POGO_DET_ R #
8M-bi t Thunderbolt
USB3.0 / DP x 2lanes or DP x 4 lanes

PDs share ROM
WC_D I S C
WC PRU Board
VBUS CHRG_IN CHG_DICS(NC )
MOSFE T
I2C#1_INT
From EC
I2C#1_DAT
Port-B VBUS PP_5V0 5V_AL W
USB Type-C CC 2 CC
I2C#1_CLK
ALT mode
with PD I2C to EC
GND
TI-ACE 65982-DD
USB (Top) From PD Port B
USB (Bottom) USB2.0 PD controller
USB2.0
p.47 USB2#2
p.45
p.46
SPI ROM
8M-bi t
TABLET Keyboard
ESPI
EC JTAG MIPI60 Debug
Hall Sensor
APX8132 or AH1806-W I2C_CLK SPI Programmer ESPI Debug
p.63
EC I2C_DAT
Kickstand Open /Close detection MEC5105 I2C_I N T
(mechanical switch)
USB PD Debug APS Debug
p.77
MEC5106
SAR Proximity Sensor I2C
Smtech SX9310 DCI Debug
4
p.64 p.58 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/05/08 Deciphered Date 2018/05/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size
P002Number
Document
- Block Diagram Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Date : Monday , J anuary 28, 2019 Shee t 2 of 100
A B C D E
A
DVT2 DVT2.1 PVT

UCPU1 UCPU1 UCPU1
CPU_NV_QS_I3@ CPU_V_QS_I5@ CPU_V0_I3@
CPU Option
Board ID Table
SA0000C6R3L SA0000CNQ0L SA0000CNT0L
CLK
I3 NonVpro QS 10W I5 Vpro QS 10W Stepping V0 I3 CPU
USB 3.0
UCPU1 UCPU1 UCPU1 UCPU1 UCPU1 UCPU1
CPU_ES2_1.8G@ CPU_QS_I7@ CPU_PS_I7@ CPU_NV_QS_12.5W_I5@ CPU_V_QS_I7@ CPU_V0_I5@
SA0000C150L SA0000C6P0L SA0000C6P1L SA0000C6Q1L SA0000CNP0L SA0000CNS0L
I5 NonVpro QS 12.5W I7 Vpro QS 10W Stepping V0 I5 CPU
Vcc 3.3V +/- 5% UCPU1 UCPU1 UCPU1 UCPU1 UCPU1
CPU_ES2_1.6G@ CPU_QS_I5@ CPU_PS_I5@ CPU_NV_QS_10W_I5@ CPU_NV_QS_10W_I5@
Board ID R C REV SA0000C160L SA0000C6Q0L SA0000C6Q2L SA0000C6Q0L SA0000C6Q0L
0 240K +/- 5% 4700p EVT1 Flexible I/O Interface DESTINATION DIFFERENTIAL DESTINATION UCPU1
I5 NonVpro QS 10W
UCPU1
EC Option
CPU_ES_QRCT_1.8G CPU_NV_10W_I5@ UE4 UE4
1 130K +/- 5% 4700p DVT1 SA0000CF00L SA0000C6Q3L 5105@ 5106@
2 62K +/- 5% 4700p DVT2 1 PCI-E#1 / USB 3.0#1 CLKOUT_PCIE0 TBT AR ES Commercial U4+2 1.8GHz I5 NonVpro 10W SA00009GL30 SA0000C5D00
3 33K +/- 5% 4700p PVT

4 8.2K +/- 5% 4700p 2 PCI-E#2 / USB 3.0#2 WF Camera CLKOUT_PCIE1 Main SSD
X76 DRAM Option DRAM Config Option
(Resistor pop location)
5 4.3K +/- 5% 4700p
6 2K +/- 5% 4700p 3 PCI-E#3 / USB 3.0#3 USB3.0 Type-A CLKOUT_PCIE2 WWAN (2nd SSD) MEM_CON F IG0 MEM_CON F IG1 MEM_CON F IG2 MEM_CON F IG3
Micron 4GB/2133
7 NC UD1 UD2 UD3 UD4 RH7 RH13 RH14 RH10
4 PCI-E#4 / USB 3.0#4 NGFF (WWAN) CLKOUT_PCIE3 WLAN PCIe Gen2 X7679031L03
CLK M4G@
SA0000AZU0L
M4G@
SA0000AZU0L
M4G@
SA0000AZU0L
M4G@
SA0000AZU0L
M4G@
SD028100280
M4G@
SD028100280
M4G@
SD028100280
M4G@
SD028100280
Board ID Option 5 PCI-E#5 / USB 3.0#5 CLKOUT_PCIE4 Card Reader Micron 8GB/2133
UD1 UD2 UD3 UD4 RH15 RH13 RH14 RH10
RE53 RE53 RE53 RE53 RE53 RE53
X7679031L06 M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@ M8G@
X00@ X01@ X02@ X03@ X04@ A00@ SA0000AM40L SA0000AM40L SA0000AM40L SA0000AM40L SD028100280 SD028100280 SD028100280 SD028100280
SD000020300 SD028130380 SD028620280 SD028330280 SD028820180 SD028430180 6 PCI-E#6 / USB 3.0#6 CLKOUT_PCIE5 N/A
240K_0402_5% 130K_0402_5% 62K_0402_5% 33K_0402_5% 8.2K_0402_5% 4.3K_0402_5%
TBT Alpine Ridge Micron 16GB/2133
UD1 UD2 UD3 UD4 RH7 RH16 RH12 RH10
7 PCI-E #7 X7679031L09 M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@ M16G@
SA00009ZN0L SA00009ZN0L SA00009ZN0L SA00009ZN0L SD028100280 SD028100280 SD028100280 SD028100280
8 PCI-E #8 Hynix 4GB/2133
USB 2.0 9 PCI-E #9 Card reader

X7679031L01 UD1
H4G@
SA0000AZR1L
UD2
H4G@
SA0000AZR1L
UD3
H4G@
SA0000AZR1L
UD4
H4G@
SA0000AZR1L
RH15
H4G@
SD028100280
RH16
H4G@
SD028100280
RH12
H4G@
SD028100280
RH10
H4G@
SD028100280
Hynix 8GB/2133
USB 2.0 PORT# DESTINATION 10 X7679031L04 UD1 UD2 UD3 UD4 RH7 RH13 RH12 RH10
PCI-E #10 WLAN PCIe Gen2 H8G@
SA0000ALP1L
H8G@
SA0000ALP1L
H8G@
SA0000ALP1L
H8G@
SA0000ALP1L
H8G@
SD028100280
H8G@
SD028100280
H8G@
SD028100280
H8G@
SD028100280
1 TBT1 Hynix 16GB/2133

11 PCI-E #11 /SATA #0 UD1 UD2 UD3 UD4 RH15 RH13 RH12 RH10
WWAN (2nd SSD) X7679031L07 H16G@ H16G@ H16G@ H16G@ H16G@ H16G@ H16G@ H16G@
2 TBT2 SA00009ZL1L SA00009ZL1L SA00009ZL1L SA00009ZL1L SD028100280 SD028100280 SD028100280 SD028100280
12 PCI-E #12 /SATA #1A
Samsung 4GB/2133
3 USB Type-A 13 X7679031L02 UD1 UD2 UD3 UD4 RH7 RH16 RH14 RH11
PCI-E #13 S4G@
SA0000BTE1L
S4G@
SA0000BTE1L
S4G@
SA0000BTE1L
S4G@
SA0000BTE1L
S4G@
SD028100280
S4G@
SD028100280
S4G@
SD028100280
S4G@
SD028100280
4 Dock Samsung 8GB/2133

14 PCI-E #14 UD1 UD2 UD3 UD4 RH15 RH16 RH14 RH11
X7679031L05 S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@ S8G@
5 IR Camera SA0000AZT2L SA0000AZT2L SA0000AZT2L SA0000AZT2L SD028100280 SD028100280 SD028100280 SD028100280
15 PCI-E #15 /SATA #1B
Main SSD (2230) Samsung 16GB/2133
6 UF Camera X7679031L08 UD1 UD2 UD3 UD4 RH7 RH13 RH14 RH11
16 PCI-E #16 /SATA #2 S16G@ S16G@ S16G@ S16G@ S16G@ S16G@ S16G@ S16G@
SA00008VV3L SA00008VV3L SA00008VV3L SA00008VV3L SD028100280 SD028100280 SD028100280 SD028100280
7 WWAN
8 USH PVT
UCPU1 UCPU1
I7_8665U_Vpro@ I5_8265U_nVpro@
9 FPR
SMBUS / I2C Control Table
SA0000CNP2L SA0000CNS6L
UCPU1 UCPU1
I5_8365U_Vpro@ I3_8145U_nVpro@
10 BT SA0000CNQ2L SA0000CNT5L
EC Touch BASE Gyro+ACC PS8811 UCPU1

E-Compass SAR sensor Bat t ery ALS I7_8565U_nVpro@
SOURCE MEC5105 Screen PD2 USH PD1 Re-driver SA0000CNR3L
Charger
1 1
SML1 _SMBDATA
SML1_SMBCLK
PCH_SMBus
V
Displayport I2C0_SDA
I2C0_SCL
PCH_I2C
V
I2C1_SDA PCH_I2C
DDI PORT# DESTINATION I2C1_SCL
DDI 1 ISH_I2C0_SDA
ISH_I2C0_SCL
PCH_ISH
V
TBT Alpine Ridge
2 ISH_I2C1_SDA
ISH_I2C1_SCL
PCH_ISH
V
eDP 1 FHD SMB00_DATA
SMB00_CLK
EC_SMBus
V
SMB01_DATA
SMB01_CLK
EC_SMBus
V V
SMB02_DATA EC_SMBus
V
Board ID Table Symbol Note :
SMB02_CLK
SMB04_DATA
SMB04_CLK
EC_SMBus
V
Board ID PCB Revision SMB05_DATA EC_SMBus
V
0
1
2
0.1
0.2
0.3
@ : means de-pop
SMB05_CLK
SMB10_DATA
SMB10_CLK
EC_SMBus
V
3 0.4
: means Digital Ground
4 0.5
5 1.0
6 : means Analog Ground
7

Issued Date 2018/05/08 Deciphered Date 2018/05/08 Titl e
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P003 - Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Date : Wednesday, March 06, 2019 Shee t 3 of 100
A
5 4 3 2 1
EN_INVPWR (EC)
CPU PWR SI3457BDV-T1-E3
PMOS (Q15) +INV_PWR_SRC
PCH PWR R5 9 0 3
GPU PWR
Type C X 2 Peripheral Device PWR PL Z 3 0 1
PL Z 3 0 2
NB502GQ- Z ALWON_P WR(E C)
G517G1TO1U DOCK_PWR_E N(E C)
+5V_DOCK
CPU_B+ PL Z 3 0 3 VR_B+PL Z 3 0 5 (PU551) +5VALW (U13)
PL Z 3 0 4 PL Z 3 0 6 PJ P 5 0 1 DOCK R91
USH Board
I MV P
MP86902 +5VALW_USH
(PUG101) +VCC_GT
PL G 1 0 1 USH Board RB38
RB39
Type A Board
I MV P
MP86902
ISL9538BHRTZ- T +VCC_SA Power LED
D (PUB1)
(PUA101) PL A 1 0 1 D
I MV P
MP86902-BGLT-Z Type C CONN
(PUZ101) +VCC_CORE For device
PL Z 1 0 1
I MV P
MP86902-BGLT-Z AP2112K +3VALW_PD1
(PUZ201) +VCC_CORE (UT2)
PL Z 2 0 1
BATTERY
(PJT1) TPS62134ARGT RUN_O N_ P
+3V_LDO
PRB2 (PU801) +1.0VS_VCCIO
PL 8 0 2
SIO _ S L P _ S U S # AUD_PWR_ E N
NB692GD-Z +1.0V_PRIM_CORE
AOZ1331D +5VS_AUDIO
(PU851) (U26)
PJ P 8 5 1
SIO _ S L P _ S U S #
SY8286RAC
(PU101) +1.0VA +1.0V_CLK
SIO _ S L P _ S 4 # PJ P 1 0 1
SU S _ O N _ E C
TLV62150ARGTR +1.8VU
(PU1851) LPDDR3PJ P 1 8 2 TPS22961 RUN_O N_ P
+VCCPRIM_1P05
(UZ6) +1.0V_VCCST
RUN_ON_ P & R190
B+
SIO _ S L P _ S 4 # CPU_C10_GATE#
+1.2V_DDR TPS22961 RUN_ON_ P &
LPDDR3 (UZ4) +VCCPLL_OC CPU_C10_GATE# +1.0V_AMPHYPLL
PJ P M0 1
NB685GQ- Z R158
TPS22961 +1.0V_VCCST G
(PUM01) (UZ5) R184
SM_ P G _ C TR L
+0.6VS RUN_O N_ P
LPDDR3 AOZ1331DI +1.2V_USB
PJ P M0 2 (U38) Type A Board R301
ALWON_P WR(E C) RUN_O N_ P

C NB679AGD-Z +5VS_USH RB40
C
(PU501) +5VD TPS22967DSGR +5VS USH Board RB41

PJ P 5 5 1 (U30) R186
+5V_FAN
Type A Board R167
AUD_PWR_ E N
AOZ1331DI
(U26) +5VS_AUDIO Camera LED
R142
SIO _ S L P _ S U S # RUN_O N_ P
TLV62150ARGTR AOZ1331DI
(PU1801) +1.8VA (UZ3) +1.8_VS
PJ P 1 8 1 R58
AUD_PWR_ E N
AOZ1331DI
(UZ2) +1.8VS_AUDIO
R122
+1.8VA_EC
RE63
SIO _ S L P _ S 3 #
ALWON_P WR(E C) R U N _ON _EC
MP8733AGLE-Z +3VS_USH
(PU301) +3VALW AOZ1331_DFN_14P +3VS USH Board RB34
PJ P 3 0 1 (UZ23) R141 RB35
LSM6DS3USTR
+3V_5105 3D accelerometer
RE51
3D gyroscope RS10
+3VALW_PD2 SX9310ICSTRT
R T8 4 SAR Proximity
Sensor RS6
B
+3VA_TBT B
VCC3P3_SX R T11 3
+3V_TBT
FPR_PWR_EN# (E C) R T11 2
DMG2301U-7
PMOS (QV12) +3.3V_FPM
R298
Realtek 5880(WF)
and OV8856
R128
MP2410AGJ-Z APX8132AI-T RG
_TSOT23- 6 IR_LED_ E N Hall sensor (U7) Realtek 5876(UF)
(PUL1) IR_LED+ and OV 5675
ENV DD R94
SY6288C20AAC +LCDVDD Realtek 5849(IR)
(U12) R85
and IMX488
R11 2
+3VALW_USH
USH Board RB36
RB37 PI3PCIE3212ZBEX
3.3 V _ TS _ E N
USB/PCIE MUX(U8)
R201
AOZ1331DI
(U9) +3VS_TS
R79
ALS
RUN_O N_ P
SSD_SCP_PWR_ E N
AMS-TAOS TSL2591
RS20
AOZ1331DI
(U9) +3.3VDX_SSD
R78
+3V_FAN
AUX_EN_WOWL _ R R153
AOZ1331DI
(U31) +3V_WLAN
R169 +3VS_USB
+3 V S
TYPE A BOARD
R77
SY6288C20AAC
(UC5) +3VS_CR
R195
AUD_PWR_ E N
AOZ1331DI
(U26) +3VS_Audio
R136
3.3V_WWAN_ E N
AOZ1331DI +3V_RF
(UZ2) +3VS_WWAN L24 Tunnable IC
A A
L25 R26
SIO _ S L P _ S U S #
AOZ1336DI
(U29) +3V_PCH +3.3V_VPS_T PM
R157 RZ1 5
DELL CONFIDENTIAL/PROPRIETARY
Issued Date 2018/05/08 Deciphered Date 2018/05/08 Tit l e
P004 - Power MAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Si ze Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-G661P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date : Monday , January 28, 2019 Sh e e t 4 of 100

5 4 3 2 1
5 4 3 2 1
Deep Sleep
[AC in] (remove RTC) [Battery only, AC absent] (remove RTC)
+VBUS1_P D_20V
+3.3V_VDD_P I C +3.3V_BAT_LDO
+RTCV CC +RTCV CC
SRTCRST# / RTCRST# tPCH01 18 - 25 ms SRTCRST# / RTCRST# tPCH01 18 - 25 ms
D PD Output EN_PD_HV1 (S1a) Power path S1a ON

B+ D
S1b pass through

1ns < Th < 4s
PD Output EN_PD_HV1 (S1b) body diode Input to EC POWER_S W _I N#
+CHG_VIN_20V
B+
ACAV_IN1 & EN_PD_HV1
Input to EC ACAV _I N AND gate to EC
DC only
EC Output ALW ON
+3VALW / +5VALW / +5VD
ALW_PWRGD_3V _5V
Power path S1b ON

EC Output DCIN1_EN / VBUS1_ECOK
tPCH04 > 9ms
+3VALW +3V_PCH_DSW (Q8)
RESET_IN #
tPCH05 > 1us
EC Output PCH_DP W ROK 10ms Delay tPCH02 > 10ms
PCH Output SIO_SLP_S US # tPCH32 > 95ms
PCH Output SIO_SLP _S 0#
PCH Output CPU_C10_GATE#
+3V_P CH
+1.8V_PRI M
+1.0V_PRIM_CORE
C
+1. 0VA tPCH06 > 200us C
PCH Output SUSCLK tPCH31 < 10ms+95ms
Input to EC PRIM_P W RGD

tPCH03 > 10ms
tPCH07 > 0ms
EC Output PCH_RSMRS T#
tPCH18 > 90us
PCH Output ESPI_RES ET#
EC Output AC_PRESENT (AC only) tPLT02 < 0ms
AC only
1ns < Th < 4s
POWER_SW_IN# (AC only)
EC Output SIO_PWRBTN# tPCH43 > 95ms
+1.2V_DDR / +1.2V_DDR_PG
+1.8V U
PCH Output SIO_SLP_W LAN#
+3VS_W LAN
EC Output RUN_ON_EC
+5VS / +3VS / +1.8VS / +1.2V_USB.....

B B
+VCCPLL_OC
+1.0V_V CCS T
+1.0V_VCCS TG tCPU03 < 25ms tCPU04 > 0ms
+1.0VS_V CCI O tCPU05 > 100ns tCPU06 > 100ns
Input to EC RUNPWROK (DDR_PG / PG_VCCIO)
EC Output IMVP_VR_ON_EN
PCH Input VCCST_PWRGD (IMVP_VR_ON_EN with Level shift) tCPU01 > 1ms tCPU00 > 1ms
+VCCS A
tPLT04 > 1ms
PCH Output DDR_VTT_CNTL tCPU19 > 100ns
+0.6V S tCPU18 > 35us
IMVP Output IMVP_V R_P G

tPCH08 > 1ms
PCH Input PCH_PWROK (IMVP_VR_PG + RUNPWROK with AND gate) tCPU16 > 0ns
PCH Output H_CPUPWRGD (PROCPWRGD)

tPLT05 > 0ms
EC Output SYS_P W ROK
PCH Output PCH_PLTRS T#
+VCC_CORE
+VCCGT
CPU_RES ET#
DDR_RES ET#
A
CPU_S V I D A

P005 - Power Sequence
Date : Monday, January 28, 2019 Shee t 5 of 100
5 4 3 2 1
5 4 3 2 1
D D
UCPU1A
(47) CPU_DP1_N0
AL5 AG4
AL6 DDI1_TXN_0 EDP_TXN_0 AG3 EDP_TXN0 (38)
(47) CPU_DP1_P0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 (38)
(47) CPU_DP1_N1
AJ5 AG2
AJ6 DDI1_TXN_1 EDP_TXN_1 AG1 EDP_TXN1 (38)
All VREF traces should (47) CPU_DP1_P1 DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 (38)
AF6 AJ4
have 10 mil trace width (47) CPU_DP1_N2
AF5 DDI1_TXN_2 EDP_TXN_2 AJ3
EDP
(47)
(47)
CPU_DP1_P2
CPU_DP1_N3
AE5 DDI1_TXP_2
DDI1_TXN_3
EDP_TXP_2
EDP_TXN_3
AJ2 EDP
(47) CPU_DP1_P3
AE6 AJ1
DDI1_TXP_3 DDI EDP_TXP_3
C COMPENSATION PU FOR eDP Alpine Ridge C
AC4
CAD Note: (47) CPU_DP2_N0
AC3 DDI2_TXN_0 AH4
(47) CPU_DP2_P0 DDI2_TXP_0 EDP_AUX_N EDP_AUXN (38)
Trace width=5 mils AC1 AH3
Isolation Spacing=25mil,
(47)
(47)
CPU_DP2_N1
CPU_DP2_P1
AC2 DDI2_TXN_1 EDP_AUX_P EDP_AUXP (38) embedded DisplayPort Ut ilit y: Out put c ontr ol
DDI2_TXP_1
Max length=100 mils. (47) CPU_DP2_N2
AE4
AE3 DDI2_TXN_2 DISP_UTILS
AM7 signal used for brightness correct i on of e mbedded
(47)
(47)
CPU_DP2_P2
CPU_DP2_N3
AE1 DDI2_TXP_2 AC7 LCD displays with backlight modulat i on.
DDI2_TXN_3 DDI1_AUX_N CPU_DP1_AUXN (47)
AE2 AC6
(47) CPU_DP2_P3 DDI2_TXP_3 DDI1_AUX_P CPU_DP1_AUXP (47)
AD4
DDI2_AUX_N CPU_DP2_AUXN (47)
AD3
+1.0VS_VCCIO DDI2_AUX_P CPU_DP2_AUXP (47)
Trace Width : 5mil AG7
Isolation Spacing : 25mil DDI3_AUX_N AG6 PAD~D @ T10
+3VS EDP_RCOMP DISPLAY SIDEBANDS
1 2 Max Length : 600mil
AM6 DDI3_AUX_P PAD~D @ T26
DISP_RCOMP
CPU_DP1_CTRL_CLK RC243 24.9_0402_1% CPU_DP1_CTRL_CLK CPU_DP1_HPD CPU_DP1_HPD
1 2 CPU_DP1_CTRL_DATA
CC8 CN6 CPU_DP2_HPD
1 2
(47) CPU_DP1_CTRL_CLK GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# GPP_E13/DDPB_HPD0/DISP_MISC0 CPU_DP1_HPD (47)
RC117 2.2K_0402_5%
CPU_DP1_CTRL_DATA (47) CPU_DP1_CTRL_DATA
Strap Pin CC9 CM6
CPU_DP2_HPD (47) CPU_DP2_HPD RC185 100K_0402_5%
1 2 GPP_E19/DPPB_CTRLDATA GPP_E14/DDPC_HPD1/DISP_MISC1 CP7 1 2
CPU_DP2_CTRL_CLK GPP_E15/DPPD_HPD2/DISP_MISC2
RC176 2.2K_0402_5% CPU_DP2_CTRL_DATA
CH4 CP6 EDP_HPD EDP_HPD RC165 100K_0402_5%
(47) CPU_DP2_CTRL_CLK Strap Pin CH3 GPP_E20/DPPC_CTRLCLK GPP_E16/DPPE_HPD3/DISP_MISC3 CM7 1 2
CPU_DP2_CTRL_CLK (47) CPU_DP2_CTRL_DATA GPP_E21/DPPC_CTRLDATA GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD (38)
1 2 CPU_DP3_CTRL_CLK PANEL_BKLEN RC184 100K_0402_5%
RC152 2.2K_0402_5%
CPU_DP2_CTRL_DATA CPU_DP3_CTRL_DATA CP4 CK11 ENVDD_PCH PANEL_BKLEN
1 2 Strap Pin CN4 GPP_E22/DPPD_CTRLCLK EDP_BKLTEN CG11 PANEL_BKLEN (10,38) RC619 1 @ 2 0.33U_0201_6.3V6M
+1.8VA GPP_E23/DPPD_CTRLDATA EDP_VDDEN CH11 ENVDD_PCH (38)
RC233 2.2K_0402_5% ENVDD_PCH
CR26 EDP_BKLTCTL EDP_BIA_PWM (38) RC620 1 @ 2 0.33U_0201_6.3V6M
CPU_DP3_CTRL_CLK GPP_H17 GPP_H16/DDPF_CTRLCLK
1 @ 2 1 @ 2 Strap PinCP26
RC614 2.2K_0402_5% RC28 20K_0201_5% 1. 8 V GPP_H17/DDPF_CTRLDATA
CPU_DP3_CTRL_DATA
1 @ 2
RC615 2.2K_0402_5% PCH GLITCH ISSUE MITIGATION(PDG p.130)
0 = DisplayPort not detected. (Default) WHL-U42_BGA1528
@
1 = DisplayPort is detected. Reserved 1 of 20
GPP_H17 (WEAK INTERNAL PD)

This signal has a weak internal pull-down.
This strap should sample LOW. There should NOT be
any on-board device driving it to opposite direction
B B
during strap sampling.
A A

P006 - WHL-U(1/14)DDI,EDP
D a te : Monday, January 28, 2019 She e t 6 of 100
5 4 3 2 1
5 4 3 2 1
DIMM TYPE PU/PD for CPU JTAG signals PU/PD for PCH JTAG signals
Connect to XDP Conn.
+1.0V_VCCSTG +1.0V_VCCSTG (Option w/ CPU JTAG)
CPU_XDP_TMS PCH_JTAG_TMS
RC255 2 1 51_0402_5% RC270 2 1 51_0402_5%
1 : Interleave @
CPU_XDP_TDI PCH_JTAG_TDI
RC190 2 @ 1 51_0402_5% RC269 2 1 51_0402_5%
0 : Non-Interleave +3V_PCH
CPU_XDP_TDO PCH_JTAG_TDO
RC241 1 @ 2 100_0402_1% RC141 1 2 100_0402_1%
D D
CPU_XDP_TCK PCH_JTAGX
RH30 1 @ 2 10K_0201_5% RC232 2 1 51_0402_5% RC229 2 @ 1 51_0402_5%
MEM_INTERLEAVED CPU_XDP_TRST# PCH_JTAG_TCK
RH2 1 2 10K_0201_5% @ RC245 2 1 51_0402_5% RC268 2 @ 1 51_0402_5%
PCH_JTAG_TRST#
RC666 2 @ 1 51_0402_5%
+1.0V_VCCST UCPU1D
H_CATERR# CPU_XDP_TCK
H_THERMTRIP#_R AA4 T6 CPU_XDP_TDI
RC192 1 2 1K_0402_1% AR1 CATERR# PROC_TCK U6
(58) PECI_EC H_PROCHOT# H_PROCHOT#_R PECI PROC_TDI CPU_XDP_TDO
H_CATERR# RC180 1 2 499_0402_1% H_THERMTRIP#_R Y4 CPU MISC JTA G Y5 CPU_XDP_TMS <CPU JTAG>
(58,83,86,90) H_PROCHOT# PROCHOT# PROC_TDO
@ RC143 1 2 49.9_0402_1% RC283 1 @ 2 0_0402_5% BJ1 T5 CPU_XDP_TRST#
(58) H_THERMTRIP# THRMTRIP# PROC_TMS AB6
XDP_BPM#0 PROC_TRST#
PVT-076 T9 @ XDP_BPM#1
U1
+1.0V_VCCSTG Change to short-pad T8 @ U2 BPM#_0
XDP_BPM#2_R BPM#_1 PCH_JTAG_TCK
H_PROCHOT# T32 @ XDP_BPM#3_R
U3 W6 PCH_JTAG_TDI +3VS
RC95 1 2 1K_0402_1% T33 U4 BPM#_2 PCH_TCK U5
@ PCH_JTAG_TDO
BPM#_3 PCH_TDI W5 PCH_JTAG_TMS <PCH JTAG>
2
PCH_TDO P5
MEM_INTERLEAVED PCH_TMS PCH_JTAG_TRST#
TOUCH_SCREEN_PD# CE9 Y6 PCH_JTAGX RC60
CN3 GPP_E3/CPU_GP0 PCH_TRST# P6 10K_0201_5%
CB34 GPP_E7/CPU_GP1 PCH_JTAGX 1 @ 2
GPP_B3/CPU_GP2 +1.0V_VCCSTG
CC35 XDP_PREQ# RC664 1K_0402_5%
1
GPP_B4/CPU_GP3 W2
PROC_PREQ# XDP_PRDY#
W1 To Wacom TS DC2 From PCH
CPU_POPIRCOMP
PCH_POPIRCOMP
BP27 PROC_PRDY# Follow PBC MLK (38) TOUCH_SCREEN_PD#_R
2 1
TOUCH_SCREEN_PD#
BW25 PROC_POPIRCOMP
EDRAM_OPIO_RCOMP PCH_OPIRCOMP
EOPIO_RCOMP RB751S40T1G_SOD523-2
L5 RC61 2 @ 1 0_0201_5%
1
N5 RSVD70
RSVD71
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC89
RC142
RC101
RC100
DC1 @
WHL-U42_BGA1528 2 1 PVT-179
ISH_LID_CL#_NB (12,58) Base on panel tream request
@ 4 of 20 NC DC1
2
RB751S40T1G_SOD523-2
C C
@ @
DC3
2 1
DISPOFF# (38)
Follow PBC MLK

+3V_PCH_DSW
1
1.5K_0402_5%
RC663
FIVR_EN
RC662 1 @ 2 0_0402_5%
FIVR_EN_R
CFG0 RC661 1 @ 2 1K_0402_5%
2
XDP_PWRBTN#
+1.0V_VCCST
FIVR_EN
0.1U_0402_25V6
RC659 1 @ 2 150_0402_5%
@ CC36
FIVR_EN
1
RC660 1 @ 2 10K_0402_5% PVT-182
Change BOM structure from XDP@ to empty (Mount 0ohm)
2
+1.0VA_XDP
+1.0VA +1.0VA_XDP
Trace length RC150
1 2
0_0402_5% 1 1
CC46 CC47
CPU_XDP_TDO XDP_TDO XDP@ XDP@
CPU_XDP_TCK RC134
RC234
1
1
XDP@
XDP@
2
2
0_0201_5%
0_0201_5%
XDP_TCK0
+3V_PCH
XDP CONN 0.1U_0201_10V6K
2 2
0.1U_0201_10V6K
<To CPU JTAG>

CPU_XDP_TDI
CPU_XDP_TMS RC183 1 XDP@ 2 0_0201_5%
XDP_TDI
XDP_TMS RC85 1 XDP@ 2 100K_0201_5%
XDP_PRSENT#
Follow PBC MLK
CPU_XDP_TRST# RC193 1 XDP@ 2 0_0201_5% XDP_TRST#
RC194 1 XDP@ 2 0_0201_5% RC658 2 @ 1 0_0402_5% +1.0VA_XDP +1.0VA_XDP
+1.0VA_XDP JXDP1
XDP_PIN1
PCH_JTAG_TDO XDP_TDO XDP_RST# CFG3
XDP_PREQ# RC146 1 XDP@ 2 1K_0402_1% 1 2
RC139 1 2 RC96 1 2 1K_0402_5% 3 1 2 4
PCH_JTAG_TDI XDP@ 0_0201_5% XDP_TDI @ XDP_PRDY#
RC173 1 XDP@ 2 0_0201_5% 5 3 4 6 CFG17 (19)
B PCH_JTAG_TMS XDP_TMS B
RC186 1 XDP@ 2 0_0201_5% +1.0V_VCCSTG 7 5 6 8 CFG16 (19)
<To PCH JTAG> PCH_JTAG_TRST#
RC171 1 2
XDP_TRST#
RC263 1 XDP@ 2 1K_0402_1% 9 7 8 10
PCH_JTAGX XDP@ 0_0201_5% XDP_TCK0 CFG0 CFG8
RC273 1 XDP@ 2 0_0201_5% RC182 2 @ 1 51_0402_5% (19) CFG0 11 9 10 12 CFG9 CFG8 (19)
PCH_JTAG_TCK XDP_TCK1 (19) CFG1 11 12 CFG9 (19)
RC135 1 XDP@ 2 0_0201_5% 13 14
15 13 14 16 CFG10
+1.0VA_XDP (19) CFG2 CFG3 17 15 16 18 CFG11 CFG10 (19)
(19) CFG3 19 17 18 20 CFG11 (19)
XDP_PREQ# XDP_OBS0 19 20
Closed to CPU RC656 2 @ 1 51_0402_5%
XDP_OBS1
21 22
23 21 22 24 CFG19 (19)
RC138 1 2 0_0402_5% 25 23 24 26 CFG18 (19)
@
(11,58)
(9,66)
SYS_PWROK
PCH_SPI_SI_R
RC174 1 XDP@ 2 1K_0201_5%
RESET_OUT#_R
XDP_PRSENT#
Follow PBC MLK (19) CFG4
27 25
27
26
28
28
CFG12 (19)
RC133 1 XDP@ 2 1K_0201_5% 29 30 CFG13
(9) PCH_SPI_IO2_R (19) CFG5 29 30 CFG13 (19)
31 32
33 31 32 34
(19) CFG6 35 33 34 36 CFG15 CFG14 (19)
XDP_BPM#0 XDP_OBS0 (19) CFG7 35 36 CFG15 (19)
<XDP Misc.> XDP_BPM#1 RC637 1 XDP@ 2 0_0201_5%
XDP_OBS1 @ T70 XDP_OBS0 PWRGD_XDP
37 38
RC636 1 XDP@ 2 0_0201_5% T73 39 37 38 40
@ XDP_OBS1 XDP_PWRBTN# 39 40 CLK_ITPXDP_P (11)
41 42 <XDP CLK>
41 42 CLK_ITPXDP_N (11)
XDP_PWRBTN# FIVR_EN_R 43 44 XDP_RST# From CPU
RC175 1 XDP@ 2 0_0201_5% 45 43 44 46
(11,58,79) SIO_PWRBTN# XDP_DBRESET# RESET_OUT#_R 45 46 XDP_DBRESET#
RC274 1 XDP@ 2 0_0201_5% XDP_RST# 47 48 +3VS
(11) PM_SYS_RESET# 47 48
RC178 2 XDP@ 1 0_0402_5% PWRGD_XDP 49 50 XDP_TDO XDP_DBRESET#
(19) XDP_ITP_PMODE 49 50
RC145 1 XDP@ 2 1K_0402_5% 51 52 1 2
(11,58,63) PCH_RSMRST#_AND (9) DDR_XDP_SMBDAT 51 52 XDP_TRST#
RC167 1 @ 2 1K_0402_5% <XDP SMBUS> (9) DDR_XDP_SMBCLK XDP_TCK1 53 54 XDP_TDI RC665 1K_0402_5%
(11,78) VCCST_PWRGD 53 54
Link to PCH SMB XDP_TCK0 55 56 XDP_TMS
57 55 56 58
59 57
59
58
60
60
XDP_PRSENT#
Follow PBC MLK
61
61
RESET_OUT#_R XDP_DBRESET# XDP_PWRBTN#
62 63
GND GND
0.1U_0201_10V6K
CC49
0.1U_0201_10V6K
CC50
Place near JXDP1.47 Place near JXDP1.48 Place near JXDP1.41

0.1U_0402_25V6
CC58
1 1
1
JXT_FP270H-061G1AM
CONN@
XDP@
XDP@
2
2 2
@
A A
P007 - WHL-U(2/14)MISC,XDP
5 4 3 2 1
5 4 3 2 1
D D
LPDDR3,non- Interleave
UCPU1C
UCPU1B
(23) DDR_M0_D[0..15] DDR_M0_D0 Interleave / Non-Interleaved (23) DDR_M0_D[16..31] DDR_M0_D16 lnterleave / LPDDR3 / DDR4 DDR_M1_CLK#0
DDR_M0_D1 A26 DDR_M0_CLK#0 DDR_M0_D17 J22 Non-lnterle a ve d AF28 DDR_M1_CLK0
D26 DDR0_DQ_0/DDR0_DQ_0 LPDDR3 / DDR4
V32 H25 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 AF29 DDR_M1_CLK#0 (24,25)
DDR_M0_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR_M0_CLK0 DDR_M0_CLK#0 (23,25) DDR_M0_D18 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 DDR_M1_CLK#1 DDR_M1_CLK0 (24,25)
DDR_M0_D3 D28 V31 DDR_M0_CLK#1 DDR_M0_D19 G22 AE28 DDR_M1_CLK1
C28 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_0/DDR0_CKP_0 T32 DDR_M0_CLK0 (23,25) H22 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKN_1/DDR1_CKN_1 AE29 DDR_M1_CLK#1 (24,25)
DDR_M0_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR_M0_CLK1 DDR_M0_CLK#1 (23,25) DDR_M0_D20 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKP_1/DDR1_CKP_1 DDR_M1_CLK1 (24,25)
DDR_M0_D5 B26 T31 DDR_M0_D21 F25 DDR_M1_CKE0
DDR0_DQ_4/DDR0_DQ_4 DDR0_CKP_1/DDR0_CKP_1 DDR_M0_CLK1 (23,25) DDR1_DQ_4/DDR0_DQ_20
DDR_M0_D6 C26 DDR_M0_CKE0 DDR_M0_D22 J25 T28 DDR_M1_CKE1
B28 DDR0_DQ_5/DDR0_DQ_5 U36 G25 DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 T29 DDR_M1_CKE0 (24,25)
DDR_M0_D7 DDR0_DQ_6/DDR0_DQ_6 DDR0_CKE_0/DDR0_CKE_0 DDR_M0_CKE1 DDR_M0_CKE0 (23,25) DDR_M0_D23 DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 DDR_B_CKE2 DDR_M1_CKE1 (24,25)
DDR_M0_D8 A28 U37 DDR_A_CKE2 DDR_M0_D24 F22 V28 DDR_B_CKE3
B30 DDR0_DQ_7/DDR0_DQ_7 DDR0_CKE_1/DDR0_CKE_1 U34 DDR_M0_CKE1 (23,25) D22 DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC V29 DDR_B_CKE2 (24,25)
DDR_M0_D9 DDR0_DQ_8/DDR0_DQ_8 DDR0_CKE_2/NC DDR_A_CKE3 DDR_A_CKE2 (23,25) DDR_M0_D25 DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC DDR_B_CKE3 (24,25)
DDR_M0_D10 D30 U35 DDR_M0_D26 C22 DDR_M1_CS#0
B33 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_3/NC DDR_A_CKE3 (23,25) C24 DDR1_DQ_9/DDR0_DQ_25 AL37
DDR_M0_D11 DDR0_DQ_10/DDR0_DQ_10 DDR_M0_CS#0 DDR_M0_D27 DDR1_DQ_10/DDR0_DQ_26 DDR1_CS#_0/DDR1_CS#_0 DDR_M1_CS#1 DDR_M1_CS#0 (24,25)
DDR_M0_D12 D32 AE32 DDR_M0_CS#1 DDR_M0_D28 D24 AL35 DDR_M1_ODT0
A30 DDR0_DQ_11/DDR0_DQ_11 DDR0_CS#_0/DDR0_CS#_0 AF32 DDR_M0_CS#0 (23,25) A22 DDR1_DQ_11/DDR0_DQ_27 DDR1_CS#_1/DDR1_CS#_1 AL36 DDR_M1_CS#1 (24,25)
DDR_M0_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CS#_1/DDR0_CS#_1 DDR_M0_ODT0 DDR_M0_CS#1 (23,25) DDR_M0_D29 DDR1_DQ_12/DDR0_DQ_28 DDR1_ODT_0/DDR1_ODT_0 DDR_M1_ODT0 (24,25)
DDR_M0_D14 C30 AE31 DDR_M0_D30 B22 AL34 Jony_12/14: Refer CFL is single name will keep NC
B32 DDR0_DQ_13/DDR0_DQ_13 DDR0_ODT_0/DDR0_ODT_0 AF31 DDR_M0_ODT0 (23,25) A24 DDR1_DQ_13/DDR0_DQ_29 NC/DDR1_ODT_1 AG36 572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf
DDR_M0_D15 DDR0_DQ_14/DDR0_DQ_14 NC/DDR0_ODT_1 DDR_M0_D31 DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0 DDR_M1_CAB_9 (24,25)
DDR_M0_D32 C32 Jony_12/14: Refer CFL is single name will keep NC DDR_M0_D48 B24 AG35
(23) DDR_M0_D[32..47] H37 DDR0_DQ_15/DDR0_DQ_15 AC37 572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf (23) DDR_M0_D[48..63] G31 DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 AF34 DDR_M1_CAB_8 (24,25)
DDR_M0_D33 DDR0_DQ_16/DDR0_DQ_32 DDR0_CAB_9/DDR0_MA_0 DDR_M0_CAB_9 (23,25) DDR_M0_D49 DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 DDR_M1_CAB_5 (24,25)
H34 AC36 G32 AG37
DDR_M0_D34 DDR0_DQ_17/DDR0_DQ_33 DDR0_CAB_8/DDR0_MA_1 DDR_M0_CAB_8 (23,25) DDR_M0_D50 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3
DDR_M0_D35 K34 AC34 DDR_M0_D51 H29 AE35 Jony_12/14: Refer CFL is single name will keep NC
K35 DDR0_DQ_18/DDR0_DQ_34 DDR0_CAB_5/DDR0_MA_2 AC35 DDR_M0_CAB_5 (23,25) H28 DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 AF35 572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf
DDR_M0_D36 Jony_12/14: Refer CFL is single name will keep NC DDR_M0_D52
H36 DDR0_DQ_19/DDR0_DQ_35 NC/DDR0_MA_3 AA35 572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf G28 DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 AE37 DDR_M1_CAA_0 (24,25)
DDR_M0_D37 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_MA_4 DDR_M0_D53 DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 DDR_M1_CAA_2 (24,25)
DDR_M0_D38 H35 AB35 DDR_M0_D54 G29 AC29
K36 DDR0_DQ_21/DDR0_DQ_37 DDR0_CAA_0/DDR0_MA_5 AA37 DDR_M0_CAA_0 (23,25) H31 DDR1_DQ_21/DDR0_DQ_53 DDR1_CAA_4/DDR1_MA_7 AE36 DDR_M1_CAA_4 (24,25)
DDR_M0_D39 DDR0_DQ_22/DDR0_DQ_38 DDR0_CAA_2/DDR0_MA_6 DDR_M0_CAA_2 (23,25) DDR_M0_D55 DDR1_DQ_22/DDR0_DQ_54 DDR1_CAA_3/DDR1_MA_8 DDR_M1_CAA_3 (24,25)
DDR_M0_D40 K37 AA36 DDR_M0_D56 H32 AB29
N36 DDR0_DQ_23/DDR0_DQ_39 DDR0_CAA_4/DDR0_MA_7 AB34 DDR_M0_CAA_4 (23,25) L31 DDR1_DQ_23/DDR0_DQ_55 DDR1_CAA_1/DDR1_MA_9 AG34 DDR_M1_CAA_1 (24,25)
DDR_M0_D41 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAA_3/DDR0_MA_8 DDR_M0_CAA_3 (23,25) DDR_M0_D57 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 DDR_M1_CAB_7 (24,25)
DDR_M0_D42 N34 W36 DDR_M0_D58 L32 AC28
R37 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAA_1/DDR0_MA_9 Y31 DDR_M0_CAA_1 (23,25) N29 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAA_7/DDR1_MA_11 AB28 DDR_M1_CAA_7 (24,25)
DDR_M0_D43 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAB_7/DDR0_MA_10 DDR_M0_CAB_7 (23,25) DDR_M0_D59 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAA_6/DDR1_MA_12 DDR_M1_CAA_6 (24,25)
DDR_M0_D44 R34 W34 DDR_M0_D60 N28 AK35
N37 DDR0_DQ_27/DDR0_DQ_43 DDR0_CAA_7/DDR0_MA_11 AA34 DDR_M0_CAA_7 (23,25) L28 DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 DDR_M1_CAB_0 (24,25)
DDR_M0_D45 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAA_6/DDR0_MA_12 DDR_M0_CAA_6 (23,25) DDR_M0_D61 DDR1_DQ_28/DDR0_DQ_60
DDR_M0_D46 N35 AC32 DDR_M0_D62 L29 AJ35
C DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_0/DDR0_MA_13 DDR_M0_CAB_0 (23,25) DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_2/DDR1_MA_14 DDR_M1_CAB_2 (24,25) C
DDR_M0_D47 R36 DDR_M0_D63 N31 AK34
R35 DDR0_DQ_30/DDR0_DQ_46 AC31 N32 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAB_1/DDR1_MA_15 AJ34 DDR_M1_CAB_1 (24,25)
(24) DDR_M1_D[0..15] DDR_M1_D0 DDR0_DQ_31/DDR0_DQ_47 DDR0_CAB_2/DDR0_MA_14 DDR_M0_CAB_2 (23,25) (24) DDR_M1_D[16..31] DDR_M1_D16 DDR1_DQ_31/DDR0_DQ_63 DDR1_CAB_3/DDR1_MA_16 DDR_M1_CAB_3 (24,25)
DDR_M1_D1 AN35 AB32 DDR_M1_D17 AJ29
DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_1/DDR0_MA_15 DDR_M0_CAB_1 (23,25) DDR1_DQ_32/DDR1_DQ_16
DDR_M1_D2 AN34 Y32 DDR_M1_D18 AJ30 AJ37
AR35 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_3/DDR0_MA_16 DDR_M0_CAB_3 (23,25) AM32 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_4/DDR1_BA_0 AJ36 DDR_M1_CAB_4 (24,25)
DDR_M1_D3 DDR0_DQ_34/DDR1_DQ_2 DDR_M1_D19 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_6/DDR1_BA_1 DDR_M1_CAB_6 (24,25)
DDR_M1_D4 AR34 W32 DDR_M1_D20 AM31 W29
AN37 DDR0_DQ_35/DDR1_DQ_3 DDR0_CAB_4/DDR0_BA_0 AB31 DDR_M0_CAB_4 (23,25) AM30 DDR1_DQ_35/DDR1_DQ_19 DDR1_CAA_5/DDR1_BG_0 DDR_M1_CAA_5 (24,25)
DDR_M1_D5 DDR0_DQ_36/DDR1_DQ_4 DDR0_CAB_6/DDR0_BA_1 DDR_M0_CAB_6 (23,25) DDR_M1_D21 DDR1_DQ_36/DDR1_DQ_20
DDR_M1_D6 AN36 V34 DDR_M1_D22 AM29 Y28
DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_5/DDR0_BG_0 DDR_M0_CAA_5 (23,25) DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_9/DDR1_BG_1 DDR_M1_CAA_9 (24,25)
DDR_M1_D7 AR36 DDR_M1_D23 AJ31 W28
AR37 DDR0_DQ_38/DDR1_DQ_6 V35 AJ32 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_8/DDR1_ACT# DDR_M1_CAA_8 (24,25)
DDR_M1_D8 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_8/DDR0_ACT# DDR_M0_CAA_8 (23,25) DDR_M1_D24 DDR1_DQ_39/DDR1_DQ_23 lnterleave / Non-lnterleaved
DDR_M1_D9 AU35 W35 DDR_M1_D25 AR31 H24
AU34 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_9/DDR0_BG_1 DDR_M0_CAA_9 (23,25) AR32 DDR1_DQ_40/DDR1_DQ_24 DDR1_DQSN_0/DDR0_DQSN_2 G24 DDR_M0_DQS#2 (23)
DDR_M1_D10 DDR0_DQ_41/DDR1_DQ_9 Interleave / Non-Interleaved
DDR_M1_D26 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQSP_0/DDR0_DQSP_2 DDR_M0_DQS2 (23)
DDR_M1_D11 AW35 C27 DDR_M1_D27 AV30 C23
AW34 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQSN_0/DDR0_DQSN_0 D27 DDR_M0_DQS#0 (23) AV29 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQSN_1/DDR0_DQSN_3 D23 DDR_M0_DQS#3 (23)
DDR_M1_D12 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQSP_0/DDR0_DQSP_0 DDR_M0_DQS0 (23) DDR_M1_D28 DDR1_DQ_43/DDR1_DQ_27 DDR1_DQSP_1/DDR0_DQSP_3 DDR_M0_DQS3 (23)
DDR_M1_D13 AU37 D31 DDR_M1_D29 AR30 G30
AU36 DDR0_DQ_44/DDR1_DQ_12 DDR0_DQSN_1/DDR0_DQSN_1 C31 DDR_M0_DQS#1 (23) AR29 DDR1_DQ_44/DDR1_DQ_28 DDR1_DQSN_2/DDR0_DQSN_6 H30 DDR_M0_DQS#6 (23)
DDR_M1_D15 AW36 J35 DDR_M1_D31 AV32 L30
AW37 DDR0_DQ_46/DDR1_DQ_14 DDR0_DQSN_2/DDR0_DQSN_4 J34 DDR_M0_DQS#4 (23) AV31 DDR1_DQ_46/DDR1_DQ_30 DDR1_DQSN_3/DDR0_DQSN_7 N30 DDR_M0_DQS#7 (23)
(24) DDR_M1_D[32..47] DDR_M1_D32 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQSP_2/DDR0_DQSP_4 DDR_M0_DQS4 (23) (24) DDR_M1_D[48..63] DDR_M1_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_DQSP_3/DDR0_DQSP_7 DDR_M0_DQS7 (23)
DDR_M1_D33 BA35 P34 DDR_M1_D49 BA32 AL31
BA34 DDR0_DQ_48/DDR1_DQ_32 DDR0_DQSN_3/DDR0_DQSN_5 P35 DDR_M0_DQS#5 (23) BA31 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQSN_4/DDR1_DQSN_2 AL30 DDR_M1_DQS#2 (24)
DDR_M1_D35 BC35 AP35 DDR_M1_D51 BD31 AU31
BC34 DDR0_DQ_50/DDR1_DQ_34 DDR0_DQSN_4/DDR1_DQSN_0 AP34 DDR_M1_DQS#0 (24) BD32 DDR1_DQ_50/DDR1_DQ_50 DDR1_DQSN_5/DDR1_DQSN_3 AU30 DDR_M1_DQS#3 (24)
DDR_M1_D37 BA37 AV34 DDR_M1_D53 BA30 BC31
BA36 DDR0_DQ_52/DDR1_DQ_36 DDR0_DQSN_5/DDR1_DQSN_1 AV35 DDR_M1_DQS#1 (24) BA29 DDR1_DQ_52/DDR1_DQ_52 DDR1_DQSN_6/DDR1_DQSN_6 BC30 DDR_M1_DQS#6 (24)
DDR_M1_D39 BC36 BB35 DDR_M1_D55 BD29 BH31
BC37 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQSN_6/DDR1_DQSN_4 BB34 DDR_M1_DQS#4 (24) BD30 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQSN_7/DDR1_DQSN_7 BH30 DDR_M1_DQS#7 (24)
DDR_M1_D41 BE35 BF34 DDR_M1_D57 BG31
BE34 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQSN_7/DDR1_DQSN_5 BF35 DDR_M1_DQS#5 (24) BG32 DDR1_DQ_56/DDR1_DQ_56 Y29
DDR_M1_D42 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQSP_7/DDR1_DQSP_5 DDR_M1_DQS5 (24) DDR_M1_D58 DDR1_DQ_57/DDR1_DQ_57 NC/DDR1_ALERT# PAD~D @ T29
DDR_M1_D43 BG35 DDR_M1_D59 BK32 AE34
BG34 DDR0_DQ_58/DDR1_DQ_42 LPDDR3 / DDR4
W37 BK31 DDR1_DQ_58/DDR1_DQ_58 NC/DDR1_PAR BU31 PAD~D @ T30
DDR_M1_D44 DDR0_DQ_59/DDR1_DQ_43 NC/DDR0_ALERT# PAD~D @ T28 DDR_M1_D60 DDR1_DQ_59/DDR1_DQ_59 DRAM_RESET# PAD~D @ T31
DDR_M1_D45 BE37 W31 DDR_M1_D61 BG29 SM_RCOMP0
BE36 DDR0_DQ_60/DDR1_DQ_44 NC/DDR0_PAR PAD~D @ T41 BG30 DDR1_DQ_60/DDR1_DQ_60 BN28
DDR_M1_D46 DDR0_DQ_61/DDR1_DQ_45 DDR_M1_D62 DDR1_DQ_61/DDR1_DQ_61 DDR_RCOMP_0 SM_RCOMP1
DDR_M1_D47 BG36 F36 DDR_M1_D63 BK30 BN27 SM_RCOMP2
BG37 DDR0_DQ_62/DDR1_DQ_46 DDR_VREF_CA D35 +V_DDR_REF_CA (25) BK29 DDR1_DQ_62/DDR1_DQ_62 DDR_RCOMP_1 BN29
DDR0_DQ_63/DDR1_DQ_47 DDR0_VREF_DQ_0 D37 +V_DDR_REFA_R (25) DDR1_DQ_63/DDR1_DQ_63 DDR_RCOMP_2
DDR0_VREF_DQ_1 E36
DDR1_VREF_DQ DDR_VTT_CNTL +V_DDR_REFB_R (25)
C35 WHL-U42_BGA1528
DDR_VTT_CTL @
WHL-U42_BGA1528 3 of 20
@
2 of 20
B B
Jony12/14:572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf - Keep setting

+1.2V_DDR
1
UC2
5
LPDDR3 COMPENSATION SIGNALS
NC VCC
DDR_VTT_CNTL SM_RCOMP0
2 1 RC224 1 2 200_0402_1%
A 4 +3VS
Y SM_RCOMP1
3 CC33 RC248 1 2 80.6_0402_1%
GND 0.1U_0402_10V7K SM_RCOMP2
1
74AUP1G07GW_TSSOP5 2 RC258 1 2 162_0402_1%

RE40
100K_0402_5%
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
2
RC155 1 @ 2 0_0402_5% Max trace length= 500 mil

SM_PG_CTRL (86)
OPEN-DRAIN OUTPUTS
A A
P08-MCP(2/14)LPDDR3
5 4 3 2 1
5 4 3 2 1
BOOT HALT CONSENT STRAP A0 PERSONALITY STRAP TLS CONFIDENTIALITY eSPI OR LPC Intel DCI-OOB
GPP_C5 / SML0ALERT#(WEAK INTERNAL PD)
SPI0_MOSI(WEAK INTERNAL PU) SPI0_IO2(WEAK INTERNAL PU) SPI0_IO3(WEAK INTERNAL PU) GPP_C2/SMBALERT#(INTERNAL PD 20K) GPP_B23(Internal 20 K internal Pull Down)
0 = LPC is selected (for EC). (Default)
0 = Enable 0 = Enable 0 = Enable 0 = TLS CONFIDENTIALITY DISABLE 0 = Disable IntelR DCI-OOB (Default)
+3V_PCH +3V_PCH +3V_PCH 1 = eSPI is selected (for EC). +3V_PCH
1 = Disable 1 = Disable 1 = Disable 1 = TLS CONFIDENTIALITY ENABLE +3V_PCH
1 = Enable IntelR DCI-OOB +3V_PCH
RH32 1 2 100K_0402_5% RH27 1 2 100K_0402_5% RH34 1 2 100K_0402_5%

RC27 1 2 4.7K_0201_5% RC110 1 2 4.7K_0402_5% GPP_B23 RC105 150K_0402_1%
PCH_SPI_SI PCH_SPI_IO2 PCH_SPI_IO3 1 2
RH19 1 @ 2 4.7K_0402_5% RH20 1 @ 2 4.7K_0402_5% RH33 1 @ 2 4.7K_0402_5% GPP_C2 @ GPP_C5 @
RC621 1 2 20K_0402_5% RC246 1 2 20K_0402_5%
D D
Intel ME Crypto (TLS)Transport Layer Security

to support Intel Active Management (AMT) w ith TLS.
+3VS
PVT-077
Change to short-pad
RC215 1 @ 2 0_0402_5%
2
+3VS
MEM_SMBCLK DDR_XDP_SMBCLK DDR_XDP_SMBDAT

6 1 2 1
DDR_XDP_SMBCLK (7)
2.2K_0402_5%
DDR_XDP_SMBCLK RN23
5
2 1
@ 2.2K_0402_5% RN22
QC1A
MEM_SMBDATA DDR_XDP_SMBDAT
3 4L2N7002DW1T1G_SC88-6
DDR_XDP_SMBDAT (7)
@
QC1B
L2N7002DW1T1G_SC88-6
RC235 1 @ 2 0_0402_5%
SPI_MOSI= SPI_IO0
PVT-078
SPI_MISO= SPI_IO1 Change to short-pad
PCH EDS R0.7 p.235~236 UCPU1E
+3V_PCH
PCH_SPI_CLK_R PCH_SPI_CLK MEM_SMBCLK
(66) PCH_SPI_CLK_R PCH_SPI_SO_R RC131 1 2 4.99_0201_1% PCH_SPI_SO CH37 CK14 MEM_SMBDATA
RC130 1 2 4.99_0201_1% CF37 SPI0_CLK GPP_C0/SMBCLK CH15
(66) PCH_SPI_SO_R PCH_SPI_SI_R
1 2
PCH_SPI_SI SPI0_MISO GPP_C1/SMBDATA GPP_C2 XDP Reserved MEM_SMBCLK
(7,66) PCH_SPI_SI_R PCH_SPI_IO2_R RC129 4.99_0201_1% PCH_SPI_IO2 Strap Pin CF36 CJ15 Strap Pin 1 @ 2
1 2 SPI0_MOSI GPP_C2/SMBALERT#
(7) PCH_SPI_IO2_R PCH_SPI_IO3_R RC123 4.99_0201_1% PCH_SPI_IO3 Strap Pin CF34 SML0_SMBCLK MEM_SMBDATA RC112 1K_0402_5%
RC127 1 2 4.99_0201_1% Strap Pin CG34 SPI0_IO2 SPI - FLASH CH14 1 @ 2
PCH_SPI_CS0#_R PCH_SPI_CS0# SPI0_IO3 GPP_C3/SML0CLK SML0_SMBDATA
PCH_SPI_CS1#_R RC63 1 @ 2 0_0201_5% PCH_SPI_CS1# CG36 SMBUS , SMLINK CF15 GPP_C5 Reser ved SML0_SMBCLK RC212 1K_0402_5%
RC62 1 @ 2 0_0201_5% CG35 SPI0_CS0# GPP_C4/SML0DATA CG15Strap Pin 1 @ 2
PCH_SPI_CS2# SPI0_CS1# GPP_C5/SML0ALERT#
CH34 SML1_SMBCLK SML0_SMBDATA RC25 499_0201_1%
(66) PCH_SPI_CS2# SPI0_CS2# CN15 1 2
C SML1_SMBDATA SML1_SMBCLK (58) @ C
GPP_C6/SML1CLK CM15
PVT-002
Change to short-pad GPP_C7/SML1DATA GPP_B23 SML1_SMBDATA (58) EC SML1_SMBCLK RC24 499_0201_1%
CF20 CC34Strap Pin 1 2
CG22 GPP_D1/SPI1_CLK/BK1/SBK1 GPP_B23/SML1ALERT#/PCHHOT# RC205 1K_0402_5%
GPP_D2/SPI1_MISO_IO1/BK2/SBK2 SML1_SMBDATA
+3V_PCH
For support Intel CF22 ESPI_IO0_R 1 2
1. 8 V CG23 GPP_D3/SPI1_MOSI_IO0/BK3/SBK3 CA291. 8 V RC113 1 2 15_0402_5% RC207 1K_0402_5%
7360 WWAN card (53) WWAN_BB_RST# GPP_D21/SPI1_IO2 SPI - TOUCH GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0 (58,79)
MEDIACARD_IRQ# MEDIACARD_IRQ# CH23 BY291. 8 V ESPI_IO2_R RC111 1 2 15_0402_5% ESPI_IO
1 2 (53) WWAN_GPIO_PERST# CG20 GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1 BY271. 8 V ESPI_IO1 (58,79)
@ ESPI_IO3_R RC259 1 2 15_0402_5% Integrated Pull-Up 20K
(70) MEDIACARD_IRQ# GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2 ESPI_IO2 (58,79)
RC107 10K_0201_5% BV271. 8 V RC109 1 2 15_0402_5%
GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 (58,79)
CA281. 8 V
GPP_A5/LFRAME#/ESPI_CS# CA271. 8 V ESPI_CS# (58,79) ESPI_CS#
CH7 LPC , ESPI GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# (58,79) Integrated Pull-Up 20K
+1.8VA (52) PCH_CL_CLK1 CH8 CL_CLK
CLINK for (52) PCH_CL_DATA1
CH9 CL_DATA C LINK
BV321. 8 V
ESPI_CLK
RC287 1 2 33_0402_5% ESPI_CLK PCH GLITCH ISSUE MITIGATION(PDG p.130)
TBT_BATLOW#
PCIe WLAN module
(52) PCH_CL_RST1# RCIN# is over to virtual w ires(VW), CL_RST# GPP_A9/CLKOUT_LPC0/ESPI_CLK BV30 ESPI_CLK_5105 (58,79) Integrated Pull-down 20K
ESPI_RESET#
so can release to FREE BV29 GPP_A10/CLKOUT_LPC1 BY30 TBT_BATLOW# (47) RC622 1 @ 2 75K_0201_1%
ESPI_ALERT# ESPI_ALERT# GPP_A0/RCIN#/TIME_SYNC1 GPP_A8/CLKRUN#
2
RC106 1 2 10K_0402_1% 1. 8 V BV28
(58) ESPI_ALERT# GPP_A6/SERIRQ GPP_A8/A10 no support LPC, can be FREE 0509 CC85
PCH_SPI_CLK Change TBT_BATLOW# to GPP_A17 12P_0402_50V8J
1
RH18 1 2 100K_0402_5% WHL-U42_BGA1528
@ @RF@
5 of 20
+3VS
TBT_BATLOW#
RC47 1 @ 2 10K_0201_5%
Closed to ROM
SPI_SI_VROM0 PCH_SPI_SI_R
SPI_CLK_VROM0 RC126 1 2 49.9_0201_1% PCH_SPI_CLK_R
SPI_SO_VROM0 RC125 1 2 49.9_0201_1% PCH_SPI_SO_R
RC128 1 2 49.9_0201_1%
SPI_IO2_VROM0
RC124 1 2 49.9_0201_1%
PCH_SPI_IO2_R Serial Peripheral Interface (SPI) 2 load Topology Guidelines
SPI_IO3_VROM0 PCH_SPI_IO3_R
RC64 1 2 49.9_0201_1%
50-ohm 5-ohm
SPI PCH
+3.3V_SPI
50-ohm
CC92
B 1 2 TPM B
0.1U_0402_25V6 1K-ohm
U34 @
PCH_SPI_CS0#_R
SPI_SO_VROM0 1
2 CS# VCC
8
7
SPI_IO3_VROM0 XDP
SPI_IO2_VROM0 DO HOLD#_RESET# SPI_CLK_VROM0
3 6 SPI_SI_VROM0
4 WP# CLK 5
GND DI JSPI
W25Q256JVEIQ_WSON8_8X6
SPI ROM FOR ME ( 32 MByte )
BIOS ROM Option

Follow Pebble Creek MLK
SPI (BIOS) U34
JSPI DEBUG Conn. GIGADEVICE@
SA0000BGM00
PVT-077 PCH_SPI_CS1#_R JSPI1 GD25B256DYIG_WSON8_8X6
Change to short-pad 1
PCH_SPI_SI_R 1
+3V_PCH +3.3V_SPI PCH_SPI_SO_R 2
3 2
PCH_SPI_CLK_R 3
RC616 1 @ 2 0_0402_5% PCH_SPI_CS0#_R 4
5 4
PCH_SPI_IO2_R 5
D95 PCH_SPI_IO3_R
6
2 1 7 6 U34
RB751S40T1G_SOD523-2 VF=0.28V 8 7 WINBOND@
9 8 SA00009RI10
@ +3.3V_SPI
10 9 W25Q256JVEIQ_WSON8_8X6
10
11
12 GND1
GND2
A ACES_50521-01041-P01 U34 A
CONN@ MXIC@
SA0000BCD00
MX25L25673GZ4I-08G WSON 8P
P09-MCP(3/14)SPI,SMB,LPC
5 4 3 2 1
5 4 3 2 1
Flash Descriptor
(56) HDA_SYNC_R
RC195 1 2 33_0402_5%
HDA_SYNC
HDA_BIT_CLK TOP SWAP OVERRIDE Security Override
RC102 1 2 33_0402_5%
(56) HDA_BIT_CLK_R
1 1
2P_0201_25V8B
CC269
2P_0201_25V8B
CC11
GPP_B14 / SPKR WEAK INTERNAL PD HDA_SDO / SPKR WEAK INTERNAL PD
0508
RF suggestion
2 2 0 = Disable Top Swap mode. (Default) 0 = Enable security measures defined in the Flash
D PCH GLITCH ISSUE MITIGATION(PDG p.130) D
@RF@
@RF@
HDA_BIT_CLK Descriptor. (Default)
RC625 1 @ 2 100K_0201_5%
1 = Enable Top Swap mode.
RC626 1 @ 2 100K_0201_5%
HDA_RST# 1 = Disable Flash Descriptor Security (override). This
HDA_SDOUT The signal has a weak internal pull-down. strap should only be asserted high using external
(56) HDA_SDOUT_R
RC197 1 2 33_0402_5% HDA_RST# Pull-up in manufacturing/debug environments
1 2 +3V_PCH
(56) HDA_RST#_R RC21 33_0402_5% HDA_SDIN0 ONLY.
(56) HDA_SDIN0
+3V_PCH The signal has a weak internal pull-down.
Capacitor to only be used for HDA_SDO, HDA_RST#, and HDA_SDI SPKR RC247 1 @ 2 4.7K_0201_5% HDA_SDOUT
for EMI purposes 1 @ 2
RC686 4.7K_0201_5%
1 1
2P_0201_25V8B
CC10
2P_0201_25V8B
CC7
For HDA_SDO and HDA_RST#
the cap should be after the series resistor closest to the PCH. +3V_PCH
2 2
TBT_CIO_PLUG_EVENT#
RF@
RF@
RC657 1 2 10K_0201_5%
PD close to PCH +3VS

CNV_RF_RESET#_R
2 1 CONTACTLESS_DET#
RC271 75K_0201_1% CLKREQ_CNV RC643 1 2 10K_0201_5%
1 2
RC26 71.5K_0201_1% HOST_SD_WP#
RC35 1 2 10K_0201_5%
HDA_SYNC UCPU1G
BN34
HDA_BIT_CLK HDA_SYNC/I2S0_SFRM
HDA_SDOUT BN37 CH36
HDA_BCLK/I2S0_SCLK GPP_G0/SD_CMD
HDA_SDIN0 Strap Pin BN36 A UDIO SDIO / SDXC CL35 TBT_CIO_PLUG_EVENT#
BN35 HDA_SDO/I2S0_TXD GPP_G1/SD_DATA0 CL36
HDA_SDI0/I2S0_RXD GPP_G2/SD_DATA1 TBT_CIO_PLUG_EVENT# (47)
HDA_RST# BL36 CM35 CONTACTLESS_DET# for TS sequence
HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G3/SD_DATA2 PANEL_BKLEN (6,38)
BL35 CN35
HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G4/SD_DATA3 HOST_SD_WP# CONTACTLESS_DET# (73)
CK23 CH35
(53) WWAN_GPIO_WAKE# GPP_D23/I2S_MCLK GPP_G5/SD_CD# HOST_SD_WP# (70)
CK36
GPP_G6/SD_CLK AUD_PWR_EN (57)
BL37 CK34
I2S1_SFRM/SNDW2_CLK GPP_G7/SD_WP SPK_DET# (57)
BL34
PVT-079 I2S1_TXD/SNDW2_DATA
Change to short-pad
CNV_RF_RESET#_R CNV_RF_RESET#
RC674 1 @ 2 0_0402_5% 1. 8 V CJ32
C (52) CNV_RF_RESET#_R GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET# C
CLKREQ_CNV CLKREQ_CNV_R CH32
RC673 1 @ 2 0_0402_5% 1. 8 V CH29 GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
(52) CLKREQ_CNV CH30 GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ BW36
(52) CNVI_EN# GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
DMIC_CLK0 BY31
RC48 1 2 33_0201_5% CP24 GPP_A16/SD_1P8_SEL
(56) PCH_DMIC_CLK0 DMIC_DATA0 GPP_D19/DMIC_CLK0/SNDW4_CLK
RC668 1 @ 2 0_0402_5% CN24
(56) PCH_DMIC_DATA0 GPP_D20/DMIC_DATA0/SNDW4_DATA
DMIC_CLK1 CK33 SD_RCOMP
RC642 1 2 33_0201_5% CK25 SD_1P8_RCOMP CM34 RC228 1 2 200_0402_1%
(40) PCH_DMIC_CLK1 DMIC_DATA1 GPP_D17/DMIC_CLK1/SNDW3_CLK SD_3P3_RCOMP
RC669 1 @ 2 0_0402_5% CJ25
(40) PCH_DMIC_DATA1 GPP_D18/DMIC_DATA1/SNDW3_DATA
1 1 1 1 SPKR Strap Pin CF35
(56) SPKR GPP_B14/SPKR
27P_0201_25V8
CC271
27P_0201_25V8
CC270
27P_0201_25V8
CC268
27P_0201_25V8
CC267
@ @ PVT-078 WHL-U42_BGA1528
Change to short-pad @
2 2 2 2
@RF@
@RF@
7 of 20
Cap placeholder for DMIC_CLK only
0509
Reserve cap for RF suggestion
0515
Change ME_FW to switch
From EC, for +3VALW
B enabl e DB@
SW8 B
ME code
programi ng 1 2 RC676 1 2 1K_0201_5%
3 4 HDA_SDOUT
(58) ME_FWP
1 2
RC639 1K_0201_5%
SKSFABE010_4P
Low = Disabled (cannot f l as h)

* High = Enabled (can f l as h)
R275 1 @ 2 0_0201_5%
PVT-003
Change to short-pad
A A
P010 - WHL-U(5/14)HDA,SD
5 4 3 2 1
5 4 3 2 1
CLKREQ_PCIE# input O.D.
UCPU1J
PVT-080
Change to short-pad Crystal 24MHz / 32.768MHz
CLOCK SINGNALS CLK_ITPXDP_N_R
AW2 AU1 CLK_ITPXDP_P_R RC72 1 @ 2 0_0402_5% XTAL24_IN XTAL24_IN_R CC62
(47) CLK_PCIE_N0 AY3 CLKOUT_PCIE_N_0 CLKOUT_ITPXDP_N AU2 1 2 0_0402_5% CLK_ITPXDP_N (7) 1 2 1 2
RC71 @
Alpine Ridge---> (47) CLK_PCIE_P0 CF32 CLKOUT_PCIE_P_0 CLKOUT_ITPXDP_P CLK_ITPXDP_P (7) RC177 33_0201_1%
(47) CLKREQ_PCIE#0 GPP_B5/SRCCLKREQ0#
RC151 1 2 10K_0402_5% BT32 SUSCLK 15P_0402_50V8J
+3VS GPD8/SUSCLK SUSCLK (52,53,68)
BC1 RC187 1 @ 2 1K_0402_5%
CLKOUT_PCIE_N_1 XTAL24_IN
3
4
(68) CLK_PCIE_N1
1M_0201_1%
Main SSD--> BC2 CK3 XTAL24_OUT
(68) CLK_PCIE_P1 CLKOUT_PCIE_P_1 XTAL_IN
RC179
CE32 CK2 YC1
(68) CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# XTAL_OUT
RC120 1 2 10K_0402_5% XCLK_BIASREF 24MHZ_12PF_7M24090001
+3VS
BD3 CJ1 RC267 1 2 60.4_0402_1%
WWA N REFCLK_CNV_L
1
2
(53) CLK_PCIE_N2 BC3 CLKOUT_PCIE_N_2 XCLK_BIASREF CM3 RC693 1 2 0_0402_5%
2nd SSD--> REFCLK_CNV (52)
1
(53) CLK_PCIE_P2 CF30 CLKOUT_PCIE_P_2 CLKIN_XTAL CC16
(53) CLKREQ_PCIE#2 PCH_RTCX1 XTAL24_OUT XTAL24_OUT_R
1
1 2 10K_0402_5% GPP_B7/SRCCLKREQ2# BN31 1 2 1 2
+3VS RC148 PCH_RTCX2 1
BH3 RTCX1 BN32 RC54 CC260 RC181 33_0201_1%
(52) CLK_PCIE_N3 BH4 CLKOUT_PCIE_N_3 RTCX2 10K_0201_5% 2.2P_0402_50V8C~D 15P_0402_50V8J
WLAN---> (52) CLK_PCIE_P3 CE31 CLKOUT_PCIE_P_3 BR37 SRTCRST#
D (52) CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# SRTCRST# PCH_RTCRST# D
RC149 1 2 10K_0402_5% BR34 2 Close to PCH side
+3VS
2
RTCRST# PCH_RTCRST# (49,79) @
BA1
(70) CLK_PCIE_N4 BA2 CLKOUT_PCIE_N_4
Card Reader---> (70) CLK_PCIE_P4 CE30 CLKOUT_PCIE_P_4 CC14
(70) CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# PCH_RTCX1 PCH_RTCX1_R
RC119 1 2 10K_0402_5% RC162 1 2 0_0402_5% 1 2
+3VS
BE1
2
BE2 CLKOUT_PCIE_N_5 +RTCVCC 6.8P_0402_50V8J
CF31 CLKOUT_PCIE_P_5 CLRP2 @ CC20
1
GPP_B10/SRCCLKREQ5#
10M_0402_5%
RC675 1 @ 2 10K_0402_5% SHORT PADS 1U_0201_6.3V6M
+3VS
RC266
WHL-U42_BGA1528 YC2
@ 10 of 20 SRTCRST# RC260 1 2 20K_0402_5% 9PF 20PPM 9H03280012
PCH_RTCRST# ESR MAX=50k ohm
2
RC244 1 2 20K_0402_5%
1
PCH_RTCX2 PCH_RTCX2_R CC12
RC169 1 2 0_0402_5% 1 2
1
CLRP1 @ CC84 6.8P_0402_50V8J
SHORT PADS 1U_0201_6.3V6M
2
3.0V SELECT
+3VS
+3VS CC6
1 2
INPUT3VSEL
5
10K_0402_5%
UC4 0.1U_0201_10V6K
0 = 3.3V supply is 3.3V +/- 5%
VCC
RC633
1
PVT-006 IN1 4
Change to short-pad
PCH_PLTRST#
2 OUT PCH_PLTRST#_AND (47,52,53,66,68,70,79) 1 = 3.3V supply is 3.0V +/- 5%
GND
2
IN2 +3V_PCH_DSW
SYS_RESET#_R SYS_RESET# External pull-up or pull-down is required
1
1 @ 2 1 2
(7) PM_SYS_RESET#
1
RC635 0_0201_5% RC634 1K_0402_5% @ MC74VHC1G08DFT2G_SC70-5
RC163
3
RC154 100K_0201_5% 2 @ 1
100K_0201_5% RC262 4.7K_0402_5%
INPUT3VSEL 2 1
2
C RC201 4.7K_0402_5% C
2
UCPU1K
SIO_SLP_S0#
SYSTEM POWER MANAGEMENT BJ37
PCH_PLTRST# GPP_B12/SLP_S0# SIO_SLP_S3# SIO_SLP_S0# (66,79,89,90)
+3V_PCH_DSW BJ35 BU36 +3V_PCH_DSW
SYS_RESET# GPP_B13/PLTRST# GPD4/SLP_S3# SIO_SLP_S4# SIO_SLP_S3# (47,58,78,79)
PCH_RSMRST#_AND CN10 BU27 SIO_SLP_S5#
(79) SYS_RESET# BR36 SYS_RESET# GPD5/SLP_S4# BT29
PCH_PCIE_WAKE# (7,58,63) PCH_RSMRST#_AND RSMRST# GPD10/SLP_S5# SIO_SLP_S5# (79) AC_PRESENT
1 2 H_CPUPWRGD_R H_CPUPWRGD SIO_SLP_SUS#
1 2
RC257 1K_0402_5% T11 @ PAD~D VCCST_PWRGD RC208 1 @ 2 1K_0402_5% VCCST_PWRGD_CPU AR2 BU29 SLP_LAN# PCH_BATLOW# RC80 10K_0402_5%
RC272 1 2 62_0402_5% BJ2 PROCPWRGD SLP_SUS# BT31 SIO_SLP_SUS# (58,78) 1 2
1 2
LAN_WAKE# (7,78) VCCST_PWRGD VCCST_PWRGOOD SLP_LAN# BT30
SIO_SLP_WLAN# PAD~D @ T12
SIO_SLP_A# RC254 10K_0402_5%
RC153 10K_0402_5% CR10 GPD9/SPL_WLAN# BU37 SIO_SLP_WLAN# (52)
(7,58) SYS_PWROK PCH_PWROK SYS_PWROK GPD6/SLP_A# SIO_SLP_A# (79)
PCH_DPWROK
BP31
(90) PCH_PWROK BP30 PCH_PWROK BU28 +RTCVCC
(58) PCH_DPWROK DSW_PWROK GPD3/PWRBTN# AC_PRESENT SIO_PWRBTN# (7,58,79)
+1.0V_VCCST BU35
GPD1/ACPRESENT PCH_BATLOW# AC_PRESENT (58)
VCCST_PWRGD ME_SUS_PWR_ACK is for LPC use only BV34 BV36 INTRUDER# 1 2
1 2 SUSACK# is for LPC use only BY32 GPP_A13/SUSWARN#/SUSPWRDACK GPD0/BATLOW# RC206 1M_0402_5%
GPP_A15/SUSACK#
RC93 1K_0402_5% PCH_PCIE_WAKE#
LAN_WAKE# BU30 BR35 INTRUDER#
+3VS (47,58) PCH_PCIE_WAKE# BU32 WAKE# INTRUDER# +3V_PCH
(58) LAN_WAKE# BU34 GPD2/LAN_WAKE# CC37
PCH_PWROK GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE#
1 2 CC36 VRALERT# VR Alert pin allows the VR to force throttling VRALERT# 1 2
RC678 100K_0201_5% GPP_B2/VRALERT# to prevent an over current shutdown. RC84 10K_0402_5%
BT27 INPUT3VSEL
INPUT3VSEL Strap Pin
1 @ 2
WHL-U42_BGA1528 RC682 0_0201_5%
@ +3VALW
11 of 20
5
UC5
VCC
SIO_SLP_S4#
1
IN1 4
OUT SIO_SLP_S4#_AND (73,78,79,87)
2
GND
(58) SUS_ON_EC IN2
B @ B
1 2
H_CPUPWRGD VCCST_PWRGD MC74VHC1G08DFT2G_SC70-5 D94
3
PVT-004
Change to short-pad
100P_0402_50V8J~D
100P_0402_50V8J~D
PCH GLITCH ISSUE MITIGATION(PDG p.130) PCH_PRIM_EN

1 1 SIO_SLP_S3# RC599 1 @ 2 0_0201_5% RC574 1 2 0_0201_5% 1 @ 2 1 2
EN_1.0VA (88) 1.2V_DDR_EN (86)
CA8
CA48
RC15 1 2 100K_0201_5% RC683 0_0201_5% RC684 0_0201_5%

1
1
@ 1
CC5 1 @ 2 0.33U_0201_6.3V6M CC253 RC681
2 2 0.1U_0201_10V6K 100K_0201_5% CC266
SIO_SLP_S4#
RC14 1 2 100K_0201_5% 2 @ 1U_0201_6.3V6M
2
2
EMC@ EMC@ CC4 1 @ 2 0.33U_0201_6.3V6M
SIO_SLP_A# RC575 1 2 0_0201_5%
EN_1.8V_PRIM (87)
ESD Request:place near CPU side RC13 1 2 100K_0201_5%
1
@
CC3 1 @ 2 0.33U_0201_6.3V6M CC254 PVT-127
0.1U_0201_10V6K Change to short-pad
SIO_SLP_WLAN#
RC12 1 2 100K_0201_5% 2
RC97 SIO_SLP_S0#
2 @ 1
VR_LPM_R_N (89)
CC2 1 @ 2 0.33U_0201_6.3V6M 0_0402_5% RE123
PO P NO Support Deep sleep RC576 1 2 0_0201_5%
DE-POP Support Deep sleep RC11 1 2 100K_0201_5%
SIO_SLP_SUS# EN_PRIM_CORE (89)
1
PCH_DPWROK PCH_RSMRST#_AND @
1 @NDS3@ 2 CC1 1 @ 2 0.33U_0201_6.3V6M CC255
RC97 0_0402_5% SIO_SLP_S5# 0.1U_0201_10V6K
RC10 1 @ 2 100K_0201_5% 2
1
1
0.01U_0402_16V7K
100K_0402_5%~D
1
RC568
CC64
RC98
10K_0201_5%
2 +3V_PCH
2
DS3@
SIO_SLP_S0# (17) VCCDSW_EN_GPIO SIO_SLP_SUS# PCH_PRIM_EN
RC9 1 2 100K_0201_5% RC691 1 DS3@ 2 0_0201_5%
PCH_PRIM_EN (78)
@NDS3@ DC5
RC631 VCCDSW_EN_Q
1 @ 2 2 1 RC690 1 @NDS3@ 2 0_0201_5%
(58) VCCDSW_EN
0_0201_5% RB751S40T1G_SOD523-2
A A
PVT-005 @NDS3@ DC4
Change to short-pad 1 2
(58) ALW_PWRGD_3V_5V
P011 - WHL-U(6/14)CLK,PM,RTC
5 4 3 2 1
5 4 3 2 1
NO REBOOT BOOT BIOS STRAP (BBS) JTAG ODT DISABLE
GPP_B18/GSPI0_MOS (WEAK INTERNAL PD) GPP_B22 / GSPI1_MOSI (Internal 20 K Pull Down) GPP_D12 (WEAK INTERNAL PU)
0 = Disable "No Reboot" mode. (Default) 0 = SPI (Default) 0 = JTAGE ODT DISABLED
1 = Enable "No Reboot" mode 1 = LPC 1 = JTAG ODT ENABLED +3V_PCH
+3VS +3V_PCH
EDS recommend 100K(RVP is 20K)
+3V_PCH RC618 1 2 100K_0201_5%
RC610 1 2 4.7K_0201_5% RC608 1 2 100K_0201_5% DCI_CLK
NRB_BIT GPP_B22 DCI_DATA RC617 1 @ 2 10K_0201_5%
RC607 1 @ 2 20K_0201_5% RC264 1 @ 2 4.7K_0201_5% RC609 1 @ 2 10K_0201_5%
D D
Enable “ No Reboot” mode ( PCH w il l di sabl e t h

e
TCO Timer system reboot feature). This function is
useful w hen running ITP/XDP.
PVT-007 GPP_B16
Change to short-pad Panel w ithout DBC function UCPU1F
TS_RST# TS_RST#_R
1 @ 2 CC27
(38) TS_RST# GPP_B15/GSPI0_CS0#
RC689 1 @ 2 0_0201_5% CC32 CN22 +3V_PCH
RC688 0_0201_5% CE28 GPP_A7/PIRQA#/GSPI0_CS1# GPP_D9/ISH_SPI_CS#/GSPI2_CS0# CR22
RTC_DET# GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK DCI_CLK
1 @ 2 NRB_BIT CE27 CM22 DCI_DATA SIO_EXT_WAKE#
(49) RTC_DET#_R GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO/GSPI2_MISO DCI_CLK (73)
RC692 0_0201_5% Strap PinCE29 ISH CP22Strap Pin
DCI_DATA (73)
RC238 1 2 10K_0402_5%
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI
PU at device side SML0B_SMBDATA
PVT-008 PME# (PCI Pow er Management Event) CA31 CK22 RC30 1 @ 2 1K_0201_5%
Change to short-pad is over to virtual wires (VW) CA32 GPP_B19/GSPI1_CS0# GPP_D5/ISH_I2C0_SDA CH20
ISH_I2C0_SDA (66) Gyro/Accelerometer + E-Compass SML0B_SMBCLK
RC29 1 @ 2 1K_0201_5%
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D6/ISH_I2C0_SCL ISH_I2C0_SCL (66)
CC29
(66) TPM_PIRQ# GPP_B20/GSPI1_CLK
CC30 CH22
(68) PCH_3.3V_TS_EN GPP_B22 GPP_B21/GSPI1_MISO GPP_D7/ISH_I2C1_SDA ISH_I2C1_SDA (42) ALS
Strap PinCA30 CJ22
ISH_I2C1_SCL (42)
+1.8VA GPP_B22/GSPI1_MOSI GPP_D8/ISH_I2C1_SCL
CNVi BRI & RGI Single Load (DT) CNV_BRI_PRX_DTX PU at device side
Resistor 33 ohm, to be placed closer to PCH 1. 8 V CK20
(52) CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX
RC22 1 2 33_0201_5% Strap Pin CG19 1.GPP_F5/CNV_BRI_RSP
8V CJ27
CNV_BRI_PRX_DTX (52) CNV_RGI_PTX_R_DRX CNV_BRI_PTX_DRX GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA
1 @ 2 RC23 1 2 33_0201_5% CNV_RGI_PRX_DTX
1. 8 V CJ20 CJ29
(52) CNV_BRI_PTX_R_DRX 1. 8 V CH19 GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL
RC210 20K_0201_5% CNV_RGI_PRX_DTX SML0B_SMBDATA +3VS
(52) CNV_RGI_PRX_DTX GPP_F7/CNV_RGI_RSP
1 @ 2 CNVi BRI & RGI Single Load (RSP) CM24 SML0B_SMBCLK Reser ved
RC209 20K_0201_5% Resistor 22 ohm, to be placed closer to the CRF connector. GPP_D13/ISH_UART0_RXD CN23
IR_CAM_DET# GPP_D14/ISH_UART0_TXD
CR12 CM23 LCD_CBL_DET#
(42) IR_CAM_DET# GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# WWAN_FULL_PWR_EN (53)
CP12 CR24 RC677 1 2 100K_0402_5%~D
CN12 GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT#
TS_INT# GPP_C22/UART2_RTS# SIO_EXT_WAKE# ISH_ACC1_INT#
CM12 CG12 ISH_ACC2_INT# RC19 1 2 10K_0201_5%
(38) TS_INT# GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD SIO_EXT_WAKE# (58)
+3VS 0509 CH12 RC630 1 2 10K_0201_5%
GPP_C13/UART1_TXD/ISH_UART1_TXD LCD_CBL_DET#
RC46@ TS (38) TS_I2C_SDA
CM11 I2C , UART CF12 ISH_ALS_INT#
GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# LCD_CBL_DET# (38)
TS_RST# TS has an internal CN11 CG14 RC53 1 @ 2 100K_0402_5%~D
(38) TS_I2C_SCL GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#
RC46 1 @ 2 10K_0201_5% pull-up resistor to VDD ISH_ACC1_INT#
TS_INT# CK12 BW35 ISH_ACC2_INT# Camera module has ALS I2C INT pull H
GPP_C18/I2C1_SDA GPP_A18/ISH_GP0 ISH_ACC1_INT# (66)
RC34 1 2 100K_0201_5% CJ12 BW34 ISH_TABLE_MODE#
GPP_C19/I2C1_SCL GPP_A19/ISH_GP1 ISH_ACC2_INT# (66)
IR_CAM_DET# CA37 ISH_ALS_INT# +3V_PCH
GPP_A20/ISH_GP2 ISH_TABLE_MODE# (58)
RC652 1 2 10K_0201_5% CF27 CA36 ISH_NB_MODE#
C GPP_H4/I2C2_SDA GPP_A21/ISH_GP3 ISH_ALS_INT# (42) C
CF29 CA35 ISH_LID_CL#_NB
GPP_H5/I2C2_SCL GPP_A22/ISH_GP4 ISH_NB_MODE# (58)
CA34 KICKSTD_SW_DET#_PCH RC41 1 @ 2 10K_0201_5%
CH27 GPP_A23/ISH_GP5 BW37 ISH_LID_CL#_NB (7,58)
GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF# KICKSTD_SW_DET#_PCH (77) ISH_TABLE_MODE#
CH28 RC4 1 2 10K_0201_5%
GPP_H7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
CJ30
CJ31 GPP_H8/I2C4_SDA
GPP_H9/I2C4_SCL ISH_GP0 for 3D accelerometer and 3D gyroscope INT#
ISH_GP1 for 3D accelerometer and 3D gyroscope INT#
WHL-U42_BGA1528 ISH_GP2 for TABLE_MODE#
@ ISH_GP3 for ALS_ALERT# +3V_PCH
6 of 20
ISH_GP4 for NB_MODE#
+3V_PCH
ISH_GP5 for ISH_LID_CL#_NB 1 2 10K_0201_5%
RC623 @
ISH_GP6 for KICKSTD_SW_DET#_PCH
ISH_GP7 ISH_LID_CL#_NB ISH_NB_MODE#
RC696 1 2 10K_0201_5% RC51 1 2 10K_0201_5%
B B
A A
P012 - WHL-U(7/14)I2C,UART,ISH
5 4 3 2 1
5 4 3 2 1
D D
UCPU1H
CB5
BW9 PCIE1_RXN/USB31_1_RXN CB6
(47) PCIE_PRX_DTX_N5 PCIE5_RXN/USB31_5_RXN PCIE1_RXP/USB31_1_RXP
(47) PCIE_PRX_DTX_P5
BW8 CA4
BW4 PCIE5_RXP/USB31_5_RXP PCIE / USB3.1 / SATA PCIE1_TXN/USB31_1_TXN CA3
(47) PCIE_PTX_DRX_N5 PCIE5_TXN/USB31_5_TXN PCIE1_TXP/USB31_1_TXP
BW3
(47) PCIE_PTX_DRX_P5 PCIE5_TXP/USB31_5_TXP BY8 USB3_PRX_DTX_N2 (39)
BU6 PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN BY9
(47) PCIE_PRX_DTX_N6
BU5 PCIE6_RXN/USB31_6_RXN PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP CA2
USB3_PRX_DTX_P2 (39) WF Camera
BU4 PCIE6_RXP/USB31_6_RXP PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN CA1
USB3_PTX_DRX_N2 (39) (USB 3.0)
(47) PCIE_PTX_DRX_N6 PCIE6_TXN/USB31_6_TXN PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_PTX_DRX_P2 (39)
BU3
(47) PCIE_PTX_DRX_P6 PCIE6_TXP/USB31_6_TXP BY7
Alpine Ridge BT7 PCIE3_RXN/USB31_3_RXN BY6
USB3_PRX_DTX_N3 (73)
PCIe Gen3 x 4 (47) PCIE_PRX_DTX_N7
BT6 PCIE7_RXN PCIE3_RXP/USB31_3_RXP BY4
USB3_PRX_DTX_P3 (73) Type-A
BU2 PCIE7_RXP PCIE3_TXN/USB31_3_TXN BY3
USB3_PTX_DRX_N3 (73) (USB3.0)
(47) PCIE_PTX_DRX_N7 PCIE7_TXN PCIE3_TXP/USB31_3_TXP USB3_PTX_DRX_P3 (73)
(47) PCIE_PTX_DRX_P7
BU1
PCIE7_TXP BW6
PCIE4_RXN/USB31_4_RXN USB3_PRX_DTX_N4 (53)
BU9 BW5
BU8 PCIE8_RXN PCIE4_RXP/USB31_4_RXP BW2
USB3_PRX_DTX_P4 (53) WWA N
BT4 PCIE8_RXP PCIE4_TXN/USB31_4_TXN BW1
USB3_PTX_DRX_N4 (53) (USB3.0)
(47) PCIE_PTX_DRX_N8 PCIE8_TXN PCIE4_TXP/USB31_4_TXP USB3_PTX_DRX_P4 (53)
BT3
PCIE8_TXP CE3
USB2_1N USB20_N1 (43)
BP5 CE4
BP6 PCIE9_RXN USB2_1P USB20_P1 (43) TBT port1
Cardreader (70) PCIE_PRX_DTX_P9
BR2 PCIE9_RXP CE1
USB2.0
C PCIe Gen2 x 1 (70) PCIE_PTX_DRX_N9
BR1 PCIE9_TXN USB2_2N CE2
USB20_N2 (45) C
(70) PCIE_PTX_DRX_P9 PCIE9_TXP USB2_2P USB20_P2 (45) TBT port2
BN6 CG3
(52) PCIE_PRX_DTX_N10 PCIE10_RXN USB2_3N USB20_N3 (73)
WLAN (52) PCIE_PRX_DTX_P10
BN5 CG4 Type-A USB
BR4 PCIE10_RXP USB2_3P USB20_P3 (73)
PCIe Gen2 x 1 (52) PCIE_PTX_DRX_N10
BR3 PCIE10_TXN CD3
(52) PCIE_PTX_DRX_P10 PCIE10_TXP USB2_4N USB20_N4 (74)
CD4
BN10 USB2_4P USB20_P4 (74) Docking
(53) PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0_RXN
BN8 CG5 USB20_N5 (41)
BN4 PCIE11_RXP/SATA0_RXP USB2_5N CG6
(53) PCIE_PTX_DRX_N11
BN3 PCIE11_TXN/SATA0_TXN USB2_5P USB20_P5 (41) IR Camera
(53) PCIE_PTX_DRX_P11 PCIE11_TXP/SATA0_TXP CC1
WWA N BL6 USB2_6N CC2
USB20_N6 (41)
2nd SSD (53) PCIE_PRX_DTX_N12
BL5 PCIE12_RXN/SATA1A_RXN USB2_6P USB20_P6 (41) UF Camera
BN2 PCIE12_RXP/SATA1A_RXP CG8
USB20_N7 (53)
BN1 PCIE12_TXN/SATA1A_TXN USB2_7N CG9
(53) PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP USB2_7P USB20_P7 (53) WWA N
BK6 CB8
PCIE13_RXN USB2_8N USB20_N8 (73)
BK5 CB9
BM4 PCIE13_RXP USB2_8P USB20_P8 (73) USH
BM3 PCIE13_TXN CH5
PCIE13_TXP USB2_9N USB20_N9 (77)
CH6
BJ6 USB2_9P USB20_P9 (77) Finger Print
BJ5 PCIE14_RXN CC3
PCIE14_RXP USB2_10N USB20_N10 (52)
BL2 CC4
BL1 PCIE14_TXN USB2_10P USB20_P10 (52) BT
PCIE14_TXP CC5 USBCOMP RC104 1 2 113_0402_1%
USB2_COMP USB2_ID
BG5 CE8 RC103 1 @ 2 0_0402_5% PVT-081
(68) PCIE_PRX_DTX_N15 PCIE15_RXN/SATA1B_RXN USB2_ID Change to short-pad
BG6 CC6 VBUSSENSE RC73 1 2 1K_0402_5%
BL4 PCIE15_RXP/SATA1B_RXP USB2_VBUSSENSE
(68) PCIE_PTX_DRX_N15 PCIE15_TXN/SATA1B_TXN USB_OC0#
BL3 CK6 USB_OC1#
(68) PCIE_PTX_DRX_P15 PCIE15_TXP/SATA1B_TXP GPP_E9/USB2_OC0#/GP_BSSB_CLK USB_OC0# (73)
CK5
PCIe SSD BE5 GPP_E10/USB2_OC1#/GP_BSSB_DI CK8
USB_OC2#
+3V_PCH
Main SSD (68) PCIE_PRX_DTX_N16
BE6 PCIE16_RXN/SATA2_RXN GPP_E11/USB2_OC2# CK9
USB_OC3#
BJ4 PCIE16_RXP/SATA2_RXP GPP_E12/USB2_OC3#
USB_OC0#
BJ3 PCIE16_TXN/SATA2_TXN CP8 RC38 1 2 10K_0201_5%
(68) PCIE_PTX_DRX_P16 PCIE16_TXP/SATA2_TXP GPP_E4/DEVSLP0
PCIE_RCOMPN CR8 USB_OC1#
CE6 GPP_E5/DEVSLP1 CM8 M3042_DEVSLP (53) 1 2 10K_0201_5%
PCIE_RCOMPP RC37
RC189 1 2 100_0402_1% CE5 PCIE_RCOMP_N GPP_E6/DEVSLP2 M2230_DEVSLP (68)
PCIE_RCOMP_P USB_OC2#
CN8 M3042_PCIE#_SATA RC36 1 2 10K_0201_5%
Motherboard Length Matching : P-N=5mil CR28 GPP_E0/SATAXPCIE0/SATAGP0 CM10
GPP_H12/M2_SKT2_CFG_0 GPP_E1/SATAXPCIE1/SATAGP1 M2230_PCIE_SATA# M3042_PCIE#_SATA (58) USB_OC3#
B CP28 CP10 RC651 1 2 10K_0201_5% B
GPP_H13/M2_SKT2_CFG_1 GPP_E2/SATAXPCIE2/SATAGP2 M2230_PCIE_SATA# (68)
CN28
CM28 GPP_H14/M2_SKT2_CFG_2 CN7
GPP_H15/M2_SKT2_CFG_3 GPP_E8/SATALED#/SPI1_CS1#
AR3 +3VS
RSVD_69
WHL-U42_BGA1528 RC45 1 2 10K_0201_5%
@ M2230_PCIE_SATA#
8 of 20 RC3 1 @ 2 10K_0201_5%
+3VS
RC44 1 2 10K_0201_5%
M3042_PCIE#_SATA
RC43 1 @ 2 10K_0201_5%
A A
P013 - WHL-U(8/14)PCIE,USB,SATA
5 4 3 2 1
5 4 3 2 1
eSPI Flash Sharing Mode XTAL Frequency Select XTAL INPUT MODE (HVM ONLY)
GPP_H23 (WEAK INTERNAL PD) GPP_H21 (WEAK INTERNAL PD) GPD7(External pull-up is required)
0 = MAFS enabled (Default) 0 = 38.4 XTAL frequency selected. (Default) 0 = XTAL INPUT IS SINGLE ENDED
1 = SAFS enabled. +3V_PCH
1 = 24MHz XTAL frequency selected. +3V_PCH 1 = XTAL IS ATTACHED +3V_PCH_DSW
2 1
1 @ 2 1 2 RH24 100K_0402_5%
GPP_H23 RC202 4.7K_0402_5% GPP_H21 RC200 4.7K_0402_5% TBT_RTD3_WAKE#
2 @ 1 1 @ 2 1 @ 2
D RC250 20K_0402_5% RC251 20K_0402_5% RC261 20K_0402_5% D
0 = Master At t ached Fl as h Shari ng

(MAFS) enabled. (Default)
1 = Slave At t ached Fl as h Shari ng
(SAFS) enabled.
CPU_C10_GATE# is a new signal

from the Whiskey Lake SoC that can be used for gat i ng off
VccSTG, VccPLL_OC and VccIO (WHL-U) in the S0/C10 system state in order to save power.
UCPU1I
CR30 CNV io CN27

PCH CNVio RX lane 0 (52) CNV_PRX_DTX_N0 CP30 CNV_WR_D0N GPP_H18/CPU_C10_GATE# CPU_C10_GATE# (58,78,89)
(52) CNV_PRX_DTX_P0 CNV_WR_D0P CM27
CM30 GPP_H19/TIMESYNC_0
PCH CNVio RX lane 1 (52) CNV_PRX_DTX_N1 CN30 CNV_WR_D1N CF25Strap Pin
GPP_H21
(52) CNV_PRX_DTX_P1 CN32 CNV_WR_D1P GPP_H21/XTAL_FREQ_SELECT CN26
(52) CNV_PTX_DRX_N0 CNV_WT_D0N GPP_H22 GPP_H23 RTD3_CIO_PWR_EN (47)
CM32 CM26Strap Pin
PCH CNVio TX lane 0 (52) CNV_PTX_DRX_P0 CNV_WT_D0P GPP_H23 CK17
CP33 GPP_F10
(52) CNV_PTX_DRX_N1 CNV_WT_D1N TBT_RTD3_WAKE#
CN33 BV35Strap Pin
PCH CNVio TX lane 1 (52) CNV_PTX_DRX_P1 CNV_WT_D1P GPD7 CN20 TBT_RTD3_WAKE# (47)
CN31 GPP_F3
(52) CLK_CNV_PRX_DTX_N CP31 CNV_WR_CLKN CG25
PCH CNVio RX CLK (52) CLK_CNV_PRX_DTX_P CP34 CNV_WR_CLKP GPP_D4/IMGCLKOUT0/BK4/SBK4 CH25
TBT_FORCE_PWR (47)
(52) CLK_CNV_PTX_DRX_N CN34 CNV_WT_CLKN GPP_H20/IMGCLKOUT_1 +1.8VA +1.8VA
C PCH CNVio TX CLK (52) CLK_CNV_PTX_DRX_P CNV_WT_CLKP CR20 1. 8 V
MEM_CONFIG0 C
CNVI_RCOMP GPP_F12/EMMC_DATA0 MEM_CONFIG1
150_0402_1% 1 2 RC203 CP32 CM20 1. 8 V
MEM_CONFIG2
CR32 CNV_WT_RCOMP_0 GPP_F13/EMMC_DATA1 CN19 1. 8 V
CNV_WT_RCOMP_1 GPP_F14/EMMC_DATA2 MEM_CONFIG3
1
(53) CNV_COEX3
1. 8 V CP20 EMM C CM19 1. 8 V
MEM_CONFIG4 U22@ CPUI7@
+3V_PCH 0521 GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3 CN18 1. 8 V RC679 RC694
Follow RVP DDR_CHA_EN GPP_F16/EMMC_DATA4 CPU_DET#
PCH_TBT_PERST# PU 10K DDR_CHB_EN
1. 8 V CK19 CR18 1. 8 V
I7I5CPU_DET# 10K_0201_5% 10K_0201_5%
1. 8 V CG17 GPP_F1 GPP_F17/EMMC_DATA5 CP18 1. 8 V
RC39 1 RTD3@ 2 10K_0201_5% GPP_F2 GPP_F18/EMMC_DATA6 CM18
PCH_TBT_PERST#
2
CR14 GPP_F19/EMMC_DATA7
PCH_TBT_PERST# (47) PCH_TBT_PERST# GPP_C8/UART0_RXD
RC32 1 2 100K_0201_5% CP14
@RTD3@ (79) SBIOS_TX CN14 GPP_C9/UART0_TXD CM16
GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK CPU_DET# CPU_DET# I7I5CPU_DET# I7I5CPU_DET#
CM14 CP16
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK CR16
1. 8 V CJ17 GPP_F11/EMMC_CMD CN16
(53) CNV_COEX2 1. 8 V CH17 GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET# HIGH U22 HIGH I7 CPU
(53) CNV_COEX1 GPP_F9/CNV_MFUART2_TXD EMMC_RCOMP
1
+1.8VS CK15 1 2 U42@ CPUI5@
GPP_F23_A4WP_PRESENT EMMC_RCOMP
1. 8 V CF17 RC144 200_0402_1% RC680 RC695
RH23 1 2 100K_0402_5%~D GPP_F23/A4WP_PRESENT LOW U42 LOW I5 CPU
10K_0201_5% 10K_0201_5%
DDR_CHA_EN Trace Width : 4mil(breakout) / 8-12mil (typically)
@ RH28 1 2 SHORT PADS WHL-U42_BGA1528 Isolation Spacing : 12mil
Max Length : NA
2
@
9 of 20
+1.8VS
RH22 1 2 100K_0402_5%~D
DDR_CHB_EN
@ RH31 1 2 SHORT PADS
+1.8VA
MEM_CONFIG0
+1.8VA RV P 10K_0402_5% 1 @ 2 RH15 10K_0402_5% 1 @ 2 RH7
MEM_CONFIG1
10K_0402_5% 1 @ 2 RH13 10K_0402_5% 1 @ 2 RH16
RC672 1 @ 2 100K_0201_5%
MEM_CONFIG2
GPP_F23_A4WP_PRESENT 10K_0402_5% 1 @ 2 RH12 10K_0402_5% 1 @ 2 RH14
RC671 1 @ 2 100K_0201_5% MEM_CONFIG3
10K_0402_5% 1 @ 2 RH11 10K_0402_5% 1 @ 2 RH10
B MEM_CONFIG4 B
10K_0402_5% 1 2 RH8 10K_0402_5% 1 @ 2 RH9
DDR Memory Configuratino Type Strap pin

GPIO Pin Pin Name Micron Micron Mircon Hynix Hynix Hynix Samsung Samsung Samsung
8Gb(4GB) 16Gb(8GB) 32Gb(16GB) 8Gb(4GB) 16Gb(8GB) 32Gb(16GB) 8Gb(4GB) 16Gb(8GB) 32Gb(16GB)
GPP_F1 2 MEM_CONFIG 0 0 1 0 1 0 1 0 1 0
GPP_F1 3 MEM_CONFIG 1 1 1 0 0 1 1 0 0 1
2133 Mbps
GPP_F1 4 MEM_CONFIG 2 0 0 1 1 1 1 0 0 0
GPP_F1 5 MEM_CONFIG 3 0 0 0 0 0 0 1 1 1
GPP_F1 6 MEM_CONFIG 4 1 1 1 1 1 1 1 1 1
A A
P014 - WHL-U(9/14)CNV,EMMC
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G661P 0.4
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
+VCC_CORE
UCPU1L
CPU POWER 1 OF 4
AN9 AW24
PSC(Primary side cap) : Place as close to the package as possible AN10 VCCCORE5 VCCCORE35 AW25
D D
BSC(Backside cap) : Place on secondary side, underneath the package AN24 VCCCORE1 VCCCORE36 AW26
AN26 VCCCORE2 VCCCORE37 AW27
AN27 VCCCORE3 VCCCORE38 AY24
AP2 VCCCORE4 VCCCORE44 AY26
Component placement order: AP9 VCCCORE6 VCCCORE45 BA5
Package edge > 0402 caps > 0805 caps > Bulk caps >Power source AP24 VCCCORE9 VCCCORE48 BA7
AP26 VCCCORE7 VCCCORE49 BA8
AR5 VCCCORE8 VCCCORE50 BA25
+VCC_CORE: 0.55~1.5V, 29A AR6
AR7
VCCCORE13
VCCCORE14
VCCCORE46
VCCCORE47
BA27
BB2
+VCC_EDRAM: 1V, 2.5A AR8
AR10
VCCCORE15
VCCCORE16
VCCCORE51
VCCCORE52
BB26
BC5
AR25 VCCCORE10 VCCCORE56 BC6
AR27 VCCCORE11 VCCCORE57 BC7
+V1.8S_EDRAM: 1.8V, 50mA - REMOVE AT9 VCCCORE12
VCCCORE19
VCCCORE58
VCCCORE59
BC9
AT24 BC10
+VCC_EOPIO: 0.8~1V, 2A - REMOVE AT26 VCCCORE17
VCCCORE18
VCCCORE53
VCCCORE54
BC26
UCPU1O AU5 BC27
AU6 VCCCORE24 VCCCORE55 BD5
RESERVED SIGNALS VCCCORE25 VCCCORE63
K12 AA24 AU7 BD8
K14 RSVD48 RSVD38 AA26 AU8 VCCCORE26 VCCCORE64 BD10
K15 RSVD49 RSVD39 AB25 AU9 VCCCORE27 VCCCORE60 BD25
K17 RSVD50 RSVD40 AC24 AU24 VCCCORE28 VCCCORE61 BD27
K18 RSVD51 RSVD41 AC25 AU25 VCCCORE20 VCCCORE62 BE9
K20 RSVD52 RSVD42 AC26 AU26 VCCCORE21 VCCCORE69 BE24
L25 RSVD53 RSVD43 AD24 AU27 VCCCORE22 VCCCORE65 BE25
M24 RSVD54 RSVD44 AD26 AV2 VCCCORE23 VCCCORE66 BE26 +VCC_CORE Jony _12/25: Refer RVP keep it test pad
RSVD55 RSVD45 VCCEOPIO_SENSE VCCCORE30 VCCCORE67 570990_CFL_U_DDR4_RVP_CRB_Sch_Rev0p8.pdf
M26 V25 VSSEOPIO_SENSE AV5 BE27
P24 RSVD56 RSVD46 T25 PAD~D @ T20 AV7 VCCCORE32 VCCCORE68 BF2
PAD~D @ T21
1
RSVD57 RSVD47 VCCCORE33 VCCCORE70
100_0402_1%
P26 AV10 BF9
R24 RSVD58 AV27 VCCCORE29 VCCCORE73 BF24
RSVD59 VCCCORE31 VCCCORE71 Close CPU
RC198
R25 AW5 BF26 PVT- 082
R26 RSVD60 AW6 VCCCORE39 VCCCORE72 BG27 Change to short-pad
RSVD61 AW7 VCCCORE40 VCCCORE74
VCC_SENSE_R
2
AW8 VCCCORE41 AN6 RC87 1 2
VSS_SENSE_R @ 0_0402_5%
VCCCORE42 VCC_SENSE VCCSENSE (90)
AW9 AN5 RC86 1 @ 2 0_0402_5%
C W25 AW10 VCCCORE43 VSS_SENSE VSSSENSE (90) C
RSVD62 VCCCORE34 H_CPU_SVIDALRT#
100_0402_1%
V24 AA3
Y25 RSVD63 VIDALERT#
RSVD64 +VCC_CORE_G0 VIDSCLK_R
RC118
Y24 BB9 AA1
RSVD65 T40 @ PAD~D +VCC_CORE_G1 RSVD3 VIDSCK
BC24 VIDSOUT_R
T7 @ PAD~D +VCC_CORE_G2 RSVD4
AY9 AA2
T18 @ PAD~D +VCC_CORE_G3
2
BB24 RSVD1 VIDSOUT
WHL-U42_BGA1528
T19 @ PAD~D RSVD2 Y3
RSVD5
@ +1.0V_VCCSTG_CPU
15 of 20 BG3 2 @ 1 1V@0.05A
VCCSTG1 RC277 +1.0V_VCCSTG
0_0603_5%
WHL-U42_BGA1528
@
12 of 20
PVT- 131
VCCOPC,VCCOPC_1P8,VCCEOPIO for SKYLAKE-U 2+3e Change to short-pad
(w/ on package cache)
+1.0V_VCCST
1
RC275
SVID ALERT 56_0402_1%
CAD Note: Place the PU resistors close to CPU
RC275 close to CPU 1000 - 1500mils
2
H_CPU_SVIDALRT#
2 1
VIDALERT_N (90)
220_0402_5% RC278
B B
+1.0V_VCCST
1
SVID DATA RC282
100_0402_1%
2
VIDSOUT_R
0_0402_5% 2 @ 1 RC276
VIDSOUT (90)
+1.0V_VCCST
PVT- 083
Change to short-pad
1
SVID CLK RC116
@
100_0402_1%
VIDSCLK_R
2
0_0402_5% 2 @ 1 RC240
VIDSCLK (90)
A A

P015 - WHL-U(10/14)Power CORE
Dat e: Monday, January 28, 2019 Sheet 15 of 100
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.55~1.5V, 54A

+VCCGTX : 0.55~1.5V, 7A +VCC_GT
+VCC_CORE +VCC_GT
EVT ES2 SAMPLE

1.5V@54A
UCPU1M
CPU POWER 2 OF 4
A5 D15
A6 VCCGT8 VCCGT58 D17
A12 VCCGT1 VCCGT61 E4
A14 VCCGT2 VCCGT64 F5
D A18 VCCGT5 VCCGT71 F8 D
VCCGT7 VCCGT65 F14
AA9 ES1/ES2 VCCGT66 F17
AB2 VCCGT11/VCCCORE75 VCCGT67 F20
AB8 VCCGT13/VCCCORE76 VCCGT68 G11
AC8 VCCGT12/VCCCORE79 VCCGT75 G15
AD9 VCCGT16/VCCCORE80 VCCGT76 G17
AE8 VCCGT17/VCCCORE81 VCCGT77 G18
AE9 VCCGT19/VCCCORE82 VCCGT78 G20
AE10 VCCGT20/VCCCORE83 VCCGT79 H5
AF2 VCCGT18/VCCCORE84 VCCGT87 H6
AG8 VCCGT21/VCCCORE87 VCCGT90 H11
AG9 VCCGT24/VCCCORE88 VCCGT80 H12
AH9 VCCGT25/VCCCORE89 VCCGT81 H14
AJ8 VCCGT26/VCCCORE90 VCCGT82 H15
AJ10 VCCGT28/VCCCORE91 VCCGT83 H17
AK2 VCCGT27/VCCCORE92 VCCGT84 H18
AK9 VCCGT29//VCCCORE93 VCCGT85 H20
AL8 VCCGT30/VCCCORE94 VCCGT86 J7
AM8 VCCGT31/VCCCORE97 VCCGT91 J14
V2 VCCGT34/VCCCORE98 VCCGT92 J17
Y10 VCCGT115/VCCCORE99 VCCGT93 J20
Y8 VCCGT119/VCCCORE100 VCCGT94 K2
VCCGT120/VCCCORE101 VCCGT98 K11
B3 VCCGT97 L7
B4 VCCGT39 VCCGT100 L8
B6 VCCGT40 VCCGT101 L10
B8 VCCGT41 VCCGT99 M9
B11 VCCGT42 VCCGT102 N7
C2 VCCGT38 VCCGT103 P2
C3 VCCGT49 VCCGT107 P8
C6 VCCGT51 VCCGT108 R9
C7 VCCGT52 VCCGT109 T8
C8 VCCGT53 VCCGT111 T9 +VCC_GT
C11 VCCGT54 VCCGT112 T10
C12 VCCGT43 VCCGT110 U8
100_0402_1%
C14 VCCGT44 VCCGT114 U10
1
C15 VCCGT45 VCCGT113
RC279
C17 VCCGT46 V9
C18 VCCGT47 VCCGT116 W8
C C20 VCCGT48 VCCGT117 W9 C
Close CPU
D4 VCCGT50 VCCGT118 RC92
2
D7 VCCGT62
VCCGT_SENSE_R
D11 VCCGT63 E3 1 @ 2 0_0402_5%
VSSGT_SENSE_R VCC_GT_SENSE (90)
D12 VCCGT55 VCCGT_SENSE D2 1 2 0_0402_5%
@
VCCGT56 VSSGT_SENSE VSS_GT_SENSE (90)
D14
VCCGT57 RC91
100_0402_1%
PVT-08 6
WHL-U42_BGA1528 Change to short-pad
RC285
@ 13 of 20
2
+1.2V_DDR
+1.0VS_VCCIO
Primary Side
Placeholder
Primary Side Primary Side
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1 1 VCCIO:
CC60
CC261
CC262
CC52
CC56
CC42
CC59
PDG Rev0.9 Page.475
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
Primary Side cap 1 1 1 1 1 1 1 1
CC91
CC87
CC71
CC72
2 2 2 2 2 2 2 4x 1uF 0201
CC18
CC13
CC21
CC22
VDDQ :
2 2 2 2 2 2 2 2
Primary Side cap Primary or Secondary Side
1x 22uF 0603 + 6x 10uF 0402 6x 10uF 0402 @ @ @ @
Secondary Side
Secondary Side cap Placeholder Only
4x 1uF 0402/0201 + 3x 10uF 0402
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4x 0402 Primary or Secondary Side

1 1 1 1 1 1 1
CC263
CC29
CC30
CC38
CC43
CC41
CC37
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1
2 2 2 2 2 2 2
CC81
CC80
CC77
CC78
CC75
CC74
B B
+1.2V_DDR
2 2 2 2 2 2
+1.0VS_VCCIO
+1.0V_VCCST
1.2V@2.6A 0.95V@3.679A
UCPU1N
PSC AK24
CPU POWER 3 OF 4 VCCIO1
close to package AD36 AK26
AH32 VDDQ1 VCCIO2 AL24
VCCST: VDDQ2 VCCIO3
1U_0201_6.3V6M
1 1 AH36 AL25
VDDQ3 VCCIO4
CC68
Primary Side cap AM36 AL26

0.1U_0402_10V7K
VDDQ4 VCCIO5
CC86
AN32 AL27
1x 1uF 0402 AW32 VDDQ5
VDDQ6
VCCIO6
VCCIO7
AM25
2 2 AY36 AM27
BE32 VDDQ7 VCCIO8 BH24
BH36 VDDQ8 VCCIO9 BH25
R32 VDDQ9 VCCIO10 BH26
Y36 VDDQ10 VCCIO11 BH27
+1.0V_VCCSTG +1.0V_VCCSTG_FUSE VDDQ11 VCCIO12 BJ24
VCCIO13 BJ26
R64 1 @ 2 0_0402_5% VCCIO14 BP16
BC28 VCCIO15 BP18 +VCC_SA
PVT-08 4 RSVD1 VCCIO16
Change to short-pad
1V@0.19A BP11 BG8 1.15V@6A
BP2 VCCST1 VCCSA2 BG10
+1.0V_VCCSTG VCCST2 VCCSA1 BH9
VCCSA3 BJ8
BG1 VCCSA5 BJ9
VCCST G: BSC 1V@0.02A
BG2 VCCSTG1 VCCSA6 BJ10
1V@0.02A VCCSTG2 VCCSA4
Primary Side cap underneath the package
VCCSA9
BK8
1U_0201_6.3V6M
1.2V@0.12A BL27 BK25 +1.0VS_VCCIO

1
1x 1uF 0402 VCCPLL_OC1 VCCSA7
CC19
BM26 BK27
VCCPLL_OC2 VCCSA8 BL8
+1.0V_VCCST BR11 VCCSA13 BL9
VCCPLL1 VCCSA14
1
2 PVT-13 2 BT11 BL10
Change to short-pad
1V@0.19A VCCPLL2 VCCSA10 BL24 RC115
1
0516 VCCSA11 BL26 100_0402_1%

RC685
CC70 mount 22uF VCCSA12 BM24
X9 Lessen Learn
@ 0_0603_5% VCCSA15 BN25
+VCCPLL_OC +1.0V_VCCPLL VCCSA16
VCCIO_SENSE PVT-08 5 2 Close CPU
BP28 Change to short-pad
VSSIO_SENSE
2
VCCIO_SENSE BP29 VCCIO_SENSE (89)

PSC PSC VSSIO_SENSE RC88
VSSIO_SENSE (89)
VSSSA_SENSE_CPU
close to package close to package BE7 VCCSA_SENSE_CPU 1 @ 2 0_0402_5%
10U_0402_6.3V6M
VSSSA_SENSE
1
1U_0201_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
BG7 1 @ 2 0_0402_5%
0.1U_0201_6.3V6K
VCCSA_SENSE
CC83
RC230 RC121
0.1U_0402_10V7K
VccPLL_OC: 1 1 1 1 1
1
CC69
CC15
CC70
CC264
CC82
WHL-U42_BGA1528 100_0402_1%
RC114
A
Primary Side cap @
14 of 20 1 2 100_0402_1% A
1x 1uF 0402
2
+VCC_SA
2
2 2 2 2 2 RC284 100_0402_1%
2
VccPLL:
VSA_SEN- (90)
Primary Side cap VSA_SEN+ (90)
1x 0.1uF 0201
Primary or Secondary Side
1x 1uF 0402
Placeholder Only. DELL CONFIDENTIAL/PROPRIETARY
1x 0805 Security Classification Compal Secret Data Compal Electronics, Inc.
2018/05/08 2018/05/08 Ti t l e
P016 - WHL-U(11/14)Power GT,IO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D S i ze Document Number Re v
Dat e : Thursday , January 31, 2019 Sheet 16 of 100
5 4 3 2 1
5 4 3 2 1
D PDG Rev0.9 Page.500 D
CC281,CC282 Close to BT12, BR14, BR15 +VCCPRIM_1P05:

+VCCPRIM_1P05
PCH PWR
1x 1uF 0402 +VCCPRIM_3P3
1.05V@5.442A UCPU1P
Close to BP20 1.05V@1.625 A CPU POWER 4 OF 4
+1.0VA +VCCPRIM_1P05 BP20 CB16 3.3V@0.199 A
BW16 VCCPRIM_1P05_1 VCCPRIM_3P3_3
1 VCCPRIM_1P05_9 +RTCVCC
RC422 1 2 0_0603_5% 1 2 BW18
CC281 1U_0201_6.3V6M CC28 BW19 VCCPRIM_1P05_10
1U_0201_6.3V6M VCCPRIM_1P05_11
RC537 1 2 0_0603_5% 1 @ 2 +VCCPRIM_1P8 BY16 BR23 3.0V@0.002 A
CC282 1U_0201_6.3V6M 2 CA14 VCCPRIM_1P05_12 VCCRTC
VCCPRIM_1P05_14 VCCRTCEXT +RTCVCC:
1U_0201_6.3V6M
PVT-133 @ Close to CP17 BY20
Change to short-pad
1.8V@0.696A
VCCPRIM_1P8: 1.8V@0.696 A CC15 VCCPRIM_1P05_13 BP24 +VCCPRIM_1P05 1 1
1x 1uF 0402
0.1U_0402_10V7K
VCCPRIM_1P8_1 DCPRTC
1x 1uF 0402
CC55
CC51
CD15 close to BP24
1x 0.1uF 0402
1U_0201_6.3V6M
VCCPRIM_1P8_4
1U_0201_6.3V6M
+1.8VA +VCCPRIM_1P8 CD16
1 VCCPRIM_1P8_5 1 2 2
+VCCPRIM_3P3 CP17 BR20
CC73
VCCPRIM_1P8_8 VCCPRIM_1P05_3 +VCCPRIM_1P05
CC26
RC535 1 @ 2 0_0603_5% @
close to CP29 3.3V@0.199 A CB22 BT12
2 CB23 VCCPRIM_3P3_4 VCCAPLL_1P05_3 +VCCPRIM_1P05 2
CC22 VCCPRIM_3P3_5 BP14 1.05V@0.009 A
3.3V@0.199A 1 1 VCCPRIM_3P3_6 VCCA_BCLK_1P05 +VCCPRIM_1P05 VCCRTCEXT:
0.1U_0201_10V6K
CC243
1U_0201_6.3V6M
CC244
CC23
VCCPRIM_3P3_7
+3V_PCH +VCCPRIM_3P3 CD22
CD23 VCCPRIM_3P3_8 VCCAPLL_1P05_1
BR14 1.05V@0.102 A
+VCCPRIM_1P05 Placeholder
RC536 1 @ 2 0_0603_5% +1.0V_PRIM_CORE 2 @ 2 @ CP29 VCCPRIM_3P3_9
VCCPRIM_3P3_10
1x 1uF 0201
BU12 1.05V@0.034 A
1.05V@4.26 A BU15 VCCA_SRC_1P05 +VCCPRIM_1P05 +1.0VA +1.0V_CLK
+1.0V_PRIM_CORE: Close to BV18 VCCPRIM_CORE1 DESIGN NOTE: BP24 / CAP EMPTY
BU22 CP5 1.05V@0.034 A PLACEHOLDER CAM BE REMOVED AFTER PI SIMULATION 2.2UH 20% / 260MA EMPTY
VCCPRIM_CORE2 VCCA_XTAL_1P05 +1.0V_CLK
1U_0201_6.3V6M
+3V_PCH +3V_1.8V_SPI
Placeholder 1 BV15
VCCPRIM_CORE3
CC89
BV16 BY24 1.24V@0.61 A PCH Internal VRM L38 1 2 LQM18PN2R2NC0L_2P Close to CP5
1x 1uF 0402 @ VCCPRIM_3P3: BV18 VCCPRIM_CORE4 VCCDPHY_1P24_2 CA24
+VCCLDOSRAM_1P24 +VCCDPHY_1P24
close to CP25
VCCPRIM_CORE5 VCCDPHY_1P24_4
1 @ 2 Placeholder BV19
VCCPRIM_CORE6 PCH Internal VRM
1U_0201_6.3V6M
1U_0201_6.3V6M
2
47U_0603_6.3V
RC627 0_0402_5% BV20 BY23 1 @ 2
4.7U_0402_6.3V6M
1x 1uF 0402 VCCPRIM_CORE7 VCCDPHY_1P24_1 1 1 1
CC31
PVT-087 BV22 CA23 RC640 0_0402_5%
Change to short-pad VCCPRIM_CORE8 VCCDPHY_1P24_3
CC280
CC65
1x 0.1uF 0402 BW20
BW22 VCCPRIM_CORE9 VCCDPHY_1P24_5
CP25
+VCCDPHY_1P24:
+VCCPDSW_1P05 VCCPRIM_CORE10 1 2 2 2
CA12
CA16 VCCPRIM_CORE11 VCCDSW_3P3_2
BT23 3.3V@0.199 A +3V_PCH_DSW 1x 4.7uF 0402
PCH Internal VRM VCCPRIM_CORE12 CA9
close to BT24 CA18 BR12 1.05V@0.027 A
VCCPRIM_CORE13 VCCA_19P2_1P05 +VCCPRIM_1P05 2
CA19
C VCCPRIM_CORE14 C
1 CA20
CB12 VCCPRIM_CORE15 +VCCPRIM_1P8
CC79 CB14 VCCPRIM_CORE16 +1.0V_CLK:
VCCDSW_1P05: 1U_0201_6.3V6M CB15 VCCPRIM_CORE17 CC18 1.8V@0.696 A Close to CP23 1x 1uF 0402
2 VCCPRIM_CORE18 VCCPRIM_1P8_2
1x 1uF 0402 1.05V@0.024 A VCCPRIM_1P8_3
CC19
1U_0201_6.3V6M
BT24 CD18 1
VCCDSW_1P05 VCCPRIM_1P8_6 CD19
+VCCPRIM_1P05 1.05V@0.102 A VCCPRIM_1P8_7 +VCCPRIM_3P3 VCCPRIM_1P8:
CC90
+VCCPRIM_1P05 BU14 CP23 @
VCCAPLL_1P05_4 VCCPRIM_1P8_9
1.05V@2.878 A BV12 BW23 2
Placeholder
Close to BV12 3.3V@0.199 A
BW12 VCCPRIM_MPHY_1P05_1 VCCPRIM_3P3_2 1x 1uF 0402
VCCPRIM_MPHY_1P05_3
22U_0603_6.3V6M
BW14 +VCCPRIM_3P3
1 VCCMPHYGTAON_1P05: VCCPRIM_MPHY_1P05_4
CC265
BY12
VCCAMPHYPLL_1P05: 1x 22uF 0603 BY14 VCCPRIM_MPHY_1P05_5 BP23 3.3V@0.199 A
VCCPRIM_MPHY_1P05_6 VCCPRIM_3P3_1
1x 1uF 0402 2 1.05V@0.152 A BV2 CB36
+1.0V_AMPHYPLL VCCAMPHYPLL_1P05 GPP_B0/CORE_VID0 CORE_VID0 (89)
CB35 CORE_VID1 (89)
+1.0VA +1.0V_AMPHYPLL BR15 GPP_B1/CORE_VID1
close UC1 <120mil +VCCPRIM_1P05 1.05V@0.102 A
VCCAPLL_1P05_2
+VCCPRIM_1P05 1.05V@0.129 A CC12 PCH Core VID Bit 0/1: Connect to discrete VRs
L37 1 2 LQM18PN2R2NC0L_2P +3V_PCH PVT-088 VCCHDA VCCDUSB_1P05 This pin will only be driven high (‘ 1’ ) in native mode, to supported voltage of 1.0 5 V
.
close to BV2
Change to short-pad 3.3V@0.001 A BR24
+3V_PCH_DSW VCCDSW_3P3_1
47U_0603_6.3V
RC172 1 @ 2 0_0603_5% 1 1 3.3V@0.006 A

1U_0201_6.3V6M
CC25
1 @ 2 VCCHDA BT20
VCCHDA
CC17
1 RC667 0_0402_5% 1 3.3V@0.002 A

0.1U_0201_10V6K
CC278
0.1U_0201_10V6K
CC279
+3V_1.8V_SPI BV23
2 2 0515 BT18 VCCSPI
RF request +VCCPRIM_1P05 BT19 VCCPRIM_1P05_4
Reserv ed cap
2 @RF@ 2 @RF@ BU18 VCCPRIM_1P05_5
BU19 VCCPRIM_1P05_7
VCCPRIM_1P05_8
BT22
+VCCPRIM_1P05 +VCCPRIM_1P05 VCCPRIM_1P05_6
BP22
VCCPRIM_1P05_2
BV14
VCCPRIM_MPHY_1P05_2
WHL-U42_BGA1528
@ 16 of 20
B B
+3V_PCH_DSW +3V_PCH
1 @NDS3@ 2 +3VALW
RC604 0_0201_5%
RC256 1 @ 2 0_0402_5%
+3V_PCH_DSW:
Placeholder Q8
PJ2301_SOT23-3
1x 1uF 0402 DS3@ +3.3V_ALW_DSW_Q8
1 2 1 3
S
D
RC108 0_0402_5%
1
1U_0201_6.3V6M
22U_0603_6.3V6M
@ CC48
R155
1 1
G
2
Close to BR24
CC35
499K_0402_1%
2 2
2
2
R143
1
100K_0402_5%
R154
0.1U_0402_25V6
49.9K_0402_1%
1
1
CC23
2
2
1
@
D
2
VCCDSW_EN_GPIO (11)
Q7 G
S
3
L2N7002WT1G_SC-70-3
A A
P017 - WHL-U(12/14)Power PCH
5 4 3 2 1
5 4 3 2 1
D D
Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_ VI D Rec o mmendat i on
UCPU1R
UCPU1T
GND 1 OF 3
CR34 BL7 UCPU1S GND 3 OF 3
BT5 VSS_1 VSS_73 AE25 BT35 BY25 N6 CF23
GND 2 OF 3
BY5 VSS_2 VSS_74 BM33 D6 VSS_145 VSS_217 J18 B37 VSS_290 VSS_362 V4
CP35 VSS_3 VSS_75 CM5 AL32 VSS_146 VSS_218 AU32 CB3 VSS_291 VSS_363 BE30
CM37 VSS_4 VSS_76 AE27 BT36 VSS_147 VSS_219 BY28 P10 VSS_292 VSS_364 CF28
CK37 VSS_5 VSS_77 BM35 D8 VSS_148 VSS_220 J21 B5 VSS_293 VSS_365 W10
AW1 VSS_6 VSS_78 CM9 AL7 VSS_149 VSS_221 AV25 CB33 VSS_294 VSS_366 BE31
CM1 VSS_7 VSS_79 AE30 D9 VSS_150 VSS_222 BY33 P3 VSS_295 VSS_367 CF3
BD6 VSS_8 VSS_80 BM36 AM10 VSS_151 VSS_223 J24 B7 VSS_296 VSS_368 W27
AY4 VSS_9 VSS_81 CN13 BU11 VSS_152 VSS_224 AV28 CB4 VSS_297 VSS_369 CF4
B34 VSS_10 VSS_82 AE7 E23 VSS_153 VSS_225 BY35 P33 VSS_298 VSS_370 W30
E35 VSS_11 VSS_83 BM9 AM28 VSS_154 VSS_226 J33 B9 VSS_299 VSS_371 BF3
A4 VSS_12 VSS_84 CN17 E27 VSS_155 VSS_227 AV3 CB7 VSS_300 VSS_372 CG33
AE24 VSS_13 VSS_85 AF27 AM33 VSS_156 VSS_228 BY36 P36 VSS_301 VSS_373 W7
AE26 VSS_14 VSS_86 BN30 BU23 VSS_157 VSS_229 J36 BA10 VSS_302 VSS_374 BF33
AF25 VSS_15 VSS_87 CN21 E29 VSS_158 VSS_230 AV33 CC11 VSS_303 VSS_375 CG7
AG24 VSS_16 VSS_88 AF3 AM35 VSS_159 VSS_231 J6 P4 VSS_304 VSS_376 BF36
AG26 VSS_17 VSS_89 BN7 BU24 VSS_160 VSS_232 AV36 BA28 VSS_305 VSS_377 Y26
AH24 VSS_18 VSS_90 CN25 E31 VSS_161 VSS_233 C1 P7 VSS_306 VSS_378 BF4
AH25 VSS_19 VSS_91 AF30 BU25 VSS_162 VSS_234 K21 BA3 VSS_307 VSS_379 CH31
B2 VSS_20 VSS_92 CN29 E33 VSS_163 VSS_235 AV4 CC20 VSS_308 VSS_380 Y27
B36 VSS_21 VSS_93 AF33 AN25 VSS_164 VSS_236 C21 R27 VSS_309 VSS_381 BG25
C36 VSS_22 VSS_94 BP15 BU7 VSS_165 VSS_237 K22 BB3 VSS_310 VSS_382 Y30
C37 VSS_23 VSS_95 AF36 E9 VSS_166 VSS_238 AV6 CC25 VSS_311 VSS_383 BG28
CN1 VSS_24 VSS_96 AF4 AN28 VSS_167 VSS_239 C25 R28 VSS_312 VSS_384 CJ11
CN2 VSS_25 VSS_97 CN5 BV11 VSS_168 VSS_240 K24 BB33 VSS_313 VSS_385 Y33
C VSS_26 VSS_98 VSS_169 VSS_241 VSS_314 VSS_386 C
CN37 AF7 F12 AV8 CC28 CJ14
CP2 VSS_27 VSS_99 BP25 AN29 VSS_170 VSS_242 C29 R29 VSS_315 VSS_387 Y35
D1 VSS_28 VSS_100 CN9 F15 VSS_171 VSS_243 K25 BB36 VSS_316 VSS_388 BH28
A32 VSS_29 VSS_101 AG10 AN30 VSS_172 VSS_244 AW28 CC31 VSS_317 VSS_389 CJ19
F33 VSS_30 VSS_102 BP3 F18 VSS_173 VSS_245 C33 R30 VSS_318 VSS_390 Y7
A3 VSS_31 VSS_103 CP1 AN31 VSS_174 VSS_246 K27 BB4 VSS_319 VSS_391 BH29
BJ7 VSS_32 VSS_104 BP32 BV3 VSS_175 VSS_247 AW29 CC7 VSS_320 VSS_392 CJ23
CJ36 VSS_33 VSS_105 CP11 F2 VSS_176 VSS_248 C4 R31 VSS_321 VSS_393 BH32
A36 VSS_34 VSS_106 AH27 AN7 VSS_177 VSS_249 K28 BC25 VSS_322 VSS_394 CJ28
BK10 VSS_35 VSS_107 BP33 BV31 VSS_178 VSS_250 AW3 CD11 VSS_323 VSS_395 BH33
CJ4 VSS_36 VSS_108 CP13 F21 VSS_179 VSS_251 C9 T27 VSS_324 VSS_396 CJ33
AB27 VSS_37 VSS_109 AH28 AN8 VSS_180 VSS_252 K29 CD12 VSS_325 VSS_397 BH35
BK2 VSS_38 VSS_110 BP4 BV33 VSS_181 VSS_253 AW30 T30 VSS_326 VSS_398 CJ35
CK1 VSS_39 VSS_111 CP15 F24 VSS_182 VSS_254 CA11 BC29 VSS_327 VSS_399 BP19
AB3 VSS_40 VSS_112 AH29 BV4 VSS_183 VSS_255 K3 CD14 VSS_328 VSS_400 BR16
BK28 VSS_41 VSS_113 BP7 F3 VSS_184 VSS_256 AW31 T33 VSS_329 VSS_401 BY18
AB30 VSS_42 VSS_114 CP19 AP3 VSS_185 VSS_257 CA15 T35 VSS_330 VSS_402 BY19
BK3 VSS_43 VSS_115 AH30 BW11 VSS_186 VSS_258 K30 BC32 VSS_331 VSS_403 CC16
CK4 VSS_44 VSS_116 CP21 F4 VSS_187 VSS_259 AY33 CD24 VSS_332 VSS_404 BU16
AB33 VSS_45 VSS_117 AH31 AP33 VSS_188 VSS_260 CA22 T36 VSS_333 VSS_405 CC14
BK33 VSS_46 VSS_118 BR19 BW15 VSS_189 VSS_261 K31 CD25 VSS_334 VSS_406 BR22
CK7 VSS_47 VSS_119 CP27 G21 VSS_190 VSS_262 AY35 T7 VSS_335 VSS_407 BU20
AB36 VSS_48 VSS_120 AH33 AP36 VSS_191 VSS_263 K32 BC8 VSS_336 VSS_408 CD20
BK4 VSS_49 VSS_121 BR25 G27 VSS_192 VSS_264 B12 CE33 VSS_337 VSS_409 BT14
CL2 VSS_50 VSS_122 AH35 AP4 VSS_193 VSS_265 K4 U26 VSS_338 VSS_410 BP12
AB4 VSS_51 VSS_123 CP37 G33 VSS_194 VSS_266 B15 BD28 VSS_339 VSS_411 CB24
BK7 VSS_52 VSS_124 AJ25 AR28 VSS_195 VSS_267 CA25 CE35 VSS_340 VSS_412 CC24
CM13 VSS_53 VSS_125 BT15 G35 VSS_196 VSS_268 K9 U7 VSS_341 VSS_413 J5
AB7 VSS_54 VSS_126 AJ28 G36 VSS_197 VSS_269 B18 BD33 VSS_342 VSS_414 U24
BL25 VSS_55 VSS_127 BT16 AT33 VSS_198 VSS_270 CB11 CE36 VSS_343 VSS_415 BD7
CM17 VSS_56 VSS_128 CP9 BW24 VSS_199 VSS_271 L27 V26 VSS_344 VSS_416 AR4
AC10 VSS_57 VSS_129 AJ7 G9 VSS_200 VSS_272 B21 BD35 VSS_345 VSS_417 AU4
BL28 VSS_58 VSS_130 CR2 AT35 VSS_201 VSS_273 L33 CE7 VSS_346 VSS_418 AW4
CM21 VSS_59 VSS_131 AK3 H21 VSS_202 VSS_274 B23 V27 VSS_347 VSS_419 BA6
AC27 VSS_60 VSS_132 CR36 AT36 VSS_203 VSS_275 L35 BD36 VSS_348 VSS_420 BC4
BL29 VSS_61 VSS_133 AK33 BW7 VSS_204 VSS_276 B25 CF11 VSS_349 VSS_421 BE4
CM25 VSS_62 VSS_134 D21 H27 VSS_205 VSS_277 CB18 V3 VSS_350 VSS_422 BE8
AC30 VSS_63 VSS_135 AK36 AT4 VSS_206 VSS_278 L36 BE10 VSS_351 VSS_423 BA4
BL30 VSS_64 VSS_136 BT25 BY11 VSS_207 VSS_279 B27 CF14 VSS_352 VSS_424 BD4
CM29 VSS_65 VSS_137 D25 AU10 VSS_208 VSS_280 CB19 V30 VSS_353 VSS_425 BG4
BL31 VSS_66 VSS_138 AK4 BY15 VSS_209 VSS_281 L6 BE28 VSS_354 VSS_426 CJ2
CM31 VSS_67 VSS_139 BT28 H9 VSS_210 VSS_282 B29 CF19 VSS_355 VSS_427 CJ3
B B
AD33 VSS_68 VSS_140 AL28 AU28 VSS_211 VSS_283 CB2 V33 VSS_356 VSS_428 AM5
BL32 VSS_69 VSS_141 BT33 BY22 VSS_212 VSS_284 N25 BE29 VSS_357 VSS_429 CM4
CM33 VSS_70 VSS_142 D5 J12 VSS_213 VSS_285 B31 CF2 VSS_358 VSS_430 AC5
AD35 VSS_71 VSS_143 AL29 AU29 VSS_214 VSS_286 CB20 V36 VSS_359 VSS_431 AG5
VSS_72 VSS_144 J15 VSS_215 VSS_287 N27 BE3 VSS_360 VSS_432 CR6
VSS_216 VSS_288 CB25 VSS_361 VSS_433
WHL-U42_BGA1528 VSS_289
@ WHL-U42_BGA1528
17 of 20 WHL-U42_BGA1528 @ 19 of 20
@ 18 of 20
A A
P018 - WHL-U(13/14)GND
5 4 3 2 1
5 4 3 2 1
1 2 CFG0 1 2 CFG7
@ RC76 1K_0402_1% @ RC77 1K_0402_1%
EAR-STALL/NOT STALL RESET

SEQUENCE AFTER PCU PLL IS LOCKED PEG DEFER TRAINING
1: (DEFAULT) PEG TRAIN IMMEDIATELY

CFG0 1:(DEFAULT)NORMAL OPERATION; NO STALL
0:STALL
CFG7 FOLLOWING XXRESETB DE ASSERTION
0: PEG WAIT FOR BIOS FOR TRAINING
1 2 CFG1 1 2 CFG8
D @ RC249 1K_0402_1% @ RC83 1K_0402_1% D
PCH/ PCH LESS MODE SELECTION ALLOW THE USE OF CFG ON LOCKED UNITS
1: DISABLED(DEFAULT); IN THIS CASE, CFG WILL BE
1: (DEFAULT) NORMAL OPERATION DISABLED IN LOCKED UNITS AND ENABLED IN UN-LOCKED UNITS AND
CFG1 0: PCH-LESS MODE CFG8 0: EENABLED; CFG WILL BE
AVAILABLE REGARDLESS OF THE LOCKING OF THE UNIT
1 2 CFG2 1 2 CFG9
@ RC78 1K_0402_1% @ RC81 1K_0402_1%
(7) CFG[0..15]
CFG0
PCI EXPRESS STATIC LANE REVERSAL NO SVID PROTOCOL CAPABLE VR CONNECTED CFG1
FOR ALL PEG PORTS CFG2
CFG3 UCPU1Q
CFG2 1: (DEFAULT)NORMAL OPERATION CFG9 1:VRS SUPPORTING SVID PROTOCOL ARE PRESENT CFG4
0: LANE REVERSAL 0: NO VR SUPPORTING SVID CFG5 RESERVED SIGNALS
F37
CFG6 T4 RSVD_TP5 F34 PAD~D @ T22
CFG0
CFG7 R4 CFG_0 RSVD_TP4 PAD~D @ T23
CFG1
CFG8 CFG2 T3 CFG_1 CP36
1 2 1 2 CFG10 CFG9 R3 CFG_2 IST_TRIG CN36 PAD~D @ T24
CFG3 CFG3
@ RC220 1K_0402_1% CFG10 J4 CFG_3 RSVD_TP3 PAD~D @ T25
@ RC75 1K_0402_1% CFG4
CFG11 CFG5 M4 CFG_4 BJ36
CFG12 CFG6 J3 CFG_5 RSVD15 BJ34
CFG13 CFG7 M3 CFG_6 RSVD14
CFG14 CFG8 R2 CFG_7 BK34
CFG15 N2 CFG_8 TP_1 BR18 PAD~D @ T27
CFG9
CFG10 R1 CFG_9 TP_2 PAD~D @ T34
PCH/ PCH LESS MODE SELECTION SAFE MODE BOOT CFG_10
CFG11 N1
CFG12 J2 CFG_11
1:(DEFAULT) NORMAL OPERATION 1: POWER FEATURES ACTIVATED DURING RESET (7) CFG12
CFG3 CFG10 0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED CFG13 L2 CFG_12 BT9
0: PCH-LESS MODE
J1 CFG_13 RSVD21 BT8 PAD~D @ T13
(7) CFG14 CFG14
CFG15 L1 CFG_14 RSVD20 PAD~D @ T15
C CFG_15 C
BP8
L3 RSVD18 BP9 PAD~D @ T16
(7) CFG16 CFG_16 RSVD19 PAD~D @ T14
1 2 (7) CFG18 N3
1 2 CFG4 CFG11 CFG_18
(7) CFG17 L4 CR4
RC99 1K_0402_5% @ RC219 1K_0402_1%
N4 CFG_17 RSVD29 PAD~D @ T17
(7) CFG19 CFG_19 CP3
RSVD26 CR3
CFG_RCOMP RSVD27
2 1 AB5 PVT-009
0: AN EXTERNAL DISPLAY PORT DEVICE PORT IS CONNECTED TO THE EMBEDDED PORT CFG_RCOMP Change to short-pad
1: NO PHYSICAL DISPLAY PORT ATTACHED TO EMBEDDED DISPLAY PORT RC222 49.9_0402_1%
2 1 W4
EAR-STALL/NOT STALL RESET +1.0VA_XDP ITP_PMODE
DISPLAY PORT PRESENCE STRAP SEQUENCE AFTER PCU PLL IS LOCKED RC170 1.5K_0402_5% BP36 2 @ 1
CG2 VSS_434 RC687 0_0201_5%
1:(DEF U LT) CG1 RSVD25
CFG4 0: ENABLED CFG11 DMI WILL BE CONFIGURED AS HALF SWING DC COUPLED (7) XDP_ITP_PMODE
1: DISABLED; RSVD24
0:DMI WILL BE CONFIGURED AS FULL SWING AC COUPLED
AT3
RSVD12 AU3
RSVD13
1 2 H4
1 2 CFG5 CFG12 RSVD34
H3
@ RC74 1K_0402_1% @ RC218 1K_0402_1% RSVD33 AN1
BV24 RSVD8 AN2
BV25 RSVD22 RSVD9
RSVD23 AN4
RSVD11 AN3
1 2 CFG6 RSVD10
@ RC79 1K_0402_1% PM SYNC LEGACY AL2
G3 RSVD72 AL1
1: (DEFAULT) PMSYNC 2.0 G4 RSVD66 RSVD73
CFG12 0 : LEGACY RSVD67
AL4
RSVD74 AL3
BK36 RSVD75
RSVD17 Jony _12/22: Refer RVP VSS_435 EMPTY
BK35 BP34 New add a 0 ohm to GND and NC
PCIE PORT BIFURCATION STRAPS 1 2 CFG13 RSVD16 TP_4 BP35 PAD~D @ T36
@ RC217 1K_0402_1% W3 TP_3 PAD~D @ T37
11: DEVICE1 FUNTION 1, DEVICE 1 FUNCTION2 DISABLED AM4 RSVD35 +VCC_GT
10: DEVICE1 FUNTION 1, ENABLED DEVICE 1 FUNCTION2 DISABLED RSVD7 C34 RC204 2 @ 1 0_0201_5%
AM3 RSVD68
100_0402_1%
RSVD6
CFG5,6 A34
PAD~D @ T38
1
RSVD_TP1 B35
PAD~D @ T39
RC140
RSVD_TP2
PCH/ PCH LESS MODE SELECTION PMSYNC AYNC MODE- PM SYNC
B CR35 B
A35 RSVD28 PAD~D @ T3
01: DEVICE1 FUNTION 1, DISABLED, DEVICE 1 FUNCTION2 ENABLED 1: (DEFAULT)SYNCHCRONOUS (1 24 MHZ CYCLE PER BIT)
00: DEVICE 1 FUNCTION 1 ENABLED, DEVICE 1 FUNCTION 2 ENABLED
CFG13 0: ASYNC - 4-24MHZ CYCLES PER BIT D34 RSVD1 @
2
RSVD30 AH26 RC213 1 @ 2 0_0402_5%
G2 RSVD36 AJ27 RC214 1 @ 2 0_0402_5%
G1 RSVD32 RSVD37
RSVD31 E1 SKTOCC# RC281 1 @ 2 0_0402_5%
SKTOCC#
1 2 CFG14 1 2 CFG15
@ RC216 1K_0402_1% @ RC221 1K_0402_1%
WHL-U42_BGA1528
@ 20 of 20
CFG14 CFG15
A A
P019 - WHL-U(14/14)RSVD, CFG
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P020 - Reserve
Date : Monday, January 28, 2019 Sheet 20 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P021 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P022 - Reserve
5 4 3 2 1
5 4 3 2 1
+1.8VU +1.8VU +1.8VU +1.8VU
D +1.8VU UD3 @ +1.8VU UD2 @ D
10U_0402_6.3V6M
10U_0402_6.3V6M
DDR_M0_D49 DDR_M0_D7
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
A3 P9 DDR_M0_D53 A3 P9 DDR_M0_D3
A4 VDD1 DQ0 N9 A4 VDD1 DQ0 N9
(8) DDR_M0_DQS#[0..7] 1 1 DDR_M0_D51 1 1 DDR_M0_D1
1
VDD1 DQ1 VDD1 DQ1
CD64
CD72
CD63
CD79
CD50
CD52
A5 N10 DDR_M0_D50
A5 N10 DDR_M0_D5
(8) DDR_M0_DQS[0..7] VDD1 DQ3 DDR_M0_D52 VDD1 DQ3 DDR_M0_D2
A10 M8 DDR_M0_D48
A10 M8 DDR_M0_D6
2
2 2 U3 VDD1 DQ4 M9 2 2 U3 VDD1 DQ4 M9
(8) DDR_M0_D[0..63] VDD1 DQ5 DDR_M0_D54 VDD1 DQ5 DDR_M0_D4
U4 M10 DDR_M0_D55 U4 M10 DDR_M0_D0
U5 VDD1 DQ6 M11 U5 VDD1 DQ6 M11
(8,25) DDR_M0_CAA_[0..9] VDD1 DQ7 DDR_M0_D11 VDD1 DQ7 DDR_M0_D38
U6 F11 DDR_M0_D8 U6 F11 DDR_M0_D39
U10 VDD1 DQ8 F10 U10 VDD1 DQ8 F10
(8,25) DDR_M0_CAB_[0..9] VDD1 DQ9 DDR_M0_D15 VDD1 DQ9 DDR_M0_D36
+1.2V_DDR F9 +1.2V_DDR F9
DQ10 DDR_M0_D9 DQ10 DDR_M0_D33
F8 DDR_M0_D12 F8 DDR_M0_D35
A8 DQ11 E11 A8 DQ11 E11
VDD2 DQ12 DDR_M0_D13 VDD2 DQ12 DDR_M0_D34
A9 E10 DDR_M0_D10 A9 E10 DDR_M0_D37
D4 VDD2 DQ13 E9 +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9
+1.2V_DDR +1.2V_DDR D5 D9 D5 D9
D6 T8 DDR_M0_D63 D6 T8 DDR_M0_D28
VDD2 DQ16 VDD2 DQ16
10U_0402_6.3V6M
G5 T9 DDR_M0_D57
G5 T9 DDR_M0_D27
VDD2 DQ17 VDD2 DQ17
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
H5 T10 DDR_M0_D56 H5 T10 DDR_M0_D30
VDD2 DQ18 VDD2 DQ18
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
H6 T11 DDR_M0_D59 1 1 1 H6 T11 DDR_M0_D24
VDD2 DQ19 VDD2 DQ19
1
CD3
CD74
CD2
CD16
1 1 1 H12 R8 DDR_M0_D62 H12 R8 DDR_M0_D29
1
VDD2 DQ20 VDD2 DQ20

CD37
CD12
CD10
CD28
J5 R9 DDR_M0_D61 J5 R9 DDR_M0_D31
J6 VDD2 DQ21 R10 J6 VDD2 DQ21 R10
2
K5 VDD2 DQ22 R11 2 2 2 K5 VDD2 DQ22 R11
2
2 2 2 K6 VDD2 DQ23 C11 K6 VDD2 DQ23 C11

K12 C10 DDR_M0_D19 K12 C10 DDR_M0_D42
L5 VDD2 DQ25 C9 L5 VDD2 DQ25 C9
P4 C8 P4 C8
P5 B11 DDR_M0_D20 P5 B11 DDR_M0_D40
P6 VDD2 DQ28 B10 P6 VDD2 DQ28 B10
U8 B9 DDR_M0_D23 U8 B9 DDR_M0_D46
U9 VDD2 DQ30 B8 U9 VDD2 DQ30 B8
+1.2V_DDR VDD2 DQ31 +1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31
+1.2V_DDR +1.2V_DDR +1.2V_DDR

DDR_M0_CAB_0 Closed to UD41 DDR_M0_CAA_0
A11 R2 DDR_M0_CAB_1
A11 R2 DDR_M0_CAA_1
VDDQ CA0 VDDQ CA0
10U_0402_6.3V6M
Closed to UD42 C12 P2 DDR_M0_CAB_2 C12 P2 DDR_M0_CAA_2
VDDQ CA1 VDDQ CA1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
E8 N2 DDR_M0_CAB_3 E8 N2 DDR_M0_CAA_3
VDDQ CA2 VDDQ CA2
10U_0402_6.3V6M
E12 N3 DDR_M0_CAB_4 1 1 1 1 1 1 E12 N3 DDR_M0_CAA_4

VDDQ CA3 VDDQ CA3
1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
CD8
CD1
CD4
CD13
CD61
G12 M3 DDR_M0_CAB_5 G12 M3 DDR_M0_CAA_5
VDDQ CA4 VDDQ CA4
CD59
CD76
1 1 1 1 1 1 H8 F3 DDR_M0_CAB_6
H8 F3 DDR_M0_CAA_6
C VDDQ CA5 VDDQ CA5 C
1
CD9
CD29
CD88
CD49
CD87
CD51
H9 E3 DDR_M0_CAB_7 H9 E3 DDR_M0_CAA_7
2
VDDQ CA6 2 2 2 2 2 2 VDDQ CA6
CD70
H11 E2 DDR_M0_CAB_8 H11 E2 DDR_M0_CAA_8

J9 VDDQ CA7 D2 J9 VDDQ CA7 D2
DDR_M0_CAB_9 DDR_M0_CAA_9
2
2 2 2 2 2 2 J10 VDDQ CA8 C2 J10 VDDQ CA8 C2

K8 VDDQ CA9 K8 VDDQ CA9
K11 VDDQ K11 VDDQ
VDDQ DDR_M0_DQS6 VDDQ DDR_M0_DQS0
L12 L10 DDR_M0_DQS1 L12 L10 DDR_M0_DQS4
N8 VDDQ DQS0 G10 N8 VDDQ DQS0 G10
VDDQ DQS1 DDR_M0_DQS7 VDDQ DQS1 DDR_M0_DQS3
N12 P10 DDR_M0_DQS2 N12 P10 DDR_M0_DQS5
R12 VDDQ DQS2 D10 R12 VDDQ DQS2 D10
U11 VDDQ DQS3 U11 VDDQ DQS3
+1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
DDR_M0_DQS#6 DDR_M0_DQS#0
L11 DDR_M0_DQS#1
L11 DDR_M0_DQS#4
F2 DQS0# G11 F2 DQS0# G11
VDDCA DQS1# DDR_M0_DQS#7 VDDCA DQS1# DDR_M0_DQS#3
10U_0402_6.3V6M
+1.2V_DDR +1.2V_DDR G2 P11 G2 P11
VDDCA DQS2# DDR_M0_DQS#2 VDDCA DQS2# DDR_M0_DQS#5
1U_0201_6.3V6M
1U_0201_6.3V6M
H3 D11 H3 D11
L2 VDDCA DQS3# L2 VDDCA DQS3#
1 1
1
VDDCA VDDCA
10U_0402_6.3V6M
CD5
CD83
CD84
M2 M2
VDDCA VDDCA
1U_0201_6.3V6M
1U_0201_6.3V6M
L8 L8
DM0 G8 DM0 G8
1 1
2
DM1 DM1
1
2 2
CD11
CD46
CD47
A1 P8 A1 P8
A2 NC DM2 D8 A2 NC DM2 D8
A12 NC DM3 A12 NC DM3
2
2 2 A13 NC A13 NC
NC DDR_A1_ZQ0 NC DDR_A0_ZQ0
B1 B3 DDR_A1_ZQ1 RD51 1 2 240_0402_1% B1 B3 DDR_A0_ZQ1 RD33 1 2 240_0402_1%
B13 NC ZQ0 B4 RD50 1 2 240_0402_1% B13 NC ZQ0 B4 RD28 1 2 240_0402_1%
C4 NC ZQ1 C4 NC ZQ1
K9 NC K9 NC
R3 NC K3 R3 NC K3
NC CKE0 DDR_A_CKE2 (8,25) NC CKE0 DDR_M0_CKE0 (8,25)
T1 K4 T1 K4
NC CKE1 DDR_A_CKE3 (8,25) NC CKE1 DDR_M0_CKE1 (8,25)
T13 T13
U1 NC U1 NC
NC DDR_M0_CS#0 NC DDR_M0_CS#0
U2 L3 DDR_M0_CS#1
U2 L3 DDR_M0_CS#1
NC CS0# DDR_M0_CS#0 (8,25) NC CS0#
U12 L4 DDR_M0_CS#1 (8,25)
U12 L4
U13 NC CS1# U13 NC CS1#
NC NC
J3 DDR_M0_CLK1 (8,25)
J3 DDR_M0_CLK0 (8,25)
P3 CK J2 P3 CK J2
VSSCA CK# DDR_M0_CLK#1 (8,25) VSSCA CK# DDR_M0_CLK#0 (8,25)
M4 M4
J4 VSSCA J4 VSSCA
VSSCA DDR_M0_ODT0 VSSCA DDR_M0_ODT0
G4 J8 DDR_M0_ODT0 (8,25)
G4 J8
G3 VSSCA ODT G3 VSSCA ODT
B B
F4 VSSCA F4 VSSCA
D3 VSSCA J11 D3 VSSCA J11
VSSCA Vref_DQ +VREFDQ_A VSSCA Vref_DQ +VREFDQ_A
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA
All VREF traces should
T12 B2 have 10 mil trace width T12 B2
T6 VSSQ VSS B5 T6 VSSQ VSS B5
VSSQ VSS
Closed to DRAM VSSQ VSS
Closed to DRAM
R6 C5 R6 C5
P12 VSSQ VSS E4 +VREFDQ_A +VREFCA P12 VSSQ VSS E4 +VREFDQ_A +VREFCA
N6 VSSQ VSS E5 N6 VSSQ VSS E5
M12 VSSQ VSS F5 M12 VSSQ VSS F5
VSSQ VSS VSSQ VSS
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
M6 H2 M6 H2
L9 VSSQ VSS J12 L9 VSSQ VSS J12
K10 VSSQ VSS K2 K10 VSSQ VSS K2
VSSQ VSS 1 1 VSSQ VSS 1 1
CD66
CD56
CD67
CD73
H10 L6 H10 L6
G9 VSSQ VSS M5 G9 VSSQ VSS M5
G6 VSSQ VSS N4 G6 VSSQ VSS N4
F12 VSSQ VSS N5 2 2 F12 VSSQ VSS N5 2 2
F6 VSSQ VSS R4 F6 VSSQ VSS R4
E6 VSSQ VSS R5 E6 VSSQ VSS R5
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 VSSQ VSS T3 C6 VSSQ VSS T3
B12 VSSQ VSS T4 B12 VSSQ VSS T4
VSSQ VSS VSSQ VSS
H9CCNNN8JTMLAR-NTM_FBGA178~D +1.2V_DDR +1.8VU H9CCNNN8JTMLAR-NTM_FBGA178~D

10U_0402_6.3V6M
10U_0402_6.3V6M
Decoupling per DRAM device

1
1
CD22
CD80
VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF

VDDCA 2x 0402 1uF 1x 0603 10uF
2
VDD2 3x 0402 1uF 1x 0603 10uF

VDD1 2x 0402 1uF 1x 0603 10uF
intel uesd 0201 for 0.1uF
A A
P023 - LPDDR3_CHA
5 4 3 2 1
5 4 3 2 1
+1.8VU +1.8VU +1.8VU +1.8VU

(8) DDR_M1_DQS#[0..7]
+1.8VU UD4 @ +1.8VU UD1 @
D (8) DDR_M1_DQS[0..7] D
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
A3 P9 DDR_M1_D48
A3 P9 DDR_M1_D10
(8) DDR_M1_D[0..63] VDD1 DQ0 VDD1 DQ0
1 1 A4 N9 DDR_M1_D54 1 1 A4 N9 DDR_M1_D9
1
VDD1 DQ1 VDD1 DQ1
CD78
CD43
CD55
CD69
CD44
CD65
(8,25) DDR_M1_CAA_[0..9]
A5 N10 DDR_M1_D55 A5 N10 DDR_M1_D12
(8,25) DDR_M1_CAB_[0..9]
A10 M8 DDR_M1_D52 A10 M8 DDR_M1_D14
2
2 2 U3 VDD1 DQ4 M9 2 2 U3 VDD1 DQ4 M9
U4 M10 DDR_M1_D51 U4 M10 DDR_M1_D8
U5 VDD1 DQ6 M11 U5 VDD1 DQ6 M11
U6 F11 DDR_M1_D24
U6 F11 DDR_M1_D38
U10 VDD1 DQ8 F10 U10 VDD1 DQ8 F10
+1.2V_DDR F9 +1.2V_DDR F9
DQ10 DDR_M1_D31 DQ10 DDR_M1_D33
F8 DDR_M1_D28 F8 DDR_M1_D34
A8 DQ11 E11 A8 DQ11 E11
A9 E10 DDR_M1_D30
A9 E10 DDR_M1_D36
+1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9 +1.2V_DDR +1.2V_DDR D4 VDD2 DQ13 E9
D5 D9 DDR_M1_D62
D5 D9 DDR_M1_D4
D6 VDD2 DQ15 T8 D6 VDD2 DQ15 T8
10U_0402_6.3V6M
10U_0402_6.3V6M
G5 T9 DDR_M1_D60 G5 T9 DDR_M1_D7
VDD2 DQ17 VDD2 DQ17
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
H5 T10 DDR_M1_D61
H5 T10 DDR_M1_D6
H6 VDD2 DQ18 T11 H6 VDD2 DQ18 T11
1 1 1 DDR_M1_D63 1 1 1 DDR_M1_D1
1
1
VDD2 DQ19 VDD2 DQ19
CD15
CD42
CD75
CD45
CD26
CD48
CD38
CD53
H12 R8 DDR_M1_D59
H12 R8 DDR_M1_D0
J5 VDD2 DQ20 R9 J5 VDD2 DQ20 R9
J6 R10 DDR_M1_D56 J6 R10 DDR_M1_D3
2
2
2 2 2 K5 VDD2 DQ22 R11 2 2 2 K5 VDD2 DQ22 R11
K6 C11 DDR_M1_D18 K6 C11 DDR_M1_D44
K12 VDD2 DQ24 C10 K12 VDD2 DQ24 C10
L5 C9 DDR_M1_D16 L5 C9 DDR_M1_D43
P4 VDD2 DQ26 C8 P4 VDD2 DQ26 C8
P5 B11 P5 B11
P6 B10 DDR_M1_D23 P6 B10 DDR_M1_D47
U8 VDD2 DQ29 B9 U8 VDD2 DQ29 B9
U9 B8 U9 B8
+1.2V_DDR +1.2V_DDR +1.2V_DDR +1.2V_DDR VDD2 DQ31 +1.2V_DDR VDD2 DQ31
+1.2V_DDR +1.2V_DDR +1.2V_DDR
DDR_M1_CAA_0 DDR_M1_CAB_0
Closed to UD44 A11 R2 DDR_M1_CAA_1 A11 R2 DDR_M1_CAB_1
VDDQ CA0 VDDQ CA0
10U_0402_6.3V6M
C12 P2 DDR_M1_CAA_2 Closed to UD43 C12 P2 DDR_M1_CAB_2

VDDQ CA1 VDDQ CA1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
10U_0402_6.3V6M
E8 N2 DDR_M1_CAA_3 E8 N2 DDR_M1_CAB_3
VDDQ CA2 VDDQ CA2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
1 1 1 1 1 1 E12 N3 DDR_M1_CAA_4 E12 N3 DDR_M1_CAB_4
1
VDDQ CA3 VDDQ CA3

CD7
CD71
CD86
CD77
CD89
G12 M3 DDR_M1_CAA_5 1 1 1 1 1 1 G12 M3 DDR_M1_CAB_5

VDDQ CA4 VDDQ CA4
1
CD68
CD85
CD20
CD91
CD60
CD92
CD90
H8 F3 DDR_M1_CAA_6 H8 F3 DDR_M1_CAB_6
VDDQ CA5 VDDQ CA5
CD81
CD36
H9 E3 DDR_M1_CAA_7
H9 E3 DDR_M1_CAB_7
C C
2
2 2 2 2 2 2 H11 VDDQ CA6 E2 H11 VDDQ CA6 E2

DDR_M1_CAA_8 DDR_M1_CAB_8
2
J9 VDDQ CA7 D2 2 2 2 2 2 2 J9 VDDQ CA7 D2
VDDQ CA8 DDR_M1_CAA_9 VDDQ CA8 DDR_M1_CAB_9
J10 C2 J10 C2
K8 VDDQ CA9 K8 VDDQ CA9
K11 VDDQ K11 VDDQ
VDDQ DDR_M1_DQS6 VDDQ DDR_M1_DQS1
L12 L10 DDR_M1_DQS3 L12 L10 DDR_M1_DQS4
N8 VDDQ DQS0 G10 N8 VDDQ DQS0 G10
VDDQ DQS1 DDR_M1_DQS7 VDDQ DQS1 DDR_M1_DQS0
N12 P10 DDR_M1_DQS2
N12 P10 DDR_M1_DQS5
R12 VDDQ DQS2 D10 R12 VDDQ DQS2 D10
U11 VDDQ DQS3 U11 VDDQ DQS3
+1.2V_DDR VDDQ +1.2V_DDR +1.2V_DDR +1.2V_DDR VDDQ
DDR_M1_DQS#6 DDR_M1_DQS#1
+1.2V_DDR +1.2V_DDR L11 L11
DQS0# DDR_M1_DQS#3 DQS0# DDR_M1_DQS#4
F2 G11 DDR_M1_DQS#7
F2 G11 DDR_M1_DQS#0
VDDCA DQS1# VDDCA DQS1#
10U_0402_6.3V6M
G2 P11 DDR_M1_DQS#2 G2 P11 DDR_M1_DQS#5
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
H3 D11 H3 D11
1U_0201_6.3V6M
1U_0201_6.3V6M
L2 1 1 L2
1
VDDCA VDDCA
CD6
CD58
CD54
1 1 M2 M2
1
VDDCA VDDCA
CD23
CD82
CD93
L8 L8
DM0 G8 DM0 G8
2
A1 DM1 P8 2 2 A1 DM1 P8
2
2 2 A2 NC DM2 D8 A2 NC DM2 D8
NC DM3 572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf NC DM3
A12 A12
A13 NC A13 NC
NC DDR_B0_ZQ0 NC DDR_B1_ZQ0
B1 B3 DDR_B0_ZQ1 RD47 1 2 240_0402_1% B1 B3 DDR_B1_ZQ1 RD24 1 2 240_0402_1%
B13 NC ZQ0 B4 RD1 1 2 240_0402_1% B13 NC ZQ0 B4 RD45 1 2 240_0402_1%
C4 NC ZQ1 C4 NC ZQ1
K9 NC K9 NC
R3 NC K3 R3 NC K3
NC CKE0 DDR_M1_CKE0 (8,25) NC CKE0 DDR_B_CKE2 (8,25)
T1 K4 DDR_M1_CKE1 (8,25)
T1 K4 DDR_B_CKE3 (8,25)
T13 NC CKE1 T13 NC CKE1
U1 NC U1 NC
NC DDR_M1_CS#0 NC DDR_M1_CS#0
U2 L3 DDR_M1_CS#1 DDR_M1_CS#0 (8,25)
U2 L3 DDR_M1_CS#1
U12 NC CS0# L4 U12 NC CS0# L4
NC CS1# DDR_M1_CS#1 (8,25) NC CS1#
U13 U13
NC NC
J3 DDR_M1_CLK0 (8,25)
J3 DDR_M1_CLK1 (8,25)
P3 CK J2 P3 CK J2
VSSCA CK# DDR_M1_CLK#0 (8,25) All VREF traces should VSSCA CK# DDR_M1_CLK#1 (8,25)
M4 have 10 mil trace width M4
J4 VSSCA J4 VSSCA
VSSCA DDR_M1_ODT0 VSSCA DDR_M1_ODT0
G4 J8 G4 J8
VSSCA ODT DDR_M1_ODT0 (8,25) VSSCA ODT
G3 G3
F4 VSSCA F4 VSSCA
B B
D3 VSSCA J11 D3 VSSCA J11
VSSCA Vref_DQ +VREFDQ_B VSSCA Vref_DQ +VREFDQ_B
C3 H4 C3 H4
VSSCA Vref_CA +VREFCA VSSCA Vref_CA +VREFCA
T12 B2 T12 B2
T6 VSSQ VSS B5 T6 VSSQ VSS B5
VSSQ VSS Closed to DRAM VSSQ VSS Closed to DRAM
R6 C5 R6 C5
P12 VSSQ VSS E4 +VREFDQ_B +VREFCA P12 VSSQ VSS E4 +VREFDQ_B +VREFCA
N6 VSSQ VSS E5 N6 VSSQ VSS E5
M12 VSSQ VSS F5 M12 VSSQ VSS F5
VSSQ VSS VSSQ VSS
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
0.047U_0402_10V7K~D
M6 H2 M6 H2
L9 VSSQ VSS J12 L9 VSSQ VSS J12
K10 VSSQ VSS K2 K10 VSSQ VSS K2
VSSQ VSS 1 1 VSSQ VSS 1 1
CD57
CD62
CD31
CD39
H10 L6 H10 L6
G9 VSSQ VSS M5 G9 VSSQ VSS M5
G6 VSSQ VSS N4 G6 VSSQ VSS N4
F12 VSSQ VSS N5 2 2 F12 VSSQ VSS N5 2 2
F6 VSSQ VSS R4 F6 VSSQ VSS R4
E6 VSSQ VSS R5 E6 VSSQ VSS R5
D12 VSSQ VSS T2 D12 VSSQ VSS T2
C6 VSSQ VSS T3 C6 VSSQ VSS T3
VSSQ VSS VSSQ VSS
H9CCNNN8JTMLAR-NTM_FBGA178~D H9CCNNN8JTMLAR-NTM_FBGA178~D
Decoupling per DRAM device

VDDQ 4x 0402 1uF 2x 0201 0.1uF 1x 0603 10uF
VDDCA 2x 0402 1uF 1x 0603 10uF
VDD2 3x 0402 1uF 1x 0603 10uF
VDD1 2x 0402 1uF 1x 0603 10uF
intel uesd 0201 for 0.1uF
A A
P023 - LPDDR3_CHB
5 4 3 2 1
5 4 3 2 1
VREF traces should be at least 20 mils wide

with 20 mils spacing to other signals/planes.
D D
+1.2V_DDR
M3 M1
1
RD82
8.2K_0402_1%
2
RD46
(8) +V_DDR_REF_CA
1 2 +VREFCA
1
4.99_0402_1%~D
CD41
0.022U_0402_16V7K~D
1
2
RD41
1
8.2K_0402_1%
RD48
2
24.9_0402_1%
2
+1.2V_DDR
M3 M1
1
C RD66 C
8.2K_0402_1%
2
RD17
(8) +V_DDR_REFA_R 1 2 +VREFDQ_A
SD000012L80 S RES 1/20W 37.4 +-1% 0201
10_0402_1%~D SD00000TS00 S RES 1/20W 80.6 +-1% 0201
1
+0.6VS +0.6VS
SD00000Z900 S RES 1/20W 68 +-1% 0201
CD24
1
0.022U_0402_16V7K~D
2
RD14
8.2K_0402_1% RD53 1 2 68_0201_1% RD52 1 2 68_0201_1%
(8,23) DDR_M0_CAA_0 (8,24) DDR_M1_CAA_0
1
RD55 1 2 68_0201_1% RD54 1 2 68_0201_1%

(8,23) DDR_M0_CAA_1 (8,24) DDR_M1_CAA_1
2
RD25 RD59 1 2 68_0201_1% RD56 1 2 68_0201_1%

(8,23) DDR_M0_CAA_2 (8,24) DDR_M1_CAA_2
24.9_0402_1% RD57 1 2 68_0201_1% RD58 1 2 68_0201_1%
(8,23) DDR_M0_CAA_3 (8,24) DDR_M1_CAA_3
RD61 1 2 68_0201_1% RD60 1 2 68_0201_1%
(8,23) DDR_M0_CAA_4 (8,24) DDR_M1_CAA_4
RD72 1 2 68_0201_1% RD73 1 2 68_0201_1%
(8,23) DDR_M0_CAA_5 (8,24) DDR_M1_CAA_5
2
RD74 1 2 68_0201_1% RD77 1 2 68_0201_1%

(8,23) DDR_M0_CAA_6 (8,24) DDR_M1_CAA_6
RD76 1 2 68_0201_1% RD75 1 2 68_0201_1%
(8,23) DDR_M0_CAA_7 (8,24) DDR_M1_CAA_7
RD78 1 2 68_0201_1% RD79 1 2 68_0201_1%
(8,23) DDR_M0_CAA_8 (8,24) DDR_M1_CAA_8
RD80 1 2 68_0201_1% RD81 1 2 68_0201_1%
(8,23) DDR_M0_CAA_9 (8,24) DDR_M1_CAA_9
+1.2V_DDR RD4 1 2 68_0201_1% RD3 1 2 68_0201_1%

(8,23) DDR_M0_CAB_0 (8,24) DDR_M1_CAB_0
RD6 1 2 68_0201_1% RD5 1 2 68_0201_1%
M3 M1 (8,23)
(8,23)
DDR_M0_CAB_1
DDR_M0_CAB_2
RD49 1 2 68_0201_1%
(8,24)
(8,24)
DDR_M1_CAB_1
DDR_M1_CAB_2
RD2 1 2 68_0201_1%
1
RD8 1 2 68_0201_1% RD7 1 2 68_0201_1%

(8,23) DDR_M0_CAB_3 (8,24) DDR_M1_CAB_3
RD10 1 2 68_0201_1% RD9 1 2 68_0201_1%
(8,23) DDR_M0_CAB_4 (8,24) DDR_M1_CAB_4
RD37 RD35 1 2 68_0201_1% RD30 1 2 68_0201_1%
(8,23) DDR_M0_CAB_5 (8,24) DDR_M1_CAB_5
8.2K_0402_1% RD40 1 2 68_0201_1% RD36 1 2 68_0201_1%
(8,23) DDR_M0_CAB_6 (8,24) DDR_M1_CAB_6
RD38 1 2 68_0201_1% RD32 1 2 68_0201_1%
(8,23) DDR_M0_CAB_7 (8,24) DDR_M1_CAB_7
2
RD29 RD43 1 2 68_0201_1% RD39 1 2 68_0201_1%

(8,23) DDR_M0_CAB_8 (8,24) DDR_M1_CAB_8
1 2 RD44 1 2 68_0201_1% RD42 1 2 68_0201_1%
(8) +V_DDR_REFB_R +VREFDQ_B (8,23) DDR_M0_CAB_9 (8,24) DDR_M1_CAB_9
1 10_0402_1%~D
B B
CD19 (8,23) DDR_M0_CS#0 RD12 1 2 80.6_0201_1%~D (8,24) DDR_M1_CS#0 RD13 1 2 80.6_0201_1%~D
1
0.022U_0402_16V7K~D RD15 1 2 80.6_0201_1%~D RD11 1 2 80.6_0201_1%~D

2 (8,23) DDR_M0_CS#1 (8,24) DDR_M1_CS#1
RD34 +0.6VS
1
8.2K_0402_1% (8,23) DDR_M0_CKE0 RD65 1 2 80.6_0201_1%~D (8,24) DDR_M1_CKE0 RD62 1 2 80.6_0201_1%~D

RD20 (8,23) DDR_M0_CKE1 RD63 1 2 80.6_0201_1%~D (8,24) DDR_M1_CKE1 RD64 1 2 80.6_0201_1%~D
2
24.9_0402_1% RD21 1 2 80.6_0201_1%~D RD16 1 2 80.6_0201_1%~D

(8,23) DDR_A_CKE2 (8,24) DDR_B_CKE2
RD18 1 2 80.6_0201_1%~D RD19 1 2 80.6_0201_1%~D
(8,23) DDR_A_CKE3 (8,24) DDR_B_CKE3
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1
2
CD21
CD27
CD35 CD33 CD14 CD30
(8,23) DDR_M0_ODT0
RD23 1 2 80.6_0201_1%~D
(8,24) DDR_M1_ODT0
RD71 1 2 80.6_0201_1%~D
2 2 2 2 2 2
+0.6VS +0.6VS
0512
CD21,CD27,CD2 5 , CD1 7
Follow Intel suggest change 22uF to 10u
RD70 1 2 37.4_0201_1%~D RD69 1 2 37.4_0201_1%~D

(8,23) DDR_M0_CLK0 (8,24) DDR_M1_CLK0
RD68 1 2 37.4_0201_1%~D RD67 1 2 37.4_0201_1%~D

(8,23) DDR_M0_CLK#0 (8,24) DDR_M1_CLK#0
+0.6VS
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1
CD25
CD17
CD32 CD40 CD18 CD34

+0.6VS +0.6VS
2 2 2 2 2 2
A RD27 1 2 37.4_0201_1%~D RD26 1 2 37.4_0201_1%~D A

(8,23) DDR_M0_CLK1 (8,24) DDR_M1_CLK1
(8,23) DDR_M0_CLK#1 RD31 1 2 37.4_0201_1%~D (8,24) DDR_M1_CLK#1 RD22 1 2 37.4_0201_1%~D
P025 - LPDDR3_VREF
Date: Monday, January 28, 2019 Sheet 25 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P026 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P027 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P028 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P029 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P030 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P031 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P032 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P033 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P034 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P035 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P036 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P037 - Reserve
5 4 3 2 1
5 4 3 2 1
+3VALW +LCDVDD
eDP Conn +3VS
PVT-153
1
Change to short-pad +LCDVDD
U12 +LCDVDD_R
5 1 1 @ 2 @ RC7
IN OUT
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
0.1U_0201_10V6K
1 R85 0_0603_5% 1 1 1 1 1 1 1 100K_0201_5%
C58
2 EDP_LVDS_TXOUT_N1
2
GND
C59
C315
C316
C317
C318
C319
1 2 0.1U_0201_10V6K
@
C75 C285 EDP_AUXP_C
(6) EDP_TXN1
0.1U_0201_10V6K ENVDD 4 3 C282 1 2 0.1U_0201_10V6K
2 EN OC 2 2 2 2 2 2 2 (6) EDP_AUXP
EDP_LVDS_TXOUT_P1
SY6288C20AAC_SOT23-5
(6) EDP_TXP1
C286 1 2 0.1U_0201_10V6K EDP_AUXN_C
(6) EDP_AUXN C281 1 2 0.1U_0201_10V6K
1
EDP_LVDS_TXOUT_N0
D42 C284 1 2 0.1U_0201_10V6K
(6) EDP_TXN0
(6) ENVDD_PCH
2 @ RC6
EDP_LVDS_TXOUT_P0 100K_0201_5%
1 ENVDD C283 1 2 0.1U_0201_10V6K
(6) EDP_TXP0
2
D LCD_VCC_TEST_EN D
3
(58) LCD_VCC_TEST_EN
BAT54CW_SOT323-3
R90 2 1 220K_0201_5% ENVDD +LCDVDD
0.1U_0201_10V6K
+3VS_TS
33P_0201_50V8J
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
2 1 1 1 1 1 1 1 TS_I2C_SD/CLK ,OD pin, external pull-up
RF@ TS_I2C_SDA_R
C60
C57
C320
C321
C322
C323
C324
C325
2.2K_0201_5% 2 1
@
TS_I2C_SCL_R RC628
2.2K_0201_5% 2 1 RC629
eDP BackLight Power 1 2 2 2 2 2 2 2
0510
Modify pin define for eDP FPC routing PVT- 011
Change to short-pad
JEDP1
TS_I2C_SCL_R
1 2 TS_I2C_SDA_R R281 1 @ 2 0_0201_5%
(12) LCD_CBL_DET# 1 2 TS_I2C_SCL (12)
3 4 R299 1 @ 2 0_0201_5%
3 4 TS_I2C_SDA (12)
VR_B+ +INV_PWR_SRC 5 6
5 6 EDP_LVDS_TXOUT_N1
7 8 EDP_LVDS_TXOUT_P1
+INV_PWR_SRC 9 7 8 10
R87 1 @ 2 0_0603_5%~D 11 9 10 12
11 12 EDP_LVDS_TXOUT_N0
0515 13 14 EDP_LVDS_TXOUT_P0
RF request 13 14
JEDP1 pin9~27 15 16
connect to GND 17 15 16 18
Q15 17 18 EDP_AUXP_C
19 20 EDP_AUXN_C
SI3457BDV-T1-E3_TSOP6~D 19 20
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
0.1U_0402_25V6K~D
R303 21 22
+INV_PWR_SRC_R 21 22
1U_0603_25V6K
1 2 1 1 1 23 24 LCD panel driving
D
1
23 24
C70
6 25 26
60mil 60mil
S
25 26 Supply voltage: 3.0~3.6V
C65
C68
C69
4 5 1A_65V_T0603FF1000TM @ 27 28
+LCDVDD
2 PVT-010 29 27 28 30 Power dissipat i on 1. 1 W
2
2 2 2 Change to short-pad 29 30 +LCDVDD
1 TS_RST# Low Active
+3VS_TS
31
31 32
32 Connector signal contact 0.3A
1
W9015A internal pull-up resistor to VDD

G
1 TS_RST#R 33 34 LCD_TST (58)

C88 R231 2 @ 1 35 33 34 36 0_0201_5% 2 @ 1 RV1
(12) TS_RST# TS_INT#_R EDP_HPD_EC (58)
3
0.1U_0402_25V6K~D R220 0_0201_5% 37 35 36 38 0_0201_5% 2 @ 1 RV2

1M_0402_5%~D 37 38 EDP_HPD (6)
0.1U_0402_25V6K~D
39 40 DISPOFF#
INV_PWM 0_0201_5% 1 @ 2 R297
(7) TOUCH_SCREEN_PD#_R 39 40 SOLC (58)
10U_0603_25V6M
2 41 42
1
2
41 42
1
1
TOUCH_SCREEN_PD#_R Low Active PVT-012 0512
C EN_INVPWR_R SOLC panel internal pull-down 10k C
W9015A internal pull-up 35k to VDD Change to short-pad
C77
C76
43 44
45 Power Power 46 @ RC644
+INV_PWR_SRC
2
Power Power
1
2 100K_0201_5%
+3VS_TS +3VS_TS 47 48
@
Backlight driving
2
R232 49 GND GND 50
100K_0402_5%~D 51 GND GND 52 Supply voltage: 5~21V +3VS_TS
TS_RST#R
1
53 GND GND 54 Power dissipat i on 2. 14 W
2
GND GND
R316 55 56 Connector power contact 2.2A
2
GND GND
TVNST52302AB0_SOT523-3
0512 100K_0201_5% 57 58
GND GND
1
Add MOS f or TS_INT#
EMC@ C287
EMC@ C72
0.1U_0402_10V7K
@EMC@ C71
D 59 60
GND GND
0.1U_0201_10V6K
(58) EN_INVPWR
2 Q16 TS_INT#_R 61 62 1 2
1
GND GND
15P_0201_50V8J
DI1 EMC@
G L2N7002WT1G_SC-70-3 6 1
(12) TS_INT#
2
S 63 64
3
65 PTH PTH 66
PU at PCH side TS_INT#_R: Low Active,OD pin, external pull-up
2
67 PTH PTH 68 2 1
QC3A PTH PTH
5
2 @ 1 I-PEX_20698-042E-01
1
0_0201_5% R317 CONN@
3 4
QC3B
BackLight PWM Control

For BL_PWR_SRC & LCDVDD monitor VR_B+
D21
(6,10) PANEL_BKLEN
2
1
1 DISPOFF# DISPOFF# (7) +LCDVDD
QV4A
1
(58) PANEL_BKEN_EC
3 MMDT3906_SOT363-6
R187 2
220K_0201_5%
BAT54CW_SOT323-3
100K_0402_5%
PVT-089
1
2
Change to short-pad
RV9
+LCDVDD
10K_0402_5%
+INV_PWR_SRC
6
+3VALW 1 @ 2
RV12
B 0509 R315 0_0402_5% B
Reserve +3VALW to UZ9 1 @ 2 1 2
2
47K_0402_5%
R314 0_0201_5% C367 0.1U_0201_10V6K
1
PANEL_PWRGD_R
2
2 1
RV10
0510 1 @ 2
PANEL_PWRGD (58)
5
Add 0.1uF for UZ9 VCC 0.1U_0402_25V6 RV7 0_0402_5%

DV2
2200P_0402_50V7K
2 NC R76, panel has 10K PD PVT-091
200K_0402_5%
G Vcc
INV_PWM
0.1U_0402_25V6
(58) BIA_PWM_EC A RB751S40T1G_SOD523-2
1M_0402_5%
4 Change to short-pad
1
1
CV5
1
Y
1
1
CV6
RV11
1
(6) EDP_BIA_PWM
CV7
1
RV8
1
2
R76 @EMC@
3
6
2
UZ9 @ 4.7K_0201_5% MC1
2
BL_PWR_MONITOR
680P_0201_25V7K 2
2
74AUP1G32GW_TSSOP5 QV1A
2
2 MMDT3904_SOT363-6
2
1
+3VS
1 @ 2
RV3 0_0402_5%
QV4B PVT-090
4
MMDT3906_SOT363-6 Change to short-pad
10K_0402_5%
1
+LCDVDD
RV5
3
2
47K_0402_5%
1
2 1
RV6
0.1U_0402_25V6
DV1
2200P_0402_50V7K
200K_0402_5%
1
1
CV4
CV3
RV4
2
2
3
2
A LCDVDD_MONITOR A
5
2
QV1B
MMDT3904_SOT363-6

P038 - eDP/ Touch
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_WF +3VS_WF
R128
1 @ 2
0_0603_5%
(+2.8V_VCM_OUT) For Rear Camera VCM
C190
C158
C148
PVT-157
Change to short-pad
C167
1 1 1 1 +2.8V_VCM_OUT
+3VS PVT-134
Change to short-pad
100mA
0.1U_0201_10V6K
2.2U_0201_6.3V6M
0.1U_0201_10V6K
1U_0201_6.3V6M
+3.3V_WF_DV33
2 2 2 2 +2.8V_VCM_OUT_R
R123 1 @ 2 0_0603_5%
R121 1 2 100K_0402_5%~D
2.2U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1
C348
C192
C187
U6
WF_EECS
D 1 8 @ D
WF_EEDI_MISO
1
2 CS# VCC 7 U25 R127
WF_WP# SO/SIO1 HOLD# WF_EESK 2 2 2 1
100P_0402_50V8J
C344
2 1 3 6 1 51K_0201_1%
+3VS_WF WP# SCLK WF_EEDO_MOSI
+3.3V_WF_DV33 R114 10K_0402_5% 4 5 C169 1 5 R1 @
GND SI/SIO0 VIN VOUT +2.8V_VCM_OUT +2.8V_VCM_OUT
0.1U_0201_10V6K 2 2
MX25V2006EZNI-13G_WSON8_6X5
2
1 2 2 GND
L32 BLM15AG121SN1D_L0402_2P
(WSON8) WFCAM_EN
R140
1 @ 2
0_0201_5%
3
EN SNS
4
1
C184
C186
C309 0515
1
MX25V2006EMDI-13G_VSOP8 materail pr epar e is s ue
R13
47P_0201_25V8J
1 1 1 EVT change to W25Q80DVZPIG_WSON8 PVT-015 RT9078N-08GJ5_TSOT23-5 1
Change to short-pad
2.2U_0201_6.3V6M
2.2U_0201_6.3V6M
@ 10K_0402_5% R2 R139 1 1
C349
C170
@ Output current 300mA 20K_0201_1% @RF@
C179
0.1U_0201_10V6K
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
Enable pin VIH 0.9V @
2
2 2 2 U23 2
2
Power 2 2
10 CMOS Interface
VFB=0.8V
+1.2V_WF_USB3_AV12 VDDTX/USB3_AV12
output for 1.2V core power
CLKI_P
32 MCSI_D_CLKP (40) VOUT=VFB(1+R1/R2)
16 31 MCSI_D_CLKN (40)
+1.2V_WF_USB2_AV12
+1.2V_WF_DV12S
1.2V output for RTS5880 core power 21 DV12S_16 CLKI_N 28 MCSI_D_DP0 (40)
=0.8*3.55=2.84V
38 DV12S_21 DATAI0_P 27
+1.2V_WF_DV12S DV12S_38 DATAI0_N MCSI_D_DN0 (40)
+3VS_WF +3.3V_WF_AV33 1.2V output for RTS5880 core power 30 MCSI_D_DP1 (40) 560K 1.5M
20 DATAI1_P 29 R144 R144
+3.3V_WF_DV33
3.3V digital power input 12 DV33 DATAI1_N 34
MCSI_D_DN1
MCSI_D_DP2
(40)
(40)
LDO IC R2 TPS79801QDGNR@ LDO IC R2 TPS7A1601DGNR@
+3.3V_WF_AV33 AV33_OUT DATAI2_P
1 2 3.3V analog power input 33 MCSI_D_DN2 (40) TPS79801QDGNR SD034560380 TPS7A1601DGNR SD034150480
L33 BLM15AG121SN1D_L0402_2P DATAI2_N 36 560K_0402_1% 1.5M_0402_1%
MCSI_D_DP3 (40)
DATAI3_P
+3VS_WF
13 35 MCSI_D_DN3 (40) U28 470K U28 1.1M
VBUS_13 DATAI3_N
C185
C310
3.3V input 19 24 (40) PVT-092 TPS79801QDGNR@ R150 TPS7A1601DGNR@ R150

VBUS_19 SCL
WF_I2C_CLK
Change to short-pad R1 R1
C152
25 WF_I2C_DATA (40) SA00004OC00 TPS79801QDGNR@ SA0000CKX00 TPS7A1601DGNR@

1 1 1 SDA
4 26 1 @ 2 SD034470380 SD00001NY00
@
+1.2V_WF_VDDRX VDDRX HCLK
0_0402_5%
WF_HCLK (40) Vref=1.275 V Vref=1.193V
1 R320 470K_0402_1% 1.1M_0402_1%
RX 1.2V input
1
0.1U_0201_10V6K
2.2U_0201_6.3V6M
4.7U_0201_6.3V6M
2P_0201_25V8B
CC273
2P_0201_25V8B
CC272
23
2 2 2 +1.8V_WF_DOVDD SVIO
1.8V output to sensor Microphone 0514
C RF request C
7
GND DMIC_DATA
DMIC_CLK
47
46
PAD~D @ T74
PAD~D @ T75
2
Reserved cap
2 +3VS
(+2.8V_WF_AVDD) For Rear Camera
@RF@
@RF@
RTS5880-GR
QFN48_6X4 GPIO/SPI
39
WF_WP#
SPI-WP#/GPIO[0] WF_EEDI_MISO +2.8V_WF_AVDD
USB 41 PVT-136
USB3_PTX_DRX_P2_C SPI-MISO/GPIO[1] WF_EEDO_MOSI Change to short-pad
C363 1 2 0.1U_0201_10V6K 5 40 0514 U28 @ 28mA
1U_0201_6.3V6M
(13) USB3_PTX_DRX_P2 USB3_PTX_DRX_N2_C WF_EESK 1
C204
SSRX+ SPI-MOSI/GPIO[2] Change WF_Vendor Detect
2.2U_0201_6.3V6M
C364 1 2 0.1U_0201_10V6K 6 42 to GPIO_AL[0] 1
(13) USB3_PTX_DRX_N2 SSRX- SPI-SCK/GPIO[3] WF_EECS +2.8V_WF_AVDD_R
C352
43 8 1 R148 1 @ 2 0_0603_5%
USB3_PRX_DTX_P2_C SPI-CS#/GPIO[4] WF_VENDOR_DET_DSP IN OUT
C365 1 2 0.1U_0201_10V6K 8 48 @
(13) USB3_PRX_DTX_P2 USB3_PRX_DTX_N2_C
1
C366 1 2 0.1U_0201_10V6K 9 SSTX+ GPIO_AL[0] 1 2 7 2
(13) USB3_PRX_DTX_N2 WF_SENSOR_RST# (40) 1
SSTX- SSOR_RST/GPIO_AL[1] 2 2 NC1 SENSE/FB R144
17 GPIO_AL[2] 44 PAD~D @ T4 6 3 560K_0402_1% @ C206
C1
T1 @ PAD~D
@ PAD~D 18 DM GPIO[15] 45
PAD~D @ T6
WF_LED (42)
NC2 NC3 R2 100P_0402_50V8J
T2 DP GPIO[7]/LED/PWM WFCAM_EN WFCAM_EN 2
1 2 11 22 1 @ 2 5 4
2
RREF GPIO[10]/SVA_CTL 3 EN GND
R134 6.2K_0402_1% R137 0_0201_5%
TP
PAD~D @ T5
1
Please Close to IC GPIO_DELINK/SPI_CS#2 +2.8V_WF_AVDD +2.8V_WF_AVDD
1
+1.2V_WF_USB3_AV12 +1.2V_WF_VDDRX 0513 System 37 R14 TPS79801QDGNRQ1_MSOP8
WF_XTLI PAD~D @ T42
9
Change to 1% resistor
14 NC PVT-014 @
WF_XTLO XTLI 10K_0402_5%
15 49 Change to short-pad @
47P_0201_25V8J
R150
1 2 XTLO GND_PAD 470K_0402_1%
R1
2.2U_0201_6.3V6M
1 1
2.2U_0201_6.3V6M
L23 BLM15AG121SN1D_L0402_2P
RTS5880-GR_QFN48_6X6 1 @RF@
C353
C193
C195
WF_XTLO
WF_XTLI
C188
C143
C173
C146
Output current 50mA @

2 2
1 1 1 1 Enable pin VIH 1.5V
2
VOUT = 1.275 V (1 + R2 / R1) + IFB* R2

0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
1U_0201_6.3V6M
2 2 2 2
VFB = 1.275 V
R306 R307
0_0201_5% 1K_0201_1%
B 2 4 B
2
GND GND
1 3
1 3
+1.2V_WF_USB2_AV12 +1.8V_WF_DOVDD
Y1
12MHZ_20PF_7V12000002
1 2
(+1.2V_WF_DVDD) For Rear Camera +1.2V_WF_DVDD
R235 220K_0402_1% +3VS
1
C165 C168 PVT-135

33P_0402_50V8J 33P_0402_50V8J Change to short-pad
95mA
C189
C151
C156
+1.2V_WF_DVDD_R
C163
1 1 1 1
R135 1 @ 2 0_0603_5%
2.2U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1
C350
C196
C194
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
2.2U_0201_6.3V6M
2 2 2 2 @
U27 1 +1.2V_WF_DVDD +1.2V_WF_DVDD
1
2 2 2
100P_0402_50V8J
C345
1 5 R138 @
VIN VOUT 11K_0402_1%
R1 2
2
+3VS_WF +3.3V_UF_D3V3 GND
2
WFCAM_EN
1 @ 2 3 4
47P_0201_25V8J
EN SNS 1
R131 0_0201_5% @RF@
2.2U_0201_6.3V6M
1
2.2U_0201_6.3V6M
0515
R138 11K_0201_1% 1
C351
C180
C177
PVT-013 1 C3 RT9078N-08GJ5_TSOT23-5 materail prepare issue R274
2
+1.2V_WF_DV12S +1.2V_WF_DV12S Change to short-pad 2.2U_0201_6.3V6M Change to 11K_0402_1% 20K_0201_1% @ 2

R2 2
R322 R323
100K_0402_5%~D 100K_0402_5%~D 2
2
2
@ Output current 300mA
0516 Enable pin VIH 0.9V
1
A Due to sensor vendor detect GPIO is 1.8V A

Add level shift for vendor detect.
WF_VENDOR_DET_DSP
C153
C142
C145
C144
1 1 1 1
UF_VENDOR_DET_DSP (41)
VFB=0.8V
VOUT=VFB(1+R1/R2)
1
1.8V D 1.8V D
=0.8*1.55=1.24V
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
1U_0201_6.3V6M
2 2
2 2 2 2 (40) WF_Vendor Detect (42) UF_Vendor Detect
LN2316ELT1G_SOT23-3
QZ5
LN2316ELT1G_SOT23-3
QZ6
G G
S S
3
Lite-on Detect(Pull Low) VGS 0.9V VGS 0.9V

Chicony Detect(Pull High)
P039 - WF RTS5880
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
MCSI_D_DN1_R
MCSI_D_DP1_R
MCSI_D_DN0_R
MCSI_D_DP0_R
Bypass cap close to CONN
+2.8V_VCM_OUT +1.8V_WF_DOVDD +2.8V_WF_AVDD +2.8V_WF_AVDD +1.2V_WF_DVDD MCSI_D_CLKN_R
MCSI_D_CLKP_R
MCSI_D_DN2_R
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2.2U_0201_6.3V6M
MCSI_D_DP2_R
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
C30
1 1 1 1 1 MCSI_D_DN3_R
1
C119
C123
C121
C122
C31
C29
C32
D D
MCSI_D_DP3_R
2
2 2 2 2 2
AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
1
1
+1.8V_WF_DOVDD
D5
D7
D11
D12
D6
D8
D14
D13
D10
D9
WF_SENSOR_RST#
RC650 1 2 4.7K_0201_5%
WF_I2C_DATA
RC70 2 1 1.5K_0402_5%
2
WF_I2C_CLK
RC69 2 1 1.5K_0402_5%
0515
Change camera CONN pin define
and sw ap common coke signal
PVT-128
Remove co-lay and change to short-pad
8M Rear Camera (WF) Microphone select
This pin is internally pulled low in module
Pull Lo: Left channel
Lite-on Detect(Pull Low) Pull Hi: Right channel
Chicony Detect(Pull High) JWFC1
R95 1 @ 2 0_0201_5%
(39) WF_Vendor Detect 1 2 PVT-093
2 1 3 1 2 4 2 1 0_0402_5% Change to short-pad
R55 @ 0_0402_5% LRSEL3
+DVDD_R236
R238 @ +DVDD
5 3 4 6 2 1 0_0402_5%
R236 @ +DVDD
PVT-017 PVT-094
7 5 6 8 Change to short-pad Change to short-pad
MCSI_D_CLKN_R (39) WF_HCLK 7 8 DMIC_CLK34_C DMIC_CLK34_R
MCSI_D_CLKN (39) 9 10 2 @ 1 1 @ 2
C
MCSI_D_CLKP_R
MCSI_D_DN3_R
MCSI_D_DP3_R
11
13
9
11
13
10
12
14
12
14
DMIC_DATA34_C
RA129 1
RA130
2 0_0201_5%
33_0201_5%
DMIC_DATA34_R
1
RA126
RA127
@ 20_0402_5%
0_0402_5%
DMIC_CLK34
DMIC_DATA34
(56)
(56) DMIC C
MCSI_D_CLKP (39) 15 16 From LDO 95mA

15 16 +1.2V_WF_DVDD
17 18 1 @ 2
MCSI_D_DN1_R 17 18 PCH_DMIC_CLK1 (10)
19 20 RA125 1 @ 2 0_0402_5%
MCSI_D_DP1_R 19 20 PCH_DMIC_DATA1 (10)
R54 2 @ 1 0_0402_5% 21 22 From LDO 28mA PVT-016 RA128 0_0402_5%
21 22 +2.8V_WF_AVDD Change to short-pad
23 24
MCSI_D_CLKN_R 23 24 WF_I2C_CLK_R WF_I2C_CLK
25 26 0_0201_5% 1 @ 2 R97 Intel DMIC
MCSI_D_CLKP_R 25 26 WF_I2C_DATA_R WF_I2C_DATA WF_I2C_CLK (39)
27 28 2 @ 1
29 27 28 30 0_0201_5% R96
WF_I2C_DATA (39) for WOV reserved
MCSI_D_DN0_R 29 30
R34 2 @ 1 0_0402_5% 31 32 From DSP 2.7mA
MCSI_D_DP0_R 31 32 WF_SENSOR_RST# +1.8V_WF_DOVDD
33 34
33 34 WF_SENSOR_RST# (39)
35 36
MCSI_D_DN0_R MCSI_D_DN2_R 35 36
MCSI_D_DN0 (39) 37 38 From LDO 100mA
MCSI_D_DP2_R 37 38 +2.8V_VCM_OUT
39 40
41 39 40 42
MCSI_D_DP0_R 41 42
MCSI_D_DP0 (39)
43 44
45 Power Power 46
Power Power
R31 2 @ 1 0_0402_5%
47 48
49 GND GND 50
51 GND GND 52
53 GND GND 54
2 1 55 GND GND 56
R37 @ 0_0402_5%
57 GND GND 58
59 GND GND 60
MCSI_D_DN1_R GND GND
MCSI_D_DN1 (39) 61 62
GND GND
63 64
B MCSI_D_DP1_R PTH PTH B
MCSI_D_DP1 (39) 65 66
67 PTH PTH 68
PTH PTH
R36 2 @ 1 0_0402_5%
I-PEX_20698-042E-01
CONN@
R35 2 @ 1 0_0402_5%
MCSI_D_DN2_R
MCSI_D_DN2 (39)
MCSI_D_DP2_R
MCSI_D_DP2 (39)
R32 2 @ 1 0_0402_5%
R51 2 @ 1 0_0402_5%
MCSI_D_DN3_R
MCSI_D_DN3 (39)
MCSI_D_DP3_R
MCSI_D_DP3 (39)
A A
R39 2 @ 1 0_0402_5%

P040 - WF Sensor CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Date: Thursday, January 31, 2019 Sheet 40 of 100
5 4 3 2 1
5 4 3 2 1
560K 1.5M
R101 R101
+3VS +3VS_UF LDO IC R2 TPS79801QDGNR@ LDO IC R2 TPS7A1601DGNR@
PVT-154 SD034560380 SD034150480
TPS79801QDGNR TPS7A1601DGNR
(+2.8V_UF_AVDD) For Front Camera
Change to short-pad 560K_0402_1% 1.5M_0402_1%
1 @ 2 U16 470K U16 1.1M
R94 0_0603_5% TPS79801QDGNR@ R93 TPS7A1601DGNR@ R93
SA00004OC00 R1 TPS79801QDGNR@ SA0000CKX00 R1 TPS7A1601DGNR@
C111
C103
SD034470380 SD00001NY00
Vref=1.275 V 470K_0402_1%
Vref=1.193V 1.1M_0402_1% +3VS
1 1
0.1U_0201_10V6K
4.7U_0201_6.3V6M
+3.3V_UF_D3V3
2 2 PVT-137
2.2U_0201_6.3V6M
47P_0201_25V8J
R105 1 2 100K_0402_5%~D Change to short-pad +2.8V_UF_AVDD
1
C354
1 U16 @ 20m A
UF_EECS U20 @ @RF@ +2.8V_UF_AVDD_R
UF_EEDI_MISO 1 8 C125 8 1 R102 1 @ 2 0_0603_5%
R107 2 CS# VCC 7 2 IN OUT
UF_WP# DO(IO1)HOLD#(IO3) UF_EESK
1
D 2 1 3 6 +2.8V_UF_SVA 2 7 2 D
WP#(IO2) CLK UF_EEDO_MOSI 1 NC1 SENSE/FB 1
+3VS_UF PVT-140 +3.3V_UF_D3V3 4 5 C120 R101
Change to short-pad GND DI(IO0) 6 3 560K_0402_1% @ C126 C1
10K_0402_5% W25X10CLSNIG_SO8 0.1U_0201_10V6K
NC2 NC3 R2 100P_0402_50V8J
R280 1 @ 2 0_0603_5% 2 1 @ 2 5 4 2
(SO-8)
2
RC132 EN GND
0_0201_5%
TP
1
1
C112
C105
C311
PVT-018 R2 TPS79801QDGNRQ1_MSOP8
9
U17 Change to short-pad @ +2.8V_UF_AVDD +2.8V_UF_AVDD
1 1 1 10K_0402_5%
R93 @
@ Power CMOS Interface 470K_0402_1% R1
2.2U_0201_6.3V6M
0.1U_0201_10V6K
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
47P_0201_25V8J
8 37
+3VS_UF
2
2 2 2 3.3V input 7 VBUS PIXDIN[9] 36 Output current 50mA
+3.3V_UF_D3V3 D3V3 PIXDIN[8] 1 1
C115
2.2U_0201_6.3V6M
3.3V input to RTS5876 23 35 Enable pin VIH 1.5V 1 @RF@
+2.8V_UF_SVA SVA PIXDIN[7]
C355
2.8V output for analog power 34 C135
2 PIXDIN[6] 32 @
+1.2V_UF_DV12S MCSI_H_DP0 (42)
1.2V output for core power 16 DV12S PIXDIN[5]/DATAI0_P 31 2 2
+1.2V_UF_DV12S
33 DV12S PIXDIN[4]/DATAI0_N 29
MCSI_H_DN0
MCSI_H_CLKP
(42)
(42)
VOUT = 1.275 V (1 + R2 / R1) + IFB* R2 2
+1.2V_UF_DV12S DV12S PIXDIN[3]/CLKI_P
+1.8V_UF_VDDIO
1.8V output for sensor IO power
18
SVIO PIXDIN[2]/CLKI_N
28
26
MCSI_H_CLKN (42) VFB = 1.275 V
PIXDIN[1]/DATAI1_P MCSI_H_DP1 (42)
25 MCSI_H_DN1 (42)
+2.8V_UF_SVA +1.8V_UF_VDDIO PIXDIN[0]/DATAI1_N 22
SSOR_VSYNC 38
USB
4 SSOR_HSYNC 21
(13) USB20_P6 DP SSOR_PIXCLK UF_I2C_CLK
3 40 UF_I2C_DATA
(13) USB20_N6 DM SCK UF_I2C_CLK (42)
5 41
RREF SDA UF_I2C_DATA (42)
RTS5876-GR SSOR_CLK
19 1 @ 2 UF_HCLK (42)
(+1.2V_UF_DVDD) For Front Camera
C107
C106
C113
C141
R321 0_0402_5%
1 1 1 1 1 2 QFN46_6P5X4P5 1 1 PVT-095
2P_0201_25V8B
CC276
2P_0201_25V8B
C108
RR1 6.2K_0402_1% Microphone Change to short-pad
Please Close to IC 43 0514
DMIC_DATA PAD~D @ T44 RF request
0.1U_0201_10V6K
2.2U_0201_6.3V6M
0.1U_0201_10V6K
2.2U_0201_6.3V6M
0513 System 42 Reserv ed cap

2 2 2 2 Change to 1% resistor UF_RST#
45 DMIC_CLK PAD~D @ T45 2 2 +3VS PVT-139 +1.2V_UF_DVDD
RESET# Change to short-pad
@RF@
@RF@
2 1 9 54m A
R103 10K_0402_5% MAIN_POWB# GPIO/SPI UF_WP#
14 UF_EEDI_MISO +1.2V_UF_DVDD_R
SPI-WP#/GPIO[0] 12 R110 1 2 0_0603_5% +1.2V_UF_DVDD +1.2V_UF_DVDD
UF_EEDO_MOSI @
+3.3V_UF_D3V3 SPI-MISO/GPIO[1] 13
SPI-MOSI/GPIO[2] UF_EESK
2.2U_0201_6.3V6M
11 UF_EECS 1 1 1
SPI-SCK/GPIO[3]
1U_0201_6.3V6M
1U_0201_6.3V6M
C356
C162
C147
10 UF_DVDD_EN
SPI-CS#/GPIO[4]
1
17 @
GPIO[8]
47P_0201_25V8J
R98 15 U21
C GPIO[9] PAD~D @ T43 1 C
1
2 2 2
100P_0402_50V8J
C346
+1.2V_UF_DV12S +1.2V_UF_DV12S +1.2V_UF_DV12S @ 100K_0402_5%~D 24 UF_LED (42)
LED/GPIO[7] 1 1
2.2U_0201_6.3V6M
46 UF_SENSOR_RST# (42) 1 5 R294 @ 1 @RF@
SSOR-RST#/GPIO_AL1 VIN VOUT
C357
C161
2.2U_0201_6.3V6M
1 11K_0402_1% C157
UF_RST# SSOR_PWDN UF_VENDOR_DET_DSP (39) R1
2
20 GPIO_AL0 44 2 2 @
27 DGND GPIO_DLK GND 2 2
UF_DVDD_EN
2
30 DGND 6 1 @ 2 3 4 2
1 DGND AGND EN SNS
C109
C104
C370
C118
C116
C371
C117
C114
C372
C110 39 47 RC157 0_0201_5%
1
@ DGND GND_PAD +1.8V_UF_VDDIO PVT-021 0515
1 1 1 1 1 1 1 1 1 Change to short-pad R294 11K_0201_1%
0.1U_0201_10V6K RTS5876-GR_QFN46 1 C1 RT9078N-08GJ5_TSOT23-5 materail prepare issue R295
2 2.2U_0201_6.3V6M Change to 11K_0402_1% 20K_0201_1%
SSOR_PWDN R2
0.1U_0201_10V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
RT115 1 2 4.7K_0201_5% Output current 300mA

2 2 2 2 2 2 2 2 2 Enable pin VIH 0.9V
2
2
@
VFB=0.8V
VOUT=VFB(1+R1/R2)
=0.8*1.55=1.24V
560K 1.5M
R100 R100
LDO IC R2 TPS79801QDGNR@ LDO IC R2 TPS7A1601DGNR@
TPS79801QDGNR
U18
TPS79801QDGNR@
470K
SD034560380
560K_0402_1%
R106
TPS7A1601DGNR
U18
TPS7A1601DGNR@
1.1M
SD034150480
1.5M_0402_1%
R106
+3VS
(+2.8V_IR_AVDD) For IR Camera

SA00004OC00 R1 TPS79801QDGNR@ SA0000CKX00 R1 TPS7A1601DGNR@
2.2U_0201_6.3V6M
47P_0201_25V8J
SD034470380 SD00001NY00
Vref=1.275 V Vref=1.193V 1
C358
470K_0402_1% 1.1M_0402_1% PVT-149 +2.8V_IR_AVDD
1
@ @RF@ U18 @ Change to short-pad 35m A +2.8V_IR_AVDD +2.8V_IR_AVDD
+3.3V_IR_D3V3 C134 +2.8V_IR_AVDD_R
2
47P_0201_25V8J
8 1 R99 1 @ 2 0_0603_5%
R117 1 2 100K_0402_5%~D 2 IN OUT
1
1
+2.8V_IR_SVA 7 2 1 1 @RF@
NC1 SENSE/FB
2.2U_0201_6.3V6M
U24
2.2U_0201_6.3V6M
IR_EECS R100 1 C133
C359
C129
1 8 6 3 560K_0402_1% @ C124
R118 IR_EEDI_MISO
IR_WP# 2 CS# VCC 7 IR_EESK
NC2 NC3 R2 100P_0402_50V8J @ 2
2 1 3 SO/SIO1 HOLD# 6 1 2 5 4 2 2
IR_EEDO_MOSI 1 @
2
4 WP# SCLK 5 C130 RC137 EN GND 2
0_0201_5%
TP
GND SI/SIO0
B B
1
10K_0402_5% 0.1U_0201_10V6K PVT-019 TPS79801QDGNRQ1_MSOP8
MX25V2006EM1I-13G_SO8
9
1
+3VS PVT-155 +3.3V_IR_D3V3 2 Change to short-pad
Change to short-pad
(SO-8) @
R1
10K_0402_5%
R106
470K_0402_1%
@
R1
1 @ 2
2
R112 0_0603_5% Output current 50mA
2
Enable pin VIH 1.5V
C140
C136
C312
1 1 1 U1
@ Power CMOS Interface
VOUT = 1.275 V (1 + R2 / R1) + IFB* R2
0.1U_0201_10V6K
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
2 2 2 26 PIXDIN[0]/DATAI1_N
28
29
VFB = 1.275 V
+2.8V_IR_SVA SVA PIXDIN[1]/DATAI1_P
12 30 MCSI_E_CLKN (42)
+1.0V_IR_DV10S DV10S PIXDIN[2]/CLKI_N
16 31 MCSI_E_CLKP (42)
+3.3V_IR_D3V3 D3V3 PIXDIN[3]/CLKI_P
22 32 MCSI_E_DN0 (42)
+1.8V_IR_VDDIO SVIO PIXDIN[4]/DATAI0_N
17 1 MCSI_E_DP0 (42)
NC PIXDIN[5]/DATAI0_P 2
PIXDIN[6]
+1.0V_IR_DV10S +1.8V_IR_VDDIO +2.8V_IR_SVA

33
DGND PIXDIN[7]
PIXDIN[8]
PIXDIN[9]
3
4
5 (+1.2V_IR_DVDD) For IR Camera +1.2V_IR_DVDD
6 +3VS PVT-138
SSOR_HSYNC PAD~D @ T46 Change to short-pad
7
SCL IR_I2C_CLK (42)
8 21m A
SDA IR_I2C_DATA (42)
RTS5849-GR 25 PVT-096
+1.2V_IR_DVDD_R
R108 1 @ 2 0_0603_5%
QFN32_3X6 SSOR-VSYNC PAD~D @ T47 Change to short-pad
C131
C127
C159
C132
C128
24
SSOR-PIXCLK IR_HCLK_R PAD~D @ T48
C160
2.2U_0201_6.3V6M
1 1 1 1 1 1 13 23 1 @ 2 IR_HCLK (42) 1 1 1
(13) USB20_N5 DM SSOR-HCLK
1U_0201_6.3V6M
1U_0201_6.3V6M
C360
C137
C138
(13) USB20_P5
14 RC156 0_0402_5%
DP @
1 1
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
2.2U_0201_6.3V6M
0.1U_0201_10V6K
2.2U_0201_6.3V6M
2P_0201_25V8B
CC277
2P_0201_25V8B
C16
15 U19 1 +1.2V_IR_DVDD +1.2V_IR_DVDD
1
2 2 2 2 2 2 RREF 2 2 2
100P_0402_50V8J
C347
GPIO/SPI 0514
IR_WP# RF request
11 Reserv ed cap 1 5 R104 @
SPI-WP/GPIO_AL[0] 10 2 2 +2.8V_IR_SVA VIN VOUT 11K_0402_1%
GPIO_AL[1]/SSOR_RST# IR_LED_EN IRCAM_RESET# (42) R1 2
@RF@
@RF@
1 2 9 IR_LED_EN (95) 2
GPIO[11]/PWM GND
47P_0201_25V8J
RR2 6.2K_0402_1% 27 IR_EEDO_MOSI IR_SYS_LED (42)
2
GPIO7/LED 21 1 2 3 4
IR_EEDI_MISO @ 1
SPI-MOSI/GPIO[2] EN SNS
C155
0513 20 IR_EESK RC147 0_0201_5% 1 @RF@
1
SPI-MISO/GPIO[1]
2.2U_0201_6.3V6M
19 IR_EECS PVT-020 0515
1 C139
SPI-SCK/GPIO[3] R104 11K_0201_1%
C361
18 Change to short-pad
SPI-CS#/GPIO[4] 1 C2 RT9078N-08GJ5_TSOT23-5 materail prepare issue R296
2
2.2U_0201_6.3V6M
A 2.2U_0201_6.3V6M Change to 11K_0402_1% 20K_0201_1% @ A
R2 2
Output current 300mA
Enable pin VIH 0.9V 2
2
RTS5849-GR_QFN32_3X6 2
@
VFB=0.8V
VOUT=VFB(1+R1/R2)
=0.8*1.55=1.24V

P041 - UF RTS5876, IR RTS5849
5 4 3 2 1
5 4 3 2 1

MCSI_E_DP0_R UF_SENSOR_RST#
+5VS +3VS +2.8V_IR_AVDD +2.8V_IR_AVDD +1.2V_IR_DVDD MCSI_E_DN0_R UF_I2C_CLK_R
UF_I2C_DATA_R
MCSI_E_CLKP_R
MCSI_E_CLKN_R MCSI_H_DP1_R
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2.2U_0201_6.3V6M
MCSI_H_DN1_R
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 IR_I2C_DATA_R
C22
1 1 1 1 IR_I2C_CLK_R MCSI_H_CLKP_R
C101
C97
C98
C27
C25
C102
CS11
MCSI_H_CLKN_R
1U_0201_6.3V6K IRCAM_RESET#
2
MCSI_H_DP0_R
2
D 2 2 2 2 D
MCSI_H_DN0_R
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
1
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
D87
D88
D89
D90
D91
D92
D93
1
D48
D44
D47
D43
D49
D51
D50
D45
D46
2
+2.8V_UF_AVDD +2.8V_UF_AVDD +1.2V_UF_DVDD +1.8V_UF_VDDIO
2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2.2U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
C21
1 1 1 1
1
C100
C96
C99
C24
C26
C23
+1.8V_UF_VDDIO
5M Front Camera (UF) IR Camera

2
2 2 2 2 0515
UF_SENSOR_RST# Change camera CONN pin define
RT10 1 2 4.7K_0201_5% and sw ap common coke signal
UF_I2C_CLK
RC68 2 1 1.5K_0402_5% UF_I2C_DATA
RC65 2 1 1.5K_0402_5% PVT-023
JUFC1 Change to short-pad
PVT-022 Lite-on Detect(Pull Low)
Change to short-pad 1 2 Chicony Detect(Pull High)
1 2 ALS_3V UF_Vendor Detect (39)
3 4 RS20 1 @ 2 0_0201_5%
CAM_LED# +5VS CAM_LED#R 3 4 ISH_I2C1_SDA_R ISH_I2C1_SDA +3VS +1.8V_IR_VDDIO
PVT-097 R92 1 @ 2 0_0201_5% 5 6 RS28 1 @ 2 0_0201_5%
C Remove co-lay and change to short-pad
(41)
(41)
UF_SENSOR_RST#
UF_I2C_DATA
RS27 1 @ 2 0_0201_5%
UF_SENSOR_RST#
UF_I2C_DATA_R
UF_I2C_CLK_R
7
9
5
7
6
8
8
10
ISH_I2C1_SCL_R
ISH_ALS_INT#_R
IR_I2C_CLK_R
RS24
RS23
1
1
@
@
2
2
0_0201_5%
0_0201_5%
ISH_I2C1_SCL
ISH_ALS_INT#
IR_I2C_CLK
ISH_I2C1_SDA
ISH_I2C1_SCL
(12)
(12) ALS RT11 1 2 4.7K_0201_5%
IRCAM_RESET#
IR_I2C_CLK
C
9 10 ISH_ALS_INT# (12)
R46 2 @ 1 0_0402_5% RS25 1 @ 2 0_0201_5% 11 12 RS26 1 @ 2 0_0201_5% RC67 2 1 1.5K_0402_5%
(41) UF_I2C_CLK 11 12 IR_I2C_DATA_R IR_I2C_DATA IR_I2C_CLK (41) IR_I2C_DATA
From DSP 2.3mA 13 14 RS21 1 @ 2 0_0201_5% RC66 2 1 1.5K_0402_5%
+1.8V_UF_VDDIO 13 14 IRCAM_RESET# IR_I2C_DATA (41)
From discrete LDO 40mA 15 16
MCSI_H_CLKN_R +1.2V_UF_DVDD 15 16 IRCAM_RESET# (41)
17 18
MCSI_H_CLKN (41)
17 18 +1.2V_IR_DVDD From discrete LDO 21mA
From discrete LDO 15.5mA 19 20 +2.8V_IR_AVDD From discrete LDO 22mA
+2.8V_UF_AVDD 19 20
21 22
MCSI_H_CLKP_R 21 22 IR_CAM_DET# (12)
MCSI_H_CLKP (41) 23 24 From DSP 2.5mA
(41) UF_HCLK 23 24 +1.8V_IR_VDDIO
25 26 IR Camera (Pull Low)
MCSI_H_DP0_R 25 26 W/O IR Camera (Pull High)
27 28
MCSI_H_DN0_R 27 28 MCSI_E_CLKN_R +3VS
R47 2 @ 1 0_0402_5% 29 30
29 30 MCSI_E_CLKP_R
31 32 Camera module has ALS I2C pull H
MCSI_H_CLKP_R 31 32
33 34
MCSI_H_CLKN_R 33 34 MCSI_E_DN0_R ISH_I2C1_SCL
35 36 RC647 1 @ 2 1K_0402_5%
35 36 MCSI_E_DP0_R ISH_I2C1_SDA
37 38 PVT-024 RC648 1 @ 2 1K_0402_5%
MCSI_H_DP1_R 37 38 Change to short-pad
R49 2 @ 1 0_0402_5% 39 40
MCSI_H_DN1_R 39 40
41 42 RS22 1 @ 2 0_0201_5%
41 42 IR_HCLK (41)
MCSI_H_DN0_R IR_LED+_R237
1 @ 2 43 44
MCSI_H_DN0 (41) IR_LED+
R237 0_0603_5% 45 Power Power
Power Power
46
IR_LED-
1A
MCSI_H_DP0_R
MCSI_H_DP0 (41) PVT-141
Change to short-pad 1A 47
49 GND GND
48
50
51 GND GND 52
2 1 0_0402_5% 53 GND GND 54
R48 @
55 GND GND 56
57 GND GND 58
59 GND GND 60
GND GND
61 62
B R41 2 @ 1 0_0402_5% GND GND B
63 64
65 PTH PTH 66
MCSI_H_DN1_R PTH PTH
MCSI_H_DN1 (41) 67 68
PTH PTH
MCSI_H_DP1_R
MCSI_H_DP1 (41) I-PEX_20698-042E-01
CONN@
R40 2 @ 1 0_0402_5%
R42 2 @ 1 0_0402_5%
System LED
+5VS
MCSI_E_CLKN_R
MCSI_E_CLKN (41)
Camera module side
1
R234
System LED
MCSI_E_CLKP_R
MCSI_E_CLKP (41) 100K_0402_5%~D
Policy about LED control solution
Reserved HW power on/off control
R43 2 @ 1 0_0402_5% 2
CAM_LED#
1 @ 2
+1.8V_IR_VDDIO
RS40 1 @ 2 0_0201_5%
+1.8V_UF_VDDIO
RS41 1 @ 2 0_0201_5%
+1.8V_WF_DOVDD
1
RS42 0_0201_5% D VGS 0.9V

VF=0.28
R44 2 @ 1 0_0402_5% 1 @ 2 2 1 2 Q5
A (39) WF_LED A
RS37 0_0201_5% D17 G LN2316ELT1G_SOT23-3
MCSI_E_DN0_R
RB751S40T1G_SOD523-2 S
3
1
MCSI_E_DN0 (41) 1 @ 2 2 1
(41) UF_LED
100K_0402_5%~D
R310
RS38 0_0201_5% D16

MCSI_E_DP0_R
MCSI_E_DP0 (41) 1 @ 2 2 1
(41) IR_SYS_LED
RS39 0_0201_5% D3
2
R45 2 @ 1 0_0402_5% 2018/05/08 2018/05/08 Title
PVT-025 R3401 2 1K_0201_5%
Change to short-pad R3411 @ 2 1K_0201_5%
P042 - UF/IR Sensor CONN
R3421 @ 2 1K_0201_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
+3.3V_LDO_PD1 +5VALW +VBUS1_PD_20V
+3VALW_PD1 +3VALW_PD1 +BMC_LDO_PD1 +1.8VA_LDO_PD1 +1.8VD_LDO_PD1 +3.3V_VOUT_PD1 +3.3V_LDO_PD1

I2C1_DAT_PD1
@ RT20 1 2 10K_0402_5%
I2C1_CLK_PD1
@ RT30 1 2 10K_0402_5%
I2C1_INT#_PD1
@ RT21 1 2 10K_0402_5% @ @
1 1 1 1 1 1 1 1 1 1 1
1
CT11 CT9 CT4 CT2 CT6
I2C2_DAT_PD1
@ RT29 1 2 10K_0402_5% CT13 CT12 10U_0402_6.3V6M 10U_0402_6.3V6M CT108 CT10 CT5 CT106 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M CT1 CT3
I2C2_CLK_PD1
@ RT27 1 2 10K_0402_5% 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 1U_0402_25V6K 1U_0402_25V6K 10U_0402_6.3V6M 1U_0201_6.3V6K 1U_0201_6.3V6K 10U_0402_6.3V6M
I2C2_INT#_PD1
2
@ RT31 1 2 10K_0402_5% 2 2 2 2 2 2 2 2 2 2 2
PD1_DEBUG1
@ RT23 1 2 4.7K_0201_5%
PD1_DEBUG2
@ RT15 1 2 4.7K_0201_5%
D D
PD1_DEBUG_CTL1
RT13 1 2 4.7K_0201_5%
PD1_DEBUG_CTL2 +3VALW_PD1
RT135 1 2 4.7K_0201_5%
+3.3V_VDD_PIC PVT-0 9 8
Change to short-pad
RT8 1 @ 2 0_0402_5%
PVT-1 5 0 UT1
+3VALW Change to short-pad
+3.3V_LDO_PD1 1 @ 2 A6 B10
RT34 0_0603_5% A7 PP_HV SENSEP A10
RT17 1 @ 2 0_0402_5% A8 PP_HV SENSEN
PD_EE_CS# PP_HV
RT129 1 2 4.7K_0201_5% B7
PD_EE_MISO +3.3V_LDO_PD1 PP_HV
RT127 1 2 4.7K_0201_5% B9
PD_HOLD# HV_GATE1 +VBUS1_PD_20V
RT118 1 2 4.7K_0201_5% +5VALW A11 A9
PD_EE_WP# PP_5V0 HV_GATE2
RT12 1 2 4.7K_0201_5% C11
TBT_A_AUX_N PP_5V0
R215 1 2 100K_0201_5% RT18 1 @ 2 0_0402_5% B11
TBT_A_AUX_P PP_5V0
R219 1 2 100K_0201_5% D11 H11
PP_5V0 VBUS J10
H10 VBUS J11
1
PP_CABLE VBUS
BAT54LPS-7
K11 1
VBUS
D22
+3VALW_PD1 B1
VDDIO C51
H1 H2 1U_0402_25V6K
VIN_3V3 VOUT_3V3 +3.3V_VOUT_PD1 2
G1 +3.3V_LDO_PD1
2
LDO_3V3 K1
TBT_I2C_DATA I2C1_DAT_PD1 LDO_1V8A +1.8VA_LDO_PD1
(45,47) TBT_I2C_DATA RT134 1 2 0_0201_5% D1 A2 +1.8VD_LDO_PD1 EMC@
TBT_I2C_CLK I2C1_CLK_PD1 I2C_SDA1 LDO_1V8D
RT123 1 2 0_0201_5% D2 E1
(45,47) TBT_I2C_CLK TBT_A_I2C_INT# I2C1_INT#_PD1 I2C_SCL1 LDO_BMC +BMC_LDO_PD1
RT22 1 2 0_0201_5% C1
(47) TBT_A_I2C_INT# I2C_IRQ1_N
UPD1_SMBDAT I2C2_DAT_PD1
RT130 1 @ 2 0_0201_5% A5
(58) UPD1_SMBDAT UPD1_SMBCLK I2C2_CLK_PD1 I2C_SDA2
RT131 1 @ 2 0_0201_5% B5
(58) UPD1_SMBCLK I2C2_INT#_PD1 I2C_SCL2 PD1_CC1
RT132 1 @ 2 0_0201_5% B6 L9 RT136 1 2 0_0402_5%
(58) UPD1_SMBINT# I2C_IRQ2_N C_CC1 PD1_CC2 USBC1_CC1 (44)
L10 RT33 1 2 0_0402_5%
C_CC2 USBC1_CC2 (44)
PVT-0 2 7
Change to short-pad PD_EE_CLK
A3 K9 CT109 1 2 220P_0201_25V7K
PD_EE_MOSI
B4 SPI_CLK RPD_G1 K10 CT8 1 2 220P_0201_25V7K
Dead batery support
PD_EE_MISO SPI_MOSI RPD_G2
C A4 C
TC12 PD_EE_CS# SPI_MISO
TC11 B3
PVT-0 2 6 SPI_SS_N K6
Change to short-pad C_USB_TP USBC1_TP1_L (44)
L6
USB20_P1_R_PD USB20_P1_R_PD C_USB_TN USBC1_TN1_L (44)
(13) USB20_P1 RT6 1 @ 2 0_0201_5% L5
USB20_N1_R_PD USB20_N1_R_PD USB_RP_P
RT5 1 @ 2 0_0201_5% K5
(13) USB20_N1 USB_RP_N K7
USB20_P1_R_PD C_USB_BP USBC1_BP2_L (44)
(47) TBT_A_USB2_D_P RT126 1 @ 2 0_0201_5% L7
USB20_N1_R_PD TBT_A_AUX_P C_USB_BN USBC1_BN2_L (44)
(47) TBT_A_USB2_D_N RT125 1 @ 2 0_0201_5% (47) TBT_A_AUX_P J1
TBT_A_AUX_N AUX_P
(47) TBT_A_AUX_N J2
AUX_N K8
C_SBU1 USBC1_SBU1 (44)
L8
TC9 G4 PVT-1 0 0
F4 SWD_CLK Change to short-pad
TC10 SWD_DATA PD1_GPIO0
B2
UART_MISO GPIO0 PD1_GPIO1 TC7
RT121 1 @ 2 1M_0402_5% C2 RT16 1 @ 2 0_0402_5%
UART_MOSI GPIO1 PD1_GPIO2 EN_PD_HV1 (82,83)
RT19 1 @ 2 1M_0402_5% E2 D10 RT141 1 @ 2 0_0402_5%
(45) UART_MOSI UART_TX GPIO2 PD1_GPIO3
F2 G11 RT38 1 @ 2 0_0402_5%
(45) UART_MISO UART_RX GPIO3 PD1_GPIO4 AC1_DISC# (82,83)
0512 C10 RT140 1 @ 2 0_0402_5%
Connect pin to another TPS65982DC UART_TX to share firmw are. TBT_A_LSTX GPIO4 PD1_GPIO5 TBT_A_HPD (47,58)
L4 E10 RT39 1 @ 2 0_0402_5%
Internal 1M pull dow n (47) TBT_A_LSTX TBT_A_LSRX LSTX/R2P GPIO5 PD1_GPIO6
K4 G10 RT37 1 @ 2 0_0402_5%
(47) TBT_A_LSRX LSRX/P2R GPIO6 PD1_GPIO7
D7 RT32 1 @ 2 0_0402_5%
PD1_DEBUG_CTL1 GPIO7 PD1_GPIO8 PD1_GPIO8_EXT
E4 H6 RT28 1 @ 2 0_0402_5%
PD1_DEBUG_CTL2 DEBUG_CTL1 GPIO8 TC2
PVT-0 2 8 D5
+3.3V_LDO_PD1 +3.3V_LDO_PD1 Change to short-pad DEBUG_CTL2 PD1_GPIO5
RT36 1 @ 2 0_0402_5%
UPD1_SMBCLK PD1_DEBUG1
RT133 1 @ 2 0_0201_5% L2
UPD1_SMBDAT PD1_DEBUG2 DEBUG1
PD_EE_CS#
U10 RT119 1 @ 2 0_0201_5% K2 E11 RT138 1 2 100K_0201_5%
1 8 DEBUG2 MRESET
PD_EE_MISO CS# VCC PD_HOLD# TBT_A_LSTX PD1_DEBUG3 TBT_RESET_N_EC_PD1
2 7 1 RT124 1 @ 2 0_0201_5% L3 F11 RT142 1 @ 2 0_0402_5%
PD_EE_WP# DO(IO1) HOLD#(IO3) PD_EE_CLK TBT_A_LSRX PD1_DEBUG4 DEBUG3 RESET_N TBT_RESET_N_EC (45,47,58)
3 6 RT128 1 @ 2 0_0201_5% K3 @ RT143 1 2 0_0402_5% +3.3V_LDO_PD1
WP#(IO2) CLK PD_EE_MOSI DEBUG4
4 5 CT107 F10 @ RT139 1 2 0_0402_5%
GND DI(IO0) BUSPOWER_N +1.8VD_LDO_PD1
0.1U_0201_10V6K F1 RT144 1 @ 2 0_0402_5%
W25Q80DVSSIG_SO8 2 I2C_ADDR G2
R_OSC PVT-1 0 1
2
PVT-0 9 9 H7 Change to short-pad
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Change to short-pad SS PD1_GPIO1
0.22U_0402_16V7K
15K_0402_1%
RT14 @ RT120 1 2 1M_0201_5%
1
@ 0_0402_5% 1 PD1_GPIO2
CT7
RT122
TPS65982DCZQZR BGA 96P RT137 1 2 1M_0201_5%
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H8
L1
L11
B B
1
2
1 +3.3V_LDO_PD1
1
10K_0402_1%
RT25
RT24 @ RT35
100K_0402_5% 0_0402_5%
2
2
PD1_GPIO8_EXT
1
100K_0402_1%
RT26
2
For "-D" version only
Factory Set Device Configurations 7
Infinite boot retry from Flash to Host I/F cycles.
DIV=RT104/(RT103+RT104)
between 0.7~1.0
A A

P043 - TYPE-C_PortA_PD
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
LA-G661P 0.4
Date: Thursday, January 31, 2019 Sheet 43 of 100
5 4 3 2 1
5 4 3 2 1
D +VBUS1_PD_20V D
+VBUS1_PD_20V
AZ4A24-01F.R7G_DFN0603P2Y2
10U_0603_25V6M
0.1U_0402_25V6
D75
D86
1 1 EMC@ EMC@
1
CT41
C64
2 2
+VBUS1_PD_20V +VBUS1_PD_20V
2
CONN@
JUSBC1
A1 B12
GND GND
TBT_A_TTX_C_DRX_P1 TBT_A_TRX_DTX_P1
TBT_A_TTX_C_DRX_N1 A2 B11 TBT_A_TRX_DTX_N1
(47) TBT_A_TTX_C_DRX_P1 SSTXP1 SSRXP1 TBT_A_TRX_DTX_P1 (47)
A3 B10
(47) TBT_A_TTX_C_DRX_N1 SSTXN1 SSRXN1 TBT_A_TRX_DTX_N1 (47)
C280 1 2 A4 B9 2 1 C279
0.47U_0201_25V USBC1_CC1 VBUS VBUS 0.47U_0201_25V
USBC1_SBU2
A5 B8
(43) USBC1_CC1 CC1 SUB2 USBC1_SBU2 (43)
USBC1_TOP_DP1 USBC1_BOT_DN2
USBC1_TOP_DN1 A6 B7 USBC1_BOT_DP2
A7 DP1 DN2 B6
DN1 DP2
USBC1_SBU1 USBC1_CC2
Bottom
A8 B5
(43) USBC1_SBU1 SUB1 CC2 USBC1_CC2 (43)
TOP
C277 1 2 A9 B4 2 1 C278
0.47U_0201_25V TBT_A_TRX_DTX_N2 VBUS VBUS 0.47U_0201_25V
TBT_A_TTX_C_DRX_N2
TBT_A_TRX_DTX_P2 A10 B3 TBT_A_TTX_C_DRX_P2
(47) TBT_A_TRX_DTX_N2 SSRXN2 SSTXN2 TBT_A_TTX_C_DRX_N2 (47)
A11 B2
(47) TBT_A_TRX_DTX_P2 SSRXP2 SSTXP2 TBT_A_TTX_C_DRX_P2 (47)
A12 B1
GND GND
JUSBC1_GND JUSBC1_GND
1 4
GND GND
1
1 2 3
LT1 EMC@ GND GND
C C
EMC@ CT19 UPB201209T-121Y-N_2P
0.1U_0402_25V6 JAE_DX07S024XJ1R1100~D
2
2
PVT-178
Remove co-lay
TBT_A_TTX_C_DRX_P1 TBT_A_TRX_DTX_N2 ML6 EMC@ USBC1_BOT_DN2

1 2 1 2 4 3
(43) USBC1_BN2_L
D67 D32
USBC1_BOT_DP2
1 2
AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2 (43) USBC1_BP2_L
EMC@ EMC@ MCM1012B900F06BP_4P
TBT_A_TTX_C_DRX_N1 TBT_A_TRX_DTX_P2
1 2 1 2
D68 D31
AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ EMC@
TBT_A_TRX_DTX_P1 TBT_A_TTX_C_DRX_N2
1 2 1 2
D23 D72 ML3 EMC@ USBC1_TOP_DP1
4 3
(43) USBC1_TP1_L
EMC@ EMC@
USBC1_TOP_DN1
1 2
(43) USBC1_TN1_L
TBT_A_TRX_DTX_N1 TBT_A_TTX_C_DRX_P2
1 2 1 2 MCM1012B900F06BP_4P
D27 D73
EMC@ EMC@
USBC1_CC1 USBC1_SBU2
B 1 2 1 2 B
D25 D69
EMC@ EMC@
1 2 1 2
D70 D30
EMC@ EMC@
USBC1_TOP_DN1 USBC1_BOT_DP2
1 2 1 2
D71 D28 Pin12
Pin1 USB Type-C Receptacle Interface (Front View)
EMC@ EMC@ A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
1 2 1 2
D29 D74 GND TX1+ TX1- VBUS CC1 D+ D- SBU1 VBUS RX2- RX2+ GND
EMC@ EMC@
GND RX1+ RX1- VBUS SBU2 D- D+ CC2 VBUS TX2- TX2+ GND
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
Printed Circuit Board
Pin13
Pin24
A A

P044 - TYPE-C_PortA_CONN
D a te : Tuesday, February 12, 2019 She e t 44 of 100
5 4 3 2 1
5 4 3 2 1
+5VALW
@ @ +VBUS2_PD_20V +BMC_LDO_PD2 +1.8VA_LDO_PD2 +1.8VD_LDO_PD2 +3.3V_VOUT_PD2 +3.3V_LDO_PD2

1 1
1
CT46 CT61
CT43 CT40 10U_0402_6.3V6M 10U_0402_6.3V6M
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
1 1 1 1 1 1 1
2
2 2 CT39 CT52 CT38
CT55 CT67 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M 2.2U_0201_6.3V6M CT45 CT63
1U_0402_25V6K 1U_0402_25V6K 1U_0201_6.3V6K 10U_0402_6.3V6M
2 2 2 2 2 2 2
D D
+3.3V_VDD_PIC +3VALW_PD2
@ RT7 1 2 0_0402_5%
+3VALW_PD2 +3VALW_PD2
+3VALW PVT-1 0 4
Change to short-pad
1 1
RT84 1 @ 2 0_0402_5% CT64 CT120
10U_0402_6.3V6M 1U_0201_6.3V6K
+3.3V_LDO_PD2 2 2
@ RT88 1 2 0_0402_5%
PVT-1 4 2 UT5
Change to short-pad
1 @ 2 A6 B10
RT59 0_0603_5% A7 PP_HV SENSEP A10
A8 PP_HV SENSEN
+3.3V_LDO_PD2 B7 PP_HV
PP_HV B9
A11 HV_GATE1 A9 +VBUS2_PD_20V
I2C1_DAT_PD2_C +5VALW PP_5V0 HV_GATE2
@ RT51 1 2 10K_0402_5% C11
I2C1_CLK_PD2_C PP_5V0
@ RT52 1 2 10K_0402_5% B11
I2C1_INT#_PD2_C PP_5V0
@ RT58 1 2 10K_0402_5% D11 H11
PP_5V0 VBUS J10
I2C2_DAT_PD2 VBUS
@ RT53 1 2 10K_0402_5% H10 J11
I2C2_CLK_PD2 1
1
PP_CABLE VBUS
BAT54LPS-7
@ RT92 1 2 10K_0402_5% K11
I2C2_INT#_PD2 VBUS
D26
@ RT54 1 2 10K_0402_5% +3VALW_PD2 B1 C66
VDDIO 1U_0402_25V6K
PD2_DEBUG1 2
C @ RT93 1 2 4.7K_0201_5% H1 H2 C
PD2_DEBUG2 VIN_3V3 VOUT_3V3 +3.3V_VOUT_PD2
@ RT94 1 2 4.7K_0201_5% G1 +3.3V_LDO_PD2
2
LDO_3V3 K1 EMC@
PD2_DEBUG_CTL1 TBT_I2C_DATA I2C1_DAT_PD2_C LDO_1V8A +1.8VA_LDO_PD2
RT95 1 2 4.7K_0201_5% (43,47) TBT_I2C_DATA RT77 1 2 0_0201_5% D1 A2 +1.8VD_LDO_PD2
PD2_DEBUG_CTL2 TBT_I2C_CLK I2C1_CLK_PD2_C I2C_SDA1 LDO_1V8D
RT91 1 2 4.7K_0201_5% (43,47) TBT_I2C_CLK RT56 1 2 0_0201_5% D2 E1 +BMC_LDO_PD2
TBT_B_I2C_INT# I2C1_INT#_PD2_C I2C_SCL1 LDO_BMC
RT156 1 2 0_0201_5% C1
TBT_B_AUX_N (47) TBT_B_I2C_INT# I2C_IRQ1_N
R230 1 2 100K_0201_5% TBT_B_AUX_P I2C2_DAT_PD2
R225 1 2 100K_0201_5% (58) UPD2_SMBDAT RT43 1 @ 2 0_0201_5% A5
I2C2_CLK_PD2 I2C_SDA2
(58) UPD2_SMBCLK RT44 1 @ 2 0_0201_5% B5
I2C2_INT#_PD2 I2C_SCL2 PD2_CC1
(58) UPD2_SMBINT# RT45 1 @ 2 0_0201_5% B6 L9 RT174 1 2 0_0402_5% USBC2_CC1 (46)
I2C_IRQ2_N C_CC1 PD2_CC2
PVT-0 3 0 L10 RT74 1 2 0_0402_5%
Change to short-pad C_CC2 USBC2_CC2 (46)
PD2_EE_CLK
RT50 1 2 100K_0402_5% A3 K9 CT65 1 2 220P_0201_25V7K
RT46 1 2 100K_0402_5%
PD2_EE_MOSI
B4 SPI_CLK RPD_G1 K10 CT48 1 2 220P_0201_25V7K
Dead batery support
PD2_EE_MISO SPI_MOSI RPD_G2
RT147 1 2 100K_0402_5% A4
PD2_EE_CS# SPI_MISO
PVT-0 2 9 RT96 1 2 100K_0402_5% B3
Change to short-pad SPI_SS_N K6
C_USB_TP USBC2_TP1_L (46)
L6
USB20_P2_R_PD USB20_P2_R_PD C_USB_TN USBC2_TN1_L (46)
(13) USB20_P2 RT2 1 @ 2 0_0201_5% L5
USB20_N2_R_PD USB20_N2_R_PD USB_RP_P
(13) USB20_N2 RT1 1 @ 2 0_0201_5% K5
USB_RP_N K7
USB20_P2_R_PD C_USB_BP USBC2_BP2_L (46)
RT3 1 @ 2 0_0201_5% L7
(47) TBT_B_USB2_D_P USB20_N2_R_PD TBT_B_AUX_P C_USB_BN USBC2_BN2_L (46)
(47) TBT_B_USB2_D_N RT4 1 @ 2 0_0201_5% (47) TBT_B_AUX_P J1
TBT_B_AUX_N AUX_P
(47) TBT_B_AUX_N J2
AUX_N K8
L8
RT167 1 @ 2 0_0201_5% G4 PVT-1 0 2
RT172 1 @ 2 0_0201_5% F4 SWD_CLK Change to short-pad
SWD_DATA PD2_GPIO0
B2
GPIO0 PD2_GPIO1 TC8
C2 RT83 1 @ 2 0_0402_5%
GPIO1 PD2_GPIO2 EN_PD_HV2 (82,83)
E2 D10 RT48 1 @ 2 0_0402_5%
(43) UART_MISO UART_TX GPIO2 PD2_GPIO3 TC1
F2 G11 RT69 1 @ 2 0_0402_5%
(43) UART_MOSI UART_RX GPIO3 PD2_GPIO4 AC2_DISC# (82,83)
C10 RT152 1 @ 2 0_0402_5%
TBT_B_LSTX GPIO4 PD2_GPIO5 TBT_B_HPD (47,58)
(47) TBT_B_LSTX L4 E10 RT158 1 @ 2 0_0402_5%
TBT_B_LSRX LSTX/R2P GPIO5 PD2_GPIO6 TC4
(47) TBT_B_LSRX K4 G10 RT160 1 @ 2 0_0402_5%
LSRX/P2R GPIO6 PD2_GPIO7 TC5
D7 RT148 1 @ 2 0_0402_5%
PD2_DEBUG_CTL1 GPIO7 PD2_GPIO8 PD2_GPIO8_EXT
TC3
PVT-1 0 3
PD2_DEBUG_CTL2
E4 H6 RT176 1 @ 2 0_0402_5%
Change to short-pad DEBUG_CTL1 GPIO8 TC6
D5
B DEBUG_CTL2 B
UPD2_SMBCLK PD2_DEBUG1
RT61 1 @ 2 0_0402_5% L2
UPD2_SMBDAT
RT85 1 @ 2 0_0402_5%
PD2_DEBUG2
K2 DEBUG1 E11 RT55 1 2 100K_0201_5%
power side pull down 1M
TBT_B_LSTX PD2_DEBUG3
DEBUG2 MRESET
TBT_RESET_N_EC_PD2
RT101 non-mount
RT173 1 @ 2 0_0402_5% L3 F11
TBT_B_LSRX PD2_DEBUG4 DEBUG3 RESET_N PD2_GPIO1
RT175 1 @ 2 0_0402_5% K3 @ RT87 1 2 0_0402_5% +3.3V_LDO_PD2 @ RT146 1 2 1M_0201_5%
DEBUG4 F10 @ RT82 1 2 0_0402_5%
BUSPOWER_N +1.8VD_LDO_PD2 PD2_GPIO2
F1 RT164 1 2 0_0402_5% RT149 1 2 1M_0201_5%
I2C_ADDR G2
R_OSC
1
H7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SS
0.22U_0402_16V7K
15K_0402_1%
@ RT67
TBT_RESET_N_EC_PD2
1
0_0402_5% 1 @ 2
1 TBT_RESET_N_EC (43,47,58)
CT62
RT162
TPS65982DCZQZR BGA 96P RT90 0_0402_5%
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H8
L1
L11
2
+3.3V_LDO_PD2
2
1
10K_0402_1%
RT86
1
1
RT151 @ RT62
100K_0402_5% 0_0402_5%
2
PD2_GPIO8_EXT
2
1
100K_0402_1%
RT89
2
A A
For "-D" version only

Factory Set Device Configurations 7
Infinite boot retry from Flash to Host I/F cycles.
DIV=RT106/(RT105+RT106)
between 0.7~1.0

P045 - TYPE-C_PortB_PD
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
LA-G661P 0.4
5 4 3 2 1
5 4 3 2 1
D D
0.1U_0402_25V6
10U_0603_25V6M
1 1 EMC@
D41
D85
EMC@
1
C84
CT86
2 2
2
CONN@
JUSBC2
A1 B12
GND GND
TBT_B_TTX_C_DRX_P1 TBT_B_TRX_DTX_P1
TBT_B_TTX_C_DRX_N1 A2 B11 TBT_B_TRX_DTX_N1 TBT_B_TRX_DTX_P1 (47)
(47) TBT_B_TTX_C_DRX_P1 SSTXP1 SSRXP1
A3 B10 TBT_B_TRX_DTX_N1 (47)
(47) TBT_B_TTX_C_DRX_N1 SSTXN1 SSRXN1
C79 1 2 A4 B9 2 1 C85
0.47U_0201_25V VBUS VBUS 0.47U_0201_25V
A5 B8
(45) USBC2_CC1 CC1 SUB2 USBC2_SBU2 (45)
USBC2_TOP_DN1
A6 B7 USBC2_BOT_DP2
A7 DP1 DN2 B6
DN1 DP2
Bottom
A8 B5
(45) USBC2_SBU1 SUB1 CC2 USBC2_CC2 (45)
TOP
C86 1 2 A9 B4 2 1 C80
0.47U_0201_25V TBT_B_TRX_DTX_N2 VBUS VBUS 0.47U_0201_25V
TBT_B_TTX_C_DRX_N2
TBT_B_TRX_DTX_P2
A10 B3 TBT_B_TTX_C_DRX_P2
(47) TBT_B_TRX_DTX_N2 SSRXN2 SSTXN2 TBT_B_TTX_C_DRX_N2 (47)
A11 B2
(47) TBT_B_TRX_DTX_P2 SSRXP2 SSTXP2 TBT_B_TTX_C_DRX_P2 (47)
A12 B1
GND GND
JUSBC2_GND JUSBC2_GND
1 4
GND GND
1
1 2 3
LT4 EMC@ GND GND
EMC@ CT51 UPB201209T-121Y-N_2P
C C
0.1U_0402_25V6 JAE_DX07S024XJ1R1100~D
2
2
PVT-177
Remove co-lay
ML7 EMC@ USBC2_TOP_DP1

TBT_B_TTX_C_DRX_P1 TBT_B_TRX_DTX_N2
4 3
(45) USBC2_TP1_L
1 2 1 2
D77 D40 USBC2_TOP_DN1
1 2
(45) USBC2_TN1_L
MCM1012B900F06BP_4P
EMC@ EMC@
TBT_B_TTX_C_DRX_N1 TBT_B_TRX_DTX_P2
1 2 1 2
D76 D38
EMC@ EMC@
TBT_B_TRX_DTX_P1 TBT_B_TTX_C_DRX_N2
1 2 1 2
D33 D83 ML4 EMC@ USBC2_BOT_DN2
4 3
(45) USBC2_BN2_L
EMC@ EMC@
USBC2_BOT_DP2
1 2
(45) USBC2_BP2_L
TBT_B_TRX_DTX_N1 TBT_B_TTX_C_DRX_P2
1 2 1 2 MCM1012B900F06BP_4P
D34 D82
EMC@ EMC@
B 1 2 1 2 B
D35 D78
Pin12
AZ5B75-01B.R7G_CSP0603P2Y2 AZ5B75-01B.R7G_CSP0603P2Y2 Pin1 USB Type-C Receptacle Interface (Front View)
EMC@ EMC@
USBC2_TOP_DP1
1 2 1 2
USBC2_BOT_DN2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
D80 D37
GND TX1+ TX1- VBUS CC1 D+ D- SBU1 VBUS RX2- RX2+ GND
EMC@ EMC@
USBC2_TOP_DN1 USBC2_BOT_DP2
1 2 1 2
D79 D36 GND RX1+ RX1- VBUS SBU2 D- D+ CC2 VBUS TX2- TX2+ GND
B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
EMC@ EMC@
Printed Circuit Board
USBC2_SBU1
1 2 1 2
USBC2_CC2
Pin13
D39 D81 Pin24
EMC@ EMC@
A A

P046 - TYPE-C_PortB_CONN
5 4 3 2 1
5 4 3 2 1
+3V_PCH
RTD3_CIO_PWR_EN
RT275 2 RTD3@ 1 10K_0201_5%
+3VA_TBT
PCIE_PTX_C_DRX_P5 UT6A PCIE_PRX_C_DTX_P5 RTD3_CIO_PWR_EN

CT32 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N5 Y 23 V23 PCIE_PRX_C_DTX_N5 CT23 2 1 0.22U_0201_6.3V6M PCIE_PRX_DTX_P5 (13)
RT70 2 @ 1 10K_0201_5%
CT31 2 1 0.22U_0201_6.3V6M Y 22 PCIE_RX0_P PCIE_TX0_P V22 CT22 2 1 0.22U_0201_6.3V6M RTD3_USB_PWR_EN
(13) PCIE_PTX_DRX_N5 PCIE_PRX_DTX_N5 (13)
PCIE_RX0_N PCIE_TX0_N
CPU PCIE RX
PCIE_PTX_C_DRX_P6 PCIE_PRX_C_DTX_P6 RT97 2 @ 1 10K_0201_5%
CPU PCIE TX
CT25 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N6 T23 P23 PCIE_PRX_C_DTX_N6 CT35 2 1 0.22U_0201_6.3V6M PCIE_WAKE#
(13) PCIE_PTX_DRX_P6 PCIE_RX1_P PCIE_TX1_P PCIE_PRX_DTX_P6 (13)
CT24 2 1 0.22U_0201_6.3V6M T22 P22 CT36 2 1 0.22U_0201_6.3V6M RT196 2 @ 1 10K_0201_5%
(13) PCIE_PTX_DRX_N6 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N6 (13)
PCIE_PTX_C_DRX_P7 PCIE_PRX_C_DTX_P7 TBT_CIO_PLUG_EVENT#
CT28 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N7 M23 K23 PCIE_PRX_C_DTX_N7 CT34 2 1 0.22U_0201_6.3V6M PCIE_PRX_DTX_P7 (13)
RT101 2 @ 1 10K_0201_5%
CT29 2 1 0.22U_0201_6.3V6M M22 PCIE_RX2_P PCIE_TX2_P K22 CT33 2 1 0.22U_0201_6.3V6M
PCIe GEN3
(13) PCIE_PTX_DRX_N7 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N7 (13)
PCIE_PTX_C_DRX_P8 PCIE_PRX_C_DTX_P8 RTD3_USB_PWR_EN
CT27 2 1 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_N8 H23 F23 PCIE_PRX_C_DTX_N8 CT30 2 1 0.22U_0201_6.3V6M RT100 2 1 100K_0201_5%
(13) PCIE_PTX_DRX_P8 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_DTX_P8 (13)
CT26 2 1 0.22U_0201_6.3V6M H22 F22 CT37 2 1 0.22U_0201_6.3V6M PCIE_PRX_DTX_N8 (13)
PCIE_RX3_N PCIE_TX3_N TBT_PERST# PCH_PLTRST#_AND
V19 L4 RT105 1 @NRTD3@2 0_0402_5%
(11) CLK_PCIE_P0 PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_AND (11,52,53,66,68,70,79)
CLKREQ_PCIE#0_R T19 PCIe_RBIAS PCH_TBT_PERST#
(11) CLK_PCIE_N0 PCIE_REFCLK_100_IN_N +3VA_TBT
RT65 2 @ 1 0_0201_5% AC5 N16 RT108 2 1 3.01K_0402_1% RT106 1 2 0_0402_5%
(11) CLKREQ_PCIE#0 PCIE_CLKREQ_N PCIE_RBIAS PCH_TBT_PERST# (14)
D PVT-031 CPU_DP1_P0_C @RTD3@ TBT_I2C_DATA D
Change to short-pad CT82 2 1 0.1U_0201_6.3V6K AB7 R2 RT197 2 1 2.2K_0201_5%
(6) CPU_DP1_P0 CPU_DP1_N0_C
CT84 2 1 0.1U_0201_6.3V6K AC7 DPSNK0_ML0_P DPSRC_ML0_P R1 TBT_I2C_CLK
(6) CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N
CPU_DP1_P1_C RT98 2 1 2.2K_0201_5%
CT78 2 1 0.1U_0201_6.3V6K CPU_DP1_N1_C AB9 N2 TBT_A_I2C_INT#
(6) CPU_DP1_P1 DPSNK0_ML1_P DPSRC_ML1_P
(6) CPU_DP1_N1
CT80 2 1 0.1U_0201_6.3V6K AC9 N1 RT184 2 1 10K_0201_5%
DPSNK0_ML1_N DPSRC_ML1_N
SOURCE PORT 0
CPU_DP1_P2_C NOTE: TBT_B_I2C_INT#
CPU DDI1
CT70 2 1 0.1U_0201_6.3V6K CPU_DP1_N2_C AB11 L2 RT99 2 1 10K_0201_5%
(6) CPU_DP1_P2 DPSNK0_ML2_P DPSRC_ML2_P ASSEMBLE R165, R166 if DPSRC
SINK PORT 0
CT68 2 1 0.1U_0201_6.3V6K AC11 L1 TBT_BATLOW#
(6) CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N NOT IN USE
CPU_DP1_P3_C RT189 2 1 10K_0201_5%
(6) CPU_DP1_P3 CT66 2 1 0.1U_0201_6.3V6K CPU_DP1_N3_C AB13 J2
CT60 2 1 0.1U_0201_6.3V6K AC13 DPSNK0_ML3_P DPSRC_ML3_P J1 TBT_SRC_CFG1 +3VA_TBT
(6) CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N
CPU_DDI1_AUXP_C R229 1 2 1M_0201_1% PCIE_WAKE#_AR
CT79 2 1 0.1U_0201_6.3V6K CPU_DDI1_AUXN_C Y 11 W19 TBT_SRC_HPD RT150 2 RTD3@ 1 10K_0201_5%
(6) CPU_DP1_AUXP DPSNK0_AUX_P DPSRC_AUX_P
CT76 2 1 0.1U_0201_6.3V6K W11 Y 19 R224 1 2 1M_0201_1% TBT_DDC_CLK
(6) CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N
CPU_DP1_HPD TBT_SRC_HPD RT103 2 1 2.2K_0201_5%
AA2 G1 TBT_DDC_DATA
(6) CPU_DP1_HPD
DPSNK0_HPD DPSRC_HPD NOTE: RT154 2 1 2.2K_0201_5%
TBT_SNK0_DDC_CLK DPSRC_RBIAS
RT68 2 1 0_0201_5% TBT_SNK0_DDC_DATA Y5 N6 RT178 2 1 14K_0402_1% TBT_SRC_CFG1 = 0 for DP mode.
(6) CPU_DP1_CTRL_CLK DPSNK0_DDC_CLK DPSRC_RBIAS
RT79 2 1 0_0201_5% R4 TBT_I2C_DATA TBT_SNK0_DDC_CLK
(6) CPU_DP1_CTRL_DATA DPSNK0_DDC_DATA
CPU_DP2_P0_C U1 TBT_I2C_CLK TBT_I2C_DATA (43,45) RT193 2 @ 1 100K_0201_5%
CT54 2 1 0.1U_0201_6.3V6K CPU_DP2_N0_C AB15 GPIO_0 U2 TBT_ROM_WP# TBT_SNK0_DDC_DATA
(6) CPU_DP2_P0 DPSNK1_ML0_P GPIO_1 TBT_I2C_CLK (43,45)
CT58 2 1 0.1U_0201_6.3V6K AC15 V1 TBT_TMU_CLK_OUT RT192 2 @ 1 100K_0201_5%
(6) CPU_DP2_N0 DPSNK1_ML0_N GPIO_2
CPU_DP2_P1_C V2 PCIE_WAKE#_AR PCIE_WAKE# TBT_SNK1_DDC_CLK
CT50 2 1 0.1U_0201_6.3V6K AB17 GPIO_3 W1 1 @NRTD3@2 RT195 2 1 100K_0201_5%
(6) CPU_DP2_P1 CPU_DP2_N1_C TBT_CIO_PLUG_EVENT# PCIE_WAKE# (52,53,58,68)
+3VA_TBT_LC CT53 2 1 0.1U_0201_6.3V6K AC17 DPSNK1_ML1_P GPIO_4 W2 RT111 0_0402_5%
(6) CPU_DP2_N1 TBT_DDC_DATA TBT_CIO_PLUG_EVENT# (10) PCH_PCIE_WAKE# TBT_SNK1_DDC_DATA
DPSNK1_ML1_N GPIO_5
CPU DDI2
VCC3V3_LC CPU_DP2_P2_C Y1 TBT_DDC_CLK 1 @ 2 PCH_PCIE_WAKE# (11,58) RT194 2 1 100K_0201_5%
LC GPIO
CT47 2 1 0.1U_0201_6.3V6K CPU_DP2_N2_C AB19 GPIO_6 Y2 TBT_SRC_CFG1 RT114 0_0402_5%
TBT_RTD3_WAKE# TBT_FORCE_PWR
(6) CPU_DP2_P2 DPSNK1_ML2_P GPIO_7
CT49 2 1 0.1U_0201_6.3V6K AC19 AA1 1 2 RT64 2 1 10K_0201_5%
SINK PORT 1
(6) CPU_DP2_N2 TBT_A_I2C_INT# TBT_RTD3_WAKE# (14)
DPSNK1_ML2_N GPIO_8 J4 RT171 @RTD3@ 0_0402_5%
CPU_DP2_P3_C TBT_B_I2C_INT# TBT_A_I2C_INT# (43) RTD3_CIO_PWR_EN
1
CT44 2 1 0.1U_0201_6.3V6K AB21 POC_GPIO_0 E2 RT190 2 @NRTD3@1 100K_0201_5%

CPU_DP2_N3_C RTD3_USB_PWR_EN
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
(6) CPU_DP2_P3 DPSNK1_ML3_P POC_GPIO_1 TBT_B_I2C_INT# (45)

(6) CPU_DP2_N3
CT42 2 1 0.1U_0201_6.3V6K AC21 D4 TBT_FORCE_PWR
CPU_DDI2_AUXP_C DPSNK1_ML3_N POC_GPIO_2 H4 TBT_BATLOW#
POC_GPIO_3 TBT_FORCE_PWR (14)
CT71 2 1 0.1U_0201_6.3V6K CPU_DDI2_AUXN_C Y 12 F2
RT60
TBT_SLP_S3_N
RT107
RT183
RT165
(6) CPU_DP2_AUXP DPSNK1_AUX_P POC_GPIO_4 TBT_BATLOW# (9)

CT74 2 1 0.1U_0201_6.3V6K W12 D2 RTD3_CIO_PWR_ENRT186 1 @ 2 0_0201_5%
SIO_SLP_S3# (11,58,78,79)
2
POC GPIO
(6) CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5
TBT_JTAG_TDI CPU_DP2_HPD F1 RTD3_CIO_PWR_EN (14)
TBT_JTAG_TMS Y6 POC_GPIO_6 TBT_TEST_EN PVT-032
(6) CPU_DP2_HPD DPSNK1_HPD Change to short-pad
TBT_JTAG_TCK TBT_SNK1_DDC_CLK E1 2 1
@ RT75 2 1 0_0201_5% Y8 TEST_EN 100_0201_1% RT163
TBT_JTAG_TDO (6) CPU_DP2_CTRL_CLK TBT_SNK1_DDC_DATA TBT_TEST_PWRG
@ RT72 2 1 0_0201_5% N4 DPSNK1_DDC_CLK AB5 2 1 PVT-033
(6) CPU_DP2_CTRL_DATA
Misc
DPSNK1_DDC_DATA TEST_PWR_GOOD 100_0201_1% RT185 Change to short-pad
DPSNK_RBIAS TBT_RESET_N_R
2 1 Y 18 F4 0_0201_5% 2 @ 1 RT198 TBT_RESET_N_EC (43,45,58)
RT182 14K_0402_1% TBT_JTAG_TDI DPSNK_RBIAS RESET_N XTAL_25_IN +3VA_TBT
+3.3V_LDO_PD1 +3.3V_TBT_FLASH TBT_JTAG_TMS Y4 D22 XTAL_25_OUT
V4 TDI XTAL_25_IN D23
TBT_JTAG_TCK CLKREQ_PCIE#0_R
RT260 1 @ 2 0_0402_5% T4 TMS XTAL_25_OUT RT155 2 @ 1 10K_0201_1%
AR/PPS COMMON FLASH PVT-105
TBT_JTAG_TDO
W4 TCK AB3
TBT_ROM_DI
MISC TBT_ROM_DO
+3VA_TBT_LC Change to short-pad
TBT_RBIAS
TDO EE_DI AC4 TBT_ROM_CS#
H6 EE_DO AC3
TBT_RSENSE TBT_ROM_CLK TBT_RESET_N_R
RT261 1 @ 2 0_0402_5% 1 2 J6 RBIAS EE_CS_N AB4 RT49 2 @ 1 10K_0201_1%
C RT157 4.75K_0402_0.5% RSENSE EE_CLK C
(44) TBT_A_TRX_DTX_P2 A15 B7 TBT_B_TRX_DTX_P2 (46) TBT_TMU_CLK_OUT
B15 PA_RX1_P PB_RX1_P A7 RT199 2 1 100K_0201_5%
(44) TBT_A_TRX_DTX_N2 PA_RX1_N PB_RX1_N TBT_B_TRX_DTX_N2 (46)
0.1U_0201_6.3V6K
3.3K_0201_1%
3.3K_0201_1%
1 TBT_A_TTX_DRX_P2 TBT_B_TTX_DRX_P2
1
CT73 2 1 0.22U_0201_6.3V6M TBT_A_TTX_DRX_N2 A17 A9 TBT_B_TTX_DRX_N2 CT87 1 2 0.22U_0201_6.3V6M C288 1 2 100P_0201_50V8J

2.2K_0201_1%
2.2K_0201_1%
CT127
(44) TBT_A_TTX_C_DRX_P2 TBT_B_TTX_C_DRX_P2 (46)

RT159
RT177
RT180
RT166
CT69 2 1 0.22U_0201_6.3V6M B17 PA_TX1_P PB_TX1_P B9 CT89 1 2 0.22U_0201_6.3V6M

(44) TBT_A_TTX_C_DRX_N2 TBT_B_TTX_C_DRX_N2 (46) TBT_B_HPD
TBT_A_TTX_DRX_P1
PA_TX1_N PB_TX1_N TBT_B_TTX_DRX_P1 RT170 2 1 100K_0201_5%
2 CT57 2 1 0.22U_0201_6.3V6M TBT_A_TTX_DRX_N1 A19 A11 TBT_B_TTX_DRX_N1 CT83 1 2 0.22U_0201_6.3V6M TBT_A_HPD
(44) TBT_A_TTX_C_DRX_P1 PA_TX0_P PB_TX0_P TBT_B_TTX_C_DRX_P1 (46)
CT59 2 1 0.22U_0201_6.3V6M B19 B11 CT81 1 2 0.22U_0201_6.3V6M RT102 2 1 100K_0201_5%
(44) TBT_A_TTX_C_DRX_N1 TBT_B_TTX_C_DRX_N1 (46)
2
PA_TX0_N PB_TX0_N
TBT PORT B
TBT_A_LSRX
B21 A13 RT169 1 2 1M_0201_5%
TBT PORT A
PORT A
PORT B
(44) TBT_A_TRX_DTX_P1 TBT_B_TRX_DTX_P1 (46)
TBT_ROM_CS# UT7 A21 PA_RX0_P PB_RX0_P B13 TBT_B_LSRX
(44) TBT_A_TRX_DTX_N1 PA_RX0_N PB_RX0_N TBT_B_TRX_DTX_N1 (46)
TBT_ROM_DO 1 8 TBT_ROM_HOLD# TBT_A_AUX_P_C TBT_B_AUX_P_C RT57 1 2 1M_0201_5%
2 CS# VCC 7 CT77 2 1 0.1U_0201_6.3V6K Y 15 Y 16 CT96 1 2 0.1U_0201_6.3V6K
TBT_ROM_WP# TBT_ROM_CLK (43) TBT_A_AUX_P TBT_A_AUX_N_C TBT_B_AUX_N_C TBT_B_AUX_P (45) TBT_B_LSTX
TBT PORTS
3 DO(IO1) HOLD#(IO3) 6 CT75 2 1 0.1U_0201_6.3V6K W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16 CT98 1 2 0.1U_0201_6.3V6K RT191 1 2 1M_0201_5%
TBT_ROM_DI (43) TBT_A_AUX_N TBT_B_AUX_N (45)
4 WP#(IO2) CLK 5 PA_DPSRC_AUX_N PB_DPSRC_AUX_N
TBT_A_LSTX
GND DI(IO0) 9 E20 E19 RT104 1 2 1M_0201_5%
thermal pad (43) TBT_A_USB2_D_P PA_USB2_D_P PB_USB2_D_P TBT_B_USB2_D_P (45)
D20 D19
(43) TBT_A_USB2_D_N PA_USB2_D_N PB_USB2_D_N TBT_B_USB2_D_N (45)
W25Q80DVZPIG TBT_A_LSTX TBT_B_LSTX
TBT_A_LSRX A5 B4 TBT_B_LSRX
POC
POC
(43) TBT_A_LSTX PA_LS_G1 PB_LS_G1 TBT_B_LSTX (45)
(43) TBT_A_LSRX TBT_A_HPD A4 B5 TBT_B_HPD TBT_B_LSRX (45)
M4 PA_LS_G2 PB_LS_G2 G2
RT44,RT47 use 3.3K ohm Use SA00005I940 for EVT debug (8M) (43,58) TBT_A_HPD PA_LS_G3 PB_LS_G3 TBT_B_HPD (45,58)
PA_USB2_RBIAS PB_USB2_RBIAS
Use SA00008DZ00 for MP (1M) RT153 1 2 499_0201_1% H19 F19 1 2
PA_USB2_RBIAS PB_USB2_RBIAS RT168 499_0201_1%
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 E18
TEST_EDM DEBUG USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC
AR-4C_BGA337
+3VALW
TBT_RTD3_WAKE# RT63 0_0201_5% RTD3@
+3VALW 2 RTD3@ 1
CT94 1 2 0.1U_0402_25V6
CT72 1 2 0.1U_0402_25V6
U15
PCH_PCIE_WAKE# RT80 0_0201_5%
RT76 @RTD3@ 0_0201_5% U14 1@RTD3@ 2 1 5
PCH_TBT_PERST# @RTD3@
2 1 1 5 NO V+ RT81 0_0201_5% PCIE_WAKE#_AR
NO V+ RT66
IN NC NO PCIE_WAKE#
2 RTD3@ 1 3 4
PCIE_WAKE#_AR_R
2 1
PCH_PLTRST#_AND TBT_PERST#_R 0_0201_5% TBT_PERST#
XTAL 2 @RTD3@1 3 4 2 1 RT78 0_0201_5% NC COM
RT71 0_0201_5% NC COM @RTD3@ 6 2
YT1 (47,58) RTD3_SELECT RTD3@
2
B RT187 0_0201_5% 6 2 IN GND B
XTAL_25_OUT_R XTAL_25_OUT (47,58) RTD3_SELECT
1
4 3 1 2 IN GND TS5A3159ADCKR_SC70-6 RT181
L COM X
1
XTAL_25_IN RT188 0_0201_5%
XTAL_25_IN_R TS5A3159ADCKR_SC70-6 RT179 RT161 RTD3@ 1M_0402_5%
2 1 1 2 RT73 @RTD3@ 1M_0402_5% 10K_0201_5% @RTD3@
1 10K_0201_5% @RTD3@ RTD3@
1
1 @RTD3@ H X COM
2
25MHZ_20PF_FL2500123Z CT92
2
CT121 27P_0201_25V8
27P_0201_25V8 2
2
RT272 0_0201_5%
2 1
@NRTD3@
+3VALW
CT141 1 2 0.1U_0402_25V6
RTD3@
5
PCH_PLTRST#_ANDRT268 RTD3@ 0_0201_5%
2 1 1 TBT_PERST#_AND RT270 0_0201_5% TBT_PERST#
P
B 4 2 1
PCH_TBT_PERST#
2 RTD3@ 1 2 O RTD3@
A
G
RT269 0_0201_5%
1
3
RT271
UE5 10K_0201_5%
MC74VHC1G08DFT2G_SC70-5 RTD3@ 0513
Intel suggest follow RVP and MERION
2
A A

P047 - TYPE-C_TBT(1/2) DP,PCIE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.4
5 4 3 2 1
5 4 3 2 1
close to UT2.R13 close to UT2.H9
+3V_TBT_S0 +3VA_TBT +3V_TBT
39P_0201_50V8J
EMC@ C53
100P_0201_50V8J
EMC@ C291
39P_0201_50V8J
EMC@ C95
100P_0201_50V8J
EMC@ C304
RF@ CT142
RF@ CT143
RF@ CT144
1 1 1 1 1 1 1
150P_0201_25V8J
82P_0201_50V8J
82P_0201_50V8J
close to UT2.F8
+3VA_TBT +3VA_TBT
2 2 2 2 2 2 2
RT47 1 @ 2 0_0402_5%~D
close to UT2.R6
39P_0201_50V8J
EMC@ C52
100P_0201_50V8J
EMC@ C295
PVT-143 +3VA_TBT_LC +3VA_TBT_LC
1 1
+3VALW Change to short-pad +3VA_TBT +3V_TBT_S0 close to UT2.A2,A3,B3 +3V_TBT
LT3
RT113 1 @ 2 0_0603_5% 1 1 2
D 2 2 D
39P_0201_50V8J
EMC@ C54
100P_0201_50V8J
EMC@ C294
0.1U_0201_10V6K
CT123
1U_0201_6.3V6M
CT124
1U_0201_6.3V6M
47U_0603_6.3V
47U_0603_6.3V
39P_0201_50V8J
EMC@ C55
100P_0201_50V8J
EMC@ C293
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
LQM18PN1R0MFHD_2P +3V_TBT +3VS
+3VS
1 1 1 1 1 1
CT129
CT97
CT93
2 1 1 1 1 1 1 1
CT56
CT104
CT101
CT102
RF@
CT112
RT109 1 @ 2 0_0603_5% 1 2
2 2 2 2 2 2 L36 BLM18KG601SN1D_2P
2 2 2 2 2 2 2 +3VALW
R13
+VCC0V9_PCIE +VCC0V9_DP +VCC0V9_DP RT110 1 2 0_0603_5%
R6
H9
@
F8
close to UT2 close to UT2 UT6B
L8 A2
VCC3P3_SX
VCC3P3A
VCC3P3_LC
VCC3P3_S0
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L11 VCC0P9_DP VCC3P3_SVR A3
VCC0P9_DP VCC3P3_SVR
39P_0201_50V8J
EMC@ C93
100P_0201_50V8J
EMC@ C296
39P_0201_50V8J
EMC@ C92
100P_0201_50V8J
EMC@ C292
1 1 1 1 1 1 1 L12 B3
M8 VCC0P9_DP VCC3P3_SVR
CT117
CT119
CT138
CT137
CT114
CT113
CT122
1 1 1 1 VCC0P9_DP
T11 +VCC0V9_SVR
T12 VCC0P9_DP L9
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
2 2 2 2 2 2 2 L6 VCC0P9_DP VCC0P9_SVR M9
2 2 2 2 M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
V11 E13
CT116
CT135
CT125
CT118
CT133
CT132
CT131
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11 close to UT2 close to UT2
+VCC0V9_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA +VCC0V9_SVR +TBT_SVR_IND
F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
VCC0P9_PCIE VCC0P9_SVR_ANA
39P_0201_50V8J
EMC@ C94
100P_0201_50V8J
EMC@ C300
39P_0201_50V8J
EMC@ C78
100P_0201_50V8J
EMC@ C303
M15 J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE 1 1 1 1
+VCC0V9_USB L19 LT2 0.68UH_MLV-YT10NR68N-M1L_2.7A_30%
CT140
CT134
CT115
CT136
VCC
VCC0P9_ANA_PCIE_1 +TBT_SVR_IND
close to UT2.R15,R16 N19 C1 1 2
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2
2 2 2 2 VCC0P9_ANA_PCIE_2 SVR_IND 2 2 2 2
47U_0603_6.3V
47U_0603_6.3V
47U_0603_6.3V
M18 D1
VCC0P9_ANA_PCIE_2 SVR_IND 1 1 1
39P_0201_50V8J
EMC@ C91
100P_0201_50V8J
EMC@ C299
CT99
CT95
CT100
N18
+VCC0V9_USB VCC0P9_ANA_PCIE_2
1 1
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
VCC0P9_USB SVR_VSS B2
2 2 R8 SVR_VSS
1 1 VCC0P9_CIO
R9
CT139
CT21
R11 VCC0P9_CIO
R12 VCC0P9_CIO F18
2 2 VCC0P9_CIO VCC0P9_LVR H18 close to UT2
+VCC_3V3_PCIE VCC0P9_LVR
+VCC_3V3_USB2 L16 J11 +VCC0V9_LVR_OUT +VCC0V9_LVR_OUT
J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11
C C
1U_0201_6.3V6M
1U_0201_6.3V6M
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
10U_0402_6.3V6M
10U_0402_6.3V6M
+VCC0V9_CIO
39P_0201_50V8J
EMC@ C90
100P_0201_50V8J
EMC@ C298
A6 V5 1 1 1 1
+VCC0V9_CIO VSS_ANA VSS_ANA
CT105
CT103
A8 V6
CT91
CT90
close to UT2.R8,R9,R11,R12 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
VSS_ANA VSS_ANA
1
A10 V8
VSS_ANA VSS_ANA
10K_0201_5%
RT267
A12 V9
1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
VSS_ANA VSS_ANA 2 2 2 2
39P_0201_50V8J
EMC@ C89
100P_0201_50V8J
EMC@ C297
A14 V15
CT128
CT88
A16 VSS_ANA VSS_ANA V16 2 2
1 1 1 1 1 VSS_ANA VSS_ANA
A18 V20
CT85
CT130
CT126
2 2 A20 VSS_ANA VSS_ANA W5

A22 VSS_ANA VSS_ANA W6
2 2 2 2 2 B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
Ref AR_DP_HOST_REF_DESIGN_R2V05 B10 VSS_ANA VSS_ANA W20
26/04/17 1. Adding 10KOhm bleeder to
PW _ V C C 3 v 3 _ A N A _ P C I e
B16 VSS_ANA VSS_ANA Y9
close to UT2.L16 close to UT2.J16 B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
+VCC_3V3_PCIE +VCC_3V3_USB2 VSS_ANA VSS_ANA
B22 AA22
D8 VSS_ANA VSS_ANA AA23
VSS_ANA VSS_ANA
39P_0201_50V8J
EMC@ C87
100P_0201_50V8J
EMC@ C305
39P_0201_50V8J
EMC@ C82
100P_0201_50V8J
EMC@ C290
D9 AB6
D11 VSS_ANA VSS_ANA AB8
1 1 1 1 VSS_ANA VSS_ANA
D12 AB10
2 2 2 2 D16 VSS_ANA VSS_ANA AB16
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
GND
F9 VSS_ANA VSS_ANA AC16
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
H12 VSS_ANA VSS E6
B B
H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
H16 VSS_ANA VSS H5
H20 VSS_ANA VSS H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
VSS_ANA VSS
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N5 T16
N20 VSS_ANA VSS T18
N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
AR-4C_BGA337
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U23
U22
A A

P048 - TYPE-C_TBT(2/2) PWR,GND
5 4 3 2 1
5 4 3 2 1
+5VALW PVT-144
Change to short-pad
I=50mA VF=0.45V
DT1 +3V_LDO_OUT RT41 1 2 0_0603_5%
For Power logic (10mA)
@ +3V_LDO
RB520SM-30T2R_EMD2-2 +5V_PD_VDD
2 1
UT2
+5V_TBT_VBUS DT2 1 5 RT42 1 @ 2 0_0603_5%
VCC VOUT +3.3V_VDD_PIC
RB520SM-30T2R_EMD2-2
D 2 1 2 D
GND For PD controller 1 (25mA)
@
0.1U_0201_10V6K
1U_0201_6.3V6M
1 1 1 2 3 4
EN ADJ/NC
0.1U_0201_10V6K
RT145 RT40 390K_0402_1% 1 1
1
CT110
CT15
2.2U_0402_6.3V6M
CT111
100K_0402_5%
CT16
RT273 1 AP2112K-3.3TRG1_SOT23-5 @
2 2 390K_0402_1%
2
@ CT14 2 2
1U_0201_6.3V6M Vin Min2.5V, Max6V
2
2
I=50mA, Vdrop=25mV
+VBUS1_PD_20V
I=50mA VF=0.45V UT4
place near UT17
DT4 1
VCC
1U_0603_25V6-K~D
+5V_TBTA_VBUS_D 1
1 2 3
VOUT
CT20
2
GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0201_6.3V6M
1 Vin Min2.3V, Max24V
I=50mA, Vdrop=350mV
CT17
2
+VBUS2_PD_20V
UT3
DT3 1
VCC
1U_0603_25V6-K~D
+5V_TBTB_VBUS_D 1
1 2 3
VOUT
CT18
2
GND
AP2204R-5.0TRG1_SOT89-3 2
C C
For MFG process use only RTC

+3VS
+3.3V_TBAT_LDO +3V_LDO +RTCBATT
2
RTCR3
+RTCBATT
BAT54HT1G_SOD323-2
BAT54HT1G_SOD323-2
100K_0201_5% +RTCVCC
W=20mi l s W=20mi l s W=20mi l s
1
BAT54HT1G_SOD323-2
@
+RTCBATT
1
2
SEIKO_MS621FE-FL11E
RTC1
RTCD3 RTCD4
RTC_DET#_R (12)
RTCR2 @ RTCD2
1
1.2K_0402_5% CLRP3
1
D
@
1
2 QRTC1
SHORT PADS
1
2
G L2N7002WT1G_SC-70-3
2
S
2
RTCR1
100K_0201_5%
+RTCVCC_EC
W=20mi l s
1
1
C264
B 1U_0201_6.3V6M B
+RTCVCC +RTCVCC_EC
@ R210
0_0402_5%
1 2
Q22
PJ2301_SOT23-3
1 3
S
D
PVT-034
Change to short-pad
1
1U_0201_6.3V6M
G
2
1
D66 RE114 1 @ 2 0_0201_5%

(11,79) PCH_RTCRST#
C263
R211 RB751S40T1G_SOD523-2
2 10K_0402_5% 2 1 1
D
Q11 2 RTCRST_ON (58)
2
L2N7002WT1G_SC-70-3 G
100K_0201_5%
S
3
1
1
R208
RE115
D
RTCRST_ON_R
Q23 2 1 2 RTCRST_ON_POWER (58)
L2N7002WT1G_SC-70-3 G
S
3
1M_0402_5%~D
0.1U_0402_25V6K~D
1
22P_0402_50V8J
100K_0201_1%
1
1
R209
C262
C261
@
2
2
2
A A

P049 - TYPE-C_PD LDO/RTC
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P050 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P051 - Reserve
5 4 3 2 1
A B C D E
WLAN/BT/CNVi/PCIe XTAL SEL
GPP_F0/CNV_BRI_DT (Internal 20 K Pull Down)

M.2 CNVI MODES
GPP_F6 / CNV_RGI_DT( no internal PU and PD)
M.2 2230 Key-E Jefferson Peak 2

Peak current 1.36A
0 = 38.4/19.2MHZ (DEFAULT)
1 = 24MHZ (25 MHZ WHEN XTAL FREQ

DIVIDER NON ZERO) +1.8VA
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.

+1.8VA
closed to pin 2, 4 closed to pin 72, 74
CNV_BRI_PTX_R_DRX 2 1
+3VS_WLAN +3VS_WLAN RC5 1 @ 2 20K_0201_5% RH21 20K_0402_5%
HCM1012GH900BP_4P USB20_P10_R CNV_RGI_PTX_R_DRX
4 3 1 @ 2
(13) USB20_P10
R156 4.7K_0201_5%
1 1
USB20_N10_R
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
C259
15P_0402_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
C225
15P_0402_50V8J
1 2 1 1 1 1
(13) USB20_N10
1
C257
C255
C256
C222
C223
C221
ML5 EMC@
C258
C224
+3VALW
2
2 2 2 2
100K_0402_5%
RZ12
1
RF@ RF@
HCM1012GH900BP_4P CLK_PCIE_P3_R
4 3 3. 3 V
(11) CLK_PCIE_P3
2
CNVI_EN# (58) CNV_RF_RST
CLK_PCIE_N3_R 1 @ 2
1 2 R331 0_0201_5%
(11) CLK_PCIE_N3
1
1. 8 V D VGS 0.9V
CNV_RF_RESET#_R
L26 EMC@ 2 QZ3
G LN2316ELT1G_SOT23-3
75K PD at PCH side S
3
PVT-175 +3VS_WLAN
Remove co-lay JNGFF3
USB20_P10_R 1 2
3 GND_1 3.3VAUX_2 4
USB#10 USB20_N10_R
5 USB_D+ 3.3VAUX_4 6
7 USB_D- LED1# 8
Wlan module no support PCM (pin8,10,12,14,20,22,32,34,36
GND_7 PCM_CLK CNV_RF_RST#_R CNV_RF_RESET#_R
PCH CNVio RX lane 1 (14) CNV_PRX_DTX_N1
9 10 1. 8 V R311 1 @ 2 0_0201_5% active low
11 SDIO_CLK PCM_SYNC 12 CNV_RF_RESET#_R (10)
(14) CNV_PRX_DTX_P1 SDIO_CMD PCM_OUT CLKREQ_CNV#_R
13 14 1. 8 V R312 1 @ 2 0_0201_5%
15 SDIO_DAT0 PCM_IN 16 CLKREQ_CNV (10) Clock request for 38.4MHz CNVi reference clock
PCH CNVio RX lane 0 (14) CNV_PRX_DTX_N0
17 SDIO_DAT1 LED2# 18 PVT-036
(14) CNV_PRX_DTX_P0 SDIO_DAT2 GND_18 Change to short-pad
19 20 CNV_BRI_PRX_R_DTX
21 SDIO_DAT3 UART_WAKE 22 1. 8 V RN2 1 2 22_0201_1%
PCH CNVio RX CLK (14) CLK_CNV_PRX_DTX_N
23 SDIO_WAKE UART_TX CNV_BRI_PRX_DTX (12) BRI bus RX
(14) CLK_CNV_PRX_DTX_P SDIO_RST BT traffic (BRI) Bluetooth radio interface
CNV_RGI_PTX_R_DRX
32 1. 8 V Control data (RGI) Radio generic interface
UART_RX CNV_RGI_PRX_R_DTX CNV_RGI_PTX_R_DRX (12) RGI bus TX
PCIE_PTX_C_DRX_P10 33
GND_33 UART_RTS
34 1. 8 V CNV_BRI_PTX_R_DRX RN1 1 2 22_0201_1%
CNV_RGI_PRX_DTX (12) RGI bus RX 1.8V logic level
CV9 1 2 .1U_0402_16V7K 35 36 1. 8 V
CV8 1 2 .1U_0402_16V7K
PCIE_PTX_C_DRX_N10
37 PET_RX_P0 UART_CTS 38
CNV_BRI_PTX_R_DRX (12) BRI bus TX
(13) PCIE_PTX_DRX_N10 PET_RX_N0 CLink_RST PCH_CL_RST1# (9)
39 40
41 GND_39 CLink_DATA 42
PCH_CL_DATA1 (9) CLINK for PCIe WLAN module
(13) PCIE_PRX_DTX_P10 PER_TX_P0 CLink_CLK PCH_CL_CLK1 (9)
PCIE#10 43 44 1. 8 V NGFF_COEX3 (53) Coex with LET module
(13) PCIE_PRX_DTX_N10 45 PER_TX_N0 COEX3 46 1. 8 V
2 CLK_PCIE_P3_R
CLK_PCIE_N3_R 47 GND_45 COEX2 48 1. 8 V WIGIG_32KHZ
NGFF_COEX2 (53) two UART(COEX1,2) out 1.8V 2
REFCLK_P0 COEX1 NGFF_COEX1 (53)
49
REFCLK_N0 SUSCLK(32KHz)
50 R181 1 @ 2 0_0201_5%
SUSCLK (11,53,68)
one GPIO(COEX3) in/out 1.8V
51 52 BT_RADIO_DIS#_R
GND_51 PERST0# PCH_PLTRST#_AND (11,47,53,66,68,70,79)
(11) CLKREQ_PCIE#3
53 54 WLAN_WIGIG60GHZ_DIS#_R C2421 2 0.1U_0201_10V6K
55 CLKREQ0# W_DISABLE2# 56 @EMC@
(47,53,58,68) PCIE_WAKE# PEWAKE0# W_DISABLE1#
57 58 0512
59 GND_57 I2C_DAT 60 SUSCLK not used by JfP2 and wlan module
(14) CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
61 62
PCH CNVio TX lane 1 (14) CNV_PTX_DRX_P1
63 RSVD/PCIE_RX_N1 I2C_IRQ 64
REFCLK_CNV_R
R168 1 2 0_0201_5%
@ 38.4MHz from CNVi to PCH
65 GND_63 RSVD_64 66 REFCLK_CNV (11)
(14) CNV_PTX_DRX_N0 RSVD/PCIE_TX_P1 RSVD_66
1
10K_0201_5%
PCH CNVio TX lane 0 (14) CNV_PTX_DRX_P0
67 68
RSVD/PCIE_TX_N1 RSVD_68
RN6
69 70 PVT-035
71 GND_69 RSVD_70 72 Change to short-pad
(14) CLK_CNV_PTX_DRX_N RSVD_71 3.3VAUX_72 +3VS_WLAN
73 74
PCH CNVio TX CLK (14) CLK_CNV_PTX_DRX_P
75 RSVD_73 3.3VAUX_74
2
GND_75 76
77 GND1 @
GND2
LOTES_APCI0147-P007A
CONN@
+3VS_WLAN +3VS_WLAN
1
10K_0201_5%
RN3
10K_0201_5%
RN8
WLAN module: Active low. Turn-off BT RF
analog and front-end. Internal pull-up
2
BT_RADIO_DIS#_R DN3
2 1
BT_RADIO_DIS# (58)
pull up on EC side
WLAN_WIGIG60GHZ_DIS#_R DN4
2 1
WLAN_WIGIG60GHZ_DIS# (58)
WLAN module: Active low. Turn-off WLAN RF

analog and front-end. Internal pull-up.
3 3
+3VALW +3V_PCH +3VALW
+3VS_WLAN
2
2
20K_0402_5%
R325
20K_0402_5%
R324
R193
10K_0201_1% @
From EC GPIO114
1
(58) SLP_WLAN#_GATE Max Current :4A

RON : 30m ohm
2
G
From PCH GPD9/SLP_WLAN# Q20 D62 VIH : 1.2V

1 3 2 +3VALW PVT-170 +3VS_WLAN
(11) SIO_SLP_WLAN# Change to short-pad
U31
D
AUX_EN_WOWL_R
1 C247 +3VS_WLAN_R R169 0_0805_5%
From EC GPIO210/ADC08 L2N7002WT1G_SC-70-3 2 1 1 7 1 @ 2
3 2 VIN_1 VOUT_1 8
(52,58) AUX_EN_WOWL VIN_2 VOUT_2 1
AUX_EN_WOWL_R 1U_0201_6.3V6M 1000P_0402_25V8J
3 6 C239 1 2 C228
BAT54CW_SOT323-3 ON CT
0.1U_0402_10V7K
2
2
+3VALW R188 4
+3VALW VBIAS
100K_0402_5%~D 5 0514
GND_1 9
Due to VBIAS is +3VALW
Change C239 to 1000P
1
GND_2 For 1ms rise time

1
RN111
75K_0201_1% AOZ1336DI_DFN8_2X2
0515
RN111,RN110 75K_ 0 2 0 1 _ 5 %
4 materail prepare issue 4
AUX_EN_WOWL_R
2
Change to 75K_00201_1% 1 2
@ VBIAS range of 2.5 V to 5.5 V
RN109 0_0201_1% VIN <= VBIAS, for RON performance
1
from PCH control D

2 QN6
(10) CNVI_EN#
G L2N7002WT1G_SC-70-3
1
S
3
RN110
@
75K_0201_1%
2
from EC control
Reserved for CNVi power control Security Classification Compal Secret Data Compal Electronics, Inc.
(Doc.573970-1.0) 2018/05/08 2018/05/08 Titl e
(52,58) AUX_EN_WOWL Issued Date Deciphered Date
P052 - WLAN/BT (w/ CNVi)
A B C D E
5 4 3 2 1
WWAN USB or 2nd SSD PCIe For support Intel 7360 WWAN card
+3VALW
1
RN5
@ 100K_0201_5%
M.2 3042 Key-B
2
WWAN_GPIO_CTRL#
From EC
1
D
WWAN_GPIO_CTRL_R @
L2N7002WT1G_SC-70-3
1 @ 2 2
(58) WWAN_GPIO_CTRL RN9 0_0201_5% G QN1
S
3
1
VGS 1.5V +3V_PCH
RN7
+3VS_WWAN +3VS_WWAN +3VS_WWAN @ 10K_0201_5%
CONTROL INPUT ON CHANNEL
USB3#4 S A 1
D U8 Common PCIe/USB3.0 D
2
L B1 @ CN2
USB3/PCIe MUX Choke
@RF@ C230
0.1U_0201_10V6K
PCIe#11 2
22U_0603_6.3V6M
0.1U_0201_10V6K
C211
33P_0201_50V8J
RF@ C212
@RF@ C213
22U_0603_6.3V6M
0.1U_0201_10V6K
C232
33P_0201_50V8J
RF@ C233
47P_0402_50V8J
1 1 1 1 1 1 1 1 1 1 1 1 1 1 H B2
C216
47P_0402_50V8J
C229
47U_0603_6.3V6M
C334
47U_0603_6.3V6M
C335
47U_0603_6.3V6M
C336
47U_0603_6.3V6M
C337
47U_0603_6.3V6M
C338
47U_0603_6.3V6M
C339
WWAN_GPIO_WAKE#_R UN1 WWAN_GPIO_CTRL#
2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 @ 2 1 6
PCH 0509 JNGFF1 (10) WWAN_GPIO_WAKE# RN20 0_0201_5%
PCIE_WAKE# 2
3
B2
GND
S
VCC
5
4
WWAN_PEWAKE#_R
1 2
WWAN_PEWAKE#
PCIE LANE#11,#12 LANE Reversal for INTEL FITc tool @
(47,52,58,68) PCIE_WAKE# @ B1 A RN19 0_0201_5%
PCIe#12 PCIe SN74LVC1G3157DCKR_SC70-6
1 2
closed to pin 64, RN18 @ 0_0201_5%
closed to pin 2, 66 1 2
4 RN114 @ 0_0201_5%
No support WWAN wake in f uture matrix
USB2#7 Common USB2.0
Choke +3VS
2 @ 1
RN11 0_0402_5%
PV T- 1 0 6 +3VS +3VALW
Change to short-pad
INP UT INP UT INP UT OUTP UT
C B A Y
2 @ 1
+3VS_U8 R201 RN10 0_0402_5% L L L L
PCIe/USB 3.0 Mux 1 @ 2

L H L H
0.1U_0201_10V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
1 @ 0_0402_5%
1
C47
C46
1 H L L L
1
C254
RN15 @ CN1 L L
H H
2
2 @ 10K_0201_5% 0.1U_0201_10V6K
UN2 2
U8 3 5
USB3_PTX_C_DRX_P4
2
C40 1 2 0.1U_0201_10V6K 19 1 1 A VCC
(13) USB3_PTX_DRX_P4 USB3_PTX_C_DRX_N4 (11,47,52,66,68,70,79) PCH_PLTRST#_AND WWAN_GPIO_PERST#_R WWAN_PERST#_R WWAN_PERST#
C41 1 2 0.1U_0201_10V6K 18 B0+ VDD 6 1 @ 2 6 B 4 1 @ 2
USB 3.0 #4 (13) USB3_PTX_DRX_N4 B0- VDD +1.8VS (9) WWAN_GPIO_PERST# C Y
17 10 RN17 0_0201_5% 2 RN16 0_0201_5%
(13) USB3_PRX_DTX_P4 B1+ VDD GND
1
10K_0201_5%
(13) USB3_PRX_DTX_N4 16 051 7
Check with WWAN v endor
1
B1-
RN14
PCIE_PTX_C_DRX_P11 PCIE_PTX_WRX_UT_P11_SW WWAN module has internal PU 74AUP1G97GW_SOT363-6
1
(13) PCIE_PTX_DRX_P11 C45 1 2 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 15 3 PCIE_PTX_WRX_UT_N11_SW @ @ RN12
C0+ A0+
10K_0201_5%
RN4
C44 1 2 0.22U_0402_10V6K 14 4 PCIE_PRX_WTX_UR_P11_SW @ 100K_0201_5%
(13) PCIE_PTX_DRX_N11 C0- A0-
13 7 @
PCIE #11 (13) PCIE_PRX_DTX_P11 PCIE_PRX_WTX_UR_N11_SW
2
12 C1+ A1+ 8 DPR (Dy namic Power Reduction)
2
C1- A1- L: Enable the SAR power back of f .
NGFF_CONFIG_1 H: Disable the SAR power back of f , internally pull up
2
9 5 DN5
C SAR_DPR_R C
SEL GND 11 1 2 RN113 1 2
(58) SAR_DPR# @ 0_0201_5%
2 GND 20
PD GND +1.8VS PV T- 1 7 2
SEL=0 A to B 21 RB751S40T1G_SOD523-2 Change to short-pad
SEL=1 A to C PGND
1
PI3PCIE3212ZBEX_TQFN20_2P5X4P5 0509
10K_0201_5%
RN92
Change MOS to diode
PV T- 1 3 0
Remov e Co-lay
2
DN6 +3VS_WWAN +3VS_WWAN
WWAN_WAKE#_R
1 2
(58) WWAN_WAKE#
2
10K_0201_5%
RN95
U S B 3 TP ML1 RB751S40T1G_SOD523-2
PCIE_PTX_WRX_UT_P11_SW EMC@ PCIE_PTX_WRX_UT_P11_SW_CONN
4 3
DN1 @
GPS_DISABLE#_R
USB3TN
PCIE_PTX_WRX_UT_N11_SW PCIE_PTX_WRX_UT_N11_SW_CONN
1 2
(58) GPS_DISABLE#
5
1 2
CMMI21T-670Y-N_4P RB751S40T1G_SOD523-2
CLKREQ_PCIE#2_R
D65 WWAN_RADIO_DIS#_R 6 1 4 3
CLKREQ_PCIE#2 (11)
(58) WWAN_RADIO_DIS# 1 2
RB751S40T1G_SOD523-2 @ @
QN7A QN7B
L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6
RN96 1 @ 2 0_0201_5%
PV T- 0 4 0
Change to short-pad
USB3RP
PCIE_PRX_WTX_UR_P11_SW CMMI21T-670Y-N_4P PCIE_PRX_WTX_UR_P11_SW_CONN
4 3 +3VS_WWAN
USB3 RN
PCIE_PRX_WTX_UR_N11_SW PCIE_PRX_WTX_UR_N11_SW_CONN
1
1 2 +3VS_WWAN
R175
ML2 EMC@ JNGFF1 10K_0201_5% PV T- 0 4 1
Change to short-pad
(58) NGFF_CONFIG_3 1 2 pin 6 : internal pull down 100K ohm,
CONFIG_3 3.3V push pull ty pe
3 4 WWAN_PWR_OFF#_R
2
5 GND 3.3V 6 RN112 1 2
USB20_P7_R WWAN_RADIO_DIS#_R @ 0_0201_5% WWAN_FULL_PWR_EN (12)
7 GND FULL_CARD_PWR_OFF# 8
USB20_N7_R USB_D+ W_DISABLE# 1
9 10 pin 8 : WWAN Enabled C241
USB_D- GPIO_9/DAS/DSS#/LED#1 internal pull up
11 L: WWAN Disabled 0.1U_0201_10V6K
GND H: WWAN Enabled
B WAKE_ON_WWAN# Signal is for power saving. 2
B
When the WWAN needs to wake up the host Solt B & Key B
it will output a one second low pulse 20 2.7 V
21 GPIO_5 22 1.8 V
(58) NGFF_CONFIG_0 WWAN_WAKE#_R
1.8 V 23 CONFIG_0 GPIO_6 24 pin 26 : GPS Enabled
SAR_DPR_R GPIO_11 GPIO_7 GPS_DISABLE#_R internal pull up
DLW21HN900HQ2L_4P CLK_PCIE_P2_R pin 23 : open drain 1.8 V 25 26 L: GPS Disabled
4 3 27 DPR GPIO_10 28 1.8 V H: GPS Enabled
(11) CLK_PCIE_P2 4 3 PCIE_PRX_WTX_UR_N11_SW_CONN GND GPIO_8
PCIE_PRX_WTX_UR_P11_SW_CONN 29 30 UIM_RESET (54)
31 PERN1/USB3RXN/SSIC-RXN UIM-RESET 32
CLK_PCIE_N2_R PERp1/USB3RxP/SSIC-RxP UIM-CLK UIM_CLK (54)
1 2 33 34
(11) CLK_PCIE_N2
1 EMC@ 2 USB 3.0 #4/PCIe #11 PCIE_PTX_WRX_UT_N11_SW_CONN
35 GND UIM-DATA 36
UIM_DATA (54)
PCIE_PTX_WRX_UT_P11_SW_CONN +SIM_PWR
L21 37 PETn1/USB3TxN/SSIC-TxN UIM-PWR 38 1 2
GNSS_SCL R173 @ 0_0201_5% M3042_DEVSLP (13)
39 PETp1/USB3TxP/SSIC-TxP DEVSLP 40 1.8 V R183 1 2
@ 0_0201_5%
41 GND GPIO_0 42 1.8 V
(13) PCIE_PRX_DTX_N12 PERn0/SATA_B+ GPIO_1
43 44 PV T- 0 3 8
(13) PCIE_PRX_DTX_P12 PERp0/SATA_B- GPIO_2 Change to short-pad
PCIE_PTX_C_DRX_N12 45 46
CV2 1 2 0.22U_0402_10V6K 47 GND GPIO_3 48
PCIE #12 (13) PCIE_PTX_DRX_N12
CV1 1 2 0.22U_0402_10V6K
PCIE_PTX_C_DRX_P12
49 PETn0/SATA_A- GPIO_4 50
WWAN_PERST#
(13) PCIE_PTX_DRX_P12 CLKREQ_PCIE#2_R
51 PETp0/SATA_A+ PERST# 52 RN13 1 @ 2 10K_0201_5%
CLK_PCIE_N2_R GND CLKREQ# WWAN_PEWAKE# +3VS_WWAN
CLK_PCIE_P2_R 53 54 RN74 1 @ 2 10K_0201_5%
REFCLKN PEWAKE# +3VS_WWAN
55 56 PV T- 0 3 7
57 REFCLKP NC 58 Change to short-pad
DLW21HN900HQ2L_4P 59 GND NC 60 1.8 V 1 2

1 2
USB20_P7_R
61 ANTCTL0 COEX3 62 1.8 V
R172
R176 1
@
2
0_0201_5% NGFF_COEX3 (52) From WLAN For LTE / Wi-Fi
@ 0_0201_5%
(13) USB20_P7
1 2 PV T- 0 3 9 63 ANTCTL1 COEX2 64 1.8 V
UIM_DET R178 1 @ 2 0_0201_5%
NGFF_COEX2 (52)
coexistence
Change to short-pad ANTCTL2 COEX1 NGFF_COEX1 (52)
USB20_N7_R WWAN_BB_RST#_R 65 66 SUSCLK_L
4 3 RN21 1 2 1.8 V 67 ANTCTL3 SIM DETECT 68 R177 1 2
(13) USB20_N7 (9) WWAN_BB_RST# @ 0_0201_5% NGFF_CONFIG_1 @ 0_0201_5% SUSCLK (11,52,68) CNV_COEX1
4 3 69 RESET# SUSCLK 70 1 2
EMC@
(58) NGFF_CONFIG_1
71 CONFIG_1 3.3V 72
RZ8
1
@
2
0_0201_5% CNV_COEX2 CNV_COEX1 (14) From SOC
L22 RZ7 @ 0_0201_5% CNV_COEX3
GND 3.3V +3VS_WWAN 1 CNV_COEX2 (14)
+1.8VS 73 74 RZ6 1 @ 2 0_0201_5%
75 GND 3.3V C38 051 7 CNV_COEX3 (14)
(58) NGFF_CONFIG_2 @
CONFIG_2 Check with WWAN v endor
0.1U_0402_10V7K Disconnect COEX between WWAN and PCH
1
2
RN105 77 76
10K_0201_5% GND GND
+1.8VS
The Reset# signal is relativ ely sensitiv e, it is LOTES_APCI0144-P007A

WWAN_BB_RST#_R
2
100K_0402_5%
recommended to install one capacitor (10~100pF)
CONN@
State# CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type Port Configuration near to the M.2 card pin.
RZ1417
+1.8VS
1
(Pin 21) (Pin 69) (Pin 75) (Pin 1) 1
100K_0402_5%
0 GND GND GND GND SSD – SATA N/A CN59 @
RZ1418
1
1 GND HIGH GND GND SSD – PCIe N/A 2
47P_0201_25V8J To WWAN module
PIN66: UIM_DET
2
A
2 GND GND HIGH GND WWAN – PCIe 0 UIM_DET
module with internal PU 1.8v
A
3 GND HIGH HIGH GND WWAN – PCIe 1 SIM CONN WWAN Module
4 GND GND GND HIGH WWAN – USB 3.0 0
2
SW pin Detect pin
SIM Card ( U I M_ D E T# ) ( U I M_ D E T )
5 GND HIGH GND HIGH WWAN – USB 3.0 1 From SIM CONN
1
D
SIM_DETECT
6 GND GND HIGH HIGH WWAN – USB 3.0 2 (54) UIM_DET#
2 QZ4 inser t e d Shot to GND f rom logic 0 to logic 1
G LN2316ELT1G_SOT23-3 SIM_DETECT
7 GND HIGH HIGH HIGH WWAN – USB 3.0 3 VGS 0.9V S pulled out Floa t i n g f rom logic 1 to logic 0
3
8 HIGH GND GND GND WWAN – SSIC 0
9 HIGH HIGH GND GND WWAN – SSIC 1
10 HIGH GND HIGH GND WWAN – SSIC 2
11 HIGH HIGH HIGH GND WWAN – SSIC 3
12 HIGH GND GND HIGH WWAN – PCIe 2 Security Classification Compal Secret Data Compal Electronics, Inc.
13 HIGH HIGH GND HIGH WWAN – PCIe 3
14 HIGH GND HIGH HIGH DDP|HCA - PCIe N/A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P053 - WWAN / 2nd SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Document Number Re v
15 HIGH HIGH HIGH HIGH No Module N/A DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4
Date : Thursday, January 31, 2019 Sheet 53 of 100
5 4 3 2 1
5 4 3 2 1
D D
+SIM_PWR
+SIM_PWR
4.7U_0402_6.3V6M
0.1U_0402_10V7K
@RF@ C226
1 1
ESD
UIM_RESET UIM_DATA
C237
JSIM1 2 2
UIM_DATA
7 1 UIM_RESET UIM_CLK UIM_DET#
(53) UIM_DATA
1
IO VCC 2
RESET UIM_CLK UIM_RESET (53)
3 R162
CLOCK UIM_CLK (53)
AZ5123-01F-R7GR_DFN1006P2X2
@ 10K_0201_5%
2
2.2P_0402_50V8C~D
C210
D55
D57
D56
D58
8
GND0 1
9 4 UIM_DET#
2
GND1 GND
2.2P_0402_50V8C~D
C218
2.2P_0402_50V8C~D
C214
10 5 UIM_DATA 1 1
GND2 DET UIM_DET# (53)
33P_0402_50V8J
EMC@
11 6
GND3 VPP 2
RF@ C227
EMC@
EMC@
EMC@
EMC@
2.2P_0402_50V8C~D
C215
12 1
2
GND4
EMC@
EMC@
13
1
14 GND5 2 2
GND6
EMC@
15
C C
1
GND7 2
T-SOL_5-501703002000-6
CONN@
NANO SIM normal Open CONN.

No Card: SW floating UIM_CLK
Card install: SW shot to GND(C5)
2
RF@ C234
47P_0402_50V8J~D
1
1
R165
10K_0201_5%
2
B B
A A
P054 - WWAN nano-SIM
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P055 - Reserve
5 4 3 2 1
5 4 3 2 1
PVT-108
Change to short-pad
RA21 1 @ 2 0_0402_5%
+AVDD1 +5VS_AUDIO
RA13 RA14 RA15 CA19 +DVDD
MONO_IN
(58) BEEP
1 2 1 2 1 2 1 2
RA22 1 @ 2 0_0402_5%
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0_0201_5% 0.1U_0201_10V6K
1
1K_0201_5% 1K_0201_5%
1 @ 1 1
CA4
CA6
CA5
RA29 LA2 1 2 BLM21PG600SN1D_2P
100K_0402_1% RA7 1 @ 2 0_0402_5%
2
2 2 2
2
JACK_PLUG# CA27
RA131 1 @ 2 0_0402_5% 10U_0402_6.3V6M
1
RA16 1
CA40 0510
Moat
(10) SPKR
1 2 0.1U_0402_10V7K Add RA131
2
GN D Moatfor AGND and GND AGND AGND
1
RA28 2
D 1K_0201_5% 1 D
RA17 @ 200K_0402_1%
1K_0201_5% CA7
100P_0201_25V7K Place near UA1 pin26/27
1
2
Beep sound Close to UA1 Pin34
2
(57) HP_PLUG#
HPOUT-R HPOUT-L
330P_0402_50V8J
330P_0402_50V8J
1 1
CA21
CA20
+DVDD
+3V_5105 2 2
1
RA39
10K_0402_5% AGND AGND
Q12
2
G
L2N7002WT1G_SC70-3
2
CODEC_MUTE# 1 UA1
3 1 MONO_IN
NB_MUTE# (58)
34
S
@ CA42
22P_0402_50V8G 6 PCBEEP
1
2 @ 1 2 I2C-DATA 30
HDA_RST#_R (10) MIC2-L/RING2 RING2 (57)
@ 0_0201_5% RA117 7
RA38 PVT- 111 I2C-CLK 31
HDA_SYNC_R MIC2-R/SLEEVE SLEEVE (57)
1K_0201_5% Change to short-pad 15
(10) HDA_SYNC_R SYNC
HDA_BLK_R 36 LINE2-L LINE2-L (57)
2
1 @ 2 14 LINE2-L
(10) HDA_BIT_CLK_R BCLK
RA32 0_0402_5% 35 LINE2-R
HDA_SDOUT_R LINE2-R LINE2-R (57)
PVT-181
(10) HDA_SDOUT_R
17
Base on EMC tream request SDATA-OUT 42
Change fuse from 0.5A to 1A SPK-OUT-L+ SPK_-OUT-L+ (57)
13
RA26 DC-DET/EPAD 43
HDA_SDIN0_R SPK-OUT-L- SPK_-OUT-L- (57)
1A_65V_T0603FF1000TM 1 2 16
(10) HDA_SDIN0 SDATA-IN
RA33 33_0402_5% 44
SPK-OUT-R- SPK_-OUT-R- (57)
1 2 1 11
+3VS_AUDIO I2S-MCLK
2P_0201_25V8B
CA51
45
SPK-OUT-R+ SPK_-OUT-R+ (57)
10
I2S-BCLK 27 HPOUT-L
2 HPOUT-L HPOUT-L (57)
For EMI
RF@
9 26 HPOUT-R
C I2S-OUT HPOUT-R HPOUT-R (57) C
@ RA27 12
1 2
20mA 10mil I2S-LRCK
+1.8VS_AUDIO +DVDD
8
I2S-IN
2.2U_0201_6.3V6M
0.1U_0201_10V6K
0_0402_5% 1 1
CA45
CA38
1
(40) DMIC_DATA34 I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
DMIC_DATA12
4
2 2 DMIC12 to JDMIC1,JDMIC2 DMIC_CLK12 DMIC_CLK_R
GPIO0/DMIC-DATA12
DMIC34 to WF camera RA30 1 2 22_0402_5% 5
GPIO1/DMIC-CLK
PVT-109
Change to short-pad
CODEC_MUTE#
RA31 1 2 22_0402_5% 2 +RTCVCC_EC +3V_PCH
(40) DMIC_CLK34 PDB
JACK_PLUG#
48
PVT- 112
RA30, RA31 close with UA1 pin 5 JD1
1
JD2 RA24 RA19
1 @ 2 0_0402_5% @
+3VS_AUDIO
RA34 0_0402_5%
0_0402_5%
CA24 1 2 10U_0402_6.3V6M 1 2 38
AGND
2
CA22 2.2U_0201_6.3V6M VREF
For EMI 1 2 39 @
AGND LDO1-CAP
RA23 100K_0201_5%
CA23 1 2 10U_0402_6.3V6M 32 33 +AVDD1
10mA 10mil AGND MIC2-CAP 5VSTB/AUX_MODE +AVDD2
+DVDDIO
40
AVDD1
2.2U_0201_6.3V6M
0.1U_0201_10V6K
MIC2-VREFO-R 29
1 1 (57) MIC2-VREFO-R MIC2-VREFO-R 10 mA +DVDD
CA43
CA41
20
(57) MIC2-VREFO-L
MIC2-VREFO-L 28
MIC2-VREFO-L
CPVDD/AVDD2
3
3.3V
@ RA20
1 2 2 2 DVDD
+1.8VS_AUDIO 1
CA52 1 2 1U_0402_10V6K 18 @
DVDD-IO 5 mA +DVDDIO
CA15
0_0402_5% CA26 1 2 1U_0402_10V6K 25 41 0.1U_0201_10V6K
PVDD1
AGND CPVEE PVDD1 2
24 46 PVDD2
CA53 1 2 1U_0402_10V6K CBN PVDD2
CA25 1 2 1U_0402_10V6K 23 49
CBP G
AGND
CA36 2 1 10U_0402_6.3V6M 21
LDO2-CAP AVSS1
37 +AVDD1 5V
B CA16 1 2 10U_0402_6.3V6M 19 22 B
LDO3-CAP AVSS2
DMIC_DATA12
RA37 1 2 100K_0201_5%
RA36 2 1 100K_0201_5%
DMIC_DATA34 50 mA CA22,CA23 close to pin 40
ALC3254-VA3-CG_MQFN48_6X6
10U_0402_6.3V6M
CA28
0.1U_0201_10V6K
CA29
AGND 1
2
+DVDD PVT- 113
Change to short-pad LRSEL select at DMIC module PVT-107
DMIC_CLK34 Pull Lo: Lef t channel Change to short-pad
DMIC_DATA12 Pull Hi: Right channel 2A
1
JDMIC2 2
DMIC_DATA34 +DVDD_RA41 DMIC_CLK12_C DMIC_CLK12_R DMIC_CLK12
1 @ 2 1 2 1 RA123 2 1 @ 2 +5VS_AUDIO
RA41 3 1 2 4
0_0402_5%
3 4 DMIC_DATA12_CBLM15HD601SN1D_0402 DMIC_DATA12_R RA3 0_0402_5% DMIC_DATA12 Bead 3A
1 5 6 1 RA124 2 1 @ 2 PVT-145
5 6 Rated current
CA3
0.1U_0201_10V6K
7 8 BLM15HD601SN1D_0402 RA1 0_0402_5% Change to short-pad AGND

1
7 8
33P_0402_50V8J
@EMC@ C197
33P_0402_50V8J
@EMC@ C198
33P_0402_50V8J
@EMC@ C205
9 10 1 @ 2 LA1
9 10 PCH_DMIC_DATA0 (10)
RA122 0_0402_5% PVDD1 LA3 1 @ 2 0_0603_5% 1 2
2 1 @ 2
2
PCH_DMIC_CLK0 (10)
11 13 RA121 0_0402_5% BLM21PG600SN1D_2P
GND GND
10U_0402_6.3V6M
0.1U_0201_10V6K
CA32
12 14 1
2
GND GND
CA30
CA33
Intel DMIC PVT- 110
CA31 Change to short-pad+1.8VS_AUDIO
HRS_BM20B(0P8)10DS0P4V(51) CA25, CA26 close to pin 41
CONN@
for WOV reserved +AVDD2
1
1
0.1U_0201_10V6K
10U_0402_6.3V6M
2
RA25
+DVDD PVT- 114
200 mA 2 @ 1
2
Change to short-pad LRSEL select at DMIC module PVDD2 LA4 1 @ 2 0_0603_5% 2
DMIC_DATA34 Pull Lo: Lef t channel
0.1U_0201_10V6K
CA34
10U_0402_6.3V6M
DMIC_DATA12 Pull Hi: Right channel 1
2
JDMIC1 0_0402_5%
DMIC_CLK12 +DVDD_RA18 DMIC_CLK12_C @
10U_0402_6.3V6M
0.1U_0201_10V6K
CA35
1 @ 2 1 2 1
1
1 2
CA47
CA44
RA18 0_0402_5% 3 4 DMIC_DATA12_C CA24,CA29 close to pin 20
1
3 4 2
CA14
0.1U_0201_10V6K
1 5 6 CA30, CA31 close to pin 46 AGND

7 5 6 8
2
9 7 8 10 2
9 10
22P_0201_25V8
22P_0201_25V8
22P_0201_25V8
1 1 1 AGND
2
CA46 @EMC@
CA39 @EMC@
CA37 @EMC@
11 13
12 GND GND 14
2 2 2 GND GND
HRS_BM20B(0P8)10DS0P4V(51)
CONN@
A A

P056 - Audio_ALC3254
D a te : Wednesday, February 27, 2019 She e t 56 of 100
5 4 3 2 1
5 4 3 2 1
Int. Speaker Conn.

40mil = For 4ohm 3W Speaker
+3V_PCH
RA43
SPK_L+ SPK_L+ SPK_DET#
EMC@ LA8 1 2 BLM15PX181SN1D_2P SPK_L- SPK_L- 2 1
(56) SPK_-OUT-L+
EMC@ LA7 1 2 BLM15PX181SN1D_2P
(56) SPK_-OUT-L-
10K_0402_5%
3
2
1000P_0402_50V7K~D
CA12
1000P_0402_50V7K~D
CA11
DA6
D 1 1 D
JSPK1
@EMC@
@EMC@
EMC@
SPK_L+
2 2 1
SPK_L-
1
2 1
SPK_R+ 2
SPK_R- 3
4 3
RA42 2 @ 1 0_0402_5% 5 4 7
(10) SPK_DET# 5 GND
6 8
6 GND
Int. Speaker Conn. PVT- 115

Change to short-pad
ACES_50376-00601-P01
CONN@
40mil = For 4ohm 3W Speaker

SPK_R+ SPK_R+
EMC@ LA6 1 2 BLM15PX181SN1D_2P SPK_R- SPK_R-
(56) SPK_-OUT-R+
EMC@ LA5 1 2 BLM15PX181SN1D_2P
(56) SPK_-OUT-R-
Speaker
SPK_DET# (SPK_ID) Vendor
2
1000P_0402_50V7K~D
CA10
1000P_0402_50V7K~D
CA13
DA7
1 1 High FG
@EMC@
@EMC@
EMC@
2 2 Low YC
1
Universal Audio Jack
C C
HPOUT-L_L EMC@ HPOL_CONN

RA121 2 16.2_0402_1% L5 1 2 BLM15AX700SN1D_2P
(56) HPOUT-L
HPOUT-R_L HPOR_CONN
RA111 2 16.2_0402_1% L4 1 2 BLM15AX700SN1D_2P
(56) HPOUT-R
EMC@
1 2 EMC@ EMC@
Universal Audio Jack CONN
1
(56) LINE2-L
1000P_0201_50V7K
1000P_0201_50V7K
CA17 10U_0603_6.3V6M
DA2
DA3
1 2 Audio Audio
(56) LINE2-R
1
Signa l CONN PIN
CA49
CA50
CA18 10U_0603_6.3V6M
Vendor recommend RING2_CONN #3 G/M
2
keep 0603 size at CA17,CA18 for Line in THD+N concern. JA1
RING2_CONN
2
use X5R for better performance PVT-042 HPOL_CONN
3 HPOL_CONN #1 L/R
HPOR_CO NN #2 R/L
RA9 1 2 2.2K_0201_5% RA8 HP_PLUG#_R 5
(56) MIC2-VREFO-L
AGND AGND (56) HP_PLUG#
1 @ 2 HPOR_CONN 6 SLEEV E_CONN #4 M/G
RA10 1 2 2.2K_0201_5% SLEEVE_CONN
2
(56) MIC2-VREFO-R
0_0201_5% 4 HP_PLUG#_R #6
EMC@ A GND #5
40mil L6 1 2 BLM15PX330SN1D_2P
SLEEVE_CONN
SINGA_2SJ3098-027111F
(56) SLEEVE
1
EMC@ RING2_CONN CONN@
L3 1 2 BLM15PX330SN1D_2P DA4
(56) RING2
EMC@
40mil EMC@ EMC@
1
1000P_0201_50V7K
1000P_0201_50V7K
2
DA1
DA5
1
1
CA1
CA2
AGND
2
B B
AGND AGND
+3VS_WWAN +3VS_WWAN +5VS_AUDIO

+1.8VS_AUDIO +3VS_AUDIO
PVT-171
Max Current : 6A R308 0_0805_5%
RON : 20m ohm 1 @ 2
Max Current : 6A
VIH : 1.2V +5VS_AUDIO
UZ2 +3VS_WWAN_R
+5VALW RON : 20m ohm
1
VIN1_1 VOUT1_1
14 1 C175 VIH : 1.2V PVT-166
2 13 1U_0201_6.3V6M U26 Change to short-pad
VIN1_2 VOUT1_2 +5VS_AUDIO_R
C220 2 1 1 14 1 @ 2 1
3 12 1 2 2 VIN1_1 VOUT1_1 13 R142
(58) 3.3V_WWAN_EN 0.1U_0402_10V7K 0_0805_5%
ON1 CT1 C240 1000P_0402_25V8J 2 VIN1_2 VOUT1_2 C202
AUD_PWR_EN
4 11 3 12 C201 1 2 220P_0402_50V8K 0.1U_0402_10V7K
+3VALW VBIAS GND (10) AUD_PWR_EN ON1 CT1
2
2
AUD_PWR_EN
RZ13 5 10 1 2 +3VS 4 11
ON2 CT2 +5VALW VBIAS GND
C172 1000P_0402_25V8J +1.8VS_AUDIO
100K_0402_5% AUD_PWR_EN
+1.8VA 6 9 R126 2 1 100K_0402_5%~D 5 10 C182 1 2 1000P_0402_25V8J +3VS_AUDIO
VIN2_1 VOUT2_1 AUD_PWR_EN ON2 CT2
C164 7 8 +1.8VS_AUDIO_R R125 2 @ 1 100K_0402_5%~D
1
1U_0201_6.3V6M VIN2-2 VOUT2_2 1 @ 2 6 9

VIN2_1 VOUT2_1 +3VS_AUDIO_R
2 1 15 R122 0_0603_5% 7 8 1 @ 2
GPAD +3VALW +3VALW VIN2-2 VOUT2_2 R136 0_0603_5%
1
A AOZ1331DI_DFN_14 PVT-156 15 A
Change to short-pad GPAD 1
0514 C171
Change C172,C240 to 1000P 0.1U_0402_10V7K 1 AOZ1331DI_DFN_14 PVT-158 C191
For 1ms rise time 2 Change to short-pad 0.1U_0201_10V6K
C181 2
1U_0201_6.3V6K
2

P057 - Audio Jack/Speaker
5 4 3 2 1
5 4 3 2 1
BOARD_ID rise t i me i s meas ur ed fr o m 5 %~68 %.

+3V_5105 TYPEC_ID rise time is measured from 5%~68%.
R C REV
RE343 CE62 REV
240K 4700p EVT +3VALW
Single Port ACE w/o AR
240K 4700p
1
PVT-165
Change to short-pad RE53 130K 4700p DVT 1 Single Port ACE w/AR
R 130K 4700p
1
240K_0402_5% @
+1.8VA +1.8VA_EC +3V_5105 62K 4700p DVT 2 RE539
Dual Port ACE w/o AR
+3VALW 33K_0201_5% 62K 4700p
33K 4700p PVT
2
RE63 +RTC_CELL_VBAT BOARD_ID
1 2 * 33K 4700p Dual Port ACE w/AR
@ +RTCVCC_EC TYPEC_ID
8.2K 4700p
2
10U_0402_6.3V6M
CE31 1 @ 2 PVT-116
CE19
1
0_0603_5%
1
0.1U_0201_10V6K RE51 0_0603_5% Change to short-pad 8.2K 4700p Dual Port ACE (w/AR +w/o AR)
4.3K 4700p 1
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K Close to EC 1
4.3K 4700p
1
CE35
2 @ 1 CE116
1 1
C 2K 4700p
1
2 2
CE12
CE26
CE37
PVT-164 CE6 4700P_0402_25V7K
Change to short-pad RE104 4700P_0402_25V7K 2 2K 4700p
1
1K 4700p
2
0_0402_5% 2 0512
1K 4700p
2
2 2 CE30 Change to common part
+3V_5105 0.1U_0201_10V6K 2 +3V_5105
RE68 2 1 100_0402_1% UE4@ TYPEC_ID

+3V_5105 +VSS_PLL F2 UPD2_SMBDAT
GPIO033/RC_ID0
@
+3V_5105 CE18 2 1 22U_0603_6.3V6M A2 J10 BOARD_ID UPD2_SMBCLK RE6 1 2 2.2K_0201_5%
D VBAT GPIO034/RC_ID1/SPI0_CLK EDP_HPD_EC (38) D
J13 UPD2_SMBDAT UPD2_SMBINT# RE5 1 2 2.2K_0201_5%
2 1 B7 GPIO036/RC_ID2/SPI0_MISO E7 1 2 100K_0201_5%
BT_RADIO_DIS# UPD2_SMBCLK RE15
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# UPD2_SMBDAT (45)
RE66 1 2 100K_0201_5% CE10 0.1U_0201_10V6K D7 UPD1_SMBDAT
SIO_SLP_SUS#_R K2 GPIO004/SMB00_CLK/SPI0_MOSI UPD2_SMBCLK (45) UPD1_SMBCLK RE80 1 2 2.2K_0201_5%
RE529 1 @NDS3@2 100K_0201_5% +3.3V_EC_PLL VREF_ADC G3 RUNPWROK
GPS_DISABLE# UPD1_SMBINT# RE101 1 2 2.2K_0201_5%
1 GPIO057/VCC_PWRGD
WWAN_WAKE# +3V_5105 F1 H5 RE62 1 2 100K_0201_5%
1 2 VTR_PLL GPIO060/KBRST/48MHZ_OUT G11 GPS_DISABLE# (53)
RE97 10K_0201_5% CE11 ME_FWP IMVP_SMBDAT
GPIO104/UART0_TX HOST_DEBUG_TX (79)
FPR_DET# 0.1U_0201_10V6K 1 2 H1 G12 IMVP_SMBCLK RE112 1 2 1K_0201_5%
1 2 2 VTR_REG GPIO105/UART0_RX B13 ME_FWP (10) 1 2 1K_0201_5%
RE530 100K_0201_5% CE38 0.1U_0201_10V6K UPD1_SMBINT# RE119
1 2 G8 GPIO127/A20M/UART0_CTS# F10 RTCRST_ON_POWER (49)
WLAN_WIGIG60GHZ_DIS# PBAT_CHARGER_SMBCLK
VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# (43)
RE2 1 2 100K_0402_5% CE16 0.1U_0201_10V6K M9 PCIE_WAKE#_R PBAT_CHARGER_SMBDAT RE88 1 2 2.2K_0201_5%
VTR3(+1.8V) N5 VTR2 N13 RE91 1 2 2.2K_0201_5%
LID_CL_SIO# +1.8VA_EC
RE42 1 2 100K_0201_5% VTR3 VTR3 +1.8V GPIO025/TIN0/nEM_INT/UART_CLK N12
PCH_DPWROK_EC FPR_PWR_EN# USH_EXPANDER_SMBDAT
2 GPIO026/TIN1 DOCK_PWR_EN_2in1 (78)
(11) PCH_DPWROK
RE82 DS3@1 0_0402_5% RUN_ON_EC F8 M11
FPR_PWR_EN# (78)
USH_EXPANDER_SMBCLK RE55 1 2 2.2K_0201_5%
BASE_SMBDAT_2IN1 SIO_EXT_WAKE#_EC E8 GPIO020 GPIO027/TIN2 H9 RE110 1 2 2.2K_0201_5%
(78) RUN_ON_EC GPIO045 GPIO030/TIN3
RE95 1 2 1K_0201_5% BASE_SMBCLK_2IN1 RE1 2 @ 1 0_0402_5% BT_RADIO_DIS# M12 VOL_UP#_2in1
1 2 (12) SIO_EXT_WAKE# C2 GPIO120 L9
RE74 1K_0201_5% PVT-129 (52) BT_RADIO_DIS# PBAT_PRES# NGFF_CONFIG_1 VOL_UP#_2in1 (77)
Change to short-pad GPIO166 GPIO017/GPTP-IN5
AC_DIS SIO_SLP_SUS#_R F9 M10 NGFF_CONFIG_0 NGFF_CONFIG_0
1 2 1 2 43K_0201_1% N4 GPIO175 GPIO151/ICT4 N9 NGFF_CONFIG_1 (53) 2 1
RE533 @ 100K_0201_5% RE3 NGFF_CONFIG_1 100K_0201_5% RE31
(11,78) SIO_SLP_SUS# M8 GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 (53) 2 1
BCM5882_ALERT# I7I5CPU_ID NGFF_CONFIG_2 100K_0201_5% RE43
(38) PANEL_PWRGD GPIO231
RE534 1 2 4.7K_0201_5% K8 C11 NGFF_CONFIG_3 100K_0201_5% 2 1 RE41
(11) AC_PRESENT GPIO233 GPIO156/LED0 D10 2 1
USH_DET# BAT1_LED# (77) 100K_0201_5% RE64
GPIO157/LED1
RE535 1 2 100K_0201_5% E11 D11
(9) SML1_SMBDATA GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# (77)
WWAN_RADIO_DIS# PCH (9) SML1_SMBCLK
WWAN_WAKE# D8
GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3
E1
LCD_VCC_TEST_EN (38)
RE61 1 2 100K_0201_5% M13 USH_EXPANDER_SMBDAT
(53) WWAN_WAKE# GPIO110/PS2_CLK2
FPR_UEFI_MGMT# WLAN_WIGIG60GHZ_DIS# K12 E5 USH_EXPANDER_SMBCLK
GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT (64,73)
RE541 2 1 100K_0201_5% L13 B3
(52) WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 USH_EXPANDER_SMBCLK (64,73)
USB_DB_DET# 0514 K11 M7 SAR_DPR# GPS_DISABLE#
Assign USB_DB_DET# (7,11,79) SIO_PWRBTN# GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 VCCDSW_EN (11)
RE546 1 2 100K_0201_5% LID_CL_SIO# K10 M4 PBAT_CHARGER_SMBDAT RE14 1 2 100K_0201_5%
for USB board (52) SLP_WLAN#_GATE GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 SAR_DPR# (53)
BASE_SMBDAT_2IN1 N11 M3 PBAT_CHARGER_SMBCLK ME_FWP
GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBDAT (82,83)
BASE_SMBCLK_2IN1 E10 N2 NGFF_CONFIG_2 RE94 1 @ 2 10K_0201_5%
(74) BASE_SMBDAT_2IN1 GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK (82,83)
C12 N10 FPR_PWR_EN#
(74) BASE_SMBCLK_2IN1 GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA NGFF_CONFIG_2 (53)
A12 IMVP_SMBDAT RE214 1 2 100K_0201_5%
RUN_ON_EC E9 GPIO140/SMB06_CLK/ICT5 B6 IMVP_SMBCLK SAR_DPR#
(79) JTAG_TDI GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# IMVP_SMBDAT (73,90)
RE117 1 2 100K_0201_5% F6 F7 UPD1_SMBDAT RE72 1 2 2.2K_0201_5%
(79) JTAG_TDO C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 IMVP_SMBCLK (73,90)
TBT_RESET_N_EC UPD1_SMBCLK BASE_SMB_ALERT#_2IN1
1 2 (79) JTAG_CLK C5 GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# C3 UPD1_SMBDAT (43) 1 2 10K_0201_5%
RE11 100K_0201_5% JTAG_RST# RE73
(79) JTAG_TMS GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK (43)
LCD_TST G13 I_BATT_R PCIE_WAKE#_R
RE60 1 @ 2 100K_0201_5% 0512 JTAG_RST# J4 I_SYS_R RE69 1 2 300_0402_5% RE105 1 2 10K_0201_5%
LCD_TEST panel PD 10K E3 GPIO200/ADC00 J5 1 2 I_BATT (83)
EN_INVPWR (77) TACH_FAN1 TBT_RESET_N_EC NB_MODE#_2IN1 RE52 300_0402_5% I_SYS (83,90) VOL_UP#_2in1
RE76 1 2 100K_0201_5% LCD_TST D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6 BASE_SMB_ALERT#_2IN1 RE17 1 @ 2 0_0201_5% RE120 1 2 10K_0201_5%
(43,45,47) TBT_RESET_N_EC M2 GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 G2 ISH_NB_MODE# (12)
IMVP_VR_ON PVT-047 USH_PWR_STATE# PCH_PCIE_WAKE#
Change to short-pad (38) LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 BASE_SMB_ALERT#_2IN1 (74)
RE75 1 2 100K_0201_5% CNV_DET# L10 H2 USH_PWR_STATE# (73) RE54 1 @ 2 10K_0201_5%
1 2 (77) PWM_FAN1 L11 GPIO053/PWM0/GPWM0 GPIO204/ADC04 J2
SYS_PWROK (52) CNV_RF_RST @ PCH_RSMRST# USB_POWERSHARE_ENL# VOL_DOWN#_2in1
GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POWERSHARE_VBUS_EN_L (73)
RE99 1 2 10K_0201_5% RE48 1 @ 20_0201_5% ISH_TABLE_MODE#_R M5 J3 CPU_ID 0513 RE545 1 2 10K_0201_5%
(7,11,63) PCH_RSMRST#_AND GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 USB_POWERSHARE_ENL# (73) VOL_DOWN# PU 10K SSD_SCP#
(12) ISH_TABLE_MODE# RE542 1 @ 20_0201_5% J8 K3 AUX_EN_WOWL
N1 GPIO056/PWM3/SHD_CLK GPIO207/ADC07 D3 1 2 100K_0201_5%
RE544 0_0201_5% CPU_C10_GATE#_Q SUS_ON_EC_R PVT-056 RE28 @
(38) BIA_PWM_EC GPIO001/PWM4 GPIO210/ADC08 AUX_EN_WOWL (52) Change to short-pad
1 @ 2 L8 D2 RE547 1 @ 2 0_0201_5%
(14,78,89) CPU_C10_GATE# GPIO002/PWM5 GPIO211/ADC09 SUS_ON_EC (11)
RE556 0_0201_5% SOLC N6 E2 VOL_DOWN#_2in1 THERMTRIP1# RE108 1 2 10K_0201_5%
(38) SOLC GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 DET_R#_2in1 (82)
J9 G5 UPD2_SMBINT# USB_POWERSHARE_ENL#
(38)
PANEL_BKEN_EC GPIO015/PWM7 GPIO213/ADC11 VOL_DOWN#_2in1 (77)
FPR_DET# H11 F5 RE506 1 2 100K_0201_5%
(56) BEEP GPIO035/PWM8/CTOUT1 GPIO214/ADC12 UPD2_SMBINT# (45)
+1.8VA_EC AC_DIS D9 K4 PCH_PCIE_WAKE#
(77) FPR_DET# GPIO133/PWM9 GPIO215/ADC13 DCIN2_EN (82)
BCM5882_ALERT# H12 L1
(83) AC_DIS G10 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 L3
SAR_ACT# 0513 PVT-055
2 1 Add RE543 for SAR_ACT# (73) BCM5882_ALERT# H10 GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# (11) Change toUPD_HPD
short-pad
RE543 100K_0201_5% (79) MSCLK MSCLK UPD_HPD_2in1
MSDATA G9 GPIO170/TFDP_CLK/UART1_TX H8 RE540 1 2
(79) MSDATA @ 0_0201_5%
GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ J7 SSD_SCP#
+3VALW A4 GPIO223/SHD_IO0 L6 3.3V_TS_EN (68)
EN_INVPWR PRIM_PWRGD SSD_SCP# (68)
+RTCVCC_EC (56) NB_MUTE# B2 GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7
RESET_IN#
C 2 1 (38) EN_INVPWR IMVP_VR_ON C1 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 M6 C
GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS2_ECOK (82)
RE46 100K_0201_5% FPR_UEFI_MGMT# N7
(78) IMVP_VR_ON
2
K9 GPIO031/GPTP-OUT1 D6 BGPO0 RE538 1 @ 2 0_0201_5%

Power SW RE89
100K_0201_5%
(77) FPR_UEFI_MGMT#
(63) M_BIST
N8 GPIO032/GPTP-OUT0
GPI0040/GPTP-OUT2
VBAT powered control pin BGPO0
GPIO164/VCI_OVRD_IN
C7
A5 ALWON
POWER_SW_IN# RE86 1 ACAV_IN
@ 2 (63,83,94)
0_0201_5% VCI_IN1#
+RTCVCC_EC
F13 VCI_OUT D5 ALWON_PWR (84,85,94) 1 2

VCI_IN1# VCI_IN2# RE100 100K_0201_5%
POWER_SW_IN# (47) RTD3_SELECT USH_DET# E13 GPIO121/PVT_IO0 GPIO163/VCI_IN0# B5 VCI_IN2# PVT-050 VCI_IN3# RE102 1 2 100K_0201_5%
1
1 2 (82) AC_DISC# C13 GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# D4 Change to short-pad 1 2

(73) USH_DET# VCI_IN3# RE12 100K_0201_5%
(63,77,79) PWRBTN# +RTCVCC_EC GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2#
RE111 1K_0201_5% 1 E12 E4
(74,82) DET_L#_2in1 GPIO126/PVT_IO3 GPIO000/VCI_IN3#
1
@ CE32 WWAN_RADIO_DIS# F11
(49) RTCRST_ON
1
2.2U_0201_6.3V6M F12 GPIO122/BCM0_DAT/PVT_IO1 C6

CE39 USB_DB_DET#
2 (53) WWAN_RADIO_DIS# D12 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN (57)
0.1U_0201_10V6K RE45 32KHZ_OUT
2 (73) USB_DB_DET# GPIO046/BCM1_DAT
@
1K_0201_5% D13 F3 CE27 1 2 10P_0402_50V8J

NGFF_CONFIG_3 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT @
SYSPWR_PRES F4 +PECI_VREF
2
(53) NGFF_CONFIG_3 GPIO041/SYS_SHDN#

+3VALW SAR_ACT# B1 J11 PECI_EC_R
VTR3(+1.8V) K7 SYSPWR_PRES GPIO044/VREF_VTT K13 RE65 1 2 43_0201_5% ALWON RE90 1 2 100K_0201_5%
(64) SAR_ACT# GPIO011/nSMI VTR3 +1.8V GPIO042/PECI_DAT/SB-TSI_DAT PECI_EC (7)
1
N3 J12 REM_DIODE1_N USH_PWR_STATE#

1
(82) VBUS1_ECOK K6 GPIO021/LPCPD# GPIO043/SB-TSI_CLK A8 1 2 2200P_0402_50V7K M3042_PCIE#_SATA (13) 1 2

@ RE56 VTR3(+1.8V) REM_DIODE1_P CE29 RE58 1M_0201_5%
(9,79) ESPI_RESET# H7 GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A A7
R63 100K_0201_5% VTR3(+1.8V) REM_DIODE2_N ME_FWP
NB_LID 47K_0201_5% (53)
(9) ESPI_ALERT#
WWAN_GPIO_CTRL
VTR3(+1.8V)
VTR3(+1.8V)
K1
G7
GPIO063/SER_IRQ/ESPI_ALERT#
GPIO064/LRESET#
DP1_DN1A
DN2_DP2A
A10
A9
REM_DIODE2_P
REM_DIODE3_N
CE17 1 2 2200P_0402_50V7K
I_BATT_R
RE215 1 @ 2 10K_0201_5%
0513
2
(9,79) ESPI_CLK_5105 GPIO065/PCI_CLK/ESPI_CLK VTR3 +1.8V DP2_DN2A BPCC function

LID_CL_SIO# VTR3(+1.8V) H6 B9 REM_DIODE3_P CE22 1 2 2200P_0402_50V7K CE21 1 2 2200P_0402_50V7K
2
(9,79) ESPI_CS# GPIO066/LFRAME#/ESPI_CS# VTR3 +1.8V DN3_DP3A CE21 change to 2200P

1 @ 2 VTR3(+1.8V) K5 B8 I_SYS_R sync with Merion
(63) LID_CL#_NB (9,79) ESPI_IO0 L4 GPIO070/LAD0/ESPI_IO0 VTR3 +1.8V DP3_DN3A A11 1 2 2200P_0402_50V7K
RE193 0_0201_5% 1 VTR3(+1.8V) OTP Setting CE24
(9,79) ESPI_IO1 VTR3(+1.8V) G6 GPIO071/LAD1/ESPI_IO1 VTR3 +1.8V DN4_DP4A B10 +VR_CAP Rest=1.58K , Tp=96 degree
PVT-054 C37 PVT-053 (9,79) ESPI_IO2 VTR3(+1.8V) L5 GPIO072/LAD2/ESPI_IO2 VTR3 +1.8V DP4_DN4A C10 Rest=1.50K , Tp=95 degree RE34 1 @ 2 10K_0201_5%
ENABLE_DS# VSET_5105
Change to short-pad Change to short-pad (9,79) ESPI_IO3 VTR3(+1.8V) L2 GPIO073/LAD3/ESPI_IO3 VTR3 +1.8V VIN C9 Rest=1.33K , Tp=93 degree
2
100P_0201_50V8J GPIO067/CLKRUN# VTR3 +1.8V VSET
0.1U_0402_10V7K
RE555 1 @ 2 0_0201_5% SYS_PWROK RESET_OUT VTR3(+1.8V) M1 B11 SOLC RE528 1 @ 2 100K_0201_5%
1 (68)
2 SSD_SCP_PWR_EN G4 GPIO100/nEC_SCI VTR3 +1.8V VCP H3 I_ADP (83)
@ THERMTRIP2# AUX_EN_WOWL
VSS_ANALOG
1
1
(7,11) SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2#
CE33
DC6 RE158 0_0201_5% L12 B12 PROCHOT#_R1
THERMTRIP1# RE13 1 @ 2 100K_0201_5%
1 2 (82) DCIN1_EN GPIO107/nSMI THERMTRIP1# H13 1 2
MEC_XTAL1 RE103 VBUS1_ECOK
VSS_ADC
VSS_PLL
ISH_LID_CL#_NB (7,12) GPIO160/PWM11/PROCHOT# H_PROCHOT# (7,83,86,90)
VR_CAP
MEC_XTAL2 A1 RE96 100_0402_5% RE92 1 2 100K_0201_5%
A3 XTAL1 VSS1 2
VSS2
VSS3
RB751S40T1G_SOD523-2 1.5K_0402_1%
XTAL2
2
1
32 KHz Clock RE179 MEC5105_WFBGA169_11X11

A6
A13
E6
H4
J1
C4
G1
0_0201_5%
1U_0201_6.3V6M
+3VALW +1.8VA_EC +3V_5105 ESPI_CLK_5105 32.768KHZ_9.0PF_9H03200033 +3V_5105
Y2
2
100K_0201_5%
1 2 +VSS_PLL
+VR_CAP
1
1
RE548
10K_0201_5%
+1.0V_VCCST
33_0402_5%
1
1
RE79
@EMC@
RE8 RE10 PVT-048

100K_0201_5% @NDS3@ 100K_0201_5% CE15 CE34 U22EC@ +PECI_VREF Change to short-pad
RE84
10P_0402_50V8J 10P_0402_50V8J 1 2
CPU_ID @
2
ENABLE_DS# JTAG_RST# CPU_ID RE67 0_0201_5%

2
2
PBAT_PRES# 1
2
CE36
+3.3V_TBAT_LDO
HIGH U22
2
33P_0402_50V8J
SHORT PADS
1U_0201_6.3V6M
CE14
1
1
RE106
100_0201_1%
RE4
RE549
10K_0201_5%
D
@EMC@
1 0.1U_0201_10V6K
1
2 RE9 2
LOW U42
CE25
CE20
G DS3@ 100K_0201_5% U42EC@

1
S L2N7002WT1G_SC-70-3
3
2
RE7 QE1 Deep Sleep support @
2
2
2M_0201_5% @
non Deep Sleep 1

2
0512 +3V_5105
B Deep Sleep 0 NC RE84,CE20 +3V_5105 B
PVT-001
1
RE553
10K_0201_5%
modify U102 from SA00000OJ00 to SA000054300 1 2
C378 0.1U_0201_10V6K
CPUI7EC@
5
RE551 1 2 0_0201_5% 1 UPD_HPD I7I5CPU_ID

I7I5CPU_I D
@
P
(43,47) TBT_A_HPD
2
INB 4
1 2 0_0201_5% 2 O
(45,47) TBT_B_HPD RE552 @ HIGH I7 CPU PVT-046
INA
G
Change to shortpad
PCIE_WAKE# (47,52,53,68)
1
RE554
10K_0201_5%
PVT-057 U102 RE550
3

MC74VHC1G32DFT2G_SC70-5 100K_0201_5% PCIE_WAKE#_R PCH_PCIE_WAKE#
CPUI5EC@
LOW I5 CPU 1 2 1 2
@ @ PCH_PCIE_WAKE# (11,47)
RE36 0_0201_5% RE35 0_0201_5%
2
2
(PCH_PCIE_WAKE# should be output with OD)
2
R194
100K_0201_5%
PVT-043
Change to shortpad
1
ALW_PWRGD_3V_5V
1 @ 2
(11) ALW_PWRGD_3V_5V 3VALW_PG (84)
RC265 0_0201_5%
1 @ 2
5VALW_PG (85)
RC253 0_0201_5%
+3VS
Thermal diode mapping

OTP thermal diode
2
RE77
10K_0201_5% 5105 Channel Locat i on REM_DIODE3_P
PVT-052
100P_0402_50V8J
Change to short-pad Q4
DP1/DN1 CPU
1
1
CE1
ALLSYS_PWRGD D59 ALW_PWRGD_3V_5V 1 C

@
RUNPWROK 1 2 2 1 2 RE47
(79) RUNPWROK RE107
@ Ambient FAN 2
8.2K_0201_5%
1
0_0201_5%
RB751S40T1G_SOD523-2 DP1A/DN1A (At USB board) E
B
MMBT3904WH_SOT323-3 +1.0VS_VCCIO
+3VALW THERMTRIP2#
3
2 REM_DIODE3_N
SIO_SLP_S3# (11,47,78,79)
1
MMBT3904WH_SOT323-3
0.1U_0402_25V6
CE7
@ QE3
DP2/DN2 SSD
2
1 2
G
@ +1.2V_DDR_PG (86)
1
RE23 0_0201_5% REM_DIODE3_N C
2
QE4
+3VS 1 3 1 2 2
DP2A/DN2A AR RE71 2.2K_0201_5% B
S
100P_0402_50V8J
Reserv e f or S3 no power issue (+5V_RUN Q6 +1.0V_VCCST E
3
2
1
CE2
1 @ 2 discharge circuit) L2N7002WT1G_SC-70-3

VCCIO_PG (89) DP3/DN3 FAN 1 C 0508
@
RE22 0_0201_5% RE59 +3VALW 2

10K_0201_5% @ +5VS B
Memory 1 @ 2
RE71 change to 2.2K
(7) H_THERMTRIP#
MMBT3904WH_SOT323-3 RE98 0_0201_5%
DP3A/DN3A Memory E
3
ALLSYS_PWRGD_R 2 REM_DIODE3_P
1
1 @ 2 @ PVT-051
RE121 0_0201_5% RE57 RE213 Change to shortpad 0514
100K_0201_5% 100_0201_5% IC(sat) = (3.3-0.2)/8.2k = 0.378mA
IB = (1-0.85)/2.2k = 0.0682mA
PVT-044 REM_DIODE2_N REM_DIODE2_P HFE = 125
6
Change to shortpad @ QE11 IB x HFE = IC = 0.0682mA x 125 = 8.52mA > IC(sat)

1
1 2
QE5A L2N7002WT1G_SC-70-3 (BJT in Saturation mode)

100P_0402_50V8J
A +3V_PCH L2N7002DW1T1G_SC88-6 RUN_ON_P# D Q14 Q13 A

1
1
1
@
CE5
2 2 C C
1
@
2 2
G
AR SSD
1
S B CE4 B
3
RE33 2 MMBT3904WH_SOT323-3 100P_0402_50V8J E MMBT3904WH_SOT323-3

E
1
3
3
PVT-049 100K_0201_5% 2
REM_DIODE2_P REM_DIODE2_N
Change to short-pad
PRIM_PWRGD PRIM_PWRGD_R REM_DIODE1_P
2
1 @ 2 1 @ 2 QE5B 5
(79) PRIM_PWRGD 1.8VA_PG (87) RUN_ON_P (68,78) REM_DIODE1_P (73)
RE78 0_0201_5% RE26 0_0201_5% L2N7002DW1T1G_SC88-6
100P_0402_50V8J
1 @ 2 Q19
1.0VA_PG (88)
1
CE13
RE25 0_0201_5% 1 C
4
1 @ 2 2
RE24 0_0201_5%
1.0V_PRIM_CORE_PG (89)
B CPU
E MMBT3904WH_SOT323-3
3
2
REM_DIODE1_N
PVT-045
Change to shortpad REM_DIODE1_N (73)

P058 - EC_MEC5105
0.4
Date: Tuesday, March 05, 2019 Sheet 58 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P059 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P060 - Reserve
5 4 3 2 1
5 4 3 2 1
CK14
SMBUS
CH15
1.5K
CH14 +1.8V_IR_VDDIO
SML 0 1.5K
CF15
2.2K
7 IR_I2C_CLK 0
2.2K +3VS_TS
IR sensor
CN11 0 DSP Realtek 5849 IMX488
TS_I2C_SCL 8 IR_I2C_DATA 0
I2C 0
CM11 0 TS
TS_I2C_SDA
Trace length
D 1.5K D
CJ12
I2C 1
CK12 +1.8V_UF_VDDIO
1.5K
2.2K
2.2K +3VS
CH20 ISH_I2C0_SCL 0 13
Gyro+ A CC 40 UF_I2C_CLK 0
ISH_I2C 0 0
CK22 ISH_I2C0_SDA 14 UF sensor
Trace length 41 UF_I2C_DATA 0 OV 5675
DSP Realtek 5876
0 1
WHL-U 0 11
E-Compas s
1.5K
+1.8V_WF_DOVDD
1.5K
@1K
@1K +3VS
CJ22 ISH_I2C1_SCL 24 WF_I2C_CLK 0
ISH_I2C 1 ALS DSP Realtek 5880 WF sensor
CH22 ISH_I2C1_SDA
25 WF_I2C_DATA 0 OV8856
Trace length In camera module
has ALS I2C
+3VS pull H 1.5K
CJ22
ISH_I2C 2
CH22
SML1
CM15 CN15
C SML1_SMBDATA 1K +3VS C
Trace length
1K +3V_PCH
SML1_SMBCLK 2.2K
G
E1 1 D8
+3VS
2.2K
SMB0 3 G
D S B1
SA R
A1
D S
+3.3V_CV2
2.2K 2.2K
G
+3VALW +3.3V_CV2
2.2K 2.2K
G
B3 USH_EXPANDER_SMBCLK D S C9
SMB0 1 US H
E5 USH_EXPANDER_SMBDAT C1 0
D S
Trace length
2.2K
0 K2
0 PD2_Debug
+3VALW L2
2.2K
TI PD2
D7 UPD2_SMBCLK B5
SMB0 0 I2C_2
E7 UPD2_SMBDAT A5
Trace length
2.2K
MEC 2.2K
+3.3V_ALW
C1 2 BASE_SMBCLK 0 9
B B
SMB0 2
0 BAS E
E1 0 BASE_SMBDAT 8
Trace length
2.2K
0 K2
+3VALW 0 PD1_Debug
L2
2.2K
TI PD1
C3 UPD1_SMBCLK B5
SMB0 4 I2C_2
B4 UPD1_SMBDAT A5
Trace length
4.7K
+3VS
+3VS
4.7K
G
33 CSC L
PS8811
D S
G Re-driver
32 CSD A
PBC MLK pull H 2.2K D S
@10K
1K
+3VALW
1K +3VALW @10K
F7 IMVP_SMBCLK @0 33
SMB0 5
@0 IMV P
B6 IMVP_SMBDAT 32
Trace length
2.2K 0 21
A A
0 Charger
22
+3VALW
2.2K
N2 PBAT_CHARGER_SMBCLK 100 7
SMB1 0 BATTE RY
M3 PBAT_CHARGER_SMBDAT 100 6 CONN
Trace length

P061 - SMB/I2C Block Diagram
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P062 - Reserve
5 4 3 2 1
5 4 3 2 1
M-BITS +3VALW
Hall sensor
CHG_LED#_Y (77)
@ DZ12 1
1 2 C35
(58,83,94) ACAV_IN
2
0.1U_0201_10V6K
3
RB751S40T1G_SOD523-2 M_BITS_R
VDD
2 @ 1 PVT- 117 QZ20 2
D (58) M_BIST RZ1415 1 2 0_0402_5% Change to short-pad 2R D
+3VALW LMUN5111T1G_SC70-3
RZ1419 1M_0402_5%~D 2 1
1 @ 2 GND
(7,11,58) PCH_RSMRST#_AND
VOUT
1R
RZ1413 330K_0402_5%
1
C APX8132AI-TRG_SOT23-3
2 1 2 U7
CZ218 2.2U_0201_6.3V6M B
3
Q31 E
3
MMBT3904WH_SOT323-3 RZ1412
1 2
(58,77,79) PWRBTN#
820_0402_5%
(58) LID_CL#_NB
Ouput is P.P. type
Mmagnet i c f iel d enters t he hal l s ensor, out put turns on ( out put i s l ow).
Magnet i c f iel d rel ease poi nt , out put turns off (output i s high
).
C C
B B
A A
P063 - LED MBITS / LID
5 4 3 2 1
5 4 3 2 1
+3VS
SAR Proximity
RF@
RF@
1 1
82P_0201_50V8J
100P_0201_50V8J
CS13
CS14
Sensor 2 2
0513
Add DN7 f or SAR_ACT# is 1.8V
D 0512 D
RF request DN7
+3VS +1.8VU +3VS Change SMBUS resistor size 1. 8 V
f rom 0402 to 0201
SAR_ACT#_R
1 2
SAR_ACT# (58)
PVT-058
Change to short-pad
RB751S40T1G_SOD523-2 +3VS
1 1
1
CS1
CS2 RS5 RS6
0.1U_0201_10V6K
0.1U_0201_10V6K @ 0_0201_5% @ 0_0201_5%
1
2 2
2
RS30 RS3 RS4
2
2
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
U2
C2 PVT-059 1 6
USH_EXPANDER_SMBCLK (58,73)
2
VDD Change to short-pad
SAR_IRQ# SAR_ACT#_R
C1 A2 1 @ 2
JANT1 SVDD NIRQ RS33 0_0201_5%
ANT_CS0 SX9306_CS0 PS_SMBCLK Q30A
ME - ANT 1 LS1 1 2 A3 B1
1 CS0 SCL L2N7002DW1T1G_SC88-6
QP-48G PS_SMBDAT
EMI_Spring 33NH_LQG15HS33NG02D_2% B3 A1 PU at PCH side
CONN@ CS1 SDA
1
C3 B2
CS2 GND
5
Need check EMI Spring CS3
10P_0201_25V8
2 SX9310ICSTRT_WLCSP9
4 3
USH_EXPANDER_SMBDAT (58,73)
1 Q30B
CS12
0.1U_0201_10V6K L2N7002DW1T1G_SC88-6
C C
Tunnable IC
JANT3 JANT4
EMI_Spring EMI_Spring
CONN@ CONN@
1
1
1
B B
A A

P064 - SAR / Tunnable
5 4 3 2 1
5 4 3 2 1
SIO_SLP_S0#
CPU_C10_GATE#
Topology +3V_PC H
100K ohm
+1.0V_VC C ST G
0 ohm
PROCHOT# Topology
GPP_B12 SIO_SLP_S0# SIO_SLP_S0# VR_LPM _R _N
LP#
+1.0V_PRIM_CORE
D 1K ohm D
CPU 0 ohm TPM_GPIO0
499 ohm H_PROCH OT #_R

TPM
H_PROC H OT # Y4 PROCH OT #
PCH
75 ohm 75 ohm 75 ohm 100 ohm
APS debug
CONN
SLP_S0#
PROCHOT #_R 1
+3VALW IMVP
PU900 PUM01 PUB1 @10K ohm

IMV P +1.2V _DDR CHG EC
@0 ohm
+1.0VS_VCCIO
GPP_H 18 CPU_C10_GAT E# 0 ohm LP_VC C IO LP#
+1.0VA +1.0V_VC C ST G
+3VALW
VIN VOUT
0 ohm
VCCSTG_EN
Load SW +1.2V_D D R +VCCPLL_OC
RUN_ON _P EN
100K ohm VIN VOUT

@0 ohm
Load SW
C 0 ohm VCCPLL_EN C
EN
PCH_PCIE_WAKE# Topology
+3VA_T BT +3VA_T BT PCH_PLTRST# Topology

IN NC NO IN NC NO
10K ohm +3VALW
@10K ohm
L COM X L COM X
AR (TBT) H X COM H X COM
@0 ohm PCIE_WAKE# 0 ohm +3VALW
AR (TBT)
@0 ohm PCH_TBT_PER ST # 0 ohm
PCIE_WAKE#_AR
NO V+
@0 ohm PCH_PCIE_WAKE# @0 ohm @0 ohm PCH_PLTR ST #_AN D 0 ohm TBT_PERST #_R 0 ohm TBT_PER ST #
NC COM
RTD3_SELEC T
+3V_PCH _D SW @0 ohm TBT_RTD3_WAKE# 0 ohm IN GND
NO V+
NC COM PCIE_WAKE#_AR _R 0 ohm PCIE_WAKE#_AR From EC 10K ohm
RTD3_SELEC T
IN GND
10K ohm
From EC 10K ohm

PCH_TBT_PER ST # PCH_PLTR ST #_AN D
B GPD 7 TBT_RTD3_WAKE#
Enable: H GPP_C 8 TPM B
Disable: L
100K ohm
+3V_PCH _D SW +3.3VDX_SSD
PCH_PLTR ST #_AN D
SSD PCIE
PCH 1K ohm 10K ohm
SSD PCIE PCH_PLTR ST #_AN D @0 ohm

ESPI BIOS
WAKE# PCH_PCIE_WAKE# PCIE_WAKE# @0 ohm PEWake#
PCH
+3VS debug CONN
PCH_PLTR ST #_AN D
GPP_B13
PCH_PLTR ST #_AN D Card Reader
+3V_5105 +3V_5105 PCIE_WAKE#
WLAN PCIE @100K ohm 100K ohm

GPP_D 23
@1K ohm 10K ohm

PCH_PLTR ST #_AN D WLAN PCIE
WWAN_GPIO_WAKE#
+3VALW
INPU T INPU T INPU T OUTPU T

GPIO216 PCH_PCIE_WAKE# @0 ohm C B A Y +3VALW +3VS
L L L L
+3VALW +3VS
@100K ohm
L H L H
0 ohm H L L L
GPIO025 PCIE_WAKE#_R
EC H H L L
@0 ohm @0 ohm
D
@
@10K ohm
A VCC
G
GPIO064 WWAN_GPIO_C T R L @0 ohm WWAN_GPIO_C T R L_R

PCH_PLTR ST #_AN D WWAN_PER ST #
CONTROL INPUT ON CHANNEL
B WWAN_PER ST #_R @0 ohm WWAN PCIE
S A GPP_D 22 WWAN_GPIO_PER ST # @0 ohm WWAN_GPIO_PER ST #_R
Y
@10K ohm +3VS_WWAN
C
S
L B1
A A
GND @10K ohm
H B2
@10K ohm
@
0 ohm @10K ohm
WWAN_GPIO_WAKE#_R WWAN_GPIO_C T R L#
B2 S
GND VCC +3V_PC H WWAN PCIE
PCIE_WAKE# WWAN_PEWAKE#_R @0 ohm WWAN_PEWAKE# 0 ohm
B1 A
0 ohm

P065 - Topology
5 4 3 2 1
5 4 3 2 1
+3VALW
TPM PCH_SPI_CLK_TPM
Close to TPM
33_0402_5%
RZ1420 1 ST@ 2 0_0402_5%
+3VALW
2
D D
@EMC@
RZ3
+3V_PCH
12P_0402_50V8J
RF@ CZ20
68P_0402_50V8J
RF@ CZ19
1 1 RZ15 1 @ST@ 2 0_0402_5%
+3.3V_VPS_TPM
0.1U_0402_25V6
RZ18 1 750@ 2 0_0402_5%
2 2
@EMC@
close to pin 1 close to pin 8 +3VS_TPM
CZ23
+3VS_TPM +3VS RZ25 1 750@ 2 0_0402_5%
+3VALW_TPM
2
+3VALW_TPM
10U_0402_6.3V6M
0.1U_0201_10V6K
RZ16 1 750@ 2 0_0402_5%
+3VALW
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1
CZ22
1 1
CZ24 750@
CZ18 750@
CZ15
+3V_PCH 2 2 UZ8
2 2
750@
TPM_PIRQ#
750@
1 2 +3.3V_VPS_TPM close to pin 22
RZ23 10K_0402_5% 22
8 VPS
NiC_5
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
1
PVT- 119 NiC_1
Change to short-pad
1 1 1
31
NiC_21
CZ21
CZ17
CZ16 750@
PCH_SPI_CS2#_TPM
16
RZ19 1 @ 2 0_0402_5% 20 NiC_13 27
(9) PCH_SPI_CS2# TPM_PIRQ# SPI_CS# NiC_17
18 26 2 2 2
(12) TPM_PIRQ# SPI_PIRQ# NiC_16 25
PCH_SPI_SI_TPM NiC_15
RZ20 1 2 49.9_0402_1% PCH_SPI_SO_TPM 21 30 TPM_GPIO0_NU
(7,9) PCH_SPI_SI_R RZ17 1 2 49.9_0402_1% 24 MOSI NiC_20 29
(9) PCH_SPI_SO_R MISO NiC_19 28
TPM_GPIO0 NiC_18
6 14
GPIO NiC_11 15
NiC_12 13
NiC_10 12
PCH_SPI_CLK_TPM NiC_9
1 2 19 11
(9) PCH_SPI_CLK_R RZ24 49.9_0402_1% SPI_CLK NiC_8 10
NiC_7 5
NiC_4 4
7 NiC_3 3
PP NiC_2
32
C NiC_22 C
23
17 NiC_14 9
(11,47,52,53,68,70,79) PCH_PLTRST#_AND SPI_RST# NC_6 2
GND0 33
THPAD
ST33HTPH2032AHC1 VQFN 32P TPM

RZ21 1 @ 2 10K_0402_5%
+3VS
TPM_GPIO0
1 ST@ 2
RZ22 0_0402_5%
TPM_GPIO0_NU
1 750@ 2
(11,79,89,90) SIO_SLP_S0# RZ14 0_0402_5%
3D accelerometer and 3D gyroscope E-Compass

U4
6 2
+3VS PVT- 118 2 1 5 GND RES 12
B B
+3VS Change to short-pad 0.22U_0402_10V6K CS7 C1 RES
Place close to LGA1 PIN1,3,22 and 23 ISH_I2C0_SCL
1 @ 2 +3VS_ECOM 1
9 SCL/SPC SDA/SDI/SDO
4
8
0_0201_5% 2 @ 1 RS8
ISH_I2C0_SDA
+3VS_GYRO RS9 0_0201_5%

VDD GND
1
ISH_I2C0_SDA 11 +3VS_ECOM PVT-062

RS19 2 1 2.2K_0201_5% RS10 PVT-061 RES 10 Change to short-pad
ISH_I2C0_SCL 1 1 1 VDD_IO
RS18 2 1 2.2K_0201_5% @ 0_0402_5% Change to short-pad
+3VS_ECOM
ISH_ACC1#_R CS8 CS10 CS9 3 7
RS11 2 @ 1 10K_0201_5% 10U_0402_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K CS INT/DRDY
ISH_ACC2#_R +3VS_GYRO
2
RS29 2 @ 1 10K_0201_5% 2 2 2
ISH_ACC1#_R LIS2MDLTR_LGA12_2X2
RS15 2 @ 1 10K_0201_5% ISH_ACC2#_R LGA1
RS14 2 @ 1 10K_0201_5% PVT-063
5 8 Change to short-pad
VDDIO VDD
ISH_ACC2#_R
1 9 1 @ 2
SDO/SA0 INT2 RS12 0_0201_5% ISH_ACC2_INT# (12)
2
SDx CS_Aux
10 +3VS PVT-060
Change to short-pad
Place close to LGA2 PIN1,3,22 and 23
+3VS_ECOM
3 11
1
SCx NC
ISH_ACC1#_R +3VS_GYRO 1 1 1
1 @ 2 4 12 RS7
(12) ISH_ACC1_INT# RS13 0_0201_5% INT1 CS @ 0_0201_5% CS4 CS6 CS5
ISH_I2C0_SCL
13 RS16 2 @ 1 0_0201_5% 10U_0402_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K
SCL ISH_I2C0_SCL (12) 2 2 2
PVT-065 6 ISH_I2C0_SDA
2
Change to short-pad 7 GND1 14 RS17 2 1 0_0201_5%
@ ISH_I2C0_SDA (12) +3VS_ECOM
GND2 SDA
PVT-064
Change to short-pad
LSM6DS3USTR_LGA14_2P5X3
A A
P066 - TPM/Gyro/Accel/E-Compass
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P067 - Reserve
5 4 3 2 1
5 4 3 2 1
SSD PCIe
M.2 2230 Key-M
D D
+3.3VDX_SSD
33P_0201_50V8J
RF@ C268
4.7U_0201_6.3V6M
0.1U_0201_6.3V6K
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
1 1 1 1 @ 1 @ 1 @
C266
47P_0201_25V8J
NGFF(PCIe) +3.3VDX_SSD
C265
C269
C267
C313
C314
2
2 2 2 2 2 2
JNGFF2
1 2
3 GND 3.3VAUX 4
5 GND 3.3VAUX 6
PERn3 N/C SSD_SCP#_R
7 8 1 @ 2
PERp3 N/C SSD_SCP# (58)
9 10 R20 0_0201_5%
11 GND DAS/DSS# 12
13 PETn3 3.3VAUX 14 PVT-066
15 PETp3 3.3VAUX 16 Change to short-pad
17 GND 3.3VAUX 18
19 PERn2 3.3VAUX 20
21 PERp2 N/C 22 +3.3VDX_SSD
23 GND N/C 24
C PETn2 N/C C
25 26
1
27 PETp2 N/C 28
29 GND N/C 30 RC231
(13) PCIE_PRX_DTX_N15 PERn1 N/C
31 32 10K_0402_5%
(13) PCIE_PRX_DTX_P15 PERp1 N/C
33 34
PCIE_PTX_C_DRX_N15 GND N/C
CD94 1 2 0.22U_0201_6.3V6M PCIE_PTX_C_DRX_P15 35 36
2
CD95 1 2 0.22U_0201_6.3V6M 37 PETn1 N/C 38 1 @ 2
(13) PCIE_PTX_DRX_P15 PETp1 DEVSLP M2230_DEVSLP (13)
39 40 R300 0_0201_5%
41 GND N/C 42
PCIe SSD (13) PCIE_PRX_DTX_N16
43 PERn0/SATA B+ N/C 44
(13) PCIE_PRX_DTX_P16 PERp0/SATA B- N/C
SATA_PTX_C_DRX_N16 45 46
CD96 1 2 0.22U_0201_6.3V6M 47 GND N/C 48
(13) PCIE_PTX_DRX_N16 SATA_PTX_C_DRX_P16 PETn0/SATA A- N/C
CD97 1 2 0.22U_0201_6.3V6M 49 50
(13) PCIE_PTX_DRX_P16 PETp0/SATA A+ PERST# PCH_PLTRST#_AND (11,47,52,53,66,70,79)
51 52
GND CLKREQ# CLKREQ_PCIE#1 (11)
0512 53 54 PEWake# R216 1 @ 2 0_0201_5%
Only PCIe storage, rev erse signal (11) CLK_PCIE_N1 REFCLKn PEWake# PCIE_WAKE# (47,52,53,58)
P C I E _ P R X_ D T X _ N 1 6 55 56 R217 1 2 10K_0201_5% +3.3VDX_SSD
P C I E _ P R X_ D T X _ P 1 6 (11) CLK_PCIE_P1 REFCLKp N/C
57 58
GND N/C
SSD_PEDET
67 68 R218 1 @ 2 0_0201_5%
N/C SUSCLK SUSCLK (11,52,53)
R212 1 @ 2 0_0201_5% 69 70
(13) M2230_PCIE_SATA# 71 PEDET 3.3VAUX 72
73 GND 3.3VAUX 74 +3.3VDX_SSD
75 GND 3.3VAUX
GND Close Pin 70, 72, 74
1
77 76 @EMC@
MTG77 MTG76 C270
0.01U_0201_16V7
2
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
1U_0201_6.3V6M
0.01U_0201_16V7
1 1 1 1 1 1
1
LOTES_APCI0146-P008A
CN47
CN60
CN61
CN62
CN63
CN46
CN48
CONN@
2
2 2 2 2 2 2 0518
Materail prepare issue
EVT change to 0.01U_0201_16V7
B B
+3VS_TS
+3.3VDX_SSD 3.3V_TS_EN_R
PVT-180
Base on EMC tream request
Change fuse from 0.5A to 1A
2 1
R329 100K_0201_5%
Max Current : 6A
+3VALW RON : 20m ohm R79
1 @ 2 VIH : 1.2V 1A_65V_T0603FF1000TM +3VS_TS
RZ1 0_0402_5% U9 +3VS_TS_R
+3VALW PVT-120 C166 2 1 1U_0201_6.3V6M 1 14 1 2
Change to short-pad 2 VIN1_1 VOUT1_1 13
VIN1_2 VOUT1_2 1000P_0402_25V8J
3.3V_TS_EN_R 1
R116 1 @ 2 0_0402_5% 3 12 C176 1 2
(12) PCH_3.3V_TS_EN ON1 CT1
1 @ 2 0_0402_5% C183
(58) 3.3V_TS_EN
5
UZ1 R115 4 11 0.1U_0402_10V7K

+3VALW VBIAS GND 2
2 1000P_0402_25V8J
G Vcc
(58,78) RUN_ON_P A SSD_EN

SSD_SCP_PWR_EN 4 5 10 C49 1 2
1 Y ON2 CT2 +3.3VDX_SSD
(58) SSD_SCP_PWR_EN B +3VALW 6 9
VIN2_1 VOUT2_1 +3.3VDX_SSD_R
1. 8 V 74LV1T32GW_SOT353-1-5 7 8 1 @ 2
3
VIN2-2 VOUT2_2 R78 0_0805_5%

1
1 15
R11 GPAD 0514
A 100K_0402_5%~D
Vih=1.37V (VCC=3.3V) C50 AOZ1331DI_DFN_14
PVT-168
1
A
Change C176,C49 to 1000P
1U_0201_6.3V6M For 1ms rise time Change to short-pad C48
2
0.1U_0402_10V7K
2
2
VBIAS range of 2.5 V to 5.5 V
VIN <= VBIAS, for RON performance

P068 - M.2 SSD_PCIE
D a te : Wednesday, February 27, 2019 She e t 68 of 100
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P069 - Reserve
5 4 3 2 1
5 4 3 2 1
Card Reader 1)Placing the RTS5242 chip and flash card socket locate to suit trace routing for SI / EMI / ESD.
2)Keep bulk and de-coupling capacitors as close as possible to the RTS5242 chip and flash card socket.
■ Bulk capacitor for Card_3V3 place closed to flash card socket.
■ Bulk capacitor for 3V3_IN / 3V3aux / DV12S place closed to RTS5242 chip.
3)Keep damping resistor (ex, for SD CLK / MS CLK) as close as possible to the RTS5242 chip.
4)Keep these capacitors for SD card / MS card signals as close as possible to flash card socket.
+3VS_CR +3VS_CR
D D
10U_0402_6.3V6M
0.1U_0402_10V7K
4.7U_0402_6.3V6M
0.1U_0402_10V7K
2 1 2
CR2
CR4
CR5
CR3
2
1 2 1
27
11
UR1
+SD_VDD1
3V3aux
3V3_IN
1 12 +DV33_18
(11,47,52,53,66,68,79) PCH_PLTRST#_AND PERST# CARD_3V3
2 18 1U_0201_6.3V6M 2 1 CR12
(11) CLKREQ_PCIE#4 CLK_REQ# DV33_18
CLK_PCIE_P4_R
CLK_PCIE_N4_R 5 SD_RCLK_M_L EMC@ SD_RCLK_M
6 REFCLKP 15 RR14 1 @ 2 0_0201_5%
REFCLKN SP1 SD_RCLK_P_L SD_RCLK_P
2.2P_0402_50V8C~D
PCIE_PTX_DRX_P9_C
16 SD_CLK_L RR12 1 @ 2 0_0201_5% SD_CLK
CR6 1 2 0.1U_0402_10V7K 3 RTS5242 SP2 17 RR11 1 @ 2 0_0201_5%
(13) PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9_C HSIP SP3 SD_CMD_L SD_CMD
CR7 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_P9_C
4 19 SD_D3_L RR9 1 @ 2 0_0201_5% SD_D3 1
(13) PCIE_PTX_DRX_N9 HSIN SP4
CR20 EMC@
CR10 1 2 0.1U_0402_10V7K PCIE_PRX_DTX_N9_C 7 20 SD_D2_L RR10 1 @ 2 0_0201_5% SD_D2
(13) PCIE_PRX_DTX_P9 HSOP SP5
(13) PCIE_PRX_DTX_N9 CR13 1 2 0.1U_0402_10V7K 8 21 SP7_SDWP RR7 1 @ 2 0_0201_5%
PVT-067 HSON SP6 29
Change to short-pad SP7 2
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2.2P_0402_50V8C~D
2 @ 1 CD_WAKE# 1 1 1 1 1
(9) MEDIACARD_IRQ#
CR8
CR11 @EMC@
CR9
CR19 @EMC@
CR18 @EMC@
RR4 1 2 0_0201_5% 32 PVT-068
+3VS_CR WAKE# Change to short-pad
RR3 10K_0201_1% SD_CD# 31
30 MS_INS#
Close to UR1 SD_CD# 2 2 2 2 2
@EMC@
@EMC@
SD_LN1_P
22 SD_LN1_M
SD_LN1_P 23
CR15 1 2 0.1U_0402_10V7K +DV12S 10 SD_LN1_M
AV12 SD_LN0_P
14 26 SD_LN0_M
DV12S SD_LN0_P 25
SD_LN0_M
0.1U_0402_10V7K
4.7U_0402_6.3V6M
+SD_VDD2
13 SD_REG2
SD_VDD2 24
2 1
E-PAD
SDREG2
CR17
1 2 RREF 9 28 2 1 +3VS_CR
RREF GPIO
CR16
RR13 6.2K_0402_1% 10K_0201_1% RR5
2
1 2 Close to UR1 RTS5242-GR_QFN32_4X4 CR1
33
0513
C 1U_0201_6.3V6M C
1
EMC@
If GPIO not use for LED function,
must be pull-high (Layout guide)
JCR1
+SD_VDD1 Close to JCR1 SD_D2
SD_D3
1
EMC@ 2 DAT2
L27 SD_CMD CD/DAT3
CLK_PCIE_P4_R 3
4 3 4 CMD
(11) CLK_PCIE_P4 4 3 SD_CLK VDD1
5
CLK
10U_0402_6.3V6M
0.1U_0402_10V7K
CLK_PCIE_N4_R SD_RCLK_P
6
1 2 7 VSS
(11) CLK_PCIE_N4 2 SD_RCLK_M
1
1 2 DAT0/RCLK+
CR21
SD_CD# 8
DAT1/RCLK-
CR14
+SD_VDD2 9
DLW21HN900HQ2L_4P CD
2
1 15
QR1 16 VDD2
SWIO
4.7U_0402_6.3V6M
0.1U_0402_10V7K
For GPIO control SD_WP L2N7002WT1G_SC-70-3 SD_LN0_P 17
18 VSS
SP7_SDWP 1 1 SD_LN0_M D0+
CR23
1 3 19
D
D0-
CR22
SD_LN1_M
20 10
21 VSS GND 11
SD_LN1_P D1- GND
2 2 22 12
G
2
PVT-176 23 D1+ GND 13

Remove co-lay VSS GND 14
GND
T-SOL_158-1090902601
(10) HOST_SD_WP# CONN@
B B
+3VS_CR
+3VALW Max Current :2A

RON : 70m ohm
C362 VIH : 1.1V PVT-161 +3VS_CR
2 1 U37 Change to short-pad
+3VS_CR_R
1U_0201_6.3V6M 6 1 1 @ 2
+3VS IN OUT R195 0_0603_5%
1 2 5 2
SET GND 1 1
10U_0402_10V6M
C249
0.1U_0201_10V6K
C250
R206 1 2 100K_0201_5% R313 20K_0402_5%

SD_PWR_EN_R
R204 1 @ 2 100K_0201_5% 4 3
EN(/EN) FLAG
2 2
G527ATP1U_TSOT23-6
EMC@
A A

P070 - Card reader uSD RTS5242
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P071 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P072 - Reserve
5 4 3 2 1
5 4 3 2 1
D D
USH CONN.
USB Board CONN PVT-121
Change to short-pad
0509
CONN current rating
+3VS_USB +3VS_USB
Modify pin define for Type A FPC routing +3VS
+3VS_USH
0.5A per pin
+1.2V_USB RB34 1 @ 2 0_0402_5%
JIO1
0.1U_0201_10V6K
RB35 1 @ 2 0_0402_5%
10U_0402_10V6M
1 2 +3VS_USH
+3VS +3VS_USB 1 2 JUSH1
0.1U_0201_10V6K
PVT-152 3 4 +3VALW_USH CONN@
1 1 Change to short-pad 3 4 USB_DB_DET # 1
C14
C7
5 6 1
2 @ 1 7 5 6 8 L = USB BOARD present 2 1
7 8 H = USB BOARD not present 2
C275
0_0603_5% R77 9 10 +5VALW_USH 3
2 2 11 9 10 12 2 4 3
C 11 12 USB_DB_DET# (58) +5VS_USH 4 C
13 14 USB_POWERSHARE_VBUS_EN_L (58)
5
15 13 14 16 6 5
15 16 USB_OC0# (13) 6
17 18 7
+5VD 17 18 USB_POWERSHARE_ENL# (58) 7
19 20 8
19 20 DCI_CLK (12) +3VALW +3VALW_USH 8
21 22 9
+1.2V_USB +1.2V_USB 21 22 DCI_DATA (12) 9
23 24 10
25 23 24 26 RB36 1 2 0_0402_5% DB9 2 1 RB751S40T1G_SOD523-2 11 10
USB20_N3 (13)
@
25 26 (10) CONTACTLESS_DET# 11
0.1U_0201_10V6K
27 28 RB37 1 @ 2 0_0402_5% 12
27 28 USB20_P3 (13) 12
10U_0402_10V6M
29 30 13
31 29 30 32 (58) BCM5882_ALERT# 14 13
1 1 31 32 USB3_PTX_DRX_P3 (13) (58) USH_PWR_STATE# 14
C13
C6
0.1U_0201_10V6K
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
33 34 1 1 1 15
35 33 34 36 USB3_PTX_DRX_N3 (13) (11,78,79,87) SIO_SLP_S4#_AND 16 15
(58,90) IMVP_SMBCLK 35 36 16
C271
C272
C9
37 38 17
2 2 (58,90) IMVP_SMBDAT 37 38 USB3_PRX_DTX_P3 (13) 17
39 40 18
(58) REM_DIODE1_P 39 40 USB3_PRX_DTX_N3 (13) 2 2 2 (13) USB20_P8 18
41 42 19
(58) REM_DIODE1_N 41 42 (13) USB20_N8 19
20
43 44 21 20
Power Power (58,64) USH_EXPANDER_SMBCLK 21
45 46 22
Power Power (58,64) USH_EXPANDER_SMBDAT 22
23
+5VD +5VD 47 48 +5VALW +5VALW_USH 24 23
49 GND GND 50 25 24
GND GND 25
0.1U_0201_10V6K
51 52 RB38 1 @ 2 0_0402_5% 26
GND GND 26
10U_0402_10V6M
53 54 RB39 1 @ 2 0_0402_5% 27
55 GND GND 56 28 27
1 1 GND GND 28
C12
C5
0.1U_0201_10V6K
4.7U_0201_6.3V6M
4.7U_0201_6.3V6M
57 58 29
59 GND GND 60 30 29
GND GND 1 1 1 (58) USH_DET# 30
61 62
2 2 GND GND
C273
C274
C10
0512 31
63 64
Add USH_DET# GND_1 32
65 PTH PTH 66 2 2 2 GND_2
67 PTH PTH 68 ELCO_046809630310846+
PTH PTH
I-PEX_20698-042E-01
+5VS
CONN@
+5VS_USH
RB40 1 @ 2 0_0402_5%
RB41 1 @ 2 0_0402_5%
0.1U_0201_10V6K
1
C276
B B
A A
P073 - TYPEA I/O, USH I/O
D a te : Thursday, January 31, 2019 She e t 73 of 100
5 4 3 2 1
5 4 3 2 1
Docking CONN
D D
JDOCK1 BASE_SMBCLK_2IN1
BASE_SMBDAT_2IN1
1
2 1
(58,82) DET_L#_2in1 2
PU at EC side 3
BASE_SMBCLK_2IN1 BASE_SMBCLK_R 3
10P_0201_25V8
@EMC@
10P_0201_25V8
@EMC@
RP4 1 @ 2 0_0201_5% 4
(58) BASE_SMBCLK_2IN1 BASE_SMBDAT_2IN1 BASE_SMBDAT_R 4 1 1
RP5 1 @ 2 0_0201_5% 5
(58) BASE_SMBDAT_2IN1 BASE_SMB_ALERT#_R 5
(58) BASE_SMB_ALERT#_2IN1 RP15 1 @ 2 0_0201_5% 6
6
C301
C302
7
PVT-069 8 7 2 2
Change to short-pad 9 8
+5V_DOCK 9
10
11 10
2A 12
13
11
12
14 13
15 14
16 15
(13) USB20_P4 16 +5V_DOCK +5V_DOCK
17
(13) USB20_N4 17
18
DET_R 18
0.1U_0201_10V6K
19
(82) DET_R 19
10U_0402_10V6M
20
20
1 1
C11
C4
21
C 22 GND C
GND 2 2
ACES_51522-02001-P02
CONN@
0509
Modify pin define for dock FPC routing
B B
A A
P074 - Dock I/O
5 4 3 2 1
5 4 3 2 1
For Power logic

For EC(VBAT), +RTCVCC
(2)+3 V _L DO
(10) +5VALW +5V_PD_V DD RT4 1
0-o h m
DT1
For PD controller 1
(1) +VBUS1_PD_20V (2)+3.3V_VDD_P IC
UT4 UT2
+5V_TBT_V BUS
20V to 5V 5V to 3V
DT4 DT2 RT4 2
0-o h m
VC C VOU T VC C VOU T
(1) +VBUS2_PD_20V
UT3
20V to 5V
DT3
VC C VOU T
(10) +3VALW (12)+3VALW_DSW

D Q8 D
MOS
(1) +VBUS1_PD_20V
PU20 0
S1 a S1 b Q7
(6) B+
(5) +CHG_VIN_20V VOU T (11) VCCDSW_EN MOS
Type-C Port-1 VIN

CHARGER
(2)+3 V _L DO (2)+3 V _L DO (7) ACAV_IN (10) +3VALW
S1a MOS Of f S1b Drain gat e 分
壓 ACOK
UT1 U29
(11) DCIN1_EN (11) VBUS1_ECOK (6) B+ VIN
(2)+3.3V_VDD_P IC VBUS
S1a MOS On S1b MOS On
PD_1 (4) EN_PD_HV1 (4) EN_PD_HV1 +3V_PCH (15) +3V_PCH
PU30 1 EN
VDD IO S1a MOS On S1 b Drai n gat e 無
分
壓 VIN (10) 3VALW_PG VOU T
VIN _3V3 PG
+3VALW
(8) ALWON (10) +3VALW (6) B+
(1) +VBUS1_PD_20V EN VOU T
S2 a S2 b PU180 1
(6) B+ VIN
PG (16) 1.8VA_PG
Type-C Port-2 PU55 1 +1.8VA
(2)+3 V _L DO (2)+3 V _L DO
壓 (3) +RTCVCC_EC VIN
PG (10) 5VALW_PG (15) +1.8VA
EN VOU T
(6) B+
UT1
(11) DCIN2_EN (11) VBUS2_ECOK +5VALW
(10)+3VALW VBUS
S1a MOS On S1b MOS On (6) B+ PU185 1
RTCD 2 (8) ALWON (10) +5VALW
PD_2 (4) EN_PD_HV2 (4) EN_PD_HV2
EN VOU T VIN
RTCR 2 PU10 1
分
壓
VIN _3V3 (0) +RTCBATT 1.2K-o h m (6) B+
VIN
(16) 1.0VA_PG +1.8VU
PG
+1.0VA EN
(26) +1.8VU
VOU T
RTCD 4 PU50 1
(2)+3 V _L DO (15) +1.0VA
(10) +3VALW VIN
PG (10) PG_5VD EN VOU T
(6) B+
G3 to AC S5
RTCD 3
(0)+3.3V_TBAT_LDO +5VD
PUM0 1
RE4 6 (8) ALWON (10) +5VD
100K-o h m EN VOU T VIN
PG (27) +1.2V_DDR_PG
(6) B+
(8) ALWON +1.2V_DDR

PU85 1
(10) +3VALW (14) SIO_SLP_SUS# EN
VIN
PG (16) 1.0V_PRIM_CORE_PG (25) SIO_SLP_S4# (26) +1.2V_DDR
(0)~(21)
VBAT GPIO_024 GPIO_164 EN(S 5 ) VOU T
nRESETI
VCI_OU T
VCI_OVR D _ I N
(11) DCIN[1-2]_EN +1.0V_PRIM _C O R E
For VR Low Power Mode
To Power Path (12) RESET_IN# (14) SIO_SLP_S0# (15) +1.0V_PRIM_CORE +0.6VS
C (11) VBUS[1-2]_ECOK 10ms Delay R14 3 LP# VOU T
C
100K-o h m
(37) SM_PG_CTRL (38) +0.6VS
(15) +3V_PCH EN2(S3) VOU T
(12)+3VALW_DSW VCCDSW_3P3 (13) PCH_DPWROK (11) VCCDSW_EN RE2 4

DSW_PWROK GPIO_020 GPIO_012 0-o h m (16) 1.0V_PRIM_CORE_PG
RE3 3
(14) SIO_SLP_SUS# 100K-o h m RE2 6
SLP_SUS# GPIO_230 0-o h m (16) 1.8VA_PG
(15) +3V_PCH
VCCPRIM_3 P 3
(18) PCH_RSMRST#_AND RE54 2 (17) PRIM_PWRGD RE2 5
(16) 1.0VA_PG
0-o h m (18) PCH_RSMRST# 0-o h m
RSMRS T # RSMRS T # GPIO_227 (6) B+ (6) B+
PU90 0 PUA1 0 1
VIN
PG (38) PCH_PWROK VIN
ESP I _ R E S E T #
(19) ESPI_RESET# MP2949AG Q +VCCS A
UC18 GPIO_061
ESP I _ R E S E T # (6) B+
(35) IMVP_VR_ON_P (36) PWM_SA (37) +VCCSA
(20) ESPI_IO EN PW M PW M VOU T
ROM SP I
ESPI _ I O ESPI _ I O
PU140 0
VIN
PG
(32) VCCIO_PG
(6) B+
ACPRESENT
(21) AC_PRESENT
GPIO_233 +1.0VS _VCCIO PUZ101/PUZ2 0 1
(30) RUN_ON_P (31) +1.0VS_VCCIO VIN
EN VOU T
(10) +5VD +VCC_COR E

(15) +1.8VA VCCPRIM_1 P 8
(23) SIO_PWRBTN#
PWRBT N# GPIO_113 (22) POWER_SW_IN#
GPIO_163/VCI_IN0# Power Button U30 (36) PWM_CORE1/2 (43) +VCC_CORE
(15) +1.0VA PW M VOU T
EC 5105
VCCPRIM_1 P 0 5 VIN
VCCPRIM_MPHY _ 1 P 0 5
SLP_S5#
(24) SIO_SLP_S5#
GPI0_040
(15) +1.0V_PRIM_CORE VCCPRIM_C OR E (6) B+
+5VS
S5 to S0
(25) SIO_SLP_S4# (30) RUN_ON_P (31) +5VS
SLP_S4# GPIO_026 PUG10 1
EN VOU T
VIN
(14) SIO_SLP_S0#
SLP_S0# (10) +3VALW
+VCCG T
(14) CPU_C10_GATE# (28) SIO_SLP_S3#
CPU_C10_GATE# SLP_S3# GPIO_032 UZ3
(10) +3VALW (36) PWM_GT (44) +VCCGT
WHL-U PCH
VIN PW M VOU T
(10) +3VALW
(22)~(42) (37) SM_PG_CTRL DDR_VT T _C T L VCCST _PW R GD

(36) VCCST_PWRGD
Level
Shi fter
UE2
UE1
(34) IMVP_VR_ON
GPIO_031
GPIO_045
(29) RUN_ON_EC
(28) SIO_SLP_S3# UC3

(30) RUN_ON_P EN
+3VS
(15) +1.8V_VA
VOU T
(31) +3VS
UZ3
RE2 9 (35) IMVP_VR_ON_P
100K-o h m VIN
+1.8VS
B (39) CPUPWRGD B
(30) RUN_ON_P (31) +1.8VS
(10) +3VALW EN VOU T
UE3 (15) +1.0VA

VIN
UZ6
VIN
(38) PCH_PWROK PCH_PWR OK
(41) PCH_PLTRST# @
Y
(42) PCH_PLTRST#_5105
PLTRST# A
PLTRST# is virtual wire +1.0V_VCCS T
(40) SYS_PWROK (30) RUN_ON_P EN VOU T
(31) +1.0V_VCCST
SYS_PWROK
(15) +1.0VA (26) +1.2V_DDR

UZ5 UZ4
(40) SYS_PWROK (10) +3VALW
GPIO_106/PWROK VIN VIN
(30) RUN_ON_P +1.0V_VCCS TG +VCCPLL_OC

(31) +3VS
(31) VCCSTG_EN
U36
EN (32) +1.0V_VCCSTG (31) VCCSTG_EN (32) +VCCPLL_OC
(14) CPU_C10_GATE# VOU T EN VOU T
QE5 A
R23 8
MOS
100K-o h m R24 0
100K-o h m
RE5 7
100K-o h m
QE5 B
GPIO_057/VCC _ P W R GD (33) RUNPWROK
(ALL_SYS_P W R G D )
MOS
RE45 7
0-o h m (27) +1.2V_DDR_PG
RE50 8
0-o h m (32) VCCIO_PG
A A
Security Classification Compal Secret Data

Titl e
Issued Date 2018/05/08 Deciphered Date 2018/05/08
P075 - AC_Power up Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Document Numb e r Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS E 0.4
Da t e : Monday, January 28, 2019 Sh e e t 75 of 100
5 4 3 2 1
5 4 3 2 1
For Power logic

For EC(VBAT), +RTCVCC
(2)+3 V _L DO
(10) +5VALW +5V_PD_V DD RT4 1
0-o h m
DT1
For PD controller 1
(1) +VBUS1_PD_20V (2)+3.3V_VDD_P IC
UT4 UT2
+5V_TBT_V BUS
20V to 5V 5V to 3V
DT4 DT2 RT4 2
0-o h m
VC C VOU T VC C VOU T
(1) +VBUS2_PD_20V
UT3
20V to 5V
DT3
VC C VOU T
D (10) +3VALW (12)+3VALW_DSW D

Q8
MOS
(1) +VBUS1_PD_20V
PU20 0
S1 a S1 b Q7
(7) B+
(6) +CHG_VIN_20V VOU T (11) VCCDSW_EN MOS
Type-C Port-1 VIN

CHARGER
(2)+3 V _L DO (2)+3 V _L DO (8) ACAV_IN (10) +3VALW
壓 ACOK
UT1 U29
(11) DCIN1_EN (11) VBUS1_ECOK (7) B+ VIN
(2)+3.3V_VDD_P IC VBUS
S1a MOS On S1b MOS On
PD_1 (4) EN_PD_HV1 (4) EN_PD_HV1 +3V_PCH (15) +3V_PCH
PU30 1
分
壓 VIN (10) 3VALW_PG
EN
VOU T
VIN _3V3 PG
+3VALW
(9) ALWON (10) +3VALW (7) B+
(1) +VBUS1_PD_20V EN VOU T
S2 a S2 b PU180 1
(7) B+ VIN
PG
(16) 1.8VA_PG
Type-C Port-2 PU55 1 +1.8VA
(2)+3 V _L DO (2)+3 V _L DO
壓 (3) +RTCVCC_EC VIN
PG (10) 5VALW_PG EN VOU T
(15) +1.8VA
UT1
(7) B+
(11) DCIN2_EN (11) VBUS2_ECOK +5VALW
(10)+3VALW VBUS
S1a MOS On S1b MOS On (7) B+ PU185 1
RTCD 2 (9) ALWON (10) +5VALW
PD_2 (4) EN_PD_HV2 (4) EN_PD_HV2
EN VOU T VIN
RTCR 2 PU10 1
分
壓
VIN _3V3 (0) +RTCBATT 1.2K-o h m (7) B+
VIN
(16) 1.0VA_PG +1.8VU
PG
+1.0VA (26) +1.8VU
EN VOU T
RTCD 4 PU50 1
(2)+3 V _L DO (15) +1.0VA
(10) +3VALW VIN
PG
(10) PG_5VD EN VOU T
(7) B+
G3 to AC S5
RTCD 3
(0)+3.3V_TBAT_LDO +5VD
PUM0 1
RE4 6 (9) ALWON (10) +5VD
100K-o h m EN VOU T VIN
PG (27) +1.2V_DDR_PG
(7) B+
(9) ALWON
+1.2V_DDR
PU85 1
(10) +3VALW (14) SIO_SLP_SUS# EN
VIN
PG (16) 1.0V_PRIM_CORE_PG (25) SIO_SLP_S4# (26) +1.2V_DDR
(0)~(21)
EN(S 5 ) VOU T
VBAT GPIO_024 GPIO_164 VCI_OU T
nRESETI VCI_OVR D _ I N
(11) DCIN[1-2]_EN +1.0V_PRIM _C O R E
For VR Low Power Mode
C
To Power Path
(11) VBUS[1-2]_ECOK
(12) RESET_IN#
R14 3
(14) SIO_SLP_S0# LP# VOU T
(15) +1.0V_PRIM_CORE +0.6VS C
10ms Delay
100K-o h m
(37) SM_PG_CTRL (38) +0.6VS
(15) +3V_PCH EN2(S3) VOU T
(12)+3VALW_DSW (11) VCCDSW_EN

VCCDSW_3P3 (13) PCH_DPWROK RE2 4
DSW_PWROK GPIO_020 GPIO_012 0-o h m (16) 1.0V_PRIM_CORE_PG
RE3 3
(14) SIO_SLP_SUS# 100K-o h m RE2 6
SLP_SUS# GPIO_230 0-o h m (16) 1.8VA_PG
(15) +3V_PCH
VCCPRIM_3 P 3
(18) PCH_RSMRST#_AND RE54 2 (17) PRIM_PWRGD RE2 5
0-o h m (18) PCH_RSMRST# 0-o h m (16) 1.0VA_PG
RSMRS T # RSMRS T # GPIO_227 (7) B+ (7) B+
PU90 0 PUA1 0 1
VIN
PG (38) PCH_PWROK VIN
ESP I _ R E S E T #
(19) ESPI_RESET# MP2949AG Q +VCCS A
UC18 GPIO_061
ESP I _ R E S E T # (7) B+
(35) IMVP_VR_ON_P (36) PWM_SA (37) +VCCSA
(20) ESPI_IO EN PW M PW M VOU T
ROM SP I
ESPI _ I O ESPI _ I O
PU140 0
VIN
PG (32) VCCIO_PG
(7) B+
ACPRESENT
(21) AC_PRESENT
GPIO_233
+1.0VS _VCCIO PUZ101/PUZ2 0 1
(30) RUN_ON_P EN VOU T
(31) +1.0VS_VCCIO VIN
(10) +5VD +VCC_COR E

(15) +1.8VA VCCPRIM_1 P 8 (23) SIO_PWRBTN#
PWRBT N# GPIO_113 (22) POWER_SW_IN#
GPIO_163/VCI_IN0# Power Button U30 (36) PWM_CORE1/2 (43) +VCC_CORE
(15) +1.0VA PW M VOU T
EC 5105
VCCPRIM_1 P 0 5 VIN
VCCPRIM_MPHY _ 1 P 0 5
(24) SIO_SLP_S5#
SLP_S5# GPI0_040
(15) +1.0V_PRIM_CORE VCCPRIM_C OR E (7) B+
+5VS
S5 to S0
(25) SIO_SLP_S4#
SLP_S4# GPIO_026 (30) RUN_ON_P EN VOU T
(31) +5VS PUG10 1
VIN
(14) SIO_SLP_S0#
SLP_S0# (10) +3VALW
+VCCG T
(14) CPU_C10_GATE# (28) SIO_SLP_S3#
CPU_C10_GATE# SLP_S3# GPIO_032 UZ3
(10) +3VALW (36) PWM_GT (44) +VCCGT
WHL-U PCH
VIN PW M VOU T
(10) +3VALW
(22)~(42) (37) SM_PG_CTRL DDR_VT T _C T L VCCST _PW R GD

(36) VCCST_PWRGD
Level
Shi fter
UE2
UE1
(34) IMVP_VR_ON
GPIO_031
GPIO_045
(29) RUN_ON_EC
(28) SIO_SLP_S3# UC3

(30) RUN_ON_P
EN
+3VS
(15) +1.8V_VA
VOU T
(31) +3VS
UZ3
RE2 9 (35) IMVP_VR_ON_P
100K-o h m VIN
B +1.8VS B
(39) CPUPWRGD
(30) RUN_ON_P (31) +1.8VS
(10) +3VALW EN VOU T
UE3 (15) +1.0VA

VIN
UZ6
VIN
(38) PCH_PWROK PCH_PWR OK
(41) PCH_PLTRST# @
Y
(42) PCH_PLTRST#_5105
PLTRST# A
PLTRST# is virtual wire +1.0V_VCCS T
(40) SYS_PWROK (30) RUN_ON_P (31) +1.0V_VCCST
SYS_PWROK EN VOU T
(15) +1.0VA (26) +1.2V_DDR

UZ5 UZ4
(40) SYS_PWROK (10) +3VALW
GPIO_106/PWROK VIN VIN
(30) RUN_ON_P +1.0V_VCCS TG +VCCPLL_OC

(31) VCCSTG_EN
(31) +3VS U36 EN
(32) +1.0V_VCCSTG (31) VCCSTG_EN (32) +VCCPLL_OC
(14) CPU_C10_GATE# VOU T EN VOU T
QE5 A
R23 8
100K-o h m R24 0
MOS 100K-o h m
RE5 7
100K-o h m
QE5 B
GPIO_057/VCC _ P W R GD
(33) RUNPWROK
(ALL_SYS_P W R G D )
MOS
RE45 7
0-o h m (27) +1.2V_DDR_PG
RE50 8
0-o h m (32) VCCIO_PG
A A
Security Classification Compal Secret Data

Titl e
Issued Date 2018/05/08 Deciphered Date 2018/05/08
P076 - DC_Power up Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Document Numb e r Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS E 0.4
Da t e : Monday, January 28, 2019 Sh e e t 76 of 100
5 4 3 2 1
5 4 3 2 1
+3VALW +RTCVCC_EC
M.2 SSD/WLAN/WWAN shielding clip *10 Standoff- CPU*4
+3VALW +RTCVCC_EC CLIP10 CLIP18 CLIP15 CLIP16 CLIP17 H4 H3 H2 H5
1 1 1 1 1 @ @ @ @
1
1 1 1 1 1
H_3P3 H_3P3 H_3P3 H_3P3
RE85 EMI_Spring EMI_Spring EMI_Spring EMI_Spring EMI_Spring
1
1
100K_0201_5% CONN@ CONN@ CONN@ CONN@ CONN@
2
EC pull L, LED ON RE83
100K_0201_5% CLIP19 CLIP20 CLIP21 CLIP11 CLIP12
5
BAT1_LED#_USH EC pull L, LED ON 1 1 1 1 1
1 6 1 2 1 1 1 1 1
(58) BAT1_LED#
2
EMI_Spring EMI_Spring EMI_Spring EMI_Spring EMI_Spring
D61 RB751S40T1G_SOD523-2
(58) BAT2_LED#
4 3 1 2
BAT2_LED#_USH
CONN@ CONN@ CONN@ CONN@ CONN@ Standoff-EDP bracket*2
Q21A
D60 RB751S40T1G_SOD523-2
H6 H7
D Q21B D
@ @
H_3P3 H_3P3
R129 R132
Cable Clip*5
1
BAT1_LED#_USH 0_0402_5% CHG_LED#_Y_L R130 CHG_LED#_Y BAT2_LED#_USH 0_0402_5% PWR_LED#_W_L R133 PWR_LED#_W
1 2 1 2 1 2 1 2
@ @
820_0402_5% 220_0402_5%
+3VALW +3VALW CLIP3 CLIP4 CLIP2 CLIP1 CLIP5
1 1 1 1 1
PVT-173 1 1 1 1 1
WWAN*1,SSD*1
1
1
For Increase the w hite LED brightness EMI_Spring EMI_Spring EMI_Spring EMI_Spring EMI_Spring
Change resistor from 470 to 220 ohm
R145 6 R147 CONN@ CONN@ CONN@ CONN@ CONN@
100K_0201_5% 100K_0201_5% H1 H9
6
@ @
+3.3V_ALW_CHG H_6P0N H_6P0N
2
2
2 +3.3V_ALW_PWR
1
Q17A 2
L2N7002DW1T1G_SC88-6 Q18A
L2N7002DW1T1G_SC88-6 SCREW HOLE with GND
1
Q17B Q18B
1
3
3
L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6
H21 H22 H23 H24 H25 H26 H27 H28 H29
BAT1_LED#_USH
5
BAT2_LED#_USH
5 @ @ @ @ @ @ @ @ @
Fiducial mark*4
Phi 4.0*9 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0
1
FD1 FD3 FD2 FD4
@ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
4
4
H30 H31 H33
1
@ @ @
Phi 4.8*2 H_4P8 H_4P8 Phi 2.2*1 H_2P2
1
Standoff- WLAN*1
H8
@
SCREW HOLE without GND H_3P2 0515
ME request
C 0510 Change H8 to H_3P2
C
1
Modify pin define for PWR FPC routing +5VD
JBTN1 H16 H17 H18 H34 H35

1 @ @ @ @ @
1 2 H_2P6X2P0N H_1P9N H_2P4X1P9N H_1P6N H_2P2X1P6N
2 3
PWR_LED#_W
CHG_LED#_Y 0508 Standoff- M/B*1
1
3 4
4 CHG_LED#_Y (63) Swaps L20 layout suggestion
5 H32
5 PWRBTN# (58,63,79)
6
FingerPrint 6 7 FPR_DET# (58)
PVT-174 @ 0515
PWR BUTTON
7 8 UEFI_MGMT#_R
Remove co-lay
FingerPrint H_6P3 Phi 6.3*1 ME request
Change H32 to Standof f M/B
1
8 9
LED
9
10
10
11
USB20_P9_FP
USB20_N9_FP
4
4
EMC@
3
3 To PCH
11 12 L20
USB20_P9 (13)
Connector 12 13 1 2 USB20_N9 (13)
13
14
14
+3.3V_FPM
1 2
DLW21HN900HQ2L_4P FAN CONN
15
16 GND
GND
1
EMC@ EMC@ +3VS +3V_FAN PVT-122 +5VS +5V_FAN

D15 D18 Change to short-pad
ELCO_046809614210846+
CONN@
R153 1 @ 2 0_0402_5% R167 1 @ 2 0_0402_5%
+3.3V_FPM
2
+3V_FAN +5V_FAN
PVT-123
1
Change to short-pad
10K_0201_5%
R293
10K_0402_5%~D
Q26
10K_0402_5%~D
10K_0402_5%~D
L2N7002WT1G_SC-70-3 R161 2 C219
2
1
@ R160
G
0_0402_5% 0.1U_0402_25V6K~D
2
R149
R152
UEFI_MGMT#_R
1 3 @
(58) FPR_UEFI_MGMT# 1
D
2
PU at EC side @
JFAN1
1
D54 2 1 RB751S40T1G_SOD523-2 2 1
B B
(58) TACH_FAN1 3 2
(58) PWM_FAN1 +5V_FAN_R 3
4
5 4
6 G1
1 G2
C199
100P_0402_50V8J @
ACES_51570-00401-P02
2 CONN@
+3.3V_TBAT_LDO
B+
Volume Up But t on SW1

+3.3V_TBAT_LDO +3.3V_TBAT_LDO
TAFG3-12WQR_3P
Battery switch
1
VOLUME_UP# 1
2
R30 1 2 1K_0201_5% 2 R278
(58) VOL_UP#_2in1
3 R276 100_0201_1%
100K_0402_5%~D
1
2
0.1U_0201_10V6K
7
6
5
4
2 2
1
1 D4 R279
Kickstand detect SW
1
C252
2.2K_0402_5%
R277
2.2K_0402_5%
R309
AZ5123-01F-R7GR_DFN1006P2X2 2M_0402_5%
EMC@ LED3
HT-191UD5_AMBER
1
+3VS 2
2
2
A
kickstan d KICKSTD_SW_DET#_PCH detects kickstand open/close status and
SW forward it to the Waves Maxx Audio algorithm
1
Open Pull L Discrete EQ profile 2
3 1
RE39
6
4
6
4.99K_0201_1%
1
Clos e Pull H Discrete EQ profile 1 SW5 QC2A QC2B D
G3
G1
MSS3-Q-T-R_3P L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6 2 Q24
2
From ship mode IC 3 2 5 G L2N7002WT1G_SC-70-3

3
(12) KICKSTD_SW_DET#_PCH PU 10K resistor locate on EC S
3
2
side (94) SYS_PRES_SHIP# 2
4
2
A 1 A
Volume Down But t on

(82) SYS_PRES# 1
SW3
G4
G2
BTE-PQR2_4P SW2
TAFG3-12WQR_3P To Battery
7
5
VOLUME_DOWN# 1 SN200004A00
R62 1 2 1K_0201_5% 2 BATT_ON: PIN1,PIN2 connect
(58) VOL_DOWN#_2in1
1
3 BATT_OFF: PIN2,PIN3 connect

R80
0.1U_0201_10V6K
R81
1
1 2 1 @ 2 1
7
6
5
4
C231
D19
100K_0201_5% 100K_0201_5%
EMC@
2
2
P077 - PWRBTN / SCREW / FAN
5 4 3 2 1
5 4 3 2 1
+5VS +5VD Max Current : 4A

RON : 30m ohm PV T - 1 6 0
+5VS
+1.0V_VCCST source
Change to short-p a d
VIH : 1.2V Max Current : 6A
U30
+5VS_R +1.0VA RON : 5m ohm
2 1 1 7 1 @ 2 VIH : 1.2V 1.05V@60mA
C238 1U_0201_6.3V6M 2 VIN_1 VOUT_1 8 R186 0_0603_5% UZ6 PV T - 1 4 8
VIN_2 VOUT_2 Change to short-p a d
RUN_ON_P C248 1
1 1 1 VIN1
3 6 1 2 2 1 2 +1.0V_VCCST
ON CT C245 C244 C243 CZ13 1U_0201_6.3V6M VIN2 R190
2200P_0402_25V7K~D 7 6 1 2 0_0603_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
@
RUN_ON _ P 4 2 2 2 VIN thermal VOUT
Already PD 100K at RE122 +5VD VBIAS 1
5 PV T - 0 7 0 3
0.1U_0402_10V7K
GND_1 Change to short-p a d +5VALW VBIAS
9
CZ12
RUN_ON_P VCCST _EN
GND_2 R247 1 @ 2 0_0201_5% 4 5
ON GND 2
AOZ1336DI_DFN8_2X2 R248 1 @ 2 0_0201_5%
@
(11,73,79,87) SIO_SLP_S4#_AND
SIO_SLP_S3# T PS22961DNYR_WSON8
R326 1 @ 2 0_0201_5%
VIN <= VBIAS, for RON performance
D D
+1.8VS +1.8VA PV T - 1 5 1
+1.8VS
+3VS Max Current : 6A

RON : 20m ohm
VIH : 1.2V
+1.8V_RUN_UZ46 R58
1 @ 2 0_0603_5%
2
+1.0V_VCCSTG source Max Current : 6A
UZ3 +1.0VA RON : 5m ohm 1.05V@20mA
1
VIN1 VOUT1
14 CZ3 VIH : 1.2V
PV T - 1 2 6 2 13 0.1U_0201_10V6K UZ5
Change to short-p a d VIN1 VOUT1
RUN_ON_P RUN_ON_1.8V 1 1 PV T - 1 4 7 +1.0V_VCCSTG
VIN1 Change to short-p a d
1 @ 2 3 12 1 2 1 2 2
RZ2 0_0402_5% ON1 CT1 CZ2 470P_0402_50V7K CZ9 1U_0201_6.3V6M VIN2
4 11 +5VALW 7 6 R184 1 @ 2 0_0603_5%
RUN_ON _ P
+3VALW VBIAS GND VIN thermal VOUT
RUN_ON_P
Already PD 100K at RE122
5 10 1 2 3
ON2 CT2 C200 2200P_0402_25V7K~D +3VS VBIAS
6 9 4 5
+3VALW 7 VIN2 VOUT2 8 +3VS_R +3VALW ON GND +1.0V_VCCSTG
VIN2 VOUT2 1 @ 2 PV T - 0 7 2
5
15 R141 0_0603_5% U36 T PS22961DNYR_WSON8
GPAD
1 1 1
GND VCC
AOZ1331DI_DFN_14 R273 1 @ 2 0_0201_5% 1 VCCST G_EN
0.1U_0402_10V7K
C174 PV T - 1 5 9 C178 (14,58,89) CPU_C10_GATE# IN1 4
CZ11
RUN_ON_P
1U_0201_6.3V6M R328 1 @ 2 0_0201_5% 2 OUT
0.1U_0402_10V7K
1
2 2 IN2 2
@
SIO_SLP_S3# 1
R327 1 @ 2 0_0201_5% R240 C369
@
MC74VHC1G08DFT 2G_SC70-5 100K_0201_5% 1U_0201_6.3V6M
3
2
2
VIN <= VBIAS, for RON performance 1 @ 2
R239 0_0201_5%
DSx
+3.3V_ALW_PCH Max Current :4A
+VCCPLL_OC source (1.2V)
RON : 30m ohm Max Current : 6A
+3VALW VIH : 1.2V PV T - 1 6 9
+3V_PCH RON : 5m ohm
C209 U29 +1.2V_DDR VIH : 1.2V
1U_0201_6.3V6M +3.3V_ALW_PCH_R 1.05V@130mA
2 1 1 7 1 @ 2 UZ4
2 VIN_1 VOUT_1 8 R157 1 PV T - 1 4 6
0_0805_5% Change to short-p a d
PCH_PWR_EN_R VIN_2 VOUT_2 2 VIN1 +VCCPLL_OC
1 VIN2
(11) PCH_PRIM_EN 1 @ 2 3 6 1 2
R159 0_0402_5% ON CT C208 1000P_0402_50V7K~D C207 7 6 R158 1 @ 2 0_0603_5%
1
VIN thermal VOUT
1U_0201_6.3V6M
+3VALW
0.1U_0402_10V7K 1
CZ8
PV T - 1 2 4 4 2 3
0.1U_0402_10V7K
Change to short-p a d +5VALW
VBIAS 5 VBIAS
CZ7
C GND_1 9 2 4 5 C
1 GND_2 ON GND
C217 2
1U_0201_6.3V6K
AOZ1336DI_DFN8_2X2 T PS22961DNYR_WSON8
2
PV T - 0 7 3
VCCST G_EN VCCPLL_EN
1 @ 2
RZ1416 0_0201_5%
+3.3V_FPM
VGS = -2.5V, ID = -2.1A , RON = 110m ohm
RUN_ON(VS EN)
VGS = -4.5V, ID = -2.7A , RON = 80m ohm tCPU06 >100ns
+3VS +3.3V_FPM 2 1
@ RE142 0_0402_5%~D close to PU1400
R256 1 @ 2 0_0402_5% R249 1 2 47K_0201_1% EN_VCCIO (89)
1
+3VALW
+3VALW QV12 PV T - 1 6 2 C368
PJ2301_SOT 23-3 0.47U_0402_6.3V6K
+3.3V_FPM_R 2
5
S
3 1 1 @ 2 SIO_SLP_S3#
D
R298 0_0603_5% 1 RUN_ON_P

1 1 (11,47,58,78,79) SIO_SLP_S3#
P
B
0.1U_0201_10V6K
C306
100P_0201_50V8J
C307 BOM structure = EMC@
4
PV T - 0 7 1 2 O RUN_ON_P (58,68)
G
Change to short-p a d (58) RUN_ON_EC

2
G
UC3 A
1
R258 1 @ 2 0_0201_5% 2 2
(58) FPR_PWR_EN#
3
1 MC74VHC1G08DFT2G_SC70-5 RE122
0.1U_0201_10V6K
C308
100K_0402_5%
Pull H at EC
@
2
2 2 1
@ RE126 0_0402_5%~D
B B
+5V_Dock source
G517G1TO1U_TSOT23 -5 +5V_DOCK
IMVP_VR_ON&VCCST_PWRGD
3.4A/Active High
+5VALW VEN(H) VIH : 1.2V
PV T - 1 6 7 2 1
U13 +5V_DOCK_R 0_0402_5% @ RE32
5 1 1 @ 2
+5VD_R
IN OUT R91 0_0805_5%
1 1 2 3 1 1 +3VALW @ CE3
FLAG
0.1U_0402_10V7K
C81
22U_0603_6.3V6M
C83
R233 100K_0201_5% 4 2
C289 EN(#EN) GND 1 2
1U_0201_6.3V6M G517G1T O1U_T SOT 23-5 UE2 +3VALW
2 2 2 0.1U_0201_10V6K
5
IMVP_VR_ON 1 5
1 IMVP_VR_ON_P_R NC VCC
(58) DOCK_PWR_EN_2in1
P
(58) IMVP_VR_ON B
SIO_SLP_S3# 4 2
2 O A 4
(11,47,58,78,79) SIO_SLP_S3#
2
UE1 A 3 Y VCCST_PWRGD (7,11)

R89 GND
MC74VHC1G08DFT2G_SC70-5
3
100K_0201_5% 74AUP1G07GW_TSSOP5 OPEN-DRAIN OUTPU T S

Pull H 1Kohm +1.0V_VCCST at PCH
1
1 @ 2
RE30 IMVP_VR_ON_P (90)
0_0402_5%
1
RE29 PV T - 1 2 5
100K_0402_5%
2
(+1.2V_USB) For Type A redriver +1.8VA Discharge +1.8VA
+1.8VA
1
Max Current :4A R57

RON : 30m ohm 1 1 1 B+ 80.6_0402_1%~D
+1.2V_DDR
VIH : 1.2V
U38 PV T - 1 6 3 +1.2V_USB C33 C34 C36
1
C332
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2 1 1 7 +1.2V_USB_R 2 2 2 R56
2 VIN_1 VOUT_1 8 1 @ 2 200K_0402_1%
3
A 1U_0201_6.3V6M VIN_2 VOUT_2 R301 A

RUN_ON_P 0_0603_5%
3 6 1 2 QE2B
1 1
2
ON CT
10U_0402_10V6M
C330
0.1U_0201_10V6K
C331
C329 L2N7002DW1T 1G_SC88-6

RUN_ON _ P +3VALW 1000P_0402_25V8J 5
Already PD 100K RE122
4
VBIAS 5 2 2
6
GND_1 9 0514
4
GND_2 Change C329 to 1000P QE2A

1 For 1ms rise time
C333 L2N7002DW1T 1G_SC88-6
1U_0201_6.3V6K AOZ1336DI_DFN8_2X2 2
(11,58) SIO_SLP_SUS#
2
1
Security Classif ication Compal Secret Data Compal Electronics, Inc.

T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENT IAL
P078 - DC/DC & Sequence Logic
AND T RADE SECRET INFORMAT ION. T HIS SHEET MAY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COMPET ENT DIVISION OF R&D Siz e Document Number R ev
DEPART MENT EXCEPT AS AUT HORIZED BY COMPAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORMAT ION IT CONTAINS 0.4
MAY BE USED BY OR DISCLOSED T O ANY T HIRD PART Y WIT HOUT PRIOR WRIT T EN CONSENT OF COMPAL ELECT RONICS, INC. LA-G661P
Monday, January 28, 2019 78 100
D ate: Sheet of
5 4 3 2 1
5 4 3 2 1
EC UART Test Power Button

Debug/80 port +3VALW
D D
PVT-075 DB@
Change to short-pad
SW7
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
@ RE131
RE137 PWRBTN# 1 2
(58,63,77) PWRBTN#
Top
RE138
RE139
RE140
RE141
RE134
RE133
RE132
@
0_0201_5% 3 4
JDEG1 +EC_DEBUG_VCC
2
1 JTAG_TDI
1 2 SKSFABE010_4P
2 JTAG_TMS JTAG_TDI (58)
3 JTAG_CLK
3 JTAG_TMS (58)
4 JTAG_TDO
4 JTAG_CLK (58)
5
5 JTAG_TDO (58)
6 MSCLK
6 7 MSDATA
7 HOST_DEBUG_TX
8 DEBUG_TX
1
8 9
9 10
10 10K_0201_5%
RE130 1 @ 2 0_0201_5% RE136
(14) SBIOS_TX
11 1 @ 2
2
GND1 12 RE135 0_0201_5%
GND2
HOST_DEBUG_TX (58)
PVT-074
ACES_50521-01041-P01
MSDATA (58) Change to short-pad
MSCLK (58)
CONN@
C C
ESPI
BIOS debug APS CONN
JAPS1
1
+3VS +3V_PCH 1
LPC 80Port 2
JESPI1 Debug (11,47,58,78) SIO_SLP_S3# 3 2
LPC ESPI +3VALW
1 4 3
2 1 (11) SIO_SLP_S5# 5 4
1 +3VS +3VS
3 2 (11,73,78,87) SIO_SLP_S4#_AND 6 5
(9,58) ESPI_IO0 4 3 (11) SIO_SLP_A# 7 6
2 +3VS +3VS +3V_PCH
(9,58) ESPI_IO1 5 4 8 7
(9,58) ESPI_IO2 5 8
6 3 LPC_LAD0 ESPI_IO0 9
(9,58) ESPI_IO3 7 6 (11,49) PCH_RTCRST# 10 9
(9,58) ESPI_CS# 7 10
RE129 1 @ 2 0_0201_5% 8 4 LPC_LAD1 ESPI_IO1 11
(9,58) ESPI_RESET# 8 (7,11,58) SIO_PWRBTN# 11
(11,47,52,53,66,68,70,79) PCH_PLTRST#_AND
RE128 1 @ 2 0_0201_5% 9 12
10 9 5 LPC_LAD2 ESPI_IO2 13 12
(9,58) ESPI_CLK_5105 10 (11) SYS_RESET# 13
14
6 LPC_LAD3 ESPI_IO3 15 14
11 (11,66,89,90) SIO_SLP_S0# 16 15
12 GND1 7 LPC_FRAME# ESPI_CS# 17 16
GND2 18 17
8 PCH_PLTRST# NA 19 18
ACES_50521-01041-P01 20 GND
CONN@ 9 GND GND GND
CONN@
10 LPC_CLK ESPI_CLK ACES_50506-01841-P01
B B
DEBUG LED
+3VS +3V_PCH +LCDVDD
1
DB@ DB@
1
R283 R284 DB@

300_0402_5% 300_0402_5% R163
100_0402_5%
2
2 2
2
DB@ DB@ DB@

LED_RUN LED_PRI LED2
HT-191UD5_AMBER HT-191UD5_AMBER HT-191UD5_AMBER
A
A A
1
(58) RUNPWROK
(58) PRIM_PWRGD
1
D DB@
2 Q9
(11,47,52,53,66,68,70,79) PCH_PLTRST#_AND
G L2N7002WT1G_SC-70-3
S
3

P079 - Debug APS,DEG,eSPI,LED
5 4 3 2 1
A B C D E
DMIC_CLK12 DMIC_CLK12 DMIC_CLK34

New Tooling in DVT DMIC_DATA12 DMIC_DATA12 DMIC_DATA34
MIC1 MIC2 Front Camera + IR Rear Camera + DMIC

New applying
FPC 10pin
FPC 10pin
Laverage others project
42pin
42pin
1 1
Leverage PBC MLK
Power BTN
LED (6Pin)
JDMIC1 JDMIC2 JBTN1 FPC 14pin
JA1(HP) (MIC1) p.32 (MIC2) p.32 JUFC1 JWFC1
p.33 p.45 p.42
Power BTN
LED
FingerPrint
p.53 FP 8pin
VOL+
SW1 JFAN1
p.49 FPC 8pin
VOL-
SW2
p.50 FP 8pin
Slot 2-Key-B
3042
JSIM1
p.30
M/B WLAN
JNGFF3 Slot 1-Key-E
2230
FP module 2
WWAN&2nd SSD
p.28
JNGFF1 p.29
JCR1
p.31 JRTC1
p.50 USB/B JUSBA1
p.03
PJT1 FPC 42Pin
(BATT) p.60 JIO1 p.30 JIO2p.04
Maini SSD
USH Wire 12 Pin
JNGFF2 CONN
p.27
FPC 30 Pin
TBT
Type C
Slot 3-Key-M
2230
JUSH1 JUSH2
p.3 USH/B NFC/RFID Smart Card
p.49 CONN. CONN
JUSBC1 JNFC1 JSC1
3
p.40 p.6 p.4 BATTERY 3
TBT
eDP 38Whr
CONN
Type C 2S1P
eDP+TS 42Pin
JUSBC2 Speaker Dock JEDP1 LCD Panel + Touch
p.40 CONN CONN p.26
12.3" 3:2
JSPK1 JDOCK1
p.33 p.49
FPC 20pin
Dock FPC (TBD)
4 4
Base Board
LS-D893P
P080 - DaughterB Block Diagram
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-G661P 0.4

A B C D E
5 4 3 2 1
Augusta_WHL Power Path Block

2019/02/11
D D
C C
B B
A A

PWR_POWER PATH DIAGRAM
Date : Friday, February 15, 2019 Shee t 81 of 100
5 4 3 2 1
5 4 3 2 1
Function feild：
Rest of support elements (37.1), EMC Part(47.1)
Type C adapter input_1

+VBUS1_PD_20V DVT1 8/29 change footprint
S1a S1b
+VBUS1_20V
PQS101
AON7405_DFN8-5
PQS102
AON7405_DFN8-5
+CHG_VIN_20V
@ PTS101
PAD~D EMC@ PLS101 1 1
HCB2012KF-800T50_2P 2 PD1_LPS2 2
1
1 2 5/11 for derating issue 3 5 5 3
1
300K_0201_1%
300K_0201_1%
PRS106
PRS108
4
4
2200P_0402_50V7K
0.01U_0402_25V7K
2200P_0402_50V7K
1000P_0201_50V7K
S TR AO7401 1P SC70-3
1
100P_0201_25V7K
100P_0201_25V7K
1U_0603_25V6K
10U_0603_25V6M
PCS101
PCS102
PCS103
PCS104
PCS105
PCS106
PCS107
PCS108
PCS109
0.1U_0402_25V6
0.1U_0402_25V6
1M_0402_1%
S TR AO7401 1P SC70-3
+3VALW
1
1
PCS110
@ PRS101
0.47U_0402_25V6K
3
1
680P_0402_50V7K
S
499K_0402_1%
D 5/11 for derating issue D
499K_0402_1%
1
2
1
3
PQS103
PCS111
@ PCS112
PRS104
G S
2
PRS102
2
1
PQS104
200K_0201_5%
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
EMC@
G
2
2
+3VALW +3V_LDO
PRS26
D
2
1
2
PD1_LPS1 330K_0201_1%
D
1
PRS107
PRS27 PRS36
2
From Charger
1
200K_0201_5%
0_0402_5% 200K_0402_1%
1 2 1 2
PRS24
SB000006O00
2
AC_DISC_OUT# (83) (58,74) DET_L#_2in1
1
PRS515 Use SB000004A0L footpin
330K_0201_1%
1
6
49.9K_0402_1%
0_0402_5% DVT2 12/03 : for EE suggest
PRS109
PD1_LPS1
1
PRS105
200K_0402_1%
1 2 PRS23 PRS25
PQS14A
PRS35
DVT2.1: 2/11 short pad 0_0402_5% 0_0402_5%
To EC AC_DIS#
+3V_LDO
1
49.9K_0402_1%
@ PRS514 Add swap solution 1 (58) AC_DISC#
1 2 1 2 2
2
1
1
D
PRS103
0_0402_5%
2
6
0_0402_5%
PQS502
1 2 2 PRS30
PRS29
2
(58,82) VBUS2_ECOK
1000P_0201_50V7K
PRS110 DVT2.1: 2/11 short pad 0_0402_5%
G To Charger
1
PQS105A
PRS33
1
@ PCS6
S 200K_0201_5% @ PRS118 1 2 CHG_PROCHOT# (83)
1 2
3
2
(58) DET_R#_2in1
1
1 2 2 D
200K_0201_5%
0_0402_5%
+3V_LDO
2
0_0402_5%
3
PQS108
2 1 2
PRS120
2
VBUS1_ECOK (58,82)
G PRS28 DVT2 12/03 : for EE suggest 2.13V when
PQS11A
PQS14B
6
S 0_0402_5% PRS32
3
docked
1
DVT2.1: 2/11 short pad 2 1 2 5 D 0_0402_5%
PQS106A
PQS15
@ PRS507 2 1 2
DET_R (74)
PQS105B
0_0402_5% 1 2 2 G
1
1 2 5 S
3
PRS113 PRS512 PRS119
PQS107A
@ PCS502 0_0402_5% 1M_0201_1%
200K_0201_5% PRS31
1
3
1 2 1 2 1 2 2 DVT2.1: 2/11 short pad 390K_0402_1%
+3V_LDO +3V_LDO
4
@ PRS526
2
PQS106B
0.1U_0402_25V6 1 2 0_0402_5%
5
DCIN1_EN_R
@ PRS508 1 2 5
1
PRS112 (43,82,83) EN_PD_HV1
0_0402_5% @ PRS111
VCC
0_0402_5% 1M_0201_1%
1 2 1 PRS114
(43,82,83) EN_PD_HV1 IN1
DCIN1_EN_R 4 1 2 1M_0201_1%
4
1 2 2 OUT PRS115 PQS107B 1 2 @ PRS121 PRS122
GND
IN2

Dell Latitude 7200 La-G661p r0.4 (x03)

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Dell Latitude 7200 La-G661p r0.4 (x03)

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A B C D E

MODEL NAME : APRDDB2000

EMC@ : EMI Component

ST33TPHF2XSP I IR discrete LDO*2 1.2V, 2.8V,

DMI C CSR1021 GPIO PTP_MODE #

VBUS CHRG_IN DP1.2 x 4lanes DDI#2

USB3.0 / DP x 2lanes or DP x 4 lanes

EC JTAG MIPI60 Debug

Security Classification Compal Secret Data Compal Electronics, Inc.

DVT2 DVT2.1 PVT

3 33K +/- 5% 4700p PVT

8 PCI-E #8 Hynix 4GB/2133

USB 2.0 9 PCI-E #9 Card reader

1 TBT1 Hynix 16GB/2133

4 Dock Samsung 8GB/2133

EC Touch BASE Gyro+ACC PS8811 UCPU1

Security Classification Compal Secret Data Compal Electronics, Inc.

ALWON_P WR(E C) RUN_O N_ P

(PU501) +5VD TPS22967DSGR +5VS USH Board RB41

Date : Monday , January 28, 2019 Sh e e t 4 of 100

SRTCRST# / RTCRST# tPCH01 18 - 25 ms SRTCRST# / RTCRST# tPCH01 18 - 25 ms

D PD Output EN_PD_HV1 (S1a) Power path S1a ON

S1b pass through

+3VALW / +5VALW / +5VD

Power path S1b ON

PCH Output SIO_SLP_S US # tPCH32 > 95ms

PCH Output SIO_SLP _S 0#

PCH Output CPU_C10_GATE#

PCH Output SUSCLK tPCH31 < 10ms+95ms

Input to EC PRIM_P W RGD

EC Output AC_PRESENT (AC only) tPLT02 < 0ms

EC Output SIO_PWRBTN# tPCH43 > 95ms

PCH Output SIO_SLP _S 5#

PCH Output SIO_SLP _S 4#

PCH Output SIO_SLP_W LAN#

PCH Output SIO_SLP _S 3#

+5VS / +3VS / +1.8VS / +1.2V_USB.....

+1.0V_VCCS TG tCPU03 < 25ms tCPU04 > 0ms

+1.0VS_V CCI O tCPU05 > 100ns tCPU06 > 100ns

Input to EC RUNPWROK (DDR_PG / PG_VCCIO)

PCH Output DDR_VTT_CNTL tCPU19 > 100ns

+0.6V S tCPU18 > 35us

IMVP Output IMVP_V R_P G

PCH Output H_CPUPWRGD (PROCPWRGD)

PCH Output PCH_PLTRS T#

Security Classification Compal Secret Data Compal Electronics, Inc.

GPP_H17 (WEAK INTERNAL PD)

Security Classification Compal Secret Data Compal Electronics, Inc.

Follow PBC MLK

<To CPU JTAG>

Place near JXDP1.47 Place near JXDP1.48 Place near JXDP1.41

Jony12/14:572136_CFL_U_LP3_Memory_Design_Sch_WP_Rev0p5.pdf - Keep setting

74AUP1G07GW_TSSOP5 2 RC258 1 2 162_0402_1%

RC155 1 @ 2 0_0402_5% Max trace length= 500 mil

RH32 1 2 100K_0402_5% RH27 1 2 100K_0402_5% RH34 1 2 100K_0402_5%

Intel ME Crypto (TLS)Transport Layer Security

MEM_SMBCLK DDR_XDP_SMBCLK DDR_XDP_SMBDAT

SPI ROM FOR ME ( 32 MByte )

BIOS ROM Option

PD close to PCH +3VS

Cap placeholder for DMIC_CLK only

Low = Disabled (cannot f l as h)

CLKREQ_PCIE# input O.D.