Verilog Hardware Description Language

(Verilog HDL)
Types of Modelling
Gate level Modelling / Structural Modelling (Using Gate primitives)
Data flow Modelling (Using Verilog Operators)
Behavioral Modelling (Using Initial and Always block)

module

HDL (Hardware Description Language) 1. Gate-level/Structural modeling

1. Verilog HDL
2. VHDL
module logic_gates (A,B,y0,y1,y2,y3,y4,y5,y6,y7);
input A,B;
output y0,y1,y2,y3,y4,y5,y6,y7;
or g1(y0,A,B);
nor g2(y1,A,B);
and g3(y2,A,B);
nand g4(y3,A,B);
xor g5(y4,A,B);
xnor g6(y5,A,B);
The inputs of the gates are A and B. not g7(y6,A);
The output of the gates are y0, endmodule
y1,y2,y3,y4,y5 and y6.

Half Adder: module half_adder(A,B,SUM,CARRY);

input A,B;
output SUM,CARRY;
xor g1(SUM,A,B);
and g2(CARRY,A,B);
endmodule

Full Adder: module full_adder(A,B,C,SUM,CARRY);

input A,B,C;
output SUM,CARRY;
wire w1,w2,w3;
xor g1(w1,A,B);
and g2(w2,w1,C);
and g3(w3,A,B);
xor g4(SUM,w1,C);
or g5(CARRY,w2,w3);
endmodule
1. Gate-level/Structural modeling 2. Data flow modeling

module logic_gates (A,B,y0,y1,y2,y3,y4,y5,y6,y7); module logic_gates(A,B,y0,y1,y2,y3,y4,y5,y6,y7);

input A,B; input A,B;
output y0,y1,y2,y3,y4,y5,y6,y7; output y0,y1,y2,y3,y4,y5,y6,y7;
or g1(y0,A,B); assign y0= A|B;
nor g2(y1,A,B); assign y1= ~(A|B);
and g3(y2,A,B); assign y2= A&B;
nand g4(y3,A,B); assign y3= ~(A&B);
xor g5(y4,A,B); assign y4= A^B;
xnor g6(y5,A,B); assign y5= ~(A^B);
not g7(y6,A); assign y6= ~A;
endmodule endmodule

module half_adder(A,B,SUM,CARRY); module half_adder(A,B,SUM,CARRY);

input A,B; input A,B;
output SUM,CARRY; output SUM,CARRY;
xor g1(SUM,A,B); assign SUM=A^B;
and g2(CARRY,A,B); assign CARRY=A&B;
endmodule endmodule
module full_adder(A,B,C,SUM,CARRY); module full_adder(A,B,C,SUM,CARRY);
input A,B,C; input A,B,C;
output SUM,CARRY; output SUM,CARRY;
wire w1,w2,w3; wire w1,w2,w3;
xor g1(w1,A,B); assign w1= A^B;
and g2(w2,w1,C); assign w2= w1&C;
and g3(w3,A,B); assign w3=A&B;
xor g4(SUM,w1,C); assign SUM=w1^C;
or g5(CARRY,w2,w3); assign CARRY=w2|w3;
endmodule endmodule

module full_adder(A,B,C,SUM,CARRY);
input A,B,C;
output SUM,CARRY;

assign SUM= (A^B)^C;

assign CARRY = ((A^B)&C)|(A&B);
endmodule
2. Data flow modeling 3. Behavioral modeling
module logic_gates(A,B,y0,y1,y2,y3,y4,y5,y6); module logic_gates(A,B,y0,y1,y2,y3,y4,y5,y6);
input A,B; input A,B;
output y0,y1,y2,y3,y4,y5,y6; output reg y0,y1,y2,y3,y4,y5,y6;
assign y0= A|B; always @(A,B)
assign y1= ~(A|B); begin
assign y2= A&B; y0<= A|B;
assign y3= ~(A&B); y1<= ~(A|B);
assign y4= A^B; y2<= A&B;
assign y5= ~(A^B); y3<= ~(A&B);
assign y6= ~A; y4<= A^B;
endmodule y5<= ~(A^B);
y6<= ~A;
end
endmodule

module half_adder(A,B,SUM,CARRY); module half_adder(A,B,SUM,CARRY);

input A,B; input A,B;
output SUM,CARRY; output reg SUM,CARRY;
assign SUM=A^B; always @(A,B)
assign CARRY=A&B; begin
endmodule SUM<=A^B;
CARRY<=A&B;
end
endmodule

module full_adder(A,B,C,SUM,CARRY); module full_adder(A,B,C,SUM,CARRY);

input A,B,C; input A,B,C;
output SUM,CARRY; output reg SUM,CARRY;
wire w1,w2,w3; reg w1,w2,w3;
assign w1= A^B; always @(A,B,C)
assign w2= w1&C; begin
assign w3=A&B; w1= A^B;
assign SUM=w1^C; w2= w1&C;
assign CARRY=w2|w3; w3=A&B;
endmodule SUM=w1^C;
CARRY=w2|w3;
end
endmodule
module full_adder(A,B,C,SUM,CARRY); module full_adder(A,B,C,SUM,CARRY);
input A,B,C; input A,B,C;
output SUM,CARRY; output reg SUM,CARRY;
reg w1,w2,w3;
assign SUM= (A^B)^C; always @(A,B,C)
assign CARRY = ((A^B)&C)|(A&B); begin
endmodule SUM= (A^B)^C;
CARRY = ((A^B)&C)|(A&B);
end
endmodule
Blocking assignment operator (=)

Non-blocking assignment operator(<=)

a=5, b=7, c=0, d

c=a+b \\12
d=a+c \\17

c<=a+b \\ 12
d<=a+c \\ 5
 module DFF(D,clk,preset,clr,q,qbar);
input D,clk,clr,preset;
output reg q,qbar;
always @(posedge clk)
begin
if(clr==1)
begin
q<=0;
qbar<=1;
end
else if(preset==1)
begin
q<=0;
q<=1;
q<=q
qbar<=0;
end
else
begin
if(d==1)
begin
q<=1;
qbar<=0;
end

else
begin
q<=0;
qbar<=1;
end

end
end
endmodule
module TFF(T,clk,clr,q,qbar);
input T,clk,clr;
output reg q,qbar;
always @(posedge clk)
begin
if(clr==1)
begin
q<=0;
qbar<=1;
end

else
begin
if(T==1)
begin
q<=qbar;
qbar<=q;
end
 else
begin
q<=q;
qbar<=qbar;
end

end
end
endmodule

module JKFF(J,K,clk,clr,preset,q,qbar);
input J,K,clk,clr,preset;
output reg q,qbar;
always @(posedge clk)
begin
if(clr==1)
begin
q<=0;
qbar<=1;
end
if(preset==1)
begin
q<=1;
qbar<=0;
end

else
begin
if ((J==0)&&(K==0))
begin
q<=q;
qbar<=qbar;
end
else if ((J==0)&&(K==1))
begin
q<=1’b0;
qbar<=1’b1;
end

else if ((J==1)&&(K==0))
begin
q<=1’b1;
qbar<=1’b0;
end

else
begin
q<=qbar;
qbar<=q;
end
 end
end
endmodule

If(a==1)