HERITAGE INSTITUTE OF TECHNOLOGY

Class Test : Odd Semester 2020

Year : 2 Discipline : CSE
Paper Code : ECEN 2104 Paper Name : Digital Logic

Time Allotted : 1 hr Full Marks : 30

Figures out of the right margin indicate full marks.

Answer all the questions
Candidates are required to give answer in their own words as far as practicable.
Part - A

1. Choose the correct alternatives for the following: 10 × 1 = 10

(i) The Equivalent Binary and Gray code for the Decimal Number 55 are _____ and
_____ respectively
(a) (010101)2, (110101)G (b) (000111)2, (110110)G
(c) (111101)2, (110010)G (d) (110111)2, (100101)G
(ii) In a XOR Gate designed by NAND Gate only, the Minimum No. of NAND Gates
required is ___
(a) 2 (b) 3
(c) 4 (d) 5
(iii) The 1’s Compliment and 2’s Compliment of the Decimal Number 37 are _____ and
_____ respectively
(a) 011010, 011011 (b) 111011, 111100
(c) 100101, 001001 (d) 000011, 100100
(iv) For a 3-I/P Function, the Dual Form of f = ∑ (0, 2, 4, 6) is ________
(a) F = π (1, 2, 3, 4) (b) F = π (1, 3, 5, 7)
(c) F = π (0, 3, 5, 7) (d) f = ∑ (1, 3, 5, 7)
(v) For (AND and NAND) Gates, the Disabling and Enabling Logic Values are _____
and _____ respectively
(a) 1, 0 (b) 0, 1
(c) All of the Above (d) None of the Above
(vi) A 1-bit full adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit.What
is the maximum rate of addition per second when four 1-bit full adders are cascaded?
(a) 107 (b) 1.25×107
6
(c) 6.25×10 (d) 105
(vii) Which one of the following can be used as a parallel to serial converter
(a) Decoder (b) Digital counter
(c) Multiplexer (d) Demultiplexer
(viii) The number of 4- line-to-16- line decoders required to make an 8- line-to -256 line
decoder is
(a) 16 (b) 17
(c) 32 (d) 64
(ix) For a binary half subtractor having two inputs A and B, the correct sets of logic
expressions for the output D(Difference) and X(Borrow) are
 HERITAGE INSTITUTE OF TECHNOLOGY
Class Test : Odd Semester 2020
Year : 2 Discipline : CSE
Paper Code : ECEN 2104 Paper Name : Digital Logic

(a) D = AB + AB, X = AB (b) D = AB + AB, X = AB

(c) D = AB + AB, X = AB (d) D = AB + A B, X = AB
(x) Assertion (A): A carry look ahead adder is a fast adder
Reason (R): A parallel carry adder generates sum digits directly from the input digits
(a) Both A and R are true and R is the correct explanation of A
(b) Both A and R are true and R is NOT the correct explanation of A
(c)A is true but R is false
(d)A is false but R is true

Part - B

2. (a) Convert the decimal number 67 to its equivalent binary form and Gray code (5) + (5) =
and design the relevant logic circuits for the conversion. 10
(b)
Derive the logic expression and logic circuit for the given function
f = ∑ m (0, 2, 4, 6) .

3. (a) A half adder is implemented with XOR and AND gates. A full adder is (3) + (3)
implemented with two half adders and one OR gate. The propagation delay +(4) = 10
of an XOR gate is twice that of AND/OR gate.The propagation delay of an
AND/OR gate is 1.2 microsecond. A 4 bit ripple carry binary adder is
implemented by using 4 full adders. What will be the total propagation delay
of this 4 bit binary adder?
(b) Realise a full adder using 3:8 decoder and OR gates.

(c) A circuit outputs a digit in the form of 4 bits, where 0 is represented by 0000,
1 is represented by 0001, ….. 9 by 1001. A combinational circuit is to be
designed which takes these 4 bits as input and output 1 if the digit>=5 and 0
otherwise. If only AND , OR, NOT gates are used, what will be the minimum
number of gates required? Draw the complete circuit and write the truth
table.

Upload the softcopy of the answer script in the prescribe format in the following link
Sec-A: https://classroom.google.com/c/MjQxNTY3NDc5OTQ0/a/MjE1MTAyMjUwMDU3/details
Sec-B: https://classroom.google.com/c/MjEyMTIzNDkwMjk4/a/MjQxNjQ3MTAwMTMz/details
Sec-C: https://classroom.google.com/u/0/w/MTI2MzQ5ODQ4NjYy/tc/MjQxNjI5ODgyMDg3