Coverage Report by file with details

File: ../rtl/read_write_controller.v
Toggle Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Toggle Bins 100 64 36 64.0

================================Toggle Details================================
0 0 3 0.00
15 reg_TSR[6] 0 0
0 0 0 0 3 0.00
15 reg_TSR[5] 0 0
0 0 0 0 3 0.00
15 reg_TSR[4] 0 0
0 0 0 0 3 0.00
15 reg_TSR[3] 0 0
0 0 0 0 3 0.00
15 reg_TSR[2] 0 0
0 0 0 0 3 0.00
15 reg_TSR[1] 1 17
0* 0* 0* 0* 2-STATE 100.00
15 reg_TSR[0] 1 14
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[7] 18 19
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[6] 1 2
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[5] 6 20
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[4] 18 41
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[3] 2 2
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[2] 2 3
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[1] 6 20
0* 0* 0* 0* 2-STATE 100.00
15 reg_TCR[0] 7 21
0* 0* 0* 0* 2-STATE 100.00
79 check 3 3
0* 0* 0* 0* 2-STATE 100.00

========
(n*) - Number was not used in coverage calculations performed by extended toggle
algorithms.

Extended Toggle Coverage Calculation Criteria:

-----------------------------------------------
ExtMode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
ExtMode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
ExtMode 3: 0L->1H & 1H->0L & all 'Z' transitions.
========

Total Node Count = 38

Toggled Node Count = 32
Untoggled Node Count = 6

Toggle Coverage = 64.0% (64 of 100 bins)

File: ../testbench/test_bench.v
Toggle Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Toggle Bins 282 60 222 21.2

================================Toggle Details================================

Toggle Coverage for File ../testbench/test_bench.v --

Line Node 1H->0L 0L->1H

0L->Z Z->0L 1H->Z Z->H1 ExtMode "Coverage"
-----------------------------------------------------------------------------------
---------------------------------------------------------------
4 udf 17 17
0* 0* 0* 0* 2-STATE 100.00
4 ovf 14 14
0* 0* 0* 0* 2-STATE 100.00
15 clk_in 46 46
0* 0* 0* 0* 2-STATE 100.00
21 clk_out 46 46
0* 0* 0* 0* 2-STATE 100.00
22 rise_edge_detect 46 46
0* 0* 0* 0* 2-STATE 100.00
31 cnt[7] 27 33
0* 0* 0* 0* 2-STATE 100.00
31 cnt[6] 28 34
0* 0* 0* 0* 2-STATE 100.00
31 cnt[5] 30 37
0* 0* 0* 0* 2-STATE 100.00
31 cnt[4] 33 39
0* 0* 0* 0* 2-STATE 100.00
31 cnt[3] 38 41
0* 0* 0* 0* 2-STATE 100.00
31 cnt[2] 41 43
0* 0* 0* 0* 2-STATE 100.00
31 cnt[1] 42 43
0* 0* 0* 0* 2-STATE 100.00
31 cnt[0] 42 43
0* 0* 0* 0* 2-STATE 100.00
32 count[2] 18 41
0* 0* 0* 0* 2-STATE 100.00
32 count[1] 46 46
0* 0* 0* 0* 2-STATE 100.00
32 count[0] 6 20
0* 0* 0* 0* 2-STATE 100.00
33 load_detected 18 19
0* 0* 0* 0* 2-STATE 100.00
8 up_down 6 20
0* 0* 0* 0* 2-STATE 100.00
8 udf 17 17
0* 0* 0* 0* 2-STATE 100.00
8 ovf 14 14
0* 0* 0* 0* 2-STATE 100.00
8 load 18 19
0* 0* 0* 0* 2-STATE 100.00
8 en 18 41
0* 0* 0* 0* 2-STATE 100.00
 9 reg_TDR[7] 3 11
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[6] 2 10
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[5] 2 12
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[4] 1 9
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[3] 3 13
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[2] 4 14
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[1] 3 13
0* 0* 0* 0* 2-STATE 100.00
9 reg_TDR[0] 4 13
0* 0* 0* 0* 2-STATE 100.00
11 cks[1] 6 20
0* 0* 0* 0* 2-STATE 100.00
11 cks[0] 7 21
0* 0* 0* 0* 2-STATE 100.00
3 pwrite 45 27
0* 0* 0* 0* 2-STATE 100.00
3 pslverr 0 0
0 0 0 0 3 0.00
3 psel 46 46
0* 0* 0* 0* 2-STATE 100.00
3 preset_n 46 46
0* 0* 0* 0* 2-STATE 100.00
3 pready 1 1
0* 0* 0* 0* 2-STATE 100.00
3 penable 46 46
0* 0* 0* 0* 2-STATE 100.00
3 pclk 46 46
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[7] 21 21
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[6] 12 9
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[5] 29 18
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[4] 44 21
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[3] 14 8
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[2] 15 9
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[1] 29 15
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[0] 29 14
0* 0* 0* 0* 2-STATE 100.00
4 prdata[7] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 prdata[6] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 prdata[5] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 prdata[4] 1 1
0* 0* 0* 0* 2-STATE 100.00
4 prdata[3] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 prdata[2] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 prdata[1] 3 19
0* 0* 0* 0* 2-STATE 100.00
4 prdata[0] 3 15
0* 0* 0* 0* 2-STATE 100.00
4 paddr[7] 0 0
0 0 0 0 3 0.00
4 paddr[6] 0 0
0 0 0 0 3 0.00
4 paddr[5] 0 0
0 0 0 0 3 0.00
4 paddr[4] 0 0
0 0 0 0 3 0.00
4 paddr[3] 0 0
0 0 0 0 3 0.00
4 paddr[2] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 paddr[1] 46 46
0* 0* 0* 0* 2-STATE 100.00
4 paddr[0] 22 14
0* 0* 0* 0* 2-STATE 100.00
5 clk[3] 46 46
0* 0* 0* 0* 2-STATE 100.00
5 clk[2] 46 46
0* 0* 0* 0* 2-STATE 100.00
5 clk[1] 46 46
0* 0* 0* 0* 2-STATE 100.00
5 clk[0] 46 46
0* 0* 0* 0* 2-STATE 100.00
6 cnt_err[9] 0 0
0 0 0 0 3 0.00
6 cnt_err[8] 0 0
0 0 0 0 3 0.00
6 cnt_err[7] 0 0
0 0 0 0 3 0.00
6 cnt_err[6] 0 0
0 0 0 0 3 0.00
6 cnt_err[5] 0 0
0 0 0 0 3 0.00
6 cnt_err[4] 0 0
0 0 0 0 3 0.00
6 cnt_err[3] 0 0
0 0 0 0 3 0.00
6 cnt_err[31] 0 0
0 0 0 0 3 0.00
6 cnt_err[30] 0 0
0 0 0 0 3 0.00
6 cnt_err[2] 0 0
0 0 0 0 3 0.00
6 cnt_err[29] 0 0
0 0 0 0 3 0.00
6 cnt_err[28] 0 0
0 0 0 0 3 0.00
6 cnt_err[27] 0 0
0 0 0 0 3 0.00
6 cnt_err[26] 0 0
0 0 0 0 3 0.00
 6 cnt_err[25] 0 0
0 0 0 0 3 0.00
6 cnt_err[24] 0 0
0 0 0 0 3 0.00
6 cnt_err[23] 0 0
0 0 0 0 3 0.00
6 cnt_err[22] 0 0
0 0 0 0 3 0.00
6 cnt_err[21] 0 0
0 0 0 0 3 0.00
6 cnt_err[20] 0 0
0 0 0 0 3 0.00
6 cnt_err[1] 0 0
0 0 0 0 3 0.00
6 cnt_err[19] 0 0
0 0 0 0 3 0.00
6 cnt_err[18] 0 0
0 0 0 0 3 0.00
6 cnt_err[17] 0 0
0 0 0 0 3 0.00
6 cnt_err[16] 0 0
0 0 0 0 3 0.00
6 cnt_err[15] 0 0
0 0 0 0 3 0.00
6 cnt_err[14] 0 0
0 0 0 0 3 0.00
6 cnt_err[13] 0 0
0 0 0 0 3 0.00
6 cnt_err[12] 0 0
0 0 0 0 3 0.00
6 cnt_err[11] 0 0
0 0 0 0 3 0.00
6 cnt_err[10] 0 0
0 0 0 0 3 0.00
6 cnt_err[0] 1 8
0* 0* 0* 0* 2-STATE 100.00

========
(n*) - Number was not used in coverage calculations performed by extended toggle
algorithms.

Extended Toggle Coverage Calculation Criteria:

-----------------------------------------------
ExtMode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
ExtMode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
ExtMode 3: 0L->1H & 1H->0L & all 'Z' transitions.
========

Total Node Count = 67

Toggled Node Count = 30
Untoggled Node Count = 37

Toggle Coverage = 21.2% (60 of 282 bins)

File: ../vip/cpu_model.v
Statement Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Stmts 37 35 2 94.5
================================Statement Details================================

Statement Coverage for file ../vip/cpu_model.v --

22 2 while (pready != 1) @(posedge pclk);

41 2 while (pready != 1) @(posedge pclk);
Toggle Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Toggle Bins 58 28 30 48.2

================================Toggle Details================================

Toggle Coverage for File ../vip/cpu_model.v --

Line Node 1H->0L 0L->1H

0L->Z Z->0L 1H->Z Z->H1 ExtMode "Coverage"
-----------------------------------------------------------------------------------
---------------------------------------------------------------
4 pwrite 45 27
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[7] 21 21
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[6] 12 9
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[5] 29 18
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[4] 44 21
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[3] 14 8
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[2] 15 9
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[1] 29 15
0* 0* 0* 0* 2-STATE 100.00
4 pwdata[0] 29 14
0* 0* 0* 0* 2-STATE 100.00
4 psel 46 46
0* 0* 0* 0* 2-STATE 100.00
4 penable 46 46
0* 0* 0* 0* 2-STATE 100.00
4 paddr[7] 0 0
0 0 0 0 3 0.00
4 paddr[6] 0 0
0 0 0 0 3 0.00
4 paddr[5] 0 0
0 0 0 0 3 0.00
4 paddr[4] 0 0
0 0 0 0 3 0.00
4 paddr[3] 0 0
0 0 0 0 3 0.00
4 paddr[2] 2 2
0* 0* 0* 0* 2-STATE 100.00
4 paddr[1] 46 46
0* 0* 0* 0* 2-STATE 100.00
4 paddr[0] 22 14
0* 0* 0* 0* 2-STATE 100.00
========
(n*) - Number was not used in coverage calculations performed by extended toggle
algorithms.

Extended Toggle Coverage Calculation Criteria:

-----------------------------------------------
ExtMode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
ExtMode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
ExtMode 3: 0L->1H & 1H->0L & all 'Z' transitions.
========

Total Node Count = 19

Toggled Node Count = 14
Untoggled Node Count = 5

Toggle Coverage = 48.2% (28 of 58 bins)

File: run_test.v
Statement Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Stmts 55 54 1 98.1

================================Statement Details================================

Statement Coverage for file run_test.v --

Branch Coverage:
Enabled Coverage Active Hits Misses % Covered
---------------- ------ ---- ------ ---------
Branches 10 7 3 70.0

================================Branch Details================================

Branch Coverage for file run_test.v --

------------------------------------IF Branch------------------------------------
13 810 Count coming in to IF
13 1 11 force pready = 1'b0;
15 1 ***0*** release pready;
Branch totals: 1 hit of 2 branches = 50.0%

------------------------------------IF Branch------------------------------------
14 14 Count coming in to IF
14 1 14 #500;
16 1 ***0*** //
Branch totals: 1 hit of 2 branches = 50.0%

------------------------------------IF Branch------------------------------------
42 10 Count coming in to IF
Branch totals: 1 hit of 2 branches = 50.0%

Total Coverage By File (code coverage only, filtered view): 67.0%