Miniproject1

EEE40002 INTEGRATED CIRCUIT
DESIGN
Mini-Project 1: Hardware Modelling Design of an

ALU (Arithmetic Logic Unit)
Insaf Saifudeen Mohamed – 101222106
13 April 2021
PART 1 A
Introduction
The DE1 board provides 10 toggle switches, called SW−90, which can be used as inputs to a circuit, and 10 red
lights, called LEDR9−0, that can be used to display output values. What are asked to do is to program the FPGA
where each switch toggles the RLEDs right above it when the switch is turned on and off the RLEDs follow for each
switch.
VHDL file for the code in Figure 1
For the above figure VHDL was used to implement it in the following manner where,
Each led is controlled by a single switch.
Include in your project the required pin assignments for the DE1
board.
AS can be seen from the blow diagram switches and LEDs are assigned to specific locations based on “DE
1 pin assignment” as seen in the location column in the pin assignment diagram below.
Download the compiled circuit into the FPGA chip.
. now after flashing the generated programming file on the FPGA chip to test the functionality of the circuit
switches can be toggled in any manner and the specific LEDR will be toggled. Below diagrams are some
instances when the switches were toggled in different orders
SW LEDR
SW <= 1110001110 LEDR<= 1110001110
SW <= 1010101010 LEDR<= 1010101010
SW<= 1101101101 LEDR<= 1101101101
SW <=0101010101 LEDR<= 0101010101
PART 1 B
Introduction
The DE1 board also provide an internal clock of 50 MHz, use this clock to design a simple binary counter. You are
free to design the output length of this counter. Design a counter that will divide the clock to generate 1 or 2 Hz
signal. Next design a simple state machine that will take this clock signal and drive the 10 LEDR as a light chaser
Using VHDL to design circuit
First, we create a clock divider using the given clock by creating a counter and to determine
length (vector size) of the output (Q) of this counter to reduce the speed of the clock up to 2Hz
following calculation was carried out ( default clock frequency 50Hz)
Vector size Frequency

24
500000
=2.9
224
3 Hz
25 500000
25
=1.49
2
1.5 Hz
26
500000
=0.75
226
Since it was determined the most suitable output length of the counter should be a 25bit, the
25th bit of the vector will give us a clock frequency of 1.5hz and will be used to drive the light
chaser.
Below is the VHDL code for the counter module used for the light chaser.
Since given the opportunity to design a light chaser of our own preference, A state machine
(Moore) is designed with 19 states so that the LED can sequentially blink from SW0 to SW9 and
from SW9 back to SW0 again. The SW value is coded in for every state therefor no need of a
sperate process to be used for it.
To reset the light chaser simply toggling the reset switch will bring the state to s0
XIllinx Simulation
Clock divider
Once the counter divider was created a test was created to observe the simulation waveforms
how this binary counter functioned.
Since the Q(25) will be used as the clock for the light chaser from the below isim simulated
figure
We can see that the clock is divide by 2 going up from Q(0) to Q(24) make its slower until 1.5Hz
State machine
As seen from the above simulation of the state machine the sequence of lights turning on and off can be
observed ( 50 MHz clock was used only for simulation purposes)
Implementation
As seen in the below port mapping diagram 10 LEDs are used as output while only 2 inputs for the clock
and reset has been used which in total is 12 pins has been used.
The sequence of the LEDs are designed in such way it goes from right to left and vice version with a
frequency of 1.5Hz and this can be observed from the demo video in the link below.
PART 2 A
Introduction
VHDL source code that implements the hardware of the sequencer shown below. To do so a DFF is designed and
used 5 times and the clock_div in the previous section was used for this part too.
Using VHDL to design circuit

One D flip flop was created and used multiple times to achieve the required sequencer circuit.
Figure D-ff modeled in VHDL.

Below figure shows how the D flip flop was called several times in the same system
One issue with the given sequencer is no instructions is given on how to start it such as an enable toggle
therefor to force start it the output from last flip flop is XORed with a standard logic signal called
“loading” for a short time period and inputted into the first flip flop.
Simulation
To simulate this sequnecer circuit a test bench for the top level was created and some modifications had
to be done within the stimulus process to obtain the exact simulation of the sequencer, therefor to do
this the clock_period was changed from 10ns to 20ns for simplicity purposes and reset was set to 0
while loading was set to 1 only for one clock period since loading will be required for the first cycle only
after that onwards it is not required since output of 5 th flip flopw will be used for the rest of the
simulation
Figure output seen in waveform in Isim
As seen from the above Isim window the X(0) goes high right when the clock edge is high and loading is
high. This satisfies the expected outcome table below
Implementation
As seen in the above pin planner window reset and loading is mapped to switch 0 and switch 1 while
the 4 outputs are mapped to RLED 0 to 4 in the DE board.
The functionality of this sequencer can be further observed in the demo video.
Part 2 B
Introduction
This sequence circuit is also similar to the previous one what make this differ is that there are delay
within the flip flops. This cannot be implemented since delay specified are 90 & 150 ns therefor only
simulation can be done.
VHDL designing.
The same design used previously can be used to simulate this circuit a small modification has to be done
which adding a generic map so that the customizable propagation delays can be inserted for each
individual FFs of all 5 flip flops.
Since each flip flop has different values for its delay the better option to assign these delay value each
flip flop is by assigning it in the top level therefor it is not required to create separate VHDL module for
individual flip flops. (refer to below set of codes)
Figure declaration of delays in FFs 1 & 2
Simulation
For simulation, a test bench is created and observed by varying the clock period value. The clock period
value was chosen in such way it is less than the delay values of the flip flops ( clock period < 90 & 150 ns)
and in between the delay values of flip flops (150ns > clock period > 90 ns) and higher than the delay
value of flip flops ( clock period > 150ns)
When the clock period is set to 20ns the loading the delay time period of the flip flops can me measure
using the cursors in Isim as we can see the first flip flop toggles at 100ns after loading is set to 1 therefor
100ns minus half clock period will give us 90ns which is the delay fir first flip flop and 160ns minus half
clock period will give us 150ns which is the delay for 2 nd flip flop.
When the clock period is 10ns

When clock period is set to 200ns
There we can conclude that the output waveform fluctuates when the clock period is altered and also
the longer, we choose the clock period the longer the delay
part 3
Introduction
An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and arithmetic micro-operations
on a pair of n-bit operands.
VHDL design implementation
This design is composed of four components connected to form a 4-bit ALU where the results output
using the 7 segment display in DE1 board . The required components are,
 A clock divider to slow down the clock frequency (1 Hz)

 State machine to feed all the required inputs to the ALU
 ALU unit to do the required operations.
 And finally, a 7-segment decoder to convert BCD code into Hex which translates to an output on the
7 segment display
Clock Divider
The clock divider is designed just like in the previous parts where the default 50MHz clock will be used
to create a counter of length 28 bits ( ~ 1 Hz ) and the last bit will be used as our clock which will be fed
to our state machine which changes states. 28 bits was chosen since the output for each state will
appear for almost 1 second time making it easier to observe.
State machine
The function of the state machine is to feed the ALU with the required input to perform the required
calculations. When analyzing the given table of the functions performed by ALU the total number of
operations can be summarized into 12 states which will make it possible to carry out each operation
once.
Therefor in total we consider only 12 combinations of inputs and specific output. The State machine will
feed the ALU with the values for A , B the carry in , operator selector and mode to the ALU
In here only the clock and reset are input while A, B, Operation selector, Mode Selector and Carry in will
be considered as output from the state machine which will later be used to input those to ALU unit.
Once the reset is set to 0 the states from s1 to s12 will cycle periodically at ( ~ 1 Hz)
ALU
ALU is where all the operations take place once the values are inputted to it from the state machine.
For the ALU all predefined operands could be used and declare in a process with a sensitive list of
mode , operation selector, carry in , A and B within the process several if and else if are declared for
different mode and carry in values every if and else if is composed of a case (case is used to make sure
all inputs are prioritized equally.
Every operation is defined within the process except for determining the min and max values to
perform Min and Max operation 2 function are introduced which compares both inputs and output the
input with max and min value.
To perform operations with carry in, A and B are expanded to 5 bits, also.
To include the carryout input A and B is expanded to 5 bits and the carryout bit is declared as the fifth
bit of the outcome of every operation.
Since the Carry in is 0 the carryout will also be zero there only the expansions are done to the input to
have an extra bit to represent carry out.
When the carry in is 1 then it is expanded by 4 bits so that it is also included in every required operation
performed.
Function to determine min and max.

7 segment
a 7-segment decoder to convert BCD code into binary code that translates to an output on the 7
segment display so that it can be viewed in the DE 7 segment display for this we use a decoder which
will convert BCD to binary code to output in the 7-segment display in hex.
When the result is more than ten then its represented in hexadecimal therefore
Simulation
Once all the component were created a top level was created to and connection were made using port
mapping then a test bench was created to simulate it below Isim window shows the outcome.
The pin planner table for the output and inputs can be seen below
HEX ( 0 -3) represent the inputs A , B and the outputs Carry out and Result of the operation carried out
all in hexadecimal values
Implementation
After simulating and confirming the functionality of the system implementing in the DE board using
Quartus was carried out.
Below is the flow summary page after running the VHDL codes in quartus software
45 pins are used to implement the functions of ALU below diagram is picture of the DE board with its
inputs and outputs are labelled.
HEX3 = input B HEX2 = input A HEX1 = Carry out HEX0 = Result
Carry In
S1 S0
Input B in Input A Results in
binary In binary Reset SW binary
Once the design is implemented and flashed to the DE board the outputs of each state are as follows
STATE FPGA Output
S0
AND
S1
S2 OR
XOR
S3
XNOR
S4
Bitwise rotate B to the right by 1

S5
Bitwise rotate A to the right by 1

S6
A+B
S7
A+B +carry in
S8
A-B
S9
A-B-carry in
S10
Min(A,B)
S11
S12 Max(A,B)
CONCLUSION
In part 1 of the project basic elements of the Quartus ii and how to implement it in DE were done and
in part 2 we were taught how to implement and simulate combinational logic gates and finally part 3
were given the freedom to design an ALU to do certain operations and output its results using the DE
board display and LEDs. Every part the expected results were seen in simulation and implementation
giving us a good understanding and practical knowledge of VHDL and structural design of systems.
https://drive.google.com/drive/folders/16Wcp7yXBa_9Dt4Mwp2cK9w0PWgBOMJ1R?usp=sharing
APPENDIX
Part1_A
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity part1 is
Port ( SW : in STD_LOGIC_VECTOR (9 DOWNTO 0 );
LEDR : out STD_LOGIC_vector (9 downto 0));
end PART1;
architecture Behavioral of Part1 is
begin
LEDR <= SW ;
End behavior ;
(PART 1_b & 2_a & 2_b clock divider)
library IEEE;
use IEEE.NUMERIC_STD.ALL;
entity clock_div is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_vector (24 downto 0));
end clock_div;
architecture Behavioral of clock_div is
signal count : integer;
begin
process(clock,reset)
begin if rising_edge(clock) then
if (reset='1') then
count<=0;
else count<=count+1;
end if;
end if;
end process;
Q <= std_logic_vector(to_unsigned(count,Q'length));
end Behavioral;
(PART 1_b states machine)

library IEEE;
entity SM_1_B is
SW : out STD_LOGIC_VECTOR (9 downto 0));
end SM_1_B;
architecture Behavioral of SM_1_B is
type state_type is (s0, s1, s2, s3 , s4 , s5 , s6 , s7 , s8 , s9 ,s10 , s11 ,s12 ,s13 ,s14, s15, s16, s17 ,
s18 );
signal state : state_type;
begin
process (clock, reset)

begin
if reset = '1' then
state <= s0;
elsif (rising_edge(clock)) then
case state is
when s0=>
state <= s1;
SW <="0000000001";
when s1=>
state <= s2;
SW <="0000000010";
when s2=>
state <= s3;
SW <="0000000100";
when s3 =>
state <= s4;
SW <="0000001000";
when s4 =>
state <= s5;
SW <="0000010000";
when s5 =>
state <= s6;
SW <="0000100000";
when s6 =>
state <= s7;
SW <="0001000000";
when s7=>
state <= s8;
SW <="0010000000";
when s8=>
state <= s9;
SW <="0100000000";
when s9=>
state <= s10;
SW <="1000000000" ;
when s10=>
state <= s11;
SW <="0100000000" ;
when s11=>
state <= s12;
SW <="0010000000" ;
when s12=>
state <= s13;
SW <="0001000000" ;
when s13=>
state <= s14;
SW <="0000100000" ;
when s14=>
state <= s15;
SW <="0000010000" ;
when s15=>
state <= s16;
SW <="0000001000" ;
when s16=>
state <= s17;
SW <="0000000100" ;
when s17=>
state <= s18;
SW <="0000000010" ;
when s18=>
state <= s0;
SW <="0000000001" ;
when others =>
state <= s0 ;
SW <="0000000000" ;
end case;
end if;
end process;
end Behavioral;
(PART b top level)
library IEEE;
entity par1b_toplevel is
Port ( clk : in std_logic;

reset : in std_logic;
LEDR : out std_logic_vector(9 downto 0));
end par1b_toplevel;
architecture Behavioral of par1b_toplevel is
signal new_clk : std_logic_vector(24 downto 0);
COMPONENT SM_1_B
PORT(
clock : IN std_logic;
reset : IN std_logic;
SW : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;
COMPONENT clock_div
PORT(
Q : OUT std_logic_vector(24 downto 0)
);
END COMPONENT;
begin
state_machine : SM_1_B PORT MAP (

clock => new_clk(0),
reset => reset,
SW => LEDR
);
clock_divider : clock_div PORT MAP (

clock => clk,
reset => reset,
Q => new_clk
);
end Behavioral;
PART 2 A
(part 2 A top level)
library IEEE;
entity part_2_A is
Port ( reset : in STD_LOGIC;

clk : in STD_LOGIC;
loading : in STD_LOGIC;
X : out STD_LOGIC_vector(4 downto 0));
end part_2_A;
architecture Behavioral of part_2_A is
signal Q_shadow : std_logic_vector (4 downto 0) ;

signal B , C , E : std_logic;
signal clk_in : std_logic_vector ( 24 downto 0 ) ;
COMPONENT clock_div
PORT(
clock_2 : OUT std_logic_vector(24 downto 0)
);
END COMPONENT;
COMPONENT DFF
PORT(
D : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
begin
clk_f : clock_div PORT MAP (

clock => clk,
reset => reset,
clock_2 => clk_in
);
DFF_1: DFF PORT MAP (

D => B,
clock => clk_in(0),
reset => reset,
Q => Q_shadow(0)
);

D => C,
clock => clk_in(0),
reset => reset,
Q => Q_shadow(1)
);
D => Q_shadow(1),
clock => clk_in(0),
reset => reset,
Q => Q_shadow(2)
);

D => E,
clock => clk_in(0),
reset => reset,
Q => Q_shadow(3)
);

D => Q_shadow(3),
clock => clk_in(0),
reset => reset,
Q => Q_shadow(4)
);
B <= Q_shadow(4) XOR loading;

C <= Q_shadow(4) XOR Q_shadow(0);
E <= Q_shadow(4) XOR Q_shadow(2);
X <= Q_shadow ;
end Behavioral;
(part 2 a dff)
library IEEE;
entity DFF is
Port ( D : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_logic;
Q : out STD_LOGIC);
end DFF;
architecture rtl of DFF is
begin
begin
if (reset ='1') then
Q <='0';
elsif (rising_edge(clock))then
Q <= D ;
end if;
end process;
end rtl;
PART 2B
(part 2 b top level)
library IEEE;
entity toplevel is
port ( reset : in std_logic;
clk : in std_logic;
loading : in std_logic;
x : out std_logic_vector(4 downto 0)
);
end toplevel;
architecture Behavioral of toplevel is

signal Q_shadow : std_logic_vector(4 downto 0);
signal A,C,B,E : std_logic;
COMPONENT dff
generic --generic map for delay value
(
delay : time := 0 ns
);
PORT ( D : in std_logic;
clk : in std_logic;
reset : in std_logic;
Q: out std_logic
);
END COMPONENT;
begin
B <= Q_shadow(1) xor loading; -- 2nd FF output XOR with "loading" to start the sequencer
DFF1: DFF
generic map -- global generic map delay value can be changed for indiviual FFs
(
delay => 90 ns --delay for the 1st FF is set to 90s
)
PORT MAP
(
D => B,
clk => clk,
reset=> reset,
Q => Q_shadow(0)
);
A <= Q_shadow(2) xor Q_shadow(0) xor Q_shadow(1); -- input for the 2nd FF
DFF2: DFF
generic map(
delay => 150 ns --delay for the 2nd FF is set to 150s
)
PORT MAP (
D => A,
clk => clk,
reset=> reset,
Q=> Q_shadow(1)
);
C<= Q_shadow(3) xor Q_shadow(1);
DFF3: dff
generic map( --sets delay value of 90 ns to FF 3

delay => 90 ns )
PORT MAP (
d => C,
clk => clk,
reset=> reset,
q=> Q_shadow(2)
);
E <= Q_shadow(3) xor Q_shadow(2) xor Q_shadow(4);
DFF4: dff
delay => 150 ns )
PORT MAP (
d => E,
clk => clk,
reset=> reset,
q => Q_shadow(3)
);
DFF15: dff
delay => 90 ns )
PORT MAP (
D => Q_shadow(3),
clk => clk,
reset=> reset,
q => Q_shadow(4)
);
x<=Q_shadow;
end Behavioral;
Part 3
(Part 3 top level)
library IEEE;
entity TOPLEVEL_3 is
port ( clk : in std_logic ;

Reset : in std_logic;
HEX_0 : out std_logic_vector(6 downto 0);
LEDG_1: out std_logic_vector(2 downto 0);
LEDG_2: out std_logic_vector(3 downto 0));
end TOPLEVEL_3;
architecture Behavioral of TOPLEVEL_3 is
signal clk_2 : std_logic_vector(26 downto 0);

signal C_in : STD_LOGIC;
signal A : std_logic_vector(3 downto 0);
signal B : std_logic_vector(3 downto 0) ;
signal OP_sel : std_logic_vector(1 downto 0 );
signal Mode_sel : std_logic;
signal C_out : std_logic;
signal F: std_logic_vector(3 downto 0);
COMPONENT clock_div
PORT(
clock_2 : OUT std_logic_vector(26 downto 0)
);
END COMPONENT;
COMPONENT SM_3
PORT(
C_in : OUT std_logic;
A : OUT std_logic_vector(3 downto 0);
B : OUT std_logic_vector(3 downto 0);
OP_sel : OUT std_logic_vector(1 downto 0);
Mode_sel : OUT std_logic
);
END COMPONENT;
COMPONENT ALU_3
PORT(
C_in : IN std_logic;
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
OP_sel : IN std_logic_vector(1 downto 0);
Mode_sel : IN std_logic;
C_out : OUT std_logic;
Z_flag : OUT std_logic;
F : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
COMPONENT SS_3
PORT(
RESULT : IN std_logic_vector(3 downto 0);
C_flag : IN std_logic;
display_0 : OUT std_logic_vector(6 downto 0);
display_3 : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;
begin
clock_divider : clock_div PORT MAP (

clock => clk,
reset => reset,
clock_2 => clk_2
);
state_machine : SM_3 PORT MAP (

clock => clk_2(0),
reset => reset,
C_in => C_in,
A => A,
B => B,
OP_sel => OP_sel,
Mode_sel => Mode_sel
);
seven_segment: SS_3 PORT MAP (

A => A,
B => B,
RESULT => F,
C_flag => C_out,
display_0 => HEX_0,
display_1 => HEX_1,
display_2 => HEX_2,
display_3 => HEX_3
);
Arithematic: ALU_3 PORT MAP (

C_in => C_in,
A => A,
B => B,
OP_sel => OP_sel,
Mode_sel => Mode_sel,
C_out => C_out,
F => F
);
LEDG_1 (2 downto 1) <=OP_sel;

LEDG_1 (0) <= C_in;
LEDG_2 <= F when mode_sel='0' else "0000" ;
end Behavioral;
(clock devider for part 3 )

library IEEE;
entity clock_div is
clock_2 : out STD_LOGIC_VECTOR (27 downto 0));
end clock_div;
architecture Behavioral of clock_div is
signal count : integer;
begin
begin
if rising_edge(clock) then
if (reset='1') then
count<=0;
else
count<=count+1;
end if ;
end if;
end process;
clock_2 <= std_logic_vector(to_unsigned(count,clock_2'length));
end Behavioral;
(part 3 state machine)

library IEEE;
entity SM_3 is
C_in : out STD_LOGIC;
A : out STD_LOGIC_VECTOR (3 downto 0);
B : out STD_LOGIC_VECTOR (3 downto 0);
OP_sel : out STD_LOGIC_VECTOR (1 downto 0);
Mode_sel : out STD_LOGIC);
end SM_3;
architecture Behavioral of SM_3 is
type state_type is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12);
signal state : state_type;
begin
process (clock,reset)
begin
if (reset='1') then
state <= S0;
C_in <='0' ;
A <= "0000";
B <= "0000";
OP_sel <="00" ;
Mode_sel <='0';
else if (rising_edge(clock)) then
case state is
when S0 =>
state <= S1;
C_in <='0' ;
A <= "0000";
B <= "0000";
OP_sel <="00" ;
Mode_sel <='0';
when S1 =>
state <= S2;
C_in <='0' ;
A <= "0011";
B <= "1101";
OP_sel <="00" ;
Mode_sel <='0';
when S2 =>
state <= S3;
C_in <='0' ;
A <= "0011";
B <= "1101";
OP_sel <="01" ;
Mode_sel <='0';
when S3 =>
state <= S4;
C_in <='0' ;
A <= "0011";
B <= "1101";
OP_sel <="10" ;
Mode_sel <='0';
when S4 =>
state <= S5;
C_in <='0' ;
A <= "0011";
B <= "1101";
OP_sel <="11" ;
Mode_sel <='0';
when S5 =>
state <= S6;
C_in <='0' ;
A <= "0101";
B <= "0011";
OP_sel <="00" ;
Mode_sel <='1';
when S6 =>
state <= S7;
C_in <='1' ;
A <= "0101";
B <= "0011";
OP_sel <="00" ;
Mode_sel <='1';
when S7 =>
state <= S8;
C_in <='0' ;
A <= "0101";
B <= "0011";
OP_sel <="01" ;
Mode_sel <='1';
when S8 =>
state <= S9;
C_in <='1' ;
A <= "0110";
B <= "1001";
OP_sel <="01" ;
Mode_sel <='1';
when S9 =>
state <= S10;
C_in <='0' ;
A <= "0111";
B <= "0010";
OP_sel <="10" ;
Mode_sel <='1';
when S10 =>

state <= S11;
C_in <='1' ;
A <= "0111";
B <= "0010";
OP_sel <="10" ;
Mode_sel <='1';
when S11 =>
state <= S12;
C_in <='0' ;
A <= "1101";
B <= "1011";
OP_sel <="11" ;
Mode_sel <='1';
when S12 =>

state <= S1;
C_in <='1' ;
A <= "1101";
B <= "1011";
OP_sel <="11" ;
Mode_sel <='1';
when others =>

state <= s0;
C_in <='0' ;
A <= "0000";
B <= "0000";
OP_sel <="00" ;
Mode_sel <='0';
end case;
end if ;
end if;
end process;
end Behavioral;
(part 3 seven segment BCD to Hex converter)
USE ieee.std_logic_unsigned.all;
entity SS_3 is
Port ( A : in STD_LOGIC_vector(3 downto 0);
B : in STD_LOGIC_vector(3 downto 0);
RESULT : in STD_LOGIC_vector(3 downto 0);
C_flag : in STD_LOGIC;
display_0 : out STD_LOGIC_vector(6 downto 0);
display_3 : out STD_LOGIC_vector(6 downto 0));
end SS_3;
architecture Behavioral of SS_3 is
begin
process(result)
begin
case result is
when "0000" =>

display_0 <= "1000000"; -- will represet 0 in the 7 segment (dispaly 1)
when "0001" =>

display_0 <= "1111001"; --will represet 1 in the 7 segment (dispaly 1)
when "0010" =>

when "0011" =>

when "0100" =>

when "0101" =>

display_0 <= "0010010";
when "0110" =>

display_0 <= "0000010";
when "0111" =>

display_0 <= "1111000";
when "1000" =>

display_0 <= "0000000";
when "1001" =>

display_0 <= "0010000";
when "1010" =>

display_0 <= "0001000";
when "1011" =>
display_0 <= "0000011";
when "1100" =>
display_0 <= "0100111"; --will represet C (12) in the 7 segment (dispaly 1)
when "1101" =>

display_0 <= "0100001";--will represet D (13) in the 7 segment (dispaly 1))
when "1110" =>

display_0 <= "0000110"; --will represet E (14) in the 7 segment (dispaly 1)
when "1111" =>

display_0<= "0001110";--will represet F (15) in the 7 segment (dispaly 1)
when others =>

display_0 <= "XXXXXXX";
end case;
end process;
process(B)
begin
case B is
when "0000" =>

display_2 <= "1000000";
when "0001" =>

display_2 <= "1111001";
when "0010" =>

display_2 <= "0100100";
when "0011" =>

display_2 <= "0110000";
when "0100" =>

display_2 <= "0011001";
when "0101" =>

display_2 <= "0010010";
when "0110" =>

display_2 <= "0000010";
when "0111" =>

display_2 <= "1111000";
when "1000" =>

display_2 <= "0000000";
when "1001" =>

display_2 <= "0010000";
when "1010" =>

display_2 <= "0001000";
when "1011" =>

display_2 <= "0000011";
when "1100" =>
display_2 <= "0100111";
when "1101" =>

display_2 <= "0100001";
when "1110" =>

display_2 <= "0000110";
when "1111" =>

display_2<= "0001110";
when others =>

end case;
end process;
process(A)
begin
case A is
when "0000" =>

display_3 <= "1000000";
when "0001" =>

display_3 <= "1111001";
when "0010" =>

display_3 <= "0100100";
when "0011" =>

display_3 <= "0110000";
when "0100" =>

display_3 <= "0011001";
when "0101" =>

display_3 <= "0010010";
when "0110" =>

display_3 <= "0000010";
when "0111" =>

display_3 <= "1111000";
when "1000" =>

display_3 <= "0000000";
when "1001" =>

display_3 <= "0010000";
when "1010" =>

display_3 <= "0001000";
when "1011" =>

display_3 <= "0000011";
when "1100" =>
display_3 <= "0100111";
when "1101" =>

display_3 <= "0100001";
when "1110" =>

display_3 <= "0000110";
when "1111" =>

display_3<= "0001110";
when others =>

end case;
end process;
process(C_flag)
begin
if (C_flag='0') then
display_1 <= "1000000";

elsif (C_flag ='1') then
display_1 <= "1111001";
else
end if;
end process;
end Behavioral;
(part 3 ALU unit)
library IEEE;
USE ieee.std_logic_unsigned.all;
entity ALU_3 is
Port (
C_in : IN std_logic;
OP_sel : IN std_logic_vector(1 downto 0);
Mode_sel : IN std_logic;
C_out : OUT std_logic;
Z_flag : OUT std_logic;
F : OUT std_logic_vector(3 downto 0)
);
end ALU_3;
architecture Behavioral of ALU_3 is
signal F_shadow : std_logic_vector(4 downto 0);
function MIN ( -- a function is delred to take in 2 inputs copare them and return min value input
A_shadow : in std_logic_vector(3 downto 0);
B_shadow : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable Min_value : std_logic_vector(3 downto 0);
begin
if (A_shadow > B_shadow) then

Min_value := B_shadow;
elsif (A_shadow < B_shadow) then
Min_value := A_shadow;
else
Min_value :="XXXX";
end if ;
return Min_value;
end function MIN;
function MAX (
A_shadow : in std_logic_vector(3 downto 0);
B_shadow : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable Max_value : std_logic_vector(3 downto 0);
begin
if (A_shadow > B_shadow) then

Max_value := A_shadow;
elsif (A_shadow < B_shadow) then
Max_value := B_shadow;
else
Max_value :="XXXX";
end if ;
return Max_value;
end function MAX;
begin
process (Mode_sel,OP_sel,C_in,A,B)
begin
if (Mode_sel ='0') then --logic operations AND, OR , XOR , XNOR
case OP_sel is
when "00" =>

F_shadow(3 downto 0) <= (A AND B) ;
F_shadow(4) <='0'; ----the carry out value is cleared for logical operations therefor 0
when "01" =>
F_shadow(3 downto 0) <= (A OR B) ;
F_shadow(4) <='0';----the carry out value is cleared for logical operations therefor 0
when "10" =>
F_shadow(3 downto 0) <= (A XOR B) ;
when "11" =>
F_shadow(3 downto 0) <= (A XNOR B) ;
when others =>
F_shadow <= (others => 'X');
end case;
elsif (Mode_sel ='1' and C_in = '0') then --arithmetic operations with C_in flag=0
case OP_sel is
when "00" =>
F_shadow <= std_logic_vector(to_unsigned(to_integer(unsigned(B) ror 1),F_shadow'length));

when "01" =>
F_shadow<= ('0'& A ) + ( '0' + B) ; --
when "10" =>
F_shadow <= ('0'& A ) - ( '0' + B) ;
when "11" =>
F_shadow(3 downto 0) <= MIN ( A,B);
when others =>
F_shadow <= (others => 'X');
end case;
elsif (Mode_sel='1' and C_in ='1') then --arithmetic operations with C_in =1
case OP_sel is
when "00" =>

F_shadow <= std_logic_vector(to_unsigned(to_integer(unsigned(A) ror 1),F_shadow'length));
when "01" =>
F_shadow <= ('0'& A ) + ( '0' + B) + ("0000" & C_in) ;
when "10" =>
F_shadow <= ('0'& A ) - ( '0' + B) -("0000" & C_in);
when "11" =>
F_shadow(3 downto 0) <= MAX(A,B);
when others =>
F_shadow<= (others => 'X');
end case;
end if ;
end process;
F <= F_shadow (3 downto 0);

Z_flag <= '1' when F_shadow = "00000" else '0';
C_out <= F_shadow(4);
end Behavioral;

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EEE40002 INTEGRATED CIRCUIT

Mini-Project 1: Hardware Modelling Design of an

Insaf Saifudeen Mohamed – 101222106

VHDL file for the code in Figure 1

SW <= 1010101010 LEDR<= 1010101010

SW<= 1101101101 LEDR<= 1101101101

SW <=0101010101 LEDR<= 0101010101

Using VHDL to design circuit

Vector size Frequency

Using VHDL to design circuit

Figure D-ff modeled in VHDL.

When the clock period is 10ns

VHDL design implementation

 A clock divider to slow down the clock frequency (1 Hz)

Function to determine min and max.

HEX3 = input B HEX2 = input A HEX1 = Carry out HEX0 = Result

STATE FPGA Output

Bitwise rotate B to the right by 1

Bitwise rotate A to the right by 1

Port ( SW : in STD_LOGIC_VECTOR (9 DOWNTO 0 );

LEDR : out STD_LOGIC_vector (9 downto 0));

architecture Behavioral of Part1 is

Port ( clock : in STD_LOGIC;

Q : out STD_LOGIC_vector (24 downto 0));

architecture Behavioral of clock_div is

signal count : integer;

begin if rising_edge(clock) then

(PART 1_b states machine)

architecture Behavioral of SM_1_B is

signal state : state_type;

process (clock, reset)

(PART b top level)

Port ( clk : in std_logic;

architecture Behavioral of par1b_toplevel is

signal new_clk : std_logic_vector(24 downto 0);

state_machine : SM_1_B PORT MAP (

clock_divider : clock_div PORT MAP (

(part 2 A top level)

Port ( reset : in STD_LOGIC;

signal Q_shadow : std_logic_vector (4 downto 0) ;

clk_f : clock_div PORT MAP (

DFF_1: DFF PORT MAP (

DFF_2: DFF PORT MAP (

DFF_4: DFF PORT MAP (

DFF_5: DFF PORT MAP (

B <= Q_shadow(4) XOR loading;

if (reset ='1') then

(part 2 b top level)

architecture Behavioral of toplevel is

generic map( --sets delay value of 90 ns to FF 3

port ( clk : in std_logic ;

architecture Behavioral of TOPLEVEL_3 is

signal clk_2 : std_logic_vector(26 downto 0);

clock_divider : clock_div PORT MAP (

state_machine : SM_3 PORT MAP (

seven_segment: SS_3 PORT MAP (

Arithematic: ALU_3 PORT MAP (

LEDG_1 (2 downto 1) <=OP_sel;

(clock devider for part 3 )

Port ( clock : in STD_LOGIC;

clock_2 : out STD_LOGIC_VECTOR (27 downto 0));

architecture Behavioral of clock_div is

signal count : integer;