Multichannel ISM Band

FSK/GFSK/OOK/GOOK/ASK Transmitter
ADF7012
FEATURES GENERAL DESCRIPTION
Single-chip, low power UHF transmitter The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK
75 MHz to 1 GHz frequency operation UHF transmitter designed for short range devices (SRDs). The
Multichannel operation using Frac-N PLL output power, output channels, deviation frequency, and mod-
2.3 V to 3.6 V operation ulation type are programmable by using four, 32-bit registers.
On-board regulator—stable performance
Programmable output power: The fractional-N PLL and VCO with external inductor enable
−16 dBm to +14 dBm, 0.4 dB steps the user to select any frequency in the 75 MHz to 1 GHz band.
Data rates: dc to 179.2 kbps The fast lock times of the fractional-N PLL make the ADF7012
Low current consumption: suitable in fast frequency hopping systems. The fine frequency
868 MHz, 10 dBm, 21 mA deviations available and PLL phase noise performance facilitates
433 MHz, 10 dBm, 17 mA narrow-band operation.
315 MHz, 0 dBm, 10 mA
Programmable low battery voltage indicator There are five selectable modulation schemes: binary frequency
24-lead TSSOP shift keying (FSK), Gaussian frequency shift keying (GFSK),
binary on-off keying (OOK), Gaussian on-off keying (GOOK),
and amplitude shift keying (ASK). In the compensation register,
APPLICATIONS
the output can be moved in <1 ppm steps so that indirect com-
Low cost wireless data transfer
pensation for frequency error in the crystal reference can be
Security systems
made.
RF remote controls
Wireless metering A simple 3-wire interface controls the registers. In power-down,
Secure keyless entry the part has a typical quiescent current of <0.1 μA.

FUNCTIONAL BLOCK DIAGRAM

CREG
PRINTED
INDUCTOR

OSC1 OSC2 CLKOUT CPVDD CPGND L1 L2 CVCO

VDD
OOK\ASK
÷CLK
VCO
RFOUT
PA

÷R PFD/ RF GND
DVDD CHARGE
PUMP

DGND CREG

LDO
OOK\ASK +FRACTIONAL N REGULATOR

TxCLK

TxDATA FSK\GFSK Σ-∆

PLL LOCK
LE DETECT MUXOUT
FREQUENCY MUXOUT
SERIAL COMPENSATION
DATA BATTERY RSET
INTERFACE
CENTER MONITOR
FREQUENCY
CLK
04617-0-001

CE AGND

Figure 1.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
ADF7012

TABLE OF CONTENTS
Specifications..................................................................................... 3 GOOK Modulation .................................................................... 15

Timing Characteristics..................................................................... 5 Output Divider ........................................................................... 16

Absolute Maximum Ratings............................................................ 6 MUXOUT Modes....................................................................... 16

Transistor Count........................................................................... 6 Theory of Operation ...................................................................... 17

ESD Caution.................................................................................. 6 Choosing the External Inductor Value.................................... 17

Pin Configuration and Function Descriptions............................. 7 Choosing the Crystal/PFD Value............................................. 17

Typical Performance Characteristics ............................................. 8 Tips on Designing the Loop Filter ........................................... 17

315 MHz ........................................................................................ 8 PA Matching................................................................................ 18

433 MHz ........................................................................................ 9 Transmit Protocol and Coding Considerations ..................... 18

868 MHz ...................................................................................... 10 Application Examples .................................................................... 19

915 MHz ...................................................................................... 11 315 MHz Operation ................................................................... 20

Circuit Description......................................................................... 12 433 MHz Operation ................................................................... 21

PLL Operation ............................................................................ 12 868 MHz Operation ................................................................... 22

Crystal Oscillator........................................................................ 12 915 MHz Operation ................................................................... 23

Crystal Compensation Register................................................ 12 Register Descriptions ..................................................................... 24

Clock Out Circuit ....................................................................... 12 R Register..................................................................................... 24

Loop Filter ................................................................................... 13 N-Counter Latch ........................................................................ 25

Voltage-Controlled Oscillator (VCO) ..................................... 13 Modulation Register .................................................................. 26

Voltage Regulators...................................................................... 13 Function Register ....................................................................... 27

FSK Modulation.......................................................................... 13 Outline Dimensions ....................................................................... 28

GFSK Modulation ...................................................................... 14 Ordering Guide .......................................................................... 28

Power Amplifier.......................................................................... 14

REVISION HISTORY
10/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 28
 ADF7012

SPECIFICATIONS
DVDD = 2.3 V – 3.6 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is −40°C to +85°C.
Table 1.
Parameter B Version Unit Conditions/Comments
RF OUTPUT CHARACTERISTICS
Operating Frequency 75/1000 MHz min/max VCO range adjustable using external inductor;
divide-by-2, -4, -8 options may be required
Phase Frequency Detector FRF/128 Hz min
MODULATION PARAMETERS
Data Rate FSK/GFSK 179.2 kbps Using 1 MHz loop bandwidth
Data Rate ASK/OOK 64 Kbps Based on US FCC 15.247 specfications for ACP; higher
data rates are achievable depending on local regulations
Deviation FSK/GFSK PFD/214 Hz min For example, 10 MHz PFD – deviation min = ± 610 Hz
511 × PFD/214 Hz max For example, 10 MHz PFD – deviation max = ± 311.7 kHz
GFSK BT 0.5 typ
ASK Modulation Depth 25 dB max
OOK Feedthrough (PA Off) −40 dBm typ FRF = Fvco
−80 dBm typ FRF = Fvco/2
POWER AMPLIFIER PARAMETERS
Max Power Setting, DVDD = 3.6 V 14 dBm FRF = 915 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 3.0 V 13.5 dBm FRF = 915 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 2.3 V 12.5 dBm FRF = 915 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 3.6 V 14.5 dBm FRF = 433 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 3.0 V 14 dBm FRF = 433 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 2.3 V 13 dBm FRF = 433 MHz, PA is matched into 50 Ω
PA Programmability 0.4 dB typ PA output = −20 dBm to +13 dBm
POWER SUPPLIES
DVDD 2.3/3.6 V min/V max
Current Comsumption
315 MHz, 0 dBm/5 dBm 8/14 mA typ DVDD = 3.0 V, PA is matched into 50 Ω, IVCO = min
433 MHz, 0 dBm/10 dBm 10/18 mA typ
868 MHz, 0 dBm/10 dBm/14 dBm 14/21/32 mA typ
915 MHz, 0 dBm/10 dBm/14 dBm 16/24/35 mA typ
VCO Current Consumption 1/8 mA min/max VCO current consumption is programmable
Crystal Oscillator Current Consumption 190 µA typ
Regulator Current Consumption 280 µA typ
Power-Down Current 0.1/1 µA typ/max
REFERENCE INPUT
Crystal Reference Frequency 3.4/26 MHz min/max
Single-Ended Reference Frequency 3.4/26 MHz min/max
Crystal Power-On Time 3.4 MHz/26 MHz 1.8/2.2 ms typ CE to Clock Enable Valid
Single-Ended Input Level CMOS Levels Refer to the LOGIC INPUTS parameter. Applied to OSC 2 –
oscillator circuit disabled.

Rev. 0 | Page 3 of 28
ADF7012
Parameter B Version Unit Conditions/Comments
PHASE-LOCKED LOOP PARAMETERS
VCO Gain
315MHz 22 MHz/V typ VCO divide-by-2 active
433MHz 24 MHz/V typ VCO divide-by-2 active
868MHz 80 MHz/V typ
915MHz 88 MHz/V typ
VCO Tuning Range 0.3/2.0 V min/max
Spurious (IVCO Min/Max) −65/−70 dBc IVCO is programmable
Charge Pump Current
Setting [00] 0.3 mA typ Refering to DB[7:6] in Function Register
Setting [01] 0.9 mA typ Refering to DB[7:6] in Function Register
Setting [10] 1.5 mA typ Refering to DB[7:6] in Function Register
Setting [11] 2.1 mA typ Refering to DB[7:6] in Function Register
Phase Noise (In band)1
315MHz −85 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA
433MHz −83 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA
868MHz −80 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA
915MHz −80 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA
Phase Noise (Out of Band)1
315MHz −103 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA
433MHz −104 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA
868MHz −115 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA
915MHz −114 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA
Harmonic Content (Second)2 −20 dBc typ FRF = FVCO
Harmonic Content (Third)2 −30 dBc typ
Harmonic Content (Others)2 −27 dBc typ
Harmonic Content (Second)2 −24 dBc typ FRF = FVCO/N (where N = 2, 4, 8)
Harmonic Content (Third)2 −14 dBc typ
Harmonic Content (Others)2 −19 dBc typ
LOGIC INPUTS
Input High Voltage,VINH 0.7 × DVDD V min
Input Low Voltage, VINL 0.2 × DVDD V max
Input Current, IINH/IINL ±1 µA max
Input Capacitance, CIN 4.0 pF max
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V min CMOS output chosen
Output High Current, IOH, 500 µA max
Output Low Voltage, VOL 0.4 V max IOL = 500 µA

1
Measurements made with NFRAC = 2048.
2
Measurements made without harmonic filter.

Rev. 0 | Page 4 of 28
 ADF7012

TIMING CHARACTERISTICS
DVDD = 3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min Data-to-clock setup time
t3 10 ns min Data-to-clock hold time
t4 25 ns min Clock high duration
t5 25 ns min Clock low duration
t6 10 ns min Clock –to-LE setup time
t7 20 ns min LE pulse width

t4 t5

CLOCK

t2 t3

DB1 DB0 (LSB)

DATA DB23 (MSB) DB22 DB2 (CONTROL BIT C2) (CONTROL BIT C1)

t7

LE

t1 t6

04617-0-002
LE

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28
ADF7012

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Table 3.
Parameter
DVDD to GND
(GND = AGND = DGND = 0 V)
Digital I/O Voltage to GND
Analog I/O Voltage to GND
Operating Temperature Range
Maximum Junction Temperature
TSSOP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Rating rating only; functional operation of the device at these or any
−0.3 V to +3.9 V other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
−0.3 V to DVDD + 0.3 V
maximum rating conditions for extended periods may affect
−0.3 V to DVDD + 0.3 V
device reliability.
150°C This device is a high performance RF integrated circuit with an
150.4°C/W ESD rating of 1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
215°C
220°C
TRANSISTOR COUNT
35819 (CMOS)

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28
 ADF7012

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DVDD 1 24 CREG2
CREG1 2 23 RSET
CPOUT 3 22 AGND
TSSOP
TxDATA 4 21 DVDD
TxCLK 5 ADF7012 20 RFOUT
MUXOUT 6 TOP VIEW 19 RFGND

DGND 7 (Not to Scale) 18 VCOIN

OSC1 8 17 CVCO
OSC2 9 16 L2
CLKOUT 10 15 L1

04617-0-003
CLK 11 14 CE
DATA 12 13 LE

Figure 3.
Table 4. Pin Functional Descriptions
Pin No. Mnemonic Description
1 DVDD Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin.
2 CREG1 A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor
improves regulator power-on time, but may cause higher spurious noise.
3 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated
current changes the control voltage on the input to the VCO.
4 TxDATA Digital Data to Be Transmitted is inputted on this pin.
5 TxCLK GFSK and GOOK only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the
ADF7012. The clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on
the falling edge of TxCLK. The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit.
6 MUXOUT Provides the Lock_Detect Signal. This determines if the PLL is locked to the correct frequency and also monitors
battery voltage. Other signals include Regulator_Ready, which indicates the status of the serial interface regulator.
7 DGND Ground for Digital Section.
8 OSC1 The reference crystal should be connected between this pin and OSC2.
9 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving
this pin with CMOS levels, and powering down the crystal oscillator bit in software.
10 CLKOUT A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive
several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high
impedance CMOS input.
13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.
14 CE Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1uA. Register values are
lost when CE is low and the part must be reprogrammed once CE is brought high.
15 L1 Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the
value of the inductor to be connected between L1 and L2.
16 L2 Connected to external printed or discrete inductor.
17 CVCO A 220 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012.
This capacitor is necessary to ensure stable VCO operation.
18 VCOIN The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The
higher the tuning voltage, the higher the output frequency.
19 RFGND Ground for Output Stage of Transmitter.
20 RFOUT The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output
should be impedance matched using suitable components to the desired load. See the PA Matching section.
21 DVDD Voltage supply for VCO and PA section. This should have the same supply as DVDD Pin 1, and should be between
2.3 V and 3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin.
22 AGND Ground Pin for the RF Analog Circuitry.
23 RSET External Resistor to set charge pump current and some internal bias currents. Use 3.6 kV as default.
24 CREG2 Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves
regulator power-on time and phase noise, but may have stability issues over the supply and temperature.

Rev. 0 | Page 7 of 28
ADF7012

TYPICAL PERFORMANCE CHARACTERISTICS

315 MHZ
–60 RBW 1MHz RF ATT 30dB
= NORMAL REF LVL 0.27dBm VBW 1MHz
FREQUENCY = 9.08 kHz 5dBm 308.61723447MHz SWT 17.5ms UNIT dBm
–70 5
LEVEL = –84.47dBc/Hz 1 A
0
3
–80 –10

–20
–90
dBc (Hz)

–30 4 1MA
2
–100
–40
D1 –41.5dBm
–110 –50

–120 –60

–70

04617-0-004
–130 1 [T1] 0.27dBm 3 [T1] –11.48dBm
–80 308.61723447MHz 939.87975952MHz

04617-0-007
2 [T1] –35.43dBm 4 [T1] –34.11dBm
–140 631.26252505MHz 1.26252505GHz
1.0k 10.0k 100.0k 1.0M 10.0M –90
–95
PHASE NOISE (Hz)
CENTER 3.5MHz 700MHz/ SPAN 7GHz

Figure 4. Phase Noise Response—DVDD = 3.0 V, ICP = 0.86 mA Figure 7. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
IVCO = 2.0 mA, FOUT = 315 MHz, PFD = 3.6864 MHZ, PA Bias = 5.5 mA

RBW 5kHz RF ATT 30dB RBW 1MHz RF ATT 30dB

REF LVL 0.45dBm VBW 5kHz REF LVL 0.18dBm VBW 1MHz
5dBm 315.05060120MHz SWT 500ms UNIT dBm 5dBm 308.61723447MHz SWT 17.5ms UNIT dBm
5 5
1 2 A 1 A
0 0

–10 –10 SGL

–20 –20
–30 1MA –30 1MA

–40 –40 3
D1 –41.5dBm
2
–50 –50 4
–60 –60

–70 –70
1 [T1] 0.18dBm 3 [T1] –42.93dBm
–80 308.61723447MHz 939.87975952MHz
04617-0-005

–80

04617-0-008
2 [T1] –50.53dBm 4 [T1] –55.48dBm
–90 –90 631.26252505MHz 1.26252505GHz
–95 –95
CENTER 315MHz 50kHz/ SPAN 500kHz CENTER 3.5MHz 700MHz/ SPAN 7GHz

Figure 5. FSK Modulation, Power = 0 dBm, Data Rate = 1 kbps, Figure 8. Harmonic Response, Fifth-Order Butterworth Filter
FDEVIATION = ±50 kHz
RBW 500kHz RF ATT 30dB RBW 5kHz RF ATT 30dB
REF LVL 0.31dBm VBW 500kHz REF LVL 20.33dBm VBW 5kHz
5dBm 315.40080160MHz SWT 5ms UNIT dBm 5dBm 26.55310621kHz SWT 500ms UNIT dBm
5 5
1 A
0 1 A
0

–10 –10

–20 –20
2 3
–30 1MA –30 1MA

–40 –40
D1 –41.5dBm
–50 D2 –49dBm –50

–60 –60

–70 –70 1 [T1] –3.49dBm

315.00012525MHz
–80 3 [T1] –20.33dB
04617-0-006

–80
04617-0-009

26.55310621kHz
1 [T1] 0.31dBm 2 [T1] –20.85dB
–90 315.40080160MHz –90 –27.55511022kHz
–95 –95
CENTER 315MHz 40MHz/ SPAN 400MHz CENTER 315MHz 50kHz/ SPAN 500kHz

Figure 6. Spurious Components—Meets FCC Specs Figure 9. OOK Modulation, Power = 0 dBm, Data Rate = 10 kbps

Rev. 0 | Page 8 of 28
 ADF7012
433 MHZ
1 2.00V/ 2 1.00V/ 1.50ms 500µs TRIG'D 1 720mv RBW 30kHz RF ATT 40dB
REF LVL 10.01dBm VBW 30kHz
15dBm 433.91158317MHz SWT 90ms UNIT dBm
15
1 A
10

–10

–20 1MA
2 CLKOUT
–30
D1 –36dBm
–40

–50

–60
1 CE

04617-0-010
–70

04617-0-013
–80
–85
CENTER 433.9500601MHz 3.2MHz/ SPAN 32MHz

Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms Figure 13. Spurious Components—Meets ETSI Specs
–40 RBW 1MHz RF ATT 40dB
= NORMAL REF LVL 10.10dBm VBW 1MHz
FREQUENCY = 393.38 kHz 15dBm 434.86973948MHz SWT 17.5ms UNIT dBm
–60 LEVEL = –102.34dBc/Hz 15
1 A
10
–80 0 3

–10 2
–100 4
dBc (Hz)

–20 1MA
–120
–30 D1 –30dBm
D1 –36dBm
–140 –40

–160 –50

–60
04617-0-011

–180 1 [T1] 10.10dBm 3 [T1] –5.12dBm

–70 434.86973948MHz 1.30460922GHz

04617-0-014
2 [T1] –15.25dBm 4 [T1] –17.57dBm
–200 869.73947896MHz 1.73947896GHz
1.0k 10.0k 100.0k 1.0M 10.0M –80
–85
PHASE NOISE (Hz)
CENTER 3.5GHz 700MHz/ SPAN 7GHz

Figure 11. Phase Noise Response—ICP = 2.0 mA, IVCO = 2.0 mA, Figure 14. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
RFOUT = 433.92 MHz, PFD = 4 MHz, PA Bias = 5.5 mA
RBW 10kHz RF ATT 40dB RBW 1MHz RF ATT 40dB
REF LVL 5.60dBm VBW 300kHz REF LVL 9.51dBm VBW 1MHz
15dBm 433.91158317MHz SWT 44ms UNIT dBm 15dBm 434.86973948MHz SWT 17.5ms UNIT dBm
15 15
A 1 A
10 1 10

0 0 SGL

–10 –10

–20 1MA –20 1MA

–30 –30 2 D1 –30dBm

D1 –36dBm D1 –36dBm
–40 –40 3 4

–50 –50

–60 –60
1 [T1] 9.51dBm 3 [T1] –43.60dBm
–70 –70 434.86973948MHz 1.30460922GHz
04617-0-012

04617-0-015

2 [T1] –33.75dBm 4 [T1] –43.44dBm

–80 –80 869.73947896MHz 1.73947896GHz
–85 –85
START 433.05MHz 174kHz/ STOP 434.79kHz CENTER 3.5GHz 700MHz/ SPAN 7GHz

Figure 12. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps, FDEVIATION Figure 15. Harmonic Response, Fifth-Order Butterworth Filter
= ±19.28 kHz

Rev. 0 | Page 9 of 28
ADF7012
868 MHZ
0 RBW 1MHz RF ATT 40dB
= NORMAL REF LVL 12.27dBm VBW 1MHz
FREQUENCY = 251.3 kHz 15dBm 869.33867735MHz SWT 16ms UNIT dBm
–20 15
LEVEL = –99.39dBc/Hz 1 A
10
–40 0 2

–10 4
–60 3
1MAX 1MA
dBc (Hz)

–20
–80
–30 D1 –30dBm

–100 –40

–50
–120
–60

04617-0-016
–140 1 [T1] 12.27dBm 3 [T1] –16.88dBm
–70 869.33867735MHz 2.59699399GHz

04617-0-019
2 [T1] –4.00dBm 4 [T1] –15.06dBm
–160 1.72865731GHz 3.46913828GHz
1.0k 10.0k 100.0k 1.0M 10.0M –80
–85
PHASE NOISE (Hz)
CENTER 3.8GHz 640MHz/ SPAN 6.4GHz

Figure 16. Phase Noise Response–ICP = 2.5 mA, IVCO = 1.44 mA, RFOUT = 868.95 Figure 19. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
MHz, PFD = 4.9152 MHz, Power = 12.5 dBm, PA Bias = Max
RBW 10kHz RF ATT 30dB RBW 1kHz RF ATT 30dB
REF LVL –40.44dBm VBW 10kHz MIXER –20dBm REF LVL 10.39dBm VBW 1kHz MIXER –20dBm
15dBm 869.20000000MHz SWT 15ms UNIT dBm 15dBm 869.33867735MHz SWT 10ms UNIT dBm
15 15
2 A 1 A
10 10 1 [T1] 10.39dBm
LN 869.33867735MHz LN
0 0 3 [T1] –50.92dBm
1.72000000GHz
–10 2 [T1] –50.40dBm
–10
2.59600000GHz
–20 1MAX 1MA –20 1MAX 1MA

–30 –30 D2 –30dBm

D2 –36dBm 1
–40 –40
2 3
–50 –50

–60 –60
1 [T1] 40.44dBm
–70 869.20000000MHz –70
04617-0-017

04617-0-020
2 [T1] 8.02dBm
–80 868.96673347MHz –80
–85 –85
CENTER 868.944489MHz 60kHz/ SPAN 600kHz START 3.8GHz 640MHz/ SPAN 6.4GHz

Figure 17. FSK Modulation, Power = 12.5 dBm, Data Rate = 38.4 kbps, Figure 20. Harmonic Response, Fifth-Order Chebyshev Filter
FDEVIATION = ±19.2 kHz
RBW 2kHz RF ATT 30dB
REF LVL 12.55dBm VBW 2kHz MIXER –20dBm
15dBm 869.025050100MHz SWT 16s UNIT dBm
15
1 A
10 1 [T1] 12.55dBm
869.02505010MHz LN
0 2 [T1] –57.89dBm
859.16695500MHz
3 [T1] –81.97dBm
–10
862.00000000MHz
–20 1MAX 1MA

–30
D2 –36dBm
–40

–50
2 D1 –54dBm
–60

–70
04617-0-018

3
–80
–85
START 856.5MHz 2.5MHz/ STOP 881.5MHz

Figure 18. Spurious Components—Meets ETSI Specs

Rev. 0 | Page 10 of 28
 ADF7012
915 MHZ
–40 RBW 50MHz RF ATT 40dB
= NORMAL REF LVL 10.25dBm VBW 50MHz
FREQUENCY = 992.38 kHz 15dBm 907.81563126MHz SWT 6.4s UNIT dBm
–60 LEVEL = –102.34dBc/Hz 15
1 A
10
–80
0
2
–100 –10
4
dBc (Hz)

1MAX 3 1MA
–20
–120
–30
–140
–40 D1 –41.5dBm

–160 –50

04617-0-021
–180 –60
1 [T1] 10.25dBm 3 [T1] –20.29dBm
–70 907.81563126MHz 2.74188377GHz

04617-0-038
–200
1.0k 10.0k 100.0k 1.0M 10.0M 2 [T1] –10.06dBm 4 [T1] –17.50dBm
–80 1.83126253GHz 3.65250501GHz
PHASE NOISE (Hz)
–85
CENTER 3.8GHz 640MHz/ SPAN 6.4GHz

Figure 21. Phase Noise Response–ICP = 1.44 mA, IVCO = 3.0 mA, RFOUT = 915.2 Figure 24. Harmonic Response, RFOUT Matched to 50 Ω, No Filter
MHz, PFD =10 MHz, Power = 10 dBm, PA Bias = 5.5 mA
RBW 10kHz RF ATT 40dB RBW 50MHz RF ATT 40dB
REF LVL 3.88dBm VBW 300kHz REF LVL 9.06dBm VBW 50MHz
15dBm 915.19098196MHz SWT 15ms UNIT dBm 15dBm 907.81563126MHz SWT 6.4s UNIT dBm
15 15
A 1 A
10 1 10

0 0

–10 –10

–20 1MAX 1MA –20 1MAX 1MA

–30 –30

–40 –40 D1 –41.5dBm

2 3 4
–50 –50

–60 –60
1 [T1] 9.06dBm 3 [T1] –46.22dBm
–70 –70 907.81563126MHz 2.74188377GHz
04617-0-036

04617-0-039
2 [T1] –48.40dBm 4 [T1] –46.96dBm
–80 –80 1.83126253GHz 3.65250501GHz
–85 –85
CENTER 915.190982MHz 50kHz/ SPAN 500kHz CENTER 3.8GHz 640MHz/ SPAN 6.4GHz

Figure 22. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps, Figure 25. Harmonic Response, Fifth-Order Chebyshev Filter
Fdeviation = ±19.2 kHz
RBW 10kHz RF ATT 40dB
REF LVL 9.94dBm VBW 300kHz
15dBm 915.23167977MHz SWT 100ms UNIT dBm
15 *
1
10 A

0 SGL

–10

–20 1MA

–30

–40
D1 –41.5dBm
D1 –49.5dBm
–50

–60

–70
04617-0-037

–80
–85
CENTER 915.2MHz 40MHz/ SPAN 400MHz

Figure 23. Spurious Components—Meets FCC Specs

Rev. 0 | Page 11 of 28
ADF7012

CIRCUIT DESCRIPTION
PLL OPERATION
A fractional-N PLL allows multiple output frequencies to be
generated from a single-reference oscillator (usually a crystal)
simply by changing the programmable N value found in the N
register. At the phase frequency detector (PFD), the reference is OSC1 OSC2

compared to a divided-down version of the output frequency
(VCO/N). If VCO/N is too low a frequency, typically the output
frequency is lower than desired, and the PFD and charge-pump
combination sends additional current pulses to the loop filter.
This increases the voltage applied to the input of the VCO.
Because the VCO of the ADF7012 has a positive frequency vs.
voltage characteristic, any increase in the Vtune voltage applied
to the VCO input increases the output frequency at a rate of kV,
the tuning sensitivity of the VCO (MHz/V). At each interval of
1/PFD seconds, a comparison is made at the PFD until the PFD
and charge pump eventually force a state of equilibrium in the
PLL where PFD frequency = VCO/N. At this point, the PLL can
be described as locked.
CRYSTAL/R
LOOP FILTER
R
PFD CP
FVCO
VCO
VCO/N
04617-0-022
04617-0-023
CP2 CP1
Figure 27.
Two parallel resonant capacitors are required for oscillation at
the correct frequency—the value of these depend on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds to give the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary between 2 pF to 5 pF, depending on board layout.
Where possible, to ensure stable frequency operation over all
conditions, capacitors should be chosen so that they have a very
low temperature coefficient and/or opposite temperature
coefficients
CRYSTAL COMPENSATION REGISTER
The ADF7012 features a 15-bit fixed modulus, which allows the
output frequency to be adjusted in steps of FPFD/15. This fine
resolution can be used to easily compensate for initial error and

N temperature drift in the reference crystal.

Figure 26. FADJUST = FSTEP × FEC (3)

where FSTEP = FPFD/215 and FEC = Bits F1 to F11 in the R

Register. Note that the notation is twos compliment, so F11
FCRYSTAL × N
FOUT = = FPFD × N (1) represents the sign of the FEC number.
R
Example
For a Fractional N PLL
FPFD = 10 MHz
FADJUST = −11 kHz
⎛ N ⎞
FOUT = FPFD × ⎜ N INT + FRAC
12 ⎟
(2) FSTEP = 10 MHz/215 = 305.176 Hz
⎝ 2 ⎠
FEC = −11 kHz/305.17 Hz = −36 = −(00000100100) =
where NFRAC can be bits M1 to M12 in the fractional N register. 11111011100 = 0x7DC

CRYSTAL OSCILLATOR CLOCK OUT CIRCUIT

The on-board crystal oscillator circuitry (Figure 27) allows an
inexpensive quartz crystal to be used as the PLL reference. The
oscillator circuit is enabled by setting XOEB low. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the error correction
register within the R register.
The clock out circuit takes the reference clock signal from the
oscillator section above and supplies a divided-down 50:50
mark-space signal to the CLKOUT pin. An even divide from
2 to 30 is available. This divide is set by the DB[19:22] in the R
register. On power-up, the CLKOUT defaults to divide by 16.
DVDD

CLKOUT
A single-ended reference may be used instead of a crystal, by ENABLE BIT
applying a square wave to the OSC2 pin, with XOEB set high.
DIVIDER ÷2
OSC1 CLKOUT
04617-0-024

1 TO 15

Figure 28.

Rev. 0 | Page 12 of 28

The output buffer to CLKOUT is enabled by setting Bit DB4 in
the function register high. On power-up, this bit is set high.
The output buffer can drive up to a 20 pF load with a 10% rise
time at 4.8 MHz. Faster edges can result in some spurious
feedthrough to the output. A small series resistor (50 Ω) can be
used to slow the clock edges to reduce these spurs at FCLK.
LOOP FILTER
The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 29.
CHARGE
VCO
PUMP OUT
04617-0-025
Figure 29.
In FSK, the loop should be designed so that the loop bandwidth
(LBW) is a minimum of two to three times the data rate.
Widening the LBW excessively reduces the time spent jumping
between frequencies, but results in reduced spurious
attenuation. See the section Tips on Designing the Loop Filter.
For OOK/ASK systems, a wider loop bandwidth than for FSK
systems is desirable. The sudden large transition between two
power levels results in VCO pulling (VCO temporarily goes to
incorrect frequency) and can cause a wider output spectrum.
By widening the loop bandwidth a minimum of 10 × data rate,
VCO pulling is minimized because the loop settles quickly back
to the correct frequency. The free design tool ADIsimPLL™ can
be used to design loop filters for the ADI family of transmitters.
VOLTAGE-CONTROLLED OSCILLATOR (VCO)
The ADF7012 features an on-chip VCO with an external tank
inductor, which is used to set the frequency range. The center
frequency of oscillation is governed by the internal varactor
capacitance and that of the external inductor combined with the
bond-wire inductance. An approximation for this is given in the
Equation 4. For a more accurate selection of the inductor, see
the section Choosing the External Inductor Value.
1
FVCO =
2π ( LINT + LEXT ) × (CVAR + CFIXED )
The varactor capacitance can be adjusted in software to increase
the effective VCO range by writing to bits VA1 and VA2 in the
R register. Under typical conditions, setting VA1 and VA2 high
increases the center frequency by reducing the varactor
capacitance by approximately 1.3 pF.
ADF7012
Figure 32 shows the VCO gain over temperature and frequency.
VCO gain is important in determining the loop filter design—
predictable changes in VCO gain resulting in a change in the
loop filter bandwidth can be offset by changing the charge-
pump current in software.
VCO Bias Current
VCO bias current may be adjusted using bits VB1 to VB4 in the
function register. Additional bias current will reduce spurious
levels, but increase overall current consumption in the part. A
bias value of 0x5 should ensure oscillation at most frequencies
and supplies. Settings 0x0, 0xE ,and 0xF are not recommended.
Setting 0x3 and Setting 0x4 are recommended under most
conditions. Improved phase noise can be achieved for lower
bias currents.
VOLTAGE REGULATORS
There are two band gap voltage regulators on the ADF7012
providing a stable 2.25 V internal supply: a 2.2 µF capacitor
(X5R, NP0) to ground at CREG1 and a 470 nF capacitor at CREG2
should be used to ensure stability. The internal reference
ensures consistent performance over all supplies and reduces
the current consumption of each of the blocks.
The combination of regulators, band gap reference, and biasing
typically consume 1.045 mA at 3.0 V and can be powered down
by bringing the CE line low. The serial interface is supplied by
Regulator 1, so powering down the CE line causes the contents
of the registers to be lost. The CE line must be high and the
regulators must be fully powered on to write to the serial
interface. Regulator power-on time is typically 100 µs and
should be taken into account when writing to the ADF7012
after power-up. Alternatively, regulator status may be monitored
at the MUXOUT pin once CE has been asserted, because
MUXOUT defaults to the regulator ready signal. Once
Regulator_ready is high, the regulator is powered up and the
serial interface is active.
FSK MODULATION
FSK modulation is performed internally in the PLL loop by
switching the value of the N register based on the status of the
TxDATA line. The TxDATA line is sampled at each cycle of the
PFD block (every 1/FPFD seconds). When TxDATA makes a low-
to-high transition, an N value representing the deviation
(4) frequency is added to the N value representing the center
frequency. Immediately the loop begins to lock to the new
frequency of FCENTER + FDEVIATION. Conversely, when TxDATA
makes a high-to-low transition, the N value representing the
deviation is subtracted from the PLL N value representing the
center frequency and the loop transitions to FCENTER − FDEVIATION.
Rev. 0 | Page 13 of 28
ADF7012
For GFSK and GOOK, the incoming bit stream to be trans-
mitted needs to be synchronized with an on-chip sampling
clock which provides one sample per bit to the Gaussian FIR
PFD/ PA STAGE
filter. To facilitate this, the sampling clock is routed to the
4R
CHARGE
PUMP
VCO TxCLK pin where data is fetched from the host microcontroller
or microprocessor on the falling edge of TxCLK, and the data is
FSK DEVIATION
FREQUENCY sampled at the midpoint of each bit on TxCLK’s rising edge.
÷N
Inserting external RC LPFs on TxDATA and TxCLK lines
–FDEV creates smoother edge transitions and improves spurious
THIRD-ORDER
+FDEV Σ-∆ MODULATOR performance. As an example, suitable components would be a

04617-0-026
TxDATA
1 kV resistor and 10 nF capacitor for a data rate of 5 kbps.
FRACTIONAL-N INTEGER-N

Figure 30. I/O TxDATA

µC ADF7012

04617-0-040
The deviation from the center frequency is set using bits D1 to INT TxCLK
D9 in the modulation register. The frequency deviation may be FETCH FETCH FETCH FETCH
set in steps of SAMPLE SAMPLE SAMPLE

FPFD
FSTEP ( Hz) = (5) Figure 31. TxCLK/TxDATA Synchronization.
214
The number of steps between symbol ‘0’ and symbol ‘1’ is
The deviation frequency is therefore determined by the setting for the index counter.
FPFD × ModulationNumber
FDEVIATION ( Hz) = (6) The GFSK deviation is set up as
214
FPFD × 2 m
where ModulationNumber is set by bits D1 to D9. GFSK DEVIATION ( Hz) = (7)
212
The maximum data rate is a function of the PLL lock time (and where m is the mod control (Bits MC1 to MC3 in the
the requirement on FSK spectrum). Because the PLL lock time modulation register).
is reduced by increasing the loop-filter bandwidth, highest data
rates can be achieved for the wider loop filter bandwidths. The The GFSK sampling clock samples data at the data rate:
absolute maximum limit on loop filter bandwidth to ensure
FPFD
stability for a fractional-N PLL is FPFD/7. For a 20 MHz PFD DataRate (bps) = (8)
frequency, the loop bandwidth could be as high as 2.85 MHz. DividerFactor × IndexCounter
FSK modulation is selected by setting bits S1 and S2 in the where DividerFactor can be bits D1 to D7, and IndexCounter
modulation register low. can be bits IC1 and IC2 in the modulation register.

GFSK MODULATION POWER AMPLIFIER

Gaussian Frequency Shift Keying, or GFSK, represents a filtered
form of frequency shift keying. The data to be modulated to RF
is prefiltered digitally using an finite impulse response filter
(FIR). The filtered data is then used to modulate the sigma-
delta fractional-N to generate spectrally-efficient FSK.
FSK consists of a series of sharp transitions in frequency as the
data is switched from one level to an other. The sharp switching
generates higher frequency components at the output, resulting
in a wider output spectrum.
With GFSK, the sharp transitions are replaced with up to 128
smaller steps. The result is a gradual change in frequency. As a
result, the higher frequency components are reduced and the
spectrum occupied is reduced significantly. GFSK does require
some additional design work as the data is only sampled once
per bit, and so the choice of crystal is important to ensure the
correct sampling clock is generated.
The output stage is based on a Class E amplifier design, with an
open drain output switched by the VCO signal. The output
control consists of six current mirrors operating as a
programmable current source.
To achieve maximum voltage swing, the RFOUT pin needs to be
biased at DVDD. A single pull-up inductor to DVDD ensures a
current supply to the output stage, PA biased to DVDD volts, and
with the correct choice of value transforms the impedance.
The output power can be adjusted by changing the value of
bits P1 to P6. Typically, this is P1 to P6 output −20dBm at 0x0,
and 13 dBm at 0x7E at 868MHz, with the optimum matching
network.

Rev. 0 | Page 14 of 28
 ADF7012
The nonlinear characteristic of the output stage results in an As is the case with GFSK, GOOK requires the bit stream
output spectrum containing harmonics of the fundamental, applied at TxDATA to be synchronized with the sampling clock,
especially the third and fifth. To meet local regulations, a low- TxCLK (see the GFSK Modulation section).
pass filter usually is required to filter these harmonics.
10

The output stage can be powered down by setting Bit PD2 in 0

the function register low.
–10
OOK
GOOK MODULATION –20

POWER (dBm)
Gaussian on-off keying (GOOK) represents a prefiltered form –30
of OOK modulation. The usually sharp symbol transitions are
–40
replaced with smooth Gaussian-filtered transitions with the
result being a reduction in frequency pulling of the VCO. –50

Frequency pulling of the VCO in OOK mode can lead to a –60

wider than desired bandwidth, especially if it is not possible to GOOK

04617-0-043
–70
increase the loop filter bandwidth to > 300kHz.
–80
909.43 910.43 910.93
The GOOK sampling clock samples data at the data rate: FREQUENCY (MHz)

FPFD Figure 33. GOOK vs. OOK Frequency Spectra

DataRate (bps) = (9) (Narrow-Band Measurement)
DividerFactor × IndexCounter

20
Bits D1 to D6 represent the output power for the system for a
10
positive data bit. Divider Factor = 0x3F represents the max-
0
imum possible deviation from PA at minimum to PA at
–10
maximum output. An index counter setting of 128 is
–20
recommended.
POWER (dBm)

–30 OOK
Figure 32 shows the step response of the Gaussian FIR filter. –40
An index counter of 16 is demonstrated for simplicity. While –50
the pre-filter data would switch the PA directly from off to on –60
with a low-to-high data transition, the filtered data gradually
–70
increases the PA output in discrete steps. This has the effect of

04617-0-044
–80 GOOK
making the output spectrum more compact.
–90
885.43 910.43 935.93
PRE-FILTER DATA FREQUENCY (MHz)
(0 TO 1 TRANSITION)
PA SETTING Figure 34. GOOK vs. OOK Frequency Spectra
16 (MAX)
(Wideband Measurement)
15
14
13
12
11
10
9
8
7
6
5 DISCRETIZED
4 FILTER OUTPUT
04617-0-041

3
2
1 (PA OFF)

Figure 32. Varying PA Output for GOOK (Index Counter = 16).

Rev. 0 | Page 15 of 28
ADF7012
OUTPUT DIVIDER Battery Voltage Read back
An output divider is a programmable divider following the By setting MUXOUT to 1010 to 1101, the battery voltage can be
VCO in the PLL loop. It is useful when using the ADF7012 to estimated. The battery measuring circuit features a voltage
generate frequencies of < 500 MHz. divider and a comparator where the divided-down supply
voltage is compared to the regulator voltage.
REFERENCE LOOP OUTPUT
PFD CP VCO PA
DIVIDER FILTER DIVIDER Table 6.
÷1/2/4/8

04617-0-042
MUXOUT MUXOUT High MUXOUT Low
÷N 1010 DVDD > 3.25 V DVDD < 3.25 V
1011 DVDD > 3.0 V DVDD < 3.0 V
Figure 35. Output Divider Location in PLL.
1100 DVDD > 2.75 V DVDD < 2.75 V
The output divider may be used to reduce feedthrough of the 1101 DVDD > 2.35 V DVDD < 2.35 V
VCO by amplifying only the VCO/2 component, restricting the The accuracy of the measurement is limited by the accuracy of
VCO feedthrough to leakage. the regulator voltage and also the internal resistor tolerances.
Because the divider is in loop, the N register values should be Regulator Ready
set up according to the usual formula. However, the VCO gain The regulator has a power-up time, dependant on process and
(KV) should be scaled according to the divider setting, as shown the external capacitor. The regulator ready signal indicates that
in the following example. the regulator is fully powered, and that the serial interface is
active. This is the default setting on power-up at MUXOUT.
Fout = 433 MHz, Fvco = 866 MHz, KV @ 868 MHz =
60 MHz/V Digital Lock Detect
Digital lock detect indicates that the status of the PLL loop.
Therefore, KV for loop filter design = 30 MHz/V.
The PLL loop takes time to settle on power-up and when the
The divider value is set in the R register. frequency of the loop is changed by changing the N value.
When lock detect is high, the PFD has counted a number of
Table 5.
consecutive cycles where the phase error is < 15 ns. The lock
OD1 OD2 Divider Status detect precision bit in the function register determines whether
0 0 Divider off this is 3 cycles (LDP = 0), or 5 cycles (LDP=1). It is recom-
0 1 Divide by 2 mended that LDP be set to 1. The lock detect is not completely
1 0 Divide by 4 accurate and goes high before the output has settled to exactly
1 1 Divide by 8 the correct frequency. In general, add 50% to the indicated
lock time to obtain lock time to within 1 kHz. The lock detect
MUXOUT MODES signal can be used to decide when the power amplifier (PA)
The MUXOUT pin allows the user access to various internal should be enabled.
signals in the transmitter, and provides information on the R Divider
PLL lock status, the regulator, and the battery voltage. The MUXOUT provides the output of the R divider. This is a
MUXOUT is accessed by programming Bits M1 to M4 in the narrow pulsed digital signal at frequency FPFD. This signal may
function register and observing the signal at the MUXOUT pin. be used to check the operation of the crystal circuit and the R
divider. R divider/2 is a buffered version of this signal at FPFD/2.

Rev. 0 | Page 16 of 28

THEORY OF OPERATION
CHOOSING THE EXTERNAL INDUCTOR VALUE
The ADF7012 allows operation at many different frequencies by
choosing the external VCO inductor to give the correct output
frequency. Figure 36 shows both the minimum and maximum
frequency vs. the inductor value. These are measurements based
on 0603 CS type inductors from Coilcraft, and are intended as
guidelines in choosing the inductor because board layout and
inductor type varies between applications.
The inductor value should be chosen so it is between the
minimum and maximum value.
1200
1100
1000
FREQUENCY (MHz)
900
800
700
600
500
400
300
0 5 10 15 20 25
INDUCTANCE (nH)
Figure 36. Output Frequency vs. External Inductor Value
Ibias = 2.0 mA.
For frequencies between 270 MHz and 550 MHz, it is
recommended to operate the VCO at twice the desired output
frequency and use the divide-by-2 option. This ensures reliable
operation over temperature and supply.
For frequencies between 130 MHz and 270 MHz, it is
recommended to operate the VCO at four times the desired
output frequency and use the divide-by-4 option.
For frequencies below 130 MHz, it is best to use the divide-by-8
option. It is not necessary to use the VCO divider for
frequencies above 550 MHz.
ADIsimPLL is a PLL design tool which can perform the
frequency calculations for the ADF7012, and is available at
www.analog.com/pll.
CHOOSING THE CRYSTAL/PFD VALUE
The choice of crystal value is an important one. The PFD
frequency must be the same as the crystal value or an integer
division of it. The PFD determines the phase noise, spurious
levels and location, deviation frequency, and the data rate in the
case of GFSK. The following sections describe some factors that
should be considered when choosing the crystal value.
ADF7012
Standard Crystal Values
Standard crystal values are 3.6864 MHz, 4 MHz, 4.096 MHz,
4.9152 MHz, 7.3728 MHz, 9.8304 MHz, 10 MHz, 11.0592 MHz,
12 MHz, and 14.4792 MHz. Crystals with these values are
usually available in stock and cost less than crystals with
nonstandard values.
Reference Spurious Levels
Reference spurious levels (spurs) occur at multiples of the PFD
frequency. The reference spur closest to the carrier is usually
highest with the spur further out being attenuated by the loop
filter. The level of reference spur is lower for lower PFD
MIN (meas)
frequencies. In designs with high output power where spurious
MAX (meas) levels are the main concern, a lower PFD frequency (<5 MHz)
MIN (eqn) may be desirable.
MAX (eqn)
Beat Note Spurs
These are spurs occurring for very small or very large values in
the fractional register. These are quickly attenuated by the loop
filter. Selection of the PFD therefore determines their location,
and ensures that they have negligible effect on the transmitter
spectrum.
Phase Noise
04617-0-031
The phase noise of a frequency synthesizer improves by 3dB for
30 35
every doubling of the PFD frequency. Because ACP is related to
the phase noise, the PFD may be increased to reduce the ACP
in the system. PFD frequencies of < 5MHz typically deliver
sufficient phase noise performance for most systems.
Deviation Frequency
The deviation frequency is adjustable in steps of
FPFD
FSTEP ( Hz) = (10)
214
To get the exact deviation frequency required, ensure FSTEP is a
factor of the desired deviation.
TIPS ON DESIGNING THE LOOP FILTER
The loop filter design is crucial in ensuring stable operation of
the transmitter, meeting Adjacent Channel Power (ACP)
specifications, and meeting spurious requirements for the
relevant regulations. ADIsimPLL is a free tool available to aid
the design of loop filters. The user enters the desired frequency
range, the reference crystal and PFD values, and the desired
loop bandwidth. ADIsimPLL gives a good starting point for the
filter, and the filter can be further optimized based on the
criteria below.
Rev. 0 | Page 17 of 28
ADF7012
Setting Tuning Sensitivity Value PA MATCHING
The tuning sensitivity or kV is usually denoted in MHz/V and is The ADF7012 exhibits optimum performance in terms of
required for the loop filter design. It refers to the amount that a transmit power and current consumption only if the RF output
change of a volt in the voltage applied to VCOIN pin, changes port is properly matched to the antenna impedance.
the output frequency. Typical data for the ADF7012 over a
ZOPT_PA depends primarily on the required output power,
frequency range is shown.
and the frequency range. Selecting the optimum ZOPT_PA
120
helps to minimize the current consumption. This data sheet
contains a number of matching networks for common
100
frequency bands. Under certain conditions it is recommended
to obtain a suitable ZOPT_PA value by means of a load-pull
80
measurement.
KV (MHz/V)

60
DVDD

40

RFOUT
20
004617-0-032

ANTENNA PA
LPF
0

04716-0-033
200 300 400 500 600 700 800 900 1000 1100 ZOPT_PA
FREQUENCY (MHz)

Figure 37. kV vs. VCO Frequency

Figure 38. ADF7012 with Harmonic Filter
Charge-Pump Current The impedance matching values provided in the next section
The charge-pump current allows the loop filter bandwidth to be are for 50 Ω environments. An additional matching network
changed using the registers. The loop bandwidth reduces as the may be required after the harmonic filter to match to the
charge pump current is reduced and vice versa. antenna impedance. This can be incorporated into the filter
Selecting Loop Filter Bandwidth design itself in order to reduce external components.
Data Rate TRANSMIT PROTOCOL AND CODING
The loop filter bandwidth should usually be at two to three CONSIDERATIONS
times the data rate. This ensures that the PLL has ample time

04617-0-034
to jump between the mark and space frequencies. SYNC ID
PREAMBLE WORD FIELD DATA FIELD CRC

ACP
In the case where the ACP specifications are difficult to meet, Figure 39. Typical Format of a Transmit Protocol
the loop filter bandwidth can be reduced further to reduce the
A dc-free preamble pattern such as 10101010… is recom-
phase noise at the adjacent channel. The filter rolls off at 20 dB
mended for FSK/ASK/OOK demodulation. Preamble patterns
per decade.
with longer run-length constraints such as 11001100…. can also
Spurious Levels be used. However, this can result in a longer synchronization
In the case where the output power is quite high, a reduced loop time of the received bit stream in the chosen receiver.
filter bandwidth reduces the spurious levels even further, and
provides additional margin on the specification.

The following sections provide examples of loop filter designs

for typical applications in specific frequencies.

Rev. 0 | Page 18 of 28
 ADF7012

APPLICATION EXAMPLES
R2

C1 C2 C3

VDD R1

U1
C5+ C5 C5 C10 C11
VDD 2.2µF 100pF
ADF7012 CREG2
470nF
10µF 0.22µF
1 24
DVDD CREG2
C6 CREG1 R9
2.2µF 2 23 3.6kΩ
CREG1 RSET

3 22
CPOUT AGND C12 C13
J1 100pF 2.2µF VDD
TxDATA 1kΩ TxDATA 4 21
TxDATA DVDD
L1 J4
1kΩ TxCLK 5 20 L2 C14 LF1 LF2
TxCLK TxCLK RFOUT

1kΩ MUXOUT 6 C15

19 CF1 CF2 CF2
MUXOUT MUXOUT RFGND

Y1 7 18
DGND VCOIN

C7 C8 OSC1 8 17
27pF 27pF OSC1 CVCO
J2 C9 OSC2 9 16
OSC2 L2
L3
1kΩ CLKOUT 10 15
CLKOUT CLKOUT L1
R3
1kΩ CLK CLK 11 14
J3–3 CLK CE VDD
9 PIN D-TYPE PLUG

R4
1kΩ DATA DATA 12 13
J3–5 DATA LE

R5 CE
1kΩ LE LE
J3–7

J3–6
TxDATA J5–1 J5–2 TxCLK
J3–8
R6 R7 R8 MUXOUT J5–3 J5–4 CLKOUT
1kΩ 1kΩ 1kΩ CLK J5–5 J5–5 DATA
LE J5–7 J5–8 CE

04617-0-035
VDD J5–9 J5–10

10 PIN HEADER (5X2)

Figure 40. Applications Diagrams with Harmonic Filter

Rev. 0 | Page 19 of 28
ADF7012
315 MHZ OPERATION
The recommendations here are guidelines only. The design Bias Current
should be subject to internal testing prior to FCC site testing. Because low current is desired, a 2.0 mA VCO bias can be used.
Matching components need to be adjusted for board layout. Additional bias current reduces any spur, but increases current
consumption.
The FCC standard 15.231 regulates operation in the band
from 260MHz to 470MHz in the US. This is used generally in The PA bias can be set to 5.5 mA and achieve 0 dBm.
the transmission of RF control signals, such as in a satellite- Loop Filter Bandwidth
decoder remote control, or remote keyless entry system. The
The loop filter is designed with ADIsimPLL Version 2.5. The
band cannot be used to send any continuous signal. The
loop bandwidth design is straightforward because the 20 dB
maximum output power allowed is governed by the duty cycle
bandwidth is generally of the order of >400 kHz (0.25% of
of the system. A typical design example for a remote control is
center frequency). A loop bandwidth of close to 100 kHz strikes
shown next.
a good balance between lock time and spurious suppression. If
Design Criteria it is found that pulling of the VCO is more than desired in OOK
315 MHz center frequency mode, the bandwidth could be increased.
FSK/OOK modulation Design of Harmonic Filter
1 mW output power
The main requirement of the harmonic filter should ensure that
House range
the third harmonic level is < −41.5 dBm. A fifth-order
Meets FCC 15.231
Chebyshev filter is recommended to achieve this, and a
The main requirements in the design of this remote are a long suggested starting point is given next. The Pi format is chosen
battery life and sufficient range. It is possible to adjust the to minimize the more expensive inductors.
output power of the ADF7012 to increase the range depending Component Values—Crystal: 3.6864MHz
on the antenna performance.
Loop Filter
The center frequency is 315 MHz. Because the ADF7012 ICP 0.866 mA
VCO is not recommended for operation in fundamental mode LBW 100 kHz
for frequencies below 400 MHz, the VCO needs to operate at C1 680 pF
630 MHz. Figure 36 (Output Frequency vs. External Inductor C2 12 nF
Value) implies an inductor value of 7.6 nH or close to this. The C3 220 pF
chip inductor chosen = 7.5 nH (0402CS-7N5 from Coilcraft). R1 1.1 kV
Coil inductors are recommended to provide sufficient Q for R2 3 kV
oscillation. Matching
Crystal and PFD L1 56 nH
L2 1 nF
Phase noise requirements are not excessive as the adjacent
C14 Short
channel power requirement is −20 dB. The PFD is chosen so as
C15 Open
to minimize spurious levels (beat note and reference), and to
ensure a quick crystal power-up time. Harmonic Filter
L4 22 nH
PFD = 3.6864 MHz − Power-Up Time 1.6ms. Figure 10 shows a L5 22 nH
typical power-on time for a 4 MHz crystal. CF1 3.3 pF
N-Divider CF2 8.2 pF
The N Divider is determined as being: CF3 3.3 pF
Nint = 85
Nfrac = (1850)/4096
VCO divide-by-2 is enabled
Deviation
The deviation is set to ± 50 kHz so as to accommodate a simple
receiver architecture.

The modulation steps available are in 3.6864 MHz/214 :

Modulation steps = 225 Hz
Modulation number = 50 kHz/225 Hz = 222

Rev. 0 | Page 20 of 28
 ADF7012

433 MHZ OPERATION

The recommendations here are guidelines only. The design Loop Filter Bandwidth
should be subject to internal testing prior to ETSI site testing. The loop filter is designed with ADIsimPLL Version 2.5. The
Matching components need to be adjusted for board layout. loop bandwidth design requires that the channel power be
< −36 dBm at ±870 kHz from the center. A loop bandwidth of
The ETSI standard EN 300-220 governs operation in the close to 160 kHz strikes a good balance between lock time for
433.050 MHz to 434.790 MHz band. For many systems, 10% data rates, including 32 kbps and spurious suppression. If it is
duty is sufficient for the transmitter to output 10 dBm. found that pulling of the VCO is more than desired in OOK
Design Criteria mode, the bandwidth could be increased.
433.92 MHz center frequency Design of Harmonic Filter
FSK modulation The main requirement of the harmonic filter should ensure
10 mW output power that the third harmonic level is < −30 dBm. A fifth-order
200 m range Chebyshev filter is recommended to achieve this, and a
Meets ETSI 300-220 suggested starting point is given next. The Pi format is chosen
The main requirement in the design of this remote is a long to minimize the more expensive inductors.
battery life and sufficient range. It is possible to adjust the Component Values—Crystal: 4.9152 MHz
output power of the ADF7012 to increase the range depending Loop Filter
on the antenna performance. Icp 2.0 mA
LBW 100 kHz
The center frequency is 433.92 MHz. It is possible to operate the
C1 680 pF
VCO at this frequency. Figure 36 shows the inductor value vs.
C2 12 nF
center frequency. The inductor chosen is 22 nH. Coilcraft
C3 270 pF
inductors such as 0603-CS-22NXJBU are recommended.
R1 910 V
Crystal and PFD R2 3.3 kV
The phase noise requirement is such to ensure the power at the
edge of the band is < −36 dBm. The PFD is chosen so as to Matching
minimize spurious levels (beat note and reference), and to L1 22 nH
ensure a quick crystal power-up time. L2 10 pF
C14 Short
PFD = 4.9152 MHz − Power-Up Time 1.6 ms. Figure 10 shows a C15 Open
typical power-up time for a 4 MHz crystal.
Harmonic Filter
N-Divider L4 22 nH
The N Divider is determined as being: L5 22 nH
Nint = 88 CF1 3.3 pF
Nfrac = (1152)/4096 CF2 8.2 pF
VCO divide-by-2 is not enabled CF3 3.3 pF
Deviation
The deviation is set to ± 50 kHz so as to accommodate a simple
receiver architecture.

The modulation steps available are in 4.9152 MHz/214 :

Modulation steps = 300 Hz
Modulation number = 50 kHz/300Hz = 167
Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used.
Additional bias current reduces any spurious, but increases
current consumption.

The PA bias can be set to 5.5 mA and achieve 10 dBm.

Rev. 0 | Page 21 of 28
ADF7012
868 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to ETSI site testing.
Matching components need to be adjusted for board layout.
The modulation steps available are in 4.9152 MHz/214 :
Modulation steps = 300 Hz
Modulation number = 19.2 kHz/300 Hz = 64.

The ETSI standard EN 300-220 governs operation in the Bias Current

868 MHz to 870MHz band. The band is broken down into Because low current is desired, a 2.5 mA VCO bias can be used.
several subbands each having a different duty cycle and output Additional bias current reduces any spurious, but increases
power requirement. Narrowband operation is possible in the current consumption. A 2.5 mA bias current gives the best
50kHz channels, but both the output power and data rate are spurious vs. phase noise trade-off.
limited by the −36 dBm adjacent channel power specification.
The PA bias should be set to 7.5 mA to achieve 12 dBm.
There are many different applications in this band, including
remote controls for security, sensor interrogation, metering Loop Filter Bandwidth
and home control. The loop filter is designed with ADIsimPLL Version 2.5. The
Design Criteria loop bandwidth design requires that the channel power be
< −36 dBm at ±250 kHz from the center. A loop bandwidth of
868.95 MHz center frequency (band 868.7MHz − 869.2 MHz)
close to <60 kHz is required to bring the phase noise at the edge
FSK modulation
of the band sufficiently low to meet the ACP specification. This
12 dBm output power
represents a compromise between the data rate requirement and
300 m range
the phase noise requirement.
Meets ETSI 300-220
38.4 kbps data rate Design of Harmonic Filter
The main requirement of the harmonic filter should ensure that
The design challenge is to enable the part to operate in this
the second and third harmonic levels are < −30 dBm. A fifth-
particular subband and meet the ACP requirement 250 kHz
order Chebyshev filter is recommended to achieve this, and a
away from the center.
suggested starting point is given next. The Pi format is chosen
The center frequency is 868.95 MHz. It is possible to operate the to minimize the more expensive inductors.
VCO at this frequency. Figure 31 shows the inductor value vs. Component Values—Crystal: 4.9152 MHz
center frequency. The inductor chosen is 1.9 nH. Coilcraft
Loop Filter
inductors such as 0402-CS-1N9XJBU are recommended.
Icp 1.44 mA
Crystal and PFD LBW 60 kHz
The phase noise requirement is such to ensure the power at C1 1.5 nF
the edge of the band is < −36 dBm. This requires close to C2 22 nF
−100 dBc/Hz phase noise at the edge of the band. C3 560 pF
R1 390 V
The PFD is chosen so as to minimize spurious levels (beat note R2 910 V
and reference), and to ensure a quick crystal power-up time. A
PFD of < 6 MHz places the largest PFD spur at a frequency of Matching
greater than 862 MHz, and so reduces the requirement on the L1 27 nH
spur level to −36 dBm instead of −54 dBm. L2 6.2 nH
C14 470 pF
PFD = 4.9152 MHz − Power Up-Time 1.6 ms. Figure 10 shows a C15 Open
typical power-on time for a 4MHz crystal.
Harmonic Filter
N-Divider
L4 8.2 nH
The N divider is determined as being: L5 8.2 nH
Nint = 176 CF1 4.7 pF
Nfrac = (3229)/4096 CF2 6.8 pF
VCO divide-by-2 is not enabled. CF3 4.7 pF
Deviation
The deviation is set to ±19.2 kHz so as to accommodate a
simple receiver architecture and also ensure that the
modulation spectrum is narrow enough to meet the adjacent
channel power (ACP) requirements.

Rev. 0 | Page 22 of 28

915 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to FCC site testing.
Matching components need to be adjusted for board layout.
FCC 15.247 and FCC 15.249 are the main regulations governing
operation in the 902 MHz to 928 MHz Band. FCC 15.247
requires some form of spectral spreading. Typically, the
ADF7012 would be used in conjunction with the frequency
hopping spread spectrum (FHSS) or it may be used in
conjunction with the digital modulation standard which
requires large deviation frequencies. Output power of < 1 W
is tolerated on certain spreading conditions.
Compliance with FCC 15.249 limits the output power to
−1.5 dBm, but does not require spreading. There are many
different applications in this band, including remote controls
for security, sensor interrogation, metering, and home control.
ADF7012
Deviation
The deviation is set to ±19.2 kHz so as to accommodate a
simple receiver architecture, and also to ensure the available
spectrum is used efficiently.
The modulation steps available are in 10 MHz/214 :
Modulation steps = 610 Hz
Modulation number = 19.2 kHz/610 Hz = 31.
Bias Current
Because low current is desired, a 3 mA VCO bias can be used
and still ensure oscillation at 928 MHz. Additional bias current
reduces any spurious noise, but increases current consumption.
A 3 mA bias current gives the best spurious vs. phase noise
trade-off.
The PA bias should be set to 5.5 mA to achieve 10 dBm power.

Design Criteria Loop Filter Bandwidth

915.2MHz center frequency The loop filter is designed with ADIsimPLL Version 2.5. A
FSK modulation data rate of 170 kHz is chosen, which allows for data rates of
10 dBm output power > 38.4 kbps. It also attenuates the beat note spurs quickly to
200 m range ensure they have no effect on system performance.
Meets FCC 15.247 Design of Harmonic Filter
38.4 kbps data rate
The main requirement of the harmonic filter should ensure
The center frequency is 915.2 MHz. It is possible to operate that the third harmonic level is < −41.5 dBm. A fifth-order
the VCO at this frequency. Figure 36 shows the inductor value Chebyshev filter is recommended to achieve this, and a
vs. center frequency. The inductor chosen is 1.6 nH. Coilcraft suggested starting point is given next. The Pi format is chosen
inductors such as 0603-CS-1N6XJBU are recommended. to minimize the number of inductors in the system.
Additional hopping frequencies can easily be generated by
changing the N value. Component Values—Crystal: 10 MHz
Loop Filter
Crystal and PFD Icp 1.44 mA
The phase noise requirement is such to ensure that the 20 dB LBW 170 kHz
bandwidth requirements are met. These are dependant on the C1 470 pF
channel spacing chosen. A typical channel spacing would be C2 12 nF
400 kHz, which would allow 50 channels in 20 MHz and enable C3 120 pF
the design to avoid the edges of the band. R1 470 V
The PFD is chosen so as to minimize spurious levels. There are R2 1.8 kV
beat note spurious levels at 910 MHz and 920 MHz, but the Matching
level is usually significantly less than the modulation power. L1 27 nH
They are also attenuated quickly by the loop filter to ensure a L2 6.2 nH
quick crystal power-up time. C14 470 pF
PFD = 10 MHz − Power-Up Time 1.8 ms (approximately). C15 Open
Figure 10 shows a typical power-on time for a 4 MHz crystal. Harmonic Filter
L4 8.2 nH
N-Divider L5 8.2 nH
The N divider is determined as being: CF1 4.7 pF
Nint = 91 CF2 6.8 pF
Nfrac = (2130)/4096 CF3 4.7 pF
VCO divide-by-2 is not enabled

Rev. 0 | Page 23 of 28
ADF7012

REGISTER DESCRIPTIONS
R REGISTER

ADDRESS
DOUBLER
CRYSTAL
XOEB

BITS
OUTPUT VCO CLOCK OUT 4-BIT R DIVIDER 11-BIT FREQUENCY ERROR CORRECTION
DIVIDER ADJUST DIVIDER

DB11
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (0) DB1

C1 (0) DB0
OD2

OD1

VA2

VA1

CL4

CL3

CL2

CL1

F11

F10
D1

R4

R3

R2

R1
X1

F9

F8

F7

F6

F5

F4

F3

F2

F1
D1 CRYSTAL DOUBLER F-COUNTER
0 CRYSTAL DOUBLER OFF F11 ....... F3 F2 F1 OFFSET
1 CRYSTAL DOUBLER ON 0 ....... 1 0 0 +1023
0 ....... 1 0 1 +1022
0 ....... . . . .
0 ....... 0 0 1 +1
X1 XOEB 0 ....... 0 0 0 +0
OD2 OD1 OUTPUT DIVIDER
0 XTAL OSCILLATOR ON (DEFAULT)
0 0 DISABLED 1 ....... 1 1 1 –1
1 XTAL OSCILLATOR OFF 1 ....... 1 1 0 –0
0 1 DIVIDE BY 2
. ....... . . . –1
1 0 DIVIDE BY 4 1 ....... 0 0 1 –1023
1 1 DIVIDE BY 8 1 ....... 0 0 0 –1024
e.g., F-COUNTER OFFSET = 1, FRACTIONAL
VA2 VA1 VCO ADJUST OFFSET = 1/215

0 0 NO VCO ADJUSTMENT
0 1 (FCENTER – (1 × f))
1 0 (FCENTER – (2 × f))
1 1 (FCENTER – (3 × f)) RF R COUNTER
RL4 RL3 RL2 RL1 DIVIDE RATIO
0 0 0 1 1
CLKOUT 0 0 1 0 2
CL4 CL3 CL2 CL1 DIVIDE RATIO 0 0 1 1 3
0 0 0 1 2 0 1 0 0 4
0 0 1 0 4 . . . . .
0 0 1 1 6 . . . . .
0 1 0 0 8 . . . . .
. . . . . 1 1 0 0 12
. . . . 16 (DEFAULT) 1 1 0 1 13

04617-0-027
. . . . . 1 1 1 0 14
1 1 1 0 28 1 1 1 1 15
1 1 1 1 30

Figure 41.

Rev. 0 | Page 24 of 28
 ADF7012
N-COUNTER LATCH

DB22 PRESCALER

ADDRESS
BITS
8-BIT INTEGER-N 12-BIT FRACTIONAL-N

DB11
DB23

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (0) DB1

C1 (1) DB0
M11
M12

M10

M9

M8

M7

M6

M5

M4

M3

M2

M1
N8

N7

N6

N5

N4

N3

N2

N1
P1

MODULUS
M12 M11 M10 ....... M3 M2 M1 DIVIDE RATIO
0 0 0 ....... 0 0 0 0
0 0 0 ....... 0 0 1 1
0 0 0 ....... 0 1 0 2
. . . ....... . . . .
. . . ....... . . . .
. . . ....... . . . .
1 1 1 ....... 1 0 0 4092
1 1 1 ....... 1 0 1 4093
1 1 1 ....... 1 1 0 4094
1 1 1 ....... 1 1 1 4095

e.g., SETTING F = 0 IN FSK MODE TURNS ON THE Σ-∆ WHILE

THE PLL IS AN INTEGER VALUE

N-COUNTER
N8 N7 N6 N5 N4 N3 N2 N1 DIVIDE RATIO
0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 2
0 0 0 0 0 0 1 0 3
. . . . . . . . .
. . . . . . . . .
. . . . . . . . .
1 1 1 1 1 1 1 0 254
1 1 1 1 1 1 1 1 255

e.g., MODULUS DIVIDE RATIO = 2048 - > 1/2

04617-0-028
P1 PRESCALER THE N-VALUE CHOSEN IS A MINIMUM OF
0 4/5 P2 + 3P + 3. FOR PRESCALER 8/9 THIS
1 8/9 MEANS A MINIMUM N-DIVIDE OF 91.

Figure 42.

Rev. 0 | Page 25 of 28
ADF7012
MODULATION REGISTER

COUNTER

CONTROL

ADDRESS
GOOK
INDEX

MOD

BITS
GFSK MOD
TEST BITS CONTROL MODULATION DEVIATION POWER AMPLIFIER

DB11
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (1) DB1

C1 (0) DB0
MC3

MC2

MC1
IC2

IC1

G1
D9

D8

D7

D6

D5

D4

D3

D2

D1

P6

P5

P4

P3

P2

P1

S2

S1
MUST BE LOW G1 GAUSSIAN OOK
0 ON
1 OFF

MODULATION
S2 S1 SCHEME
0 0 FSK
0 1 GFSK
1 0 ASK
1 1 OOK

IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0 POWER AMPLIFIER OUTPUT LEVEL

D6 . . D2 D1 P6 . . P2 P1
0 . . X X PA OFF 0 . . X X PA OFF
. . . 0 0 –16.0dBm 0 . . 0 1 –16.0dBm
0 . . 0 1 1/31 * 14dBm 0 . . 1 0 1/31 * 14dBm
0 . . 1 0 2/31 * 14dBm 0 . . 1 1 2/31 * 14dBm
. . . . . . . . . . . .
. . . . . . . . . . . .
1 1 1 1 1 14dBm 1 1 1 1 1 13dBm

IF FREQUENCY SHIFT KEYING SELECTED

FSTEP = FPFD /214
D9 ....... D3 D2 D1 F DEVIATION
0 ....... 0 0 0 PLL MODE
0 ....... 0 0 1 1 × –FSTEP
0 ....... 0 1 0 2 × –FSTEP
0 ....... 0 1 1 3 × –FSTEP
. ....... . . . .......
1 ....... 1 1 . 511 × –FSTEP

IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED

IC2 IC1 INDEX COUNTER D7 ....... D3 D2 D1 DIVIDER FACTOR

0 0 16 0 ....... 0 0 0 0
0 1 32 0 ....... 0 0 1 1
1 0 64 0 ....... 0 1 0 2
1 1 128 0 ....... 0 1 1 3
. ....... . . . .......
MC3 MC2 MC1 GFSK MOD CONTROL 1... ....... 1 1 1 127
0 0 0 0
0 0 1 1
. . . .
04617-0-029

1 1 1 7

Figure 43.

Rev. 0 | Page 26 of 28
 ADF7012
FUNCTION REGISTER

PLL ENABLE
PRECISION

ADDRESS
DISABLE

CLKOUT
ENABLE

ENABLE
INVERT
DATA

BITS
VCO

PA
LD
SD TEST PLL TEST PA BIAS VCO BIAS MUXOUT BLEED CHARGE
MODES MODES CURRENT PUMP

DB11
DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (1) DB1

C1 (1) DB0
PA3

PA2

PA1

VB4

VB3

VB2

VB1

VD1

CP4

CP3

CP2

CP1

PD3

PD2

PD1
LD1
ST4

ST3

ST2

ST1

PT5

PT4

PT3

PT2

PT1

M4

M3

M2

M1

I1
I1 DATA INVERT
0 DATA
1 DATA

PA3 PA2 PA1 PA BIAS CP4 BLEED DOWN PD1 PLL ENABLE
0 0 0 5µA 0 BLEED OFF 0 PLL OFF
0 0 1 6µA 1 BLEED ON 1 PLL ON
0 1 0 7µA
. . . .
. . . . CP3 BLEED UP PD2 PA ENABLE
1 1 1 12µA 0 BLEED OFF 0 PA OFF
1 BLEED ON 1 PA ON

CHARGE PUMP
CP2 CP1 CURRENT
0 0 0.3mA
0 1 0.9mA
1 0 1.5mA
1 1 2.1mA

VCO BIAS VD1 VCO DISABLE PD3 CLKOUT

VB4 VB3 VB2 VB1 CURRENT 0 VCO ON 0 CLKOUT OFF
0 0 0 1 0.5mA 1 VCO OFF 1 CLKOUT ON
0 0 1 0 1mA
. . . . .
1 1 1 1 8mA

M4 M3 M2 M1 MUXOUT
0 0 0 0 LOGIC LOW
0 0 0 1 LOGIC HIGH
0 0 1 0 INVALID MODE – DO NOT USE
0 0 1 1 REGULATOR READY (DEFAULT)
0 1 0 0 DIGITAL LOCK DETECT
0 1 0 1 ANALOG LOCK DETECT
0 1 1 0 R DIVIDER/2 OUTPUT
0 1 1 1 N DIVIDER/2 OUTPUT
1 0 0 0 RF R DIVIDER OUTPUT
1 0 0 1 DATA RATE
1 0 1 0 BATTERY MEASURE IS > 3.25V
1 0 1 1 BATTERY MEASURE IS > 3V
1 1 0 0 BATTERY MEASURE IS > 2.75V
1 1 0 1 BATTERY MEASURE IS > 2.35V
04617-0-030

1 1 1 0 NORMAL TEST MODES

1 1 1 1 Σ-∆ TEST MODES

Figure 44.

Rev. 0 | Page 27 of 28
ADF7012

OUTLINE DIMENSIONS
7.90
7.80
7.70

24 13

4.50
4.40
4.30
6.40 BSC
1 12

PIN 1
0.65 1.20
BSC MAX
0.15
0.05
8° 0.75
0.30 0° 0.60
SEATING 0.20
0.19 PLANE 0.45
0.09
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AD

Figure 45. 24-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-24)

ORDERING GUIDE
Model Temperature Range Package Description Package Option Frequency Range
ADF7012BRU −40°C to +85°C TSSOP RU-24 50 MHz to 1 GHz
ADF7012BRU-REEL −40°C to +85°C TSSOP, 13”REEL RU-24 50 MHz to 1 GHz
ADF7012BRU-REEL7 −40°C to +85°C TSSOP, 7” REEL RU-24 50 MHz to 1 GHz
EVAL-ADF7012EB1 Evaluation Board 902 MHz to 928 MHz
EVAL-ADF7012EB2 Evaluation Board 860 MHz to 880 MHz
EVAL-ADF7012EB3 Evaluation Board 418 MHz to 435 MHz
EVAL-ADF7012EB4 Evaluation Board 310 MHz to 330 MHz
EVAL-ADF7012EB5 Evaluation Board 50 MHz to 1 GHz

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04617–0–10/04(0)

Rev. 0 | Page 28 of 28