QuavTun oo Digital nissan + Topic-wise coverage of entire syllabus in Question-Answer form. + Short Questions (2 Marks) Scanned with CamScanner‘pram Singh a pupListte0 8} Quantum Page Pvt. Ltd. aNet No, 5972/7, Sita 4, ads ‘sahibabad, Ghaziabad-201 010 0120-16089 Poet graeme reg ieee ast Rohtas Nagar, Sshadara, Dety.1y pethi Office: 16590, Bs ‘© AuRicias Resteveo polation may be reproduced 0 transmit, ry msont, without permission, ths peels ‘Float conbined in this work s derived from sources Inova tbe real Every effort has been made to ensure euacy, however neither the publisher nor the authors [prance the accuracy or completeness of any information Prlshed herein and neither the publisher nor the authors hall be esponable for any errors, omissions, or damages asin out of use of tis information, Digital Electronies (EN : Sem-) 1 ition + 2009-10 2 Editon : 2010-11 39 Béition + 2011-22 4° Baiton : 2012-13 5° Bultion = 2019.14 6 Edition : 201415, 7 Biiton : 2015-16 8" Bdition : 2016-17 9 Edition : 2017-18 10° Baltion : 2018-19 r 118 Edition : 2019.20 Price: Rs. 25/- only mee Printed at Mayank Enterprises, Da AIOODS _ == CONTENTS eee (-tAto1-34a) UNIT: ; DIGITAL SYSTEM & BINARY NUMBERS. ‘Number System andits arithmetic Sigredbinary numbers, Binary ‘oes Cyclic codes, Hamming Code, the map method wp to five Sariable, Dont care conditions, POS simplification, NAND and NORimplementation, Quine e-Chasky method (Tabular method), LUNIT:2: COMBINATIONALLOGIC (2-1Ato2-33 8) ‘Combinational Cieuts: Analysis Procedure, Design procedure, inary adder subtractor, Decimal adder, Binary multiplier, Magnitude comparator, Multiplexers, Demuliplexers, Decoders, Encoders. \UNIT-3: SEQUENTIAL LOGIC (1At03-97A) ‘Storage elements: latches & flip ops, Characteristic Equations of Flip ops, lip Rop Conversion, Sift Registers, Ripple Counters, ‘Synchronous Counters, ther Counters: Johnson &e Ring Counter. UNIT: SYNCHRONOUS SEQUENTIALCIRCUITS (4-1 Ato4-51A) “Analysis of clocked sequential circuits with state machine designing, State reduction and assignments, Design procedure, Analysts ‘Asynchronous sequential drew, circuit with aches, jure, Reduction of state and flow table, Race-tree (-1At0S-454) ‘Digital Logic Families: DTL, DCTL, TIL, ECT. & CMOS etc. Fan ‘Out, Fan in, Noise Margin; RAM, ROM, PLA, PAL: Circuits of {Logic Families, Interfacing of Digital Logic Families, Circuit Implementation using ROM, PLA and PAL; CPLD and FPGA. (SQ1At0SQ-15 A) SHORT QUESTIONS ~ (SP-LAtSP-26 A) ‘SOLVED PAPERS (2014-150 2018-19) Scanned with CamScannerDigital System ang Binary Numbers (0-24 to ea) L-2A ECICSIT-Sem-3) Digital System & Binary Numbers Se] re PART-1 Nuber System ond Is Arihmel, Signed Binary Numbers, Pe pinary Codes, Cylis Codes, Hamming Cale. CONCEPT GUTLINE : PART-1 +‘ Thenumber system are as follows : i Decimal numaber system. i Binary number system. i Octal number system. fy, Hexadecimal number system. + “Complements These are wed in digital computers to simplify thesubtraction operation and for logical manipulation. - 1+ Oneofthe mast common error correcting codes is the Hamming code + Kreede which has one bit change in successive code words is called eyticcode A.Concipt Outline: Part-1 2B Long and Medium Ansuer Type Question To RieelionsAniwers Concept Outing 2 tongand Medium Answer Bie Ga cations 1-1A Geers, define signed and ‘QeETI] Derine number aystem and al ‘unsigned binary number ? (Answer: [Number system It isa language of digital systems consisting ofa set of ‘atote called digits with rules defined for their addition, multiplication and ‘ther mathematieal operations. ‘The clasifeation of number system are as fll 1 Decimal number aystem It has 10 symbols othe base or radix of {his number systema ie 10, The 10 symbols are, 1,2,3,4,5,5,7.8,9. inary number system Teiea base 2 number system, Thetwo binary digita are Land 0. 8. Octal number system Ithas abe f8, thas eight posiblediit 0, 1,2,3,45, 6and Hexadecimal number system: It isa base 16 number system, It has Aigitsfrom 0t09, A,B,C, D, EandF. Complements ; Thete are used in digital computers to simplify the ‘Sheroction operation and or logical manipulation, Scanned with CamScannerieee _ EAA BCICUTT An aa] equlalentas ar iL st, i, n325,, Ww, coas.228),, a on 1 Conver the deci number 225225 to binary number. Tnwwer atone, nan) dia Sin mg it notation, red ot ony nitude (aba avert the following decimal numbers to thelr binary Thus, (63), = 1010011), ostera fae! wma cho 12014 st240 ea baa oan oie st, =. iow * toon», °° 10111100000, PRU ee JAA WCICHIT Sem-3) Digital atom & Binary Numbers 1, 00325), 2 [30 0 + sus «2 560 aps aaa pare oxox abit 2p 0500 «2 L000 af 0 aire 0.000» 2 -b00- aoe (200, «x01100, (309.325), = 43013010010, fw, casz2H), 2| 20 oex2 0ST? apm oas «225207 ato 090 +2. 507 t 2] 25-0 oso 2- Leo apace gon 2- 207 210 0.20 x 2= 0.40, 2 oaos2cdsar? a4 on «20 i567! on 6x 2u12 ash coo ome, I cocrc is may, f anmysOn-05 & Wore Gaeth Tharwer £627,020 ho “010 a» star (627), «(926)g=(00110010.1110, He BCByg# Oyo =O, (CO) = 114 16612 16! +6 «169 = 9014, (G044),y= (101111000110), ue TA | Represent the decimal number Gin ) excens.d code, i) CD code, (it) Gray code, (ie) 8491 code and (v) 2421 coder. ARTUSOIE15, Marks 08 0011 0010 .1110->(32B), Scanned with CamScanner1-8A (RCICSIT-Sem-3) Digital System & Binary Numbers 1010 10111100 (in binary) 00 1011110, Toni 1001 7010, kL neDendet (y= ON06in B00) + OTA fi Grayeode: (6,000 7 (7Dy_* 000 111 111 Gnbinary ae (aoe = 001 ¢00 111 ww (+ G0, = 10000 it = 206), tied Gy oe = 001 ‘EaTAT] Represent the unsigned decimal number 965 and 672in fe ed ede: 6, 010 ‘cate 00 ‘21 code: ha given number are as follows: ‘5 1001 OLl0 O101 sr oo ott __ 010 (7-185) using CESARE R= uN nom a) 2 Since, F>9a0dD>9,ce java BCD, therefor, ang 6 (0110, nF feel and Beet CAS} oeULAHOI0L uM or on & egg "no | teat ot Taken an, Si ooo ssdziton tee conn, Hence, th um is 1597 sane igerlenetoti85 =. onnoot - Watinay torn + oolooot JIETRE The solution othe quadratic equation s*~ 1x +22 20 oe Toman sre=3.and.x=6. hat it tho bae ofthe number system used? fora. The anon e "eT negative and isin the 2 complement [ARTO 01-19, 2015-76 Niarka 05] aug, ems wer themes otis =D) aerer =] SOMO Le C118)? 1 Sopa thease te namber in, The given quadratic quaint PARE) Adin ttonint neater, 2 Themluinotqudratiehaton i, a paren) 4. Taquadratic quation formed with these rot is Guve-oee-Grdzeer9 82) 4. Comperingea (82 with to pvon qunraiseg C8) ‘eat, Scanned with CamScannerBade Bxd= 18 26+ 1)= 18, ence the bas of the umber system is 8 Fei [Pertorm he following subtraction using 2 aaa ne sing 2s complemen, PY ewo-o1001 corn. .01-o001.1110 Taner] A Ascuniag, Yecorplement: (ASTOR Naw) x= 01000, 1001 Y= 1010 +1 jou X= 01000 -Ye1m1 Diference = 14111 There isto endear, {ecomplemeat: X-¥y-(2e complement of 110) S Acsuning, X= 00111001, Y= 0001.10 Vecomplement Ye 110.0001 n : +1 ccaplemest: Y= Topo gal das N to ot toen Leeap atin eeTbOLS, words or letters. As the ‘Propofnary numbers, we callitasthe bit forte 5 detignng and analyse of itl ‘edigtalommuntaton The codes 1-8A(ECICSIT-Sem-3) Digital Systom & Binary Numbers classified into certain following categories: ‘Weighted codes ‘Non-weighted codes Reflective codes ‘Sequential eodes Alphanumeric codes ‘Error detecting and correcting codes. 3. Since allthese codes use only O and 1, soit is easier to implement. The binary codes ean aleo be ueed for representing the numbers as well ax thealphanumeric letters of codes can be composed in tabular form which sas aeeRer Codes ‘aden ASCH Error detecting TEBCDIC & correcting cod +2 Non-weihted, $221 Binary RCD codes Seana + Earesed suai +r 5. Weighted binary codes are those which cbeythe positional weight for ‘the numer to represent. 6. Innon-weighted code, the positional weights are nat assigned. 7, Im reflective code, the reflectivity is desirable, For example, in 9 complement subtraction Le. code for 9isthe complement for 0, code for Sis complement of 1, for, 6 for 3 and Sor 4. 8, _Insequential code, each eveesoding code is ane binary number greater than the preceding code 9, The alphanumerie codes ae designed to represent numbers aswell as characters. 10, The error detecting and correcting endes are sed to detect and correct the errr lke O may change to Lor vice-versa by using some special ‘des which posses the capacity to detect and correct the error. STAT] Represent decimal number“-13"inall three methods of negative binary number representation using eight bits. “ARTUOIS14, Marks 5) Scanned with CamScannerSSHHEH 1 SEER BY Hessen pn RRR ntt_rre ere ro 19a @oesmr Sema) HOAwaCeATSems) __Diiyten Easy Numb Awe ene ARR in, exon, Re tineeroienat as | tn, Oona, ‘eae eth tn ee 8 shady ne samc = OHB10D, ASMPSRINI AT atest one eee Sees Selisuoyicods Merit hint ota abegeie: ror, SevGnnnlplcons hcrecomcnvtr cago ese com, =m noes Sarees FEE comnts 1.0 cpocte Te generator ayo .* 7 for this code is given as G(x) = 1 +x +x*. Find all the code words of Teeonplemeat = @¥—1-(00001100), ee = cm, sano, is ee TE] ntact rte Genco acptc code? 2 row teri aingrenby =] rimee@ om | Answer: Here nad, hed and men-ke7-4, m=3 1 Wiese it pater of tro eonseeutive numbers " SOR) = Qi) G2) mae tive punbers fer in only ooeit =. For 21 2 Gqueedstnnena HR (0=Q109/0 Sevier . Givers Sse Hck eis ead ae code iit natn the tee Meneicle eset sat By sing Male? abr) ia tun 5 oencaratC tanta nie —- mae whteteingt neeotet See derctoret 7 SEE Cialy one place to the right, isalso® eoeeees 5 aaa os (1122) QG@esexer _ ‘Ry@)=22+1 srseisaeceDateseD 4 rrww ton ‘Teorem:If gic a gris (1123) S ested 2 en) ple depen P andisatcorel Pron ple ial Vs) fortes 22 OB eee te ty ich the cole 5 are Tae acapella Fre a, Anetampoteiceut” a2 ee . = Boxed ——e Scanned with CamScannerEe pig LaieDeien at tat at 100 OL OL ese aefo 1 o ofr oo roid ooo word Fi expe Dew ooo cyedae0 000000 1o0010 7g oO rootid cat 00 foe to oa 0 9 poor01g = 00101 ‘Sir cleating fr oter neta Message block Ganda word vector 7 7) O 20 0 0 0 o do 0 oo O10 4 go Oo ey a Do tat ue o1oo 1d we ff oy g42 © Al aso 6 0 vad ot Ten ot 1 ten tg tos0 0 1 6 ie roo did vet 10m oe 1 rad 10 110 0 ii ri ooo 2 Ty tioi1o0 0 rad 111010 priridt er ttalng code forthe message "0100100101" ce lero 2 20a ror detection and corresti® by wesuming an error in any one ofthe 7 i 1 tit data word We ncade «party Se ity be Waite astallonss Yh the L1-bi¢ word and arrande® ‘tpoaition EGER 2 [w]npehs] vfofeftfe afar NOW of a3, 8, 79.10.19, 18) Taw1oa1DoH0ed a) OR of te 67, 10,11. 16,19) dwowoa0aoa1e0 n OW of it (8, 7,12. 18, 14, 18) fieoeoa1@ oat 0 1 {OR of bit (2, 10, 12,12, 18, 14,18) Trees aia 08100 1 A Subetituting the 4 parity bits in thle proper position, we obtain the AB-it composite won stored in memory. Bitposition: thn Papel hye Ge Ts [ele [a Tele [oofsafialia [res ‘When the 1bits aro read from memory they are checked again for ‘rv, the pity seheck her tho sare combats ot inating hope, A Thed check bite reevaluated as flows: G,« NORofbite U8, 7.9 11 15 18140 ye NORotits 2, 8,6, 7, 10,11, 14 1800 Cla NORotBte 4 5,8, 7, 12,1 14 19040 ye NORCBHS 9 10,1 12 ALE 1S 1 A Oeheck bit designates even party over the stevked Bits and at Jaigtstevintd party Since the ttewee store with even part, the SOREN and inicates that no error has occured. However, if Boovea thet bt Binary number med the check bts ves the position athe eeeneons hits 6 Forexample, consider the flloeing three 4568 Nevo: Tas TTR TLS) weet fo] fof elofi a) [0 Seem eevee] fofaP rfofole fo] so lemrin ofr afafo fo] oft fot operon Scanned with CamScannerLoge Desen 118A Ecegy ng the XOR of the corresponding bits tobe as follows : chee G Forno error: 0 Witherrorinbit1: 0 Fi ‘With error in bi 0 1 she enor ean be corecied hy complement Foitnottbeiineror Error detection and correction : 1 Tsai psa itr of thle sila ay putheemoon tay coe soa err ont retrieving the binary information, 2 Therelibilty ofamemory unit may be improved by employing sigan erorsocingcedes. The met ominoncns ee shel te pay 8. Inthe Hanning cide, parity bits are aed van nit jt fonng anew worden Hike , 4 Tit sin are numbered in sequence fom tom +b: Tine Foie mated va pwer of ae reserved fora pak Tereosning his rthe data, The ade cane soca tiers 5 The Haning cde can dtct and coret only a single en ing ther pry tthe coed word the Hams eal c ¢__imibliret ng errand dle dose vein this addon] parity i, then the previous Ide Hxiitome olnuworttooio Re where Paiseoncl noes iOH of fh other 16 bit. this prodGeen the let an ioon.r010 een party, Frode the 26-bit wer 1. Wen th 18 word w er ia read trom memory, the check bits a reat ithe party Paver the enti le Ss tS san i odd peert) but if P= 1, then the parity over the 16-isit 96 the corresponding i 1 asingle yrrected. & wero or occurred that can be co: Canoot be earn error occurred that is detected, bt! ' Weeoaape ‘This scheme may gen TF Oeeurred in the P,, bit. sei more than two errors, but i not guaran! 114A ECICSAT-Sem-3) Digital System & Binary Numbers Given, Hamming code received = 1001101001 Pi] Pa] Ps| Pa] Ps] Pa] Ps] Ps | Po] Pro] tfofe[s]ifefaleofo|a 2 Let code is sent and received on the basis of odd parity. Therefore, we can find the correction bits as fellows Cy=EXOR (P,,D,,Ds, Dy,Dy) 4,0,1,1,0)=0 p= EX-OR (Py,Dy,Dy.D;,D,) (,0,0,3,1)=1. Cy=EXOR —” P,.Dy,D,,D,) 1,0, 20 Cy=EX-OR — (y.Dy, Diy Dy))= EX-OR 0,0 =0 8. Thuserrorbit location is C{C\C,C, = 0010 ‘4. Thuserror isin 2" bit. Thus correct codeis 1101101001. ‘QESTAGE] Detect and correct error (ifany) in the folowing received ven parity Hamming code word 00111101010, Also find out the correct message. “ARTU 2010-13, Marks 05 “Anewer 1 ‘The received Hamming code word = 00111101010 2 The parity bit required is determined by Donekel where, ‘n= number of data bits ‘k= number ofparity bite 3. Since, the Hamming code word is of I-bit, ie, nekell %, ae 4 Hence, numberof party bit required, k= 4,(P,,P,. P,P) ‘Thus, in this received Hamming code, number ofdata bits 7 and number ‘ofparity bit is 4 5. 11-bit Hamming code can be represented as PF. |F | d,| | of dD] 0, Te, ofefafalafafofa itscan be determined at ©,=P,80,8D,0D,80, 0D, =00101808000-0 Scanned with CamScannerDigital Lage Design 115A @oreg Sen 9D, D,8D, @D,, OD, 1-10 (ECICSIT:Sern) Digital System & Binary Numbers o1@1 90816) K-map and logie diagram : G,=P,8D,8D,9D, Ce =1916100-1 Coo C,=P,8D,8D,9D,, eo 1908160=0 A rs 1. ence the chee itis 10, his indcates thatthe number ato “ ie lesDyvanere Hee isgen andi sbouldbeO Theres] ¥eAepocap correct esiogs its 00411001010, ; 4 so ‘QSETI] Desir apaity generator togencratean odd payin zl foraAit word. Use EXOR and EX-OR gate. sg) zie F=AQBOCOD = EKNOR(A, B,C,D) siete . = Songs Ths out that generates the party bit inthe transmitters calleda eA PART-2. ‘ary eterator. The circuit that checks the partyin the soe Method upta Foe cae parity checker Gad 7 Tle Map Method pte Fie Vari 2 Conier tata when input bitieA, B,C and D, So, the truth tale | foran odd parity generator i es, Dont Care Conditions; | [SSS alte MeClhey Method Tabular Meta aitiewnage CONCEPT OUTLINE | PARTS [ae ep * Bsc theorems and properties ofboalean algebra? an rtocr hele sent 1 eo zevel aero soy ft] @ ssicl w Eoso + Tewlutins | eyez o1$o] 0 Caetiveccayeyen haere faa ol Aes Gerster es Bagel tole otto 1 Axbsdegte bree syete ean 0 aaryesy bogierey 6 o0 0 axtnyes bate+y)ax reo g| 3s 2 roig] ? 2 ie tela 1 99 : i Meee te leec alte age Q sat Scanned with CamScannerDeaeoer____LEA Pt AROSE So Digital System & Binary Numbers oa] Wit short nat on ie - MAP Also thoy y ADS CB_G>_cp ch 00 or 0 vueton af boolean expression and how to mark pairs, imp [mr | omy | my 0 | 000] oon] oo13 [ooxo reduc aon implemented ? How gy, AB 00 | 09 01 or | ooxo [Answer i: KB} mg | mg | my | mg on 04 | 0100 | o101 | o113 J o110| 1. Karnaugh mapis another way of prosenting the information gi * fre Hoe map real Kaown by the nana Range lB ma | mn me ma 3 {sea 0 mse tho np for two varibles, There may be four yt ominatons within four square Sale se ie lsc) ail alo 2 Bachequre ropreante unique interes a shown in Fig, 1.4 77 NEo Nod (eras 7 arco [foi GSTADI] Minimize the given boolean function using Ke-map. 4 oR | 4 FA, B, C, D) = m(3, 4,5, 7,9, 13, 14, 15) 4B a] 10 | an ee: Yor thrce variables: Thore aro eight minterms for theo bis ‘ribs Hencothe map consists of eight squares. ic ATE Te no nt Non or a1 0 Xm] ™]ms]m] — 0Jooo]oor] ors [oxo Ph. on ete fl fmm] ofa] 1 {r00) 01/14) ri0 eof ee (ia 1945 / (righi8.2, Fe Abé+AcD+AcD+ABc ‘The map drawn in Fig 1.18.2, for threo variables in marked wit ‘umber in each rw and each column to show the relationship bel" Explain with example using four variable map. How ‘the squares and the three variables. For example, ' exon care conditions are implemented in Kmap minimization? ‘hesquare assigned tom, whch corresponds {hi colurn OL, When these two numbers reconsidered, they ve binary number 101, ers reenalaere on when dina qalalnt in. Payty th sien tneton, For four variables ; : oe ™ "Foy, 9, 8) = 20,3, 7, 14,18) interme het funtion of four binary variables require s#*whieh has the don't care conditions bemepconsateofsntem agueres. sy 598) =10,2,8) eats 015, 16minrm, THe mapso™ the four variablow In every square th whi lean function quand con the Rubers are written, The number dones# MI,” Consider tho example, which has bool Pond to that numbers rainterm. nen gh aE MOST 118) Scanned with CamScannerRES TRUER conn —— TEES RA vetsinedein AOU agg nomen) Distt nay unter ax, 992) = Em, 2 8 ‘ABCD + ABCD. ABicD + ABGD + aBcD + ABCD ‘2. ThemintermsofF are the variable combinations that make the funetiog . ee el Tei retsntrme of are the doncare minterms that may y Y=Em(,9, 11,12 13,16) titer Or 1 2. Now for POS form we will take complement Function, 3, The K-map simplifications shown in Fig. 120.1 ¥ =11M00,1,2,3,4,6,6,8, 10,10) wXEoo oh 10 TOO OL_ 11 10 Minimfration through K-mapisshownin Fig. 121.1 on ool = 1(2, 0), aw erp c+ G+B G+p we w a ae. sol{Car To ate 7 ay ad oll halal £ ai a 1 ot | Mal ad AF | oo al bs cra * XL] | al ‘lig 1 200 pai ee] (wigan A. ThemintermsofFare markedby 1', those od are marked by xs and cal the remaining led with FAs BA+OKS +D)B+D) 5 ToptibesinfderrenieninSOP frm wemustindealfve tig, ACD + CD + AB ABCD ‘inthe map, butwe may or mayot include ay ofthe depending ot : the way the functions simplified, " dependingos | ygyy= ACD +CD+AB+ ABCD © InFig 12031, dont care minterms O and 2 are inched withthe 1s = Alt+B)CDs1A+ ANB + PCD +AB(C+CXD+D)+ ABCD Beeler = AlB+B)CDs(Av AN BAB ICD + AB(C+END Die ABCD 7. TaFig- 1.20.10), dont cate interm 5 isincuded with the 1, resulting ++ ABCD + ABCD + ABCD + ABCD Feytue Y= Em, 5,8, 9,30, 11,19, 14,15) 8 2. Now for POS form, we have to take complement function, ¥ = 11 AM0,2,9,4,6,7,12) EBRD] steoptty en 3, Minimization through K:map isshown in Fig,1.21.. Be] Simptity the following expression into product of sum er (08) form AiRcsDe+BE+DE+D {ABC ABD nep ‘The Kapa Ps inven a) amet became, we hee twee == ayy asBlfe L ABC + ABD+ BeD AS of ot x Real L It Y= ABO+ ABD + Bop . nana = ABC(Ds B+ ABC +6 . vigtats.) P+ABic+0>D-1A+ ABCD ¥ =AsDus OB C+D) Scanned with CamScannerDigital Logic Design 2a | ACCS, ‘TEETH simplty he fotlowingboot se 1-284 (ECICAITT-Bom-9) Digital Sytem Binary Numbers number of literals, . 710 ai i AC +ABC+ AC + AB We (25 ex)ezeay ewe RU, ‘Aniwer: , AC +aBC+ AC + AB D Let Y= AC +AG+AB4 anc = 0A+A)+ As Bo) Given, (CD + ABCD = ABDIC+C) = 2+AB+o) WeAedeg omer C+AC+AB te G+ Ac G+arecy ——* _ YU B.C.) ABB = C+A+AB Que 1.25. | Express the following boolean function F in a sum of =S+aa+B) tminterma and a product of maxterms. = Ase Fla,y,2)= ay 42) 422) BT sasseayews bl Y<(2y ta) ¢24ay ee 1 Given Fi, 9,2) = Gay + 2) (9 +22) EY tesxytuz uy +maye + yet aes tEy soeeaees 2 By associative property to =: stews Fasayeayeryeoseongee Denotes Fyermlys 5) ‘RET sin the otowing expression as mach an possi syetgE+fyesy2 (exer) Flsss3,2)=¥2' sure’ su'aye uy? PLE, 5,6.0 ‘04 implement your result using universal pater only Byala, = G19 0B oFoskeyeDeoFo) Ponaan2) WESTIE] tmplement the fellowing boolean function with NAND Fusnatlaye sue guige eu sates Fs, 3,2) «E2345. LEE Oe ee tie 7 2PO' sty ewe oy) 1 HG twmewrerey :ATABeA OH 1 TYE Sag sure TY Hy wee) Tey whew B) Tee toi rae ‘The Kemap simplification shown in Fig. L261. Scanned with CamScanner2 Dita Lge Desi 2 Hens te inp foe Perens 4 Ioplemestaton sing AND g F | im = (Rer262] QEEEEE] Simplty the boolean function + together with doot {$re condition °F using K-map and implement it with two level NAND pate circuit YeBD+ BCD+ ABCD (ARrosores warts arg L Gres, Fs BD BCD ABCD = As DBIC+0)D+(A+ ABCD + ABCD BCD + ABCD + ABCD+ABCD+ ABCD +ABCD+ABCD 567,10, 13, 14,15) ‘tren any doa care condition so K-map is as showait © 0 « ch Y. 2 Asters Fem ou io =a pvp B0+ (D+ BC) © y a DPE pt fl J > )>-+—_—_ia igia72) QaeTSA | Minimize the given boolean function using K-map and {implement the simplified function using NAND gates only. FUA,B,C,D)=Emm(0,1,2,9, 1, 15) +dl8, 10, 10) Hees] ‘Minimization using K-map : 1 Given, FUA,B,C,D)= 2m, 1,2,9, 11, 15)+4(, 10,14) LPh59 oy a0 nan Implementation using NAND gates: LL Taking double inversion ofeg. (L281) Scanned with CamScanner1 The K-map method is suitable for x Etat tate ha, Enesco scan nem te ediiccatparce eer Consider the funtion, ms ra Pree hae ich ee ‘The binary epresentat of the numberof indeed set Now compare each Bory. tinge 'Pr=Emt0.2.8,6,7, 8,10, 1219 for sping wig ie 2m of numbers in tras ‘index as shown In Table 129.1, binary term with every term in the net het cate ampere each binary term wit tebe Mannion cel vhich ae dinety Lago 1-26 ECICSIT-Sem.3) Digital System & Binary Numbers Table129.1. No.of] Minterms] Binary] Minterms] Binary | Minterm | Binary] Ys (Geel) (eel) o | ™, | 0000! a2 | 00-0 [02810] 0-0 ose | 000 29° [oor | 2367] o1_ m, |oo10] 267 |o_10 1 2107 | 010 1000] g10¢ | 100 812 | 100 a 2} moor) ex oss m {0110 1233 | o11_ my, | 1010] 13 | 110. m, [1100 3 |=, port m, [101 8. Applysameprocessto the resultant stag. Allthe term which remain unchecked are the P's. Now prepare «PL chart o determine essential prize implicants 10. Allthe PTs are represented in rows and sch minterm of fnction in a ‘column shown in Tele 129.2" 1, Puttheo in each row to show the composition ef misters that make Pn Tableis92 Pine Ayal interme imoticant | m| mm] | mo, |e ale acb_| si Let fel casey [zis | Tere wy [e280] ofo fel dev [2ae7| folololo I 18 The column that contains eng dt Os esata rime plas 14 Atick mark spot above each column which hasoaly one © mark. Scanned with CamScannerA EES a eae a je Design 127A Eres, a esa worcerrsem Digital System & Binary Numbers 15, Thesumof sll EPTs gives the function ints minimsl SOP feng | FA,B.C,D)= ABC+BD +c Table 1203, Pie npn 7 Faz ‘GHG site the flowing ewitehing fonction ang sme |ma mlm] Quine-Me Cluskey method. eon easy te) Em(0, 12,8) a ° olo 2 | lo o| |o ° e |olo} Jo > o| © Be ° ° 0 | m [ovov0| 01K |o000-| 0.1.80 |o00. clo T | —m, [o0001[ 0,20 )000_0|1,9,17,25|__oo1.| i m Joooro| ev Joooo|nezu2{ 100.4 | elo m_[ox000 ne ole nev [o_oor 2m loroor| irr | soon! 1 | Je m, }iov0i] sav [oroo. - ’ ° My _|11000] 8,24 |_1000) of bad a ™, (10101) 9,254 | 1004] - |2\s mu_|11003| stata [30-03 Sette etl rine pinta 4} om. Jornal ana5v|1_001 PaytptytesDeEVH ed ma |r014 24280 |rivo,| st +B 5] om ental sare [oa EET] antics the tollowing using Quine-Me Clusuey wae] Ty etheds maw [it ay FOF RY +2 m0,3,5,67 10,1819) +54, 15) [ARTO 2016-16, Marks 15] 1. FW,X,YZ)=E m0, 9, 5, 6,7, 10,12, 19)+2d(2, 8,18) Fret, we group the minterms according tothe numbers of 1. Scanned with CamScanner1 STS, No.of interme [Binary |[Mintorms] Binary M1-90 (ECICSTT:Sem-3) Digital System & Binary Numbers ‘Nolof [Minterms| Binary |Minterms] Binary] Minterm [Binary] 0 0000 00_0 Ts | @eell) Geel) 1 oo10 001, z | m [1000] se |i00_/ 89100 | 10. 2 | m, |ooi o_10 2 | m [oror] sor | 10 0/10,13,24,35] 11 , 0101] 2,10 | _o10 m, jo110[ 37 [oar my |1010| 5,7 |o1_a nn | 1200} 513” | 101 3 | dm, [i001] 6% | ora , forta] 113 | 110, m, |1101| 913 | 101 4 dm, [aria] tas7 | ait 13,157 | 11h m, | 1001{ 5,7 [ora my [1010] 9,7 | 1074 3 [om for] son | ror roi1| aot | 110 ti0[ aus fan raat] anise aaa rye | ia 2 Allthe terms which are unchecked are prime implicants ‘Now, we prepare prime implicant chart to determine essential prime implicant inas follows 7] 7 2._Then, we prepare the table of prime implicants. Minterms [Prime implicants || my mlm [miu] ia| midis Prime ‘Ano? 37 ° Minterm| implicant | m,|m, | m, | my | my ae ai 5 a2 lo ap | 8810.40 efe[e 2,10 ° ac_7 | totais lo 12,18 ©] — tereore, A,B,C, D)=AC+ ABs ABD ato To & Loge diasram wie x * ac " et DS Wry | 23,67 © ole I Gea Deore) XZ? |6,7, 15,166 ° of | B . > a or) FUN Y.Z= Wee XZ RZ 6 EWP = GETS] vse quine-ate Cluskey (QHD method 1° #1" Fig 1.32.1 following function ‘Qua TSS] Uso the Quine-Me Cluskey method toenerate theset of FU,B,CD) «2 m8, 7,8 9,10, 11,14 18) 5G prime implicants forthe following function: FETT CCD) m amie ene a Is) or4 ‘Also obtain ail minimal expressivny forthe fan Answer, 1 FIA,B,C,D)= 2 m(5,7,8,9,10, 11, 14,15) Scanned with CamScannerISIA Gee gp, igalbogeDesisa i ae ARTO, Se — 1 Grea, FALB,C.D)=E70, 1, 43.6, 7, apa ‘Na of] Minterms Binary pete Binary) Minter, Minter Fig 1a B (4eed pe i mF “aE | Minimize the folowing fenetion using Quine-te ; 000] a2 Ons |p pee 7 0001 | o4v 4.5.6.7 | 0) FULB.CD)=Em(02.36,7.89,10,19) foro LE [007], 165,7,15) 12 ‘ARTO 2073, Marks © *, a| 1.9 | oor Tm a == : or | es || = Liven, FA,B,C,D)=E710,2,3,6,7, 8,9, 10,18) ; nm, |1001] 4.6” | o1_0 Table 1341. am, |1o10[ 577 | 01-1 ‘Na of] Minteras| Bina S] morn] @zv | orr_ * torr} g1ev! 110 a] = [0000 fimo} ym | toa 1 | m, [oo10 4 mit] war | 101 m, | 1000 mee | aaa 2] m= | oon nas | lar m_{or10 m, [2001 1010 ont 1101 aE | | implicants 0.2.3,10 | o | Jo] 23.67 ololo| LI ae | lolo | 23 | BRAG Scanned with CamScannerLe : a SS cde ie iment corespending tye SRR Speck oak is foe! Boies ape my PABC.Di= BD+AC+ ABC Fig 1341. 916135 | sininiethe following function by tabular meted, {tsplement the result using NAND gate only. Flayz.ya) = Em, 48,8513, 14,15) 2.3, 11 19 i Vp-p 7 ° elo 5 olo ° wa | IAe o|olo Fe | aie © | Thus, seatial pric implicant are, Pues, 2 +7 608 AF E Implementation using NAND gates + oun astern binary pntrndinarl t Goat) altars ai 30 ; 1 [3 lee fe _ i 381 m_|tooe o18 100. eo 100 es Scanned with CamScanner‘Combinational Cireuta: Avalysie Procedure Design Procedure Binary Adder Subtractor, Decimal Adder A.Concept Outline: Part-1 2 B. Long and Medium Answer Type Questions. a (Binary Maliplier Magnitude Comperator Multiplexers 28 22 sven QA1GA tO 2-984 A.Concept Outline Part... B.Long and Medium Answer Type Questions. 21A@OCSIT Sem) 216. 21. 2-2A (ECICSAT-Sem-3) Combinational Logie PART-1 | Combinational Circuits Analysis Procedure, Design Procedure, = Binary Adder-Subtractor, Decimal Adder. CONCEPT OUTLINE : PART-1 Combinational cireuts It consists of input variables logic gates and output variable, The lgie gates accept signals fom the input variables and generate output signals. This process rforms binary information froathe given input data othe required output data, Hlalfadder: It needs twobinary inputs, augend and addond bits and twa binary ostputs, um and exer E 3 + Fulladder:t performs tho arithmetic sum ofthree input bits Tteonsists of thres inputs und tro outputs. ‘+ Malt subtractor: It is «combinational circuit that subtracts ‘ovo bits and produces their difference, I also has an output to specify if 1 has been borrowed. + Fulleubtractor It performs a subtraction between two bits, taking into account borrow of the lower significant stage. The tircult has thee inputs and two outputs. Eat Anus Type ad Medium Anewer Type Questions | jonal logic eireult with Its block ‘Combinational logic circuite consist ofan interconnection ofloge gates {nwhich the output at any time depends upon the eombination of input ‘Smale present at that instant only, and does not depend on any past Incombinational reat, the output does nt depen on the pat value of ‘npator output Hence combinational eit donot require any menar. sm tepute re] Combinational TEL" circuit [E> nowtpute rey Scanned with CamScannerDigital Logie Design 2SA(ECICST-Sema 3 Inacombinationa ireut, fora change in the input the output appean, immediately, except forthe propagation delay through circuit gates, 4. For m input variables, there are 2° possible combi input values. tions of binan, Que 22,_] Explain the analysis procedure for combinational logic ‘Answer 1, Theanalysisofa combinational circuits that we determine the functist that the circuit implements. In this analysis, the loge diagram is giver and culminates with aset of boolean function, a truth table or possi: ‘explanation of the circuit operation, 2. The important note thatthe analysis is to make is whether the giver circuit is combinational or sequential loge cireuit, The diagram oft ‘combinational logic circuit has logie gates with no feeluack paths « ‘memory elements io : oes LD D-_, . 7 @ o Fig, 22:1, (a) Example ofcombisntional logic circuit and (6) Nota combinational logic cnet, Feedback path Bootean expression from logie diagram : 5. Once the loge diagram i verified a. comb ‘un bain the bola fonction, Lotta gate outputs that area finetion of itary ‘funtion ofinpt wit atitrary eymtlt ‘Determine the boolean funetions for each gate output. = Label the gto that area fection o tat eae octon of fot variables and prevowl! Tartiese eget othe aritrary symbal Find the bclea fonetans inational cireuit, hen we |v. Byrepeatedsubstitution of previously de Ti*AB,T,=BC,Y=7, +7, =AB + B= Bu 0) PHA ECCSTT- Sem.) a [Eenenonefar Explain the design procedure for combinational logte circuits, ccilfcations of tho cirewits, determi of inputs and outputs and assign a aytibo to each Derive the truth table that defines tho required relations inputs and outs, 3. Obtain the simplified boolean functions foreach output ava function of ut variables, 4. Draw thelogidiagramand verify the eorrectnos of Une design usually or by simulation) Que 2A. ] Construct a BCD to excene:t code converter with a 4cbit adder, What must be done to change the eireuit to excess} to BCD [ARTO ROTTTe, Marka 10) on Design a combinational ciroult that converts code converter ? HED code to excess.3 code. (ARTO DO-IT, Marka Te) “Answer ‘Truth table: Taput BOD. Oaliyat excoswd code a;ete [po fw] ify] = ofofo;o | oj ofi|i ofofo/ i |ojifo]a ofe |i: | a] tie|f a efolas) 1 | a@ | a lits'| o ofirfo}o fofalil]d ofilto) 1 fa}ololo ofif1}o]if]ofo]i Of ttt] a [are] 0 a | rfofo}o}]alofir] gy stotlotiyartitole Scanned with CamScannerDigna age Desi 2A (ECCSTT Sem) Combinational Logie 3. To change the circuit to an excess-3 code to BCD exde, the aos cade thosld be provided as inp of combinational ireait and BCD nussber shouldbe generated at oot ‘QacES. | Design « combinational circuit that converts a bit oo oo or 10 ag of 1210 Gray code to a 3 bit binary sumber. Implement the cireuit with Lia “alias i Exclusive-OR gate al ll ee ! Teer] (Gray coe tohinary cade converter? Grayeode Binary ode rex c1e[o|e)] ala awe ort 10, lo ° o o ol} o aap AS ole o_qGied OF lee oes | ad ofir}aloli] of rfefofijala “ddd pieltlitils a rjifolile Lingard atitstitols =D y=@D+CD=CDs(C+Dr C+ BD+BCD =BiC+D)+BCD =51C+D)sBCsDr Piet Scanned with CamScannerRoaienes 2A ECICSIT-Sem.s, Fk as Logie diagram i. Using XOR gates: «, c & Using NAND gates: GE RVERGNCL OGL 0) FB +EBG,+666,+T65, Foy-CHyEo,-8 cag, Fig. 253 Que2s. | Describe half adder and full adder in brief. Implement the cireuit using logic gates. on Design a fall adder using two half adders, [ARTU 2015-16, Marks 75] Half adder: 1. The Block diagram of i lagram ofhalf adder i shown in Fig. 26.1 B i—=s Taitadier {_faraaiee [-——$ Pig 26 Hated) where, A and B are the in ae Carry respectively ut and § od C are the outputs sum and 28AECICSIT Sem) Combinational Logie 2 Thetruth table and K-map ofthe system are shown in Fig. 2.6.2 Taput [Output Fors 3 Porc Ayers ye} ao 1 4A oftii fo} dey) Lay iLife ls} Le Fig.203, 2. Using two-variable Knap, separately for tho sum and cre. S= AB+AB =AOB c=aB 4. Thecireuit canbe implemented using XOR gate. ay iSD-s LEpD-e ¥ig.2.63. Full adder 1. Fulladder is acireuit that performs the addition of three binary digits. It vhas three inputs A, B and C with two output S and C,, where C is the previous earry. Th block diagram is shown in Fig. 2.64 s °, Full Adder Fig. 20-4: Foll Adder, 2 there are three input variables the combinations are eight (2 = 8). [Now form the truth table of the full adder. Taputs ‘Outputs Ani] Bs [ aoe: | ease 0 {ofo ]o |o o fo] a tes | o | 1] o 1 | o 0 | 1g) sl <0. laa. 1 | o]o a [20 4 oe} o a a | a [eax [oe fea a jadi pee eed no Fore {ol Jo, {ay fo, Scanned with CamScannera) oe eat Fr aa aul $= ABC + ABC + ABC + ABC Som: oe = Abc + ABic + ABC + ABC = C(AB + Aliy+ G1AB + AB) (AB + iby +C'(AB + By aomac carry 1B + AC + BC SAB+CA +B) = ABSC(A+ BAS AB + B = ADs CIAB+ ABs Ais) = AB4 ABC +C(AB+ AB) = AB(L+C) 40 OB) = AB+CA®B) ter ‘Pie Nes. wo baer cea Sarr Har saee ‘Que277"] Describe a half subtractor with its logic diagram. ‘Anema 1.” Theblock diagram shown in Fig. 2.7.2, A "8g AOA UECICHITHem) Combinational Logie Tapata_[ Oaipate ea ee Ao | a co} ooo |_| o|_ {2 of] fa yo: fa LJ Lt 4 ifijolo DeATeAT=AOR —TyeKD 24, “The logical implementation using basielogie guten and XOR gate Quo 2B) | Design a full subtractor elreult with three Inputa x,y, 2B, and two outputs DIff und B..¢ The elrcult subtracts x ~~ By where, B,, Iv the Input borrow, Hi, {s the output borrow and ‘Ditt Inthe difference. ARTU 016-17, Marke 10] Tl 1. Tein combinational ireuit that porforma the pubteaction ofthree binary digit x Dit y By! Pull wbiractor Bea Waa, Fig. 28.1 shows the Bock diogram approach of fll subtracor. thas three inputs, and J, and bwo outputa Diff and, produced by subtraction of three inp it 8, For the formation of truth table, eight possible combinations of three Input variables with their outputeure required, $ 2 B Hatfeubtractor a etiam, 2 (ited at 088 een ‘and two outputs D ‘Aiton ad, awe oe aterm ef re. ty keeping in minal tpt alacant inmind that difference (outpost! waita- fA 6 B-The K-map and truth table are show Tapata Outputs 7 woconnmolt wuereccels pononce ole Scanned with CamScannerDigital Logic Design 1 6 PALACECICSIT-Sems.9 12 a (ECICSIT-Sem-S) Combinational Logie ‘Using th eancptof rap, reduce he truth able toafunction algebras Fig, 2.9.1 shows the interconnection of four full addersto provide abit or oolean). binary parallel adder. oth Ph ‘The augend bits ofA andthe added hits ofBare designated by subscript f o_o 4 to oe = ‘nuubers from right tolet, with subscript O denoting the low order bit. feo] T_T) strc cerieae anced in chain through the al adders The opt 4 carr) is denoted by C,, and output is Cy The output generates the 1 i) ele ed required sum its DifexYD gr VD, 970g! By Daa FB Dr *T Bla: Bra, By AL By A Fig 282. ti ok ery -Afl subtrctor can so be implemeniod using two half subtracton Com | ran ren |,_f run |= and an O1 yes, jase] eer Jadder|— Dit = sylh, 62y0, 63°96, 6273, = Bglay +94 B slay 449) 2x09) 4B 07) 9) OB, and Bn ey 4, 490, 4 B,O 49) Sx ABLE EEO YD ee Bayley py sxylexy oxyB eBay oxy) BBEBo 290,44 {e Oy? ax'y +B OyF Cy Que Ady | Describe carry look ahead adder. ‘Anewer 1 The addition of to binary numbersin parallel implies that ll the ite of the augend and addend are available for computation at the same time. 2. ‘The carry propagation timeis an important attribute ofthe adder because it limits the speed with which two numbers are added. 3. Anobvious solution isto increase the complexity ofthe equipment in ‘such away thatthe earry delay time is reduced. Halfadder Malt aubernctors REG Ss revious ea than one bit, Fry, in order to add binary ‘additional full adders must be ‘A4-at parallel adder cont constructed: = ing, 201. Tow four ade ns Hef addersae shows 4, Consider the cc of he fal adder shows in Fig. 2-10. 1f we define try inpu ofthe next blgher-onder gg ee cascade, ie, the twonew binary variables Scanned with CamScannerQASA(ECICSIT-Sey Digtallape ese eds ‘gum and carry can respect 5, P86. Cia lybe expressed a3 1% Theoutpst 20,+PC, and dar rearessftbw input carry ©, scaledacarry rope eau it determines wheter acary into stage wil propagate! sages y= input cary C= Oy PCy ©.96,+PC,=6,+P(G,+P,C) =6,+P.0,+P PC, C.90,4PC,=6,+P.6,+P.PG,+ PPG Wis2] Describe acireltof bit binary addensubtractor # overflow detection, on Relic a drei sublenton with besa els of performing addition * The addton and subtraction opera sith one common binary ade by eke into cae ‘ach ill adder» MY 88d by including an exclusive OR gate ® 2 Adtitaddersbtractor ie ‘Meontols the operation, tS Sto*RIn Fg. 211.1, The mode SALA ECKSIT Sem 3) Combinational Logie AB Fig SALA ENE asueeAtee Ge eto detection, 8 When M=0, thecireltis an akier, and when M = I. the cireuitocames a sabtractor, each exclusive OR gate receives input M and ane of the inputs of. ‘When M = 0, we have B@ 08, The fall adders receive the value of, the input carry is and the eieait performs. ples B. When Ma 1, we Rave B 2 1.= Band Cy= 1. The B i conplementad anda 1is added through the inpat ean. ‘The cnet perfores the operation A plasthe complement ofB,(The ‘exchusine OR with output V infor detecting an overflow, 2. When two masters with # digits each are add andthe sum is a number cccupying = + 1 8eiee we say that an overflow oocarre & Overflow isa problem indigtal computers tecanee the mumter of Kits ‘hatheld the sumberis Site and a result that contains + UNts annot feacummadatedbyan et word, REE | Discuss BCD adder with its block diagram, AL. BDadieriscireait that adds two BCD dicts in paral and pnatares a ‘sum digit which is also BD, BCD murabers use 20 sym (gro of ‘Ths 06U0 to IOUT ABCD adercirait musthe able to dothe Allowing antitisabown in Rg. 2222, 2 Addtwo £8 BCD nemthes using straight nary addition, A Ue titeom sequal mer essthang the somisavald BCD number and po ceeretion i eed, A. Wtbe tbitsem is eater han Sorifacary is fom he mam, the sum is arab BOD number, Them te Set § MIO, sgl DS aided tthe sum to pratice the a ROD EN + ts are all poe Scanned with CamScanner215A ECICSAT-Sema, Digital Logie Desun ‘ddend BCD digi) Augend CD digit) syatier’ = bo Carry in ie Byatt uipat any ot ee 1 CuK 4 ty 044 Dy 2q ° ‘bicbinury adder THF 54858; (Wi Ba. Bleek dara of» BOD wader} Binary Sum [BOD Bum Decimal PA CC ofo fT ofolofolo ° o} 1] olofolola 1 alo] olololi|o 2 yh) oleloji) + 3 olo} ofolsfo| o 4 ofa} ofalalols 5 rlo} ololili|o 6 tla} ofolalr| $ o}o| olilololo o}1] ofifolol¢ 1/0) 1Jolololo Pee a] 61] @. 10: |, Q02.18;] Discuss excen udder with ita block dlageam. [Amwer 1. Excean code obtined by: ‘excomsl code of 0011. 2 Theexcons-d adser performs the adi {allowing step ae followed to perfor, ene 8 nuber, TH iding, 3,8 YCD code, For example, tht ZAGA(ECICSIT-Sem-3) Combinational Logic By ByByBy Ay AgAy Ay 1 “| [7 Lit sine ater 0 2Caa0 Pig- 2.18.1. 4bit excess adder.” i. Add two excess-3 number. Ifthe above sura produces acarry, ald 3 (0011)to the sum of two digits [the above sum (step 1) does not produce a carry, subtract 3 from the ‘above sum (or) add 13 to the sum of two digits. PART-2] - Binary Multiplier, Magnitude Comparator, Multiplexers, Demultiplezers, Decoders, Encoters, CONCEPT OUTLINE : PART-2 + Binary multiplier:Itis a combinational circuit which performs the multiplication of binary numbers in the same way as ‘multiplication of decimal nurabers. + Magnitude comparator : It is a combinational cireut that ‘compares two nurabirsA and B and determines their relative ‘magnitudes. The outcome ofthe comparisons specified by three binary variables that indicate whether A>B, A= Bora BorA Bye AD) + AD + 85 ABL+ ABS, cis Ail +s AiB, + AB +A ADL. ‘Te logical plementation isshown in Fig, 2.17. Scanned with CamScannerpamm o- 21AECICSAT-Sem Digital Logic Design = 2) 9 90. A (RCICSIT-Sem-9) Combinational Logic T)°]o|? 7] ° ° r}o}a]|o o | 2 ° rfofa]}a o | o 1 tt r[afo| eo 1 | ad] fe rfijo[o 1] 0 ° r}faijalo 1 | 0 ° aa rfifilo o | 4 ° a LH MA BB, ForA=B. By ay MAX! 9 or 110 AWAQ\_go__ on __t0 o ofo lo] mm@[olo]e ” til a ofofe] alo ° By. 4A > BY i J 7 sf oy [o ule ° (a=) wl Llfe Jo} wf ololo \a sibgulde, erparier sing logis gates. REGIE] stem a combina BP on ity, EERIE pies acento chet ht conpare tno 2 aaNebe 01 yy a0 [NOR gates nly to lmplement your amen one NAND sates only oF wo Hh (ARTUGOIS-Ta; Mark 05) af of «iJ nf efofo Stern ete Fi °totoTs asa] ace olf ofols ° irierBi6.| oe t geld 5 (rie 2 ofelil? o | 3 1 (> B= ApliBs + AB, + Araby ofalol 2 oF |g ' A= B= AyAoBiliy+ AaB By + Ar AaB By + AvAyB By Se ees 0 ° i ‘= A,B, Hpbi + AgBo)+ AD (AaB + Aa) ae : 1 ° = (Ag OBXA, 08) al eetlee le a 0 2 cB) = AyAoBy + hobby + AB ° ° i 1 mtto|io Pe Scanned with CamScannerBSBA BOLSAT Sen, SS 2-24 A RCESTTSem-) “Answer Implementation of fall adder cireuit using 4x 1 MUX: Canora fren of sam and earry for full adder Shitty 2.4, N= BGA + BCA + BCA + BCA = BCA+ BCA + BCA+ BCA Beas BCA+ BC Carry = m8 5, e [Ole] s j—} 1, MUX ste Ly @ @ Fig. 218.2. ‘For carry: Que2.19, | What is the role of multiplexer in the digital electro | wth Explain the logic how it selects a one input among several inpub Lau slo = ony 2 Amultiplexer MUM is combinational iret that selects one in gutof several inputs and directs ittoa single output. TERE npr selections controlled by a set ofselect inputs QUERBH] Implement the function : Sintering eT latina FtA,B,0)= ABC ARC + ABC+ ABC = ‘Using 4: 1 multiplexer using B and C variables to the selection line et ARTO ROITa Marke an tod 5 ED] aes ‘Anewer | 1. Given, RA,B,C)= ABC + ABC + ABC + ABC S58 TE 2 mplementation eng 41 MUX, A,B, C)=2m(1,2,4,0) cmt Mux 7 a NIMS geayggy OM: TMUX toot] Pa eTe] 4 For selecting one input out en bey x Te [Olole a muinitheen ‘pats, sot afm select input Tipriea datasource tthe eect gpa, one uth! OMT AN A * Purpose Emenee Anetable np Dis un for casead®——mulpleser a & Neareut dinrame org NUTTY active reas Tesible 41 data lt at “st multiplesor as show"! GEERT] construct a 16-1 multiplexer with two 8x Land one 2 1 multiplexer. Use block diagrams. Tmplesnent a ‘Plomenta full adder cireuit using 4x11 multiples Scanned with CamScanner‘Aareerc] 2 Wehavetodesign it sing 2-25 ECICSIT Seq {following boolean function using 4" eee ARTO BOIL I6;Marksl 2-28 A ECICSAT-Sera-3) Connbiastionas its L_ Logic diagram is shown in Fig. 223-4 c I aad MUX ty ke (eg 228-1) A,B, C.D) GasFEE] Design the following boolean function using the multiplexer: (AKTU S012 16, Marks 05) FUA,B,C,D)=£m(0, 3,5, 6,8, 9,14, 15). Aaewer FA, B,C,D) (0,3, 5,6, 8,9, 14, 15) A DAD; [D2 [Ps] Ps] Ds [D.| Ps AOL: Oo- L- Given, F(A, B,C, D)=Em(0,1, 8,4 8,9, 15) Joo" [2] ale) ‘aultplerer, so we can use two var oR: A,B) forsee ines and implement can TAO tation table sas follows: Goimptementation table (b) Multiplexer implementation tet |e Ta Figa2er a 2lololo[s RaSABEL] Write a ort note on decoder. 21 Olsl@ [as ale nm o s ” Mw L Adecoder is a combinational circuit that converts binary information COMER ETC) poe spit ine toamaximum of unique output lines. Eola le 2. If the n-bit coded information has unused combinations, the decoder Ton Bree. may have fewer than 2 outputs. be Dro come 3. The decoders presented here are called n to m line decoders, where he Ds t26 = CD mi2- Their purpose is to generate the 2 (or fewer) minterms of n input variables. Scanned with CamScannerDigital Logie Design 2TA(ECICSIT Sem. Dinital Vor Devin 1 input lines a2 montpat lines ecenes| 2 maa Enable ig: 8.25.1, Blak dagen Ow eer 2 to binary decoder Fig. 225.2 shownthe 210 Adecuder. Here? represent the input lines seg ‘A representa output lines, Fig. 225.2 shows the truth table for, Fig!8381Tispletsoaiua opt ghea . 2tn Adeeoder. Iensble 2) ia 1,one and only oneof the outputs ¥, ta, ofthe Fines Bésleaa Rseioa wag BE ARC) nen ‘WaeEaT] Drow the loi diagram of «wo tofu ine deren a Re using NOR enter oly. RT RET MST ots AB eaable on : Jogran ft din desde wien eae ola lx input using only NOR gates. ie Ls] . Zz teh : ‘rath tables 1jijo a Output itp ¥ yy ie bs 0 0 oO 4 steals QieazET] Using ign the alert combinational elreul ing a 2 2 fomblnalona crult dtined bythe following tee beste Myadipe 425, Pyasye sy, Ryastye ony ([AuerU pore r6; marks 19] Yet un considers to 8 ine decoder. The in thee functions co implementation of the € careninctlon# using 3 to line decoder anda few OR gate are shO™ YoetA+B EY = ABE ¥ietAe B's BY = ABE yet BEY = ADE get's B+ Ey = ABE pmezenr Design a full subtractor elreuit with » decoder and two PAT BORIS, Marka 10] Byaxye! esr arye' sly sy) 92 392 439/21 Em(2,7, 5) Fraw't ty'anyy su4xy,2 2 2y't ty8' +9 «E12, 4,6) ya xy? eryaxy sayieeey one A HY +E +92 = Em(0,6,7) Ee Scanned with CamScannerDigital ogi Des 280A (ECICSITT-Sem-3) Contin Lai isa mec __Cronnonntoi Taker sing dvd: enep silicon: Output eD_ La cD be aa Wen, ot r ® ° ° ° ° : : : ut — Save % ‘REERE Rilvawaieuig awaccaie BERT] Deen a BOD to Taegmene decoder. Assume psi! ‘otic, minimize the fonction, — [ARTO 201415) Marke +BG+BC+CD 2 The unused BCD ees place x (don't care eongar® 1010, Saito 2H, Top, ‘theeg 1200, 13, corre Scanned with CamScannera 231A EOCSMTSem; 2-92 AECCSTT Sema national Lage Dial oxi Trakdngramof BCDieTacgment play deco, Implementation of given function uslog3 «8 decors Fig 2.2dhonthele dag acm eve tm, ae) er a) Fame Ema eh a a FAT.C) «2 m0 1.9.6.8) © (reaana,, ‘RseHIT] What do you mean by encoder ? Impl following functions using :8 decoder. FYA,B, C= m0,1,3,5,6) (AB, O mE m0,2.4,7) Encoder: the inverse operation of a decoder, It is a in an encoder, the number of outputs is less than - wa ie 2 Encoder "Fie aabay QueRST, | What is priority encoder ? Explain with 4 table example. »,| D, any Decoder Pal »,| D,| YAA.,C1=2 0,2, 4,7) Fig 2902) help of Priority encoder In priority encoder Ito oF more inputs nre equal {a Lat the same timo, the input having highest priority willbe considered. Example: Four inputs Dy, Dy, Dy D, where D, has highest priority and Dy has lowest pronty Yo, ¥, binary output VE validity of output “able 2d Truth able for dit cori encoer Taput Output DP mm | % |v o}o}ofolx |x |o of ofo}o jo]. xf} a}oofoafo fafa ef ef afolta fofa Pe ee irs sad Scanned with CamScannerSequential Logic and its Applications wwnmnee (BZA 80 B-1GA) ‘Storage Elements Latches and Flip-Flops Characteristic Equations of Flip-Flops Flip-Flop Conversion A. Concept Outline PAP oer, vnnnnne SBA B. Long and Medium Answer Type Questiona. 2A Parte. (3-194 to 2-374) ‘Shift Registers E Ripple Counters ‘Synchronous Counters Other Counters : Johnson and Ring Counter A. Concept Outline : Part 2 voces B.Long and Medium Answer Type Questions S49” 3-20a SAA (CICSIY Sem) Ja Scanned with CamScannerSAA ECISITSem-) ‘sequential Loge & ts Application ' 1 ip Flops, Characteristic Base Blements : Latches and Flip-Flops, i oa Emp Pane pen Concern, | GONGEPT OUTLINE : PART-1 [Seen ciel cenit of conbiatoal eat to Seen acces frm afedbac pa, 2 Diesen eens hk operate ih sgl levels et uum ert lthes Latchet sr et este ged Sees. + Mplope! Surge dentate contoed by ack {rw ot ts fipdoe is inary storage iqrccpectsongone i finn, ip Oop re irewards + Gheetrat cqetins of fipsopes 1. SROip-top: HERE tannic. TT | wwe 3 30 ncn by ergs lent place Describe the operation of SR latch. sera Tanewer Sat dred yan Latches: " long as power ean Srna Peri deter ote ee a Lendl der mage st roe i ih, ta ee bs are fot acronaue ees ota binary information and for et, they ae not practical toes adore aca rrethebuling bcs eee iets Beco Digital Logie Design 2 Thelatch hast useful states, When output Q= Land @ SUA QCICSIT-Sem-B) SR latch: 1. The SR lateh is a cireut with two cross-coupled NOR gate or tw ‘coupled NAND gates, snd to ints labeled S for et wn fore ‘The SRlatch constructed with to cross-coupled NOR gate isshovn it Fig 311 the hte sin tho vent ata, {s said ta bein the set state When @ = Oand Q = 3 Outputs Qand Q’are normally the complement of each other. However ‘when both inputs are equal to 1 at the came time, a eoition in which both outputs ae equal to 0 (rather than bo mutually complementary) 4. Ifboth inputs are then switehed to 0 simltancousy, the devico will coter an unpredictable or undefined stato or a metastable state CConsequentlyn practical applications, setting input Yi obi. 1 Ln ot Lm aq 10 1 O(aiter 8 = o1 © Leaner 8 « 8.O«lorbiddent aelion table =o) Qaeda) ] Explain the mechaniam that afip-flop holds a onebit of Information. Describe the operation and working of the following, flip-flops: 1” SR, iL JK, on ‘What is fip-Nop ? Draw the logic diagram and givethe characteristic table of JK Aip-foy iT and v.D. "Flip-flops are binary cells capable of storing one bit of information, A Aignop creat has two outputs, one forthe normal value and one for the complement value ofthe bt stored init. A. SRnip-op: LL. The circuit diagram and truth table of SR flip-flop are shown in Fig. 9 2.1, This is also knoven as clocked set-reeet flip-op. 2.” The circuit functions when clock pulse is otherwise it wll hhold its output values (Qand @). Scanned with CamScannerDistal Levies SSA (ECCT Sem) a Master Slave JE ip op. 1h Baestrisrere ip. ope BL Tfip-Mop: | opof[x|@ ‘The T Aip-p is also known by the name of togxling Hip-op ofr po} a aerator ip Bop along ith thetruth ables shown a Fig. 923. t}o}i |e eli bi Le | « J etevatiay aC iF a 4 5 ojyojo (Fig: 32 Si Pup-ep:, ojala cK 4 rom thetruth-t i 1 i = 4. Meant chev fom the trthablethatif'S = R= Oand CLK actin ° a theme ouput ane previous. Lilisto . aT 4 US-Oand = he pop wil bein reset stage, output Q wil Figi833) G et nd 1 when ite ing fipop means the output topes between O a 5 UsetmdRs0tetipwieintaascevospstQwiltet —™ Tiptie Ta tat Guia Utd» = 18K tio he ronaing 6, IS=1and R= 1then output isinvalidie., Qand Q both will attic ‘fip-Mopis known as 7 ip-Nop. lie which cotradicsthe assumption ofcomplementary outputs, %+ Dfip flop: C i JKAip-op: 1 Danis no dy in Sopbcnaeovist e 1 The circuit diagram and truth table of JK Aipfop are shown it Rheiapot afer aclock pulse ne 2 In JK flip-flop when J =K then the ‘resulting flip-flop acts os D ) TET & [Reon ‘top dingram along with trthtabeisshown ns 3.24 TF oO] 0] 0 | yNochange 2 tH Meee he eles | » iso el Tpo Te pee i aux. oft [at | dase ° el 8 ax | Src G Girfo]i| i | pee - Blea i a pep = ij 11a [STS | prose pres] Ne sa30K tam dana delay device oF a3 latch to store Lit of binary ‘The prvi proble that = = isiavalid 2 igre overcome by JK fipfop. 18 0validin SR flip Nop has bee? mation. & Segmasen : 7] write sence between latches and flip-flops. JK theupaeey eae OSA REE aT] wate ene at Previous outputs O and Difite, — 4 Dacndion J «Kt a ‘Anewer Caton J = R= 1 causes a mj = ae freon Coir ds end geek gm es raearowel [BIN [ tale ion : se applied at CLS that ‘Storage clements that are fares 1 | Strege ee al leve controlled by clock transitions. Sates in series. The output wil eet eeey through two NAND operate withsign a ; Ae thend CLK thong eae 2 | Teisleve triepered <—- Besngs Se Meearetwo methods any tition i race TL) Tere ono lock pul. “There is clock pl Scanned with CamScannersequential Lope it Application SATACECICSAT Sem) wecsrt sen == : Digital Logic Design a OTT ry oe ‘Truth table of D Aip-op. is @ @ of SR Mip-flopand ‘Tae 3H obtain te characteristic equa tip ep. awe ‘Characterati equation: 1. The algebra dJescption the net tat (QF fips scaled Raikceuemainastetiptep pression is etily obtained by constructing the K-map tho present tate and ip ey TeeSRfipdophaswoinpt Rand. Thebes SR flip-flop are shown in Fig. 3.4.1, Tee ana Fmerte “Trt blot Si top Hite Ra ate Rls i a ss oft ; lit 1 re 2 10 aft 8 7 fel : ; ‘Thecharae erat equation of SR ip. fopig Guay= $+ RQ, Provont mate oe ‘The characteristic equation of 2 plop Quan P GueSA | Otain the characteriatle ea Aip-op. Kanwar FordKMip-top: ‘The characteristic equation of J lip flop inobtained hy using variaben Tap the troth table nnd Kemap for JK flip-flop are shown in Fig 35.1. ‘ruth table of JK Hipp, (ion of JK fip-flop and T Flipfiop | Present [ Next | inputs | state | sate Te) a [en ope] o | ° ofe) 1 ]a Beefs fan 0-0]. 10 ofil 1 fo teed id rfo}oa | a peleseleco | 0 ajij| rte ie: 3.5.1,) ‘The characteristic equation ofJK ip opi: Q.41= JG, + RQ, For Ffip-lop: the rath able snd K-map for T-pop are shown inFig 382, Scanned with CamScannerSHA (ECICSITSem) Sequential Logie & 8-94 ECICSIT-Sem-3) ‘rth tbo Apo. [ Fiip.top | Prevent | Next pute | state | sate : : Remimeonn Nvo 1 ° 0] o ° va o} J 1 oft i ite lol | Aig 352. ‘Tho characteritic equation o pops Que TAHT, 1 aa ow does ad fp-lop difer from an SR Mip-op ini operation ? What is its advantages over an SR Mip-flop ? What is Unitaton How lait emoved? & Working operation : When J= 1and K'= 0, the Master sets on the postive clock. The high Y output of the Master drives the $ input of the Slave. Thus when negative clock rises the Slave fip-fop sets When J = and K'=1, the master resets on the positive clock. The high F output of the Master goes to R input of the Slave. Therefore at negative clock, Slave rest ala on Wen J=1 and X= 1 Master topes on the postive cok an Save lain Master Slave Nip Atop, Whats toggles on the negative clock. At tis instant, feedback inputs to socal lininated tr amen sareene condition How Meter fipop ae complemeated bt ain egative alee ack = lave JE Miptlop t pale, Master fipiop is inactive This prevent race around condition. wer aEaed c the excitation table of SR, JK, Tand D Mip-flops. IK Alp.Nop und SR Mip-nop :Reter 2 Ques] Ovtain ip flops = *Q.82,Page3-84, Units — ——_ 1, Raseaound contin: mee A race around conditions said to exist i he ct bevtteas htises? Cia when enitenitsidtocitinananrchronoussequntid Techarcertitalerareanalowe: | oponstoachange nanan wake Yaiales change value SA Mpa ip-flop: 2 When unequal delays are enon = a ee 7) /)@. [en ‘state variables to change in an ang erat BMition may cause the >To] oT oO apo * Kecmaragase nner Tertitl (sitio: ‘Alip-Nop is net thed = K= 1, i ° ofilo}jo {_hfepislese than pulsewidth ofeack snd PeAtion delay ot Bi tiiit ole ole . Jeket atada aileo |,o | 3 = burst ryofaja r}ofala Elimination of race ant, r]}afo]« ae la |eor lea Rip-fop: ‘round condition using MasterSlave JE Teletebe rtililo 1 The Mastenst oe fh Master ants cN® Setubination cons: TMipflop: D8ipfop: a tna MaUSLSE App aca stage SESAME Bip top a5 * T [| [ee P| | Quy averting ante tv : te oS othe ke, the Seer ae tothe presence ne epoye erlecelas carting tte Se lob-[ a irl? ive whereas when chek Master is acti a aster isinactive ACL way Se a tbe Slave aie |eo telat Scanned with CamScannerar ‘Sequential Logie & its Ap, AOA(ECRSTTS sO nasfollong, SDititel Logic Design Tre earan tae oflltbe above props isa follows exit SALA (ECICSAT-Sem-3) 7] ¥ on [orca | net ail D Explain race around condition and its remedy in brief. Real paisiea Ea TPO |e | a pyr en to SR Miptop. ARTU2OTE15; Marks 0@ ° apo} al x] a lty $ Ppa | tt a] pers 1 : x{o | <1 0] 0 ]{ Race around condition: Refer @.3.6, Page 3-88, Units 1 JK Hip-Nop with preset and clear: in how will you convert SR flip-flop into p gl. Preset and elear inputs are ealled neynchronovsor direct inputs, These QeeRARY] Bevan bow will ye 1° inputs are connected direty into the latch portion ofthe fips that ‘flop? they override the effect ofthe synchronous inputs JX and loc (CLK. awe ret ‘SR Alip op to fipop: TruthtabletoeDipfoy Excitation table for SR peop [Present | Nest | Flip-top Tapate [States tate | state | Inpate pe yen)| fealent s TR) >’ | 0 | o 0 | o}o] xi 1 }oosfea ota lsaaleg ofa fo 1 fo fo }a tela ue a] eae : ‘ig: 0c ip-nop wih ear aaa pret) Courerson taba: Knap simplification: 9. yf presot and clear inputs are 1, cireuit operates as JK flip op. If fnpsts[Preeeni] Next [Flipfigp] gq, FOrR oq ForS preset = Oand clear= 1, output of NAND gate wil certainly be 1 ea aiste fe tapute | DN Ot NY 91s onsequently all the three inputs of NAND gate 2 will be 1 which will Seif Renn a q make Q = 0, Hence, preset = 0 sets the Mip lop. Preset i active low s{[o¢ fe : A ‘Signal. Similarly, low (0) on the clear input resets the Nip-lop making r}o 3 rtoly 4 Qa Leta 1 ° TMlip-Mop to SR Mip-Nop: Step 1: Truth tuble for SR flip Mop: sof Ren 7 fo [@ o [4 o 1 po z Ber [=a x Scanned with CamScannerS2A(ECICSIT Sem) sequential Logie &its App ale for i Digital Logie Design, SABA(ECCSIT-Sem-3) 1. PAip-op is obtained by shorting J and K terminal with the same input. 2 _Conversion table for the given JK Mip-lop into Tis Nip opis Tnput | Present state | Next state | Flip Mopinpuay r a Qa 4K ° ° ° ° % Fiptopiag | ° : 1 x Jo : 3 1 x ar & ont 1 1 ° x 1 o 2 . 0 o 1 9 0 o u 0 0 0 1 o 0 1 1 7 i 1 o 2 ' 5 : 0 1 ; : 1 1 o 7 a rit ‘ : x TF ToT erie. B.001, ‘K-map simplification : i BQ, — s\\‘oo__01_1_10. a ta em a1 cux-4 2 oi Ka Fig. 3.102.) D4 — sp qT Pipa Q cP fon ie. $512) ‘Que S.A] Construct a JK Mlip-lop, using a D flip-lop, a two to four one line multiplexer and an inverter. TARTU 2016-17, Marka 10) {310 | Drew Jkt pana writethe characteristic ts? ‘characteristic equation for it. Explain he Thip.Nop? Answer JEM RTO DIETS, a fetQ.8.2, Page 3 3A, Unit-3 | Note : Since a two to four one line multiplexer isnot possible hence the solutions given by assuming our to one line multiplexer. 1, The ireuitdingratn of JK flip-flop constructed with aD ip-lop and sates is showa in Fig, 3.11.1 2 ‘The Jinput sets the flip op to 1, the K input resets it to O, and when both inputs are enabled, the output is complemented. When J=0,K=0,D=Q=Q, 4. When =0, K= 1, Olixeis selected, the output @= 0. Scanned with CamScannerDigital Logie Design S16 A (ECICSAT-Sem-3) 3, K-map simpliiation: or Fors. Cele KQ, Soo or nto Koo ort. ° APLI ° Fig. 3122 ig. 28! 4. Theobtained boolean expression: ‘S= J, and R=KQ, Waco 1k — a ‘op. ‘GiTETE convert she Se npfon to K * eS 7 eLk peo, ei x ne tracted by using SR flip-flop. { Ce eee Tape eatin able of SR ip sop — Se Tae 3 ate _| state Fiabste:| Qaesils] Construct aD Nip-op using JK Mp-Nop. aoa 5 afta TLS aor] one 2 | 2 | 1 theDiiptop isconstructd using JK Ap fop. ofa afe Given ip op ie JK fip-Aopand required Mip-op is DNipsNop |i rath Excitation table of JK pop fi Tieter [Pree [Nel] [Feast | Pieter Tinputa”|"atates | etate,| [staat | ate | oput ifs : Z i * 2. Form the conversion table a EAS Sees Suse Ee: 3 ° | 8 ye | x Required Nip-fop ® a eel * Fie Pret al |e sal ee eat i eeslle sali eal Mua 5 oy] 3 g ¢ x | 0 EE [en a ape o |: s |e TIRED [leven tip 8 a | [ilipstop iapats | Present state [ Next state] Fllp-op input ii ° ¢ ee ee ila a 1 a ° 2 t* rfoa ‘ Cia ° ele a] i® | a4 1 o 1 1 i" Pa bee La ee 1 ole | Scanned with CamScannerDigital Lose Dosisn SUTA(ECRSTESems) i] 4. Legiedingram: Rese Que STE] What is ASM chart ? Eeplaia. Draw the state diagram, state table and ASM chart fora D Mip-top. (ARTUSOISTG Naas iO arr ‘AS Mchart i composed ofthres hasslamente: State oe, decision bos sedcoacionaltoe State bor The atthe stem sinicate bya ates. Theshape GETTE convent gen ipo oT Hip om ofthe tatetoeis a netansie oe (General deeciption entry m= : pence] mevilh is eoastructed by using D flip-flop. 2 mere Excitation table of D flip-Bop Register operation or TrahsslecT Sipe eoitecltin Fist [recat [Nat] [Tete | Present] Nos t mur Sor | Pcie [ate | |_ inputs | state | sii a i Qe [Rao Qe | en | PF Fig K18L 7 To |e ° T [a Decsionbos:Trisa diamond shapedtac used tadeerite thee of o a 1 o a + an input on the control subsystem. + | oft 1 o fe ae ij ito t ae 2. From ibeconersn tele and Knap simplification. : ForD x st 1 sit path 2 Esme conditional bax Iisa uniqes Bor of ASM chart. The area shane of Gonasional bas sw im Big. 3.10. The round corners {terentate tom thestatebae Scanned with CamScannersequential Logie rt se) al Logi HIsaece’ i Digital Logie Design 319A (ECICSIT-Sem-3) ter ASM chart: eae Ext Fig. 3183- 0 state table for easy unders parm aS cat fist we OTE stat andy Toaertion nthe given cL Da Ql > x 7 &y ax Fig. AEA State table: Pesaran ale epee paces — tale [0 Fat |S S[ parte) RS Qi ].Mo | Ries] Que [1% | Arn] Qos |Z ‘Shift Register, Ripple Counter, Synchronous Soto yi yi} it} tye Counter, Other Counters :dohnson and Ring Counter. ofifojafayrfaula es t/ofo}o}ofa] ofa [Concert OUTLINE: Ts _ ror oy ered of ola CONCEPT GUTLINE : PART-2 + Shift registers :The binary data ina register can be moved ‘State diagram ‘within the register from one fip-lop to the other or outside it ‘with application of lock pulses. The registers that allow such data transfers are called shift registers. 1m of u shift register 1. Serial in serial out (SISO) 2. Serial in parallel out (SIPO) 8. Parallel in serial out (PISO) ‘4 ParalleLin parallel out (PIPO) + Ripple counter (asynchronous counter) : For these Counters the external clock signal is applied to one ip-lop and then output of preceding flip-flops is connected to the clock of next flip-flop. + Synchronous counter : In these counters all the Rip-lops receive the external clock pulse simultaneously. Scanned with CamScannersequential Logit Sits Applica, you menn bys a ‘ anor the cassiicat prensa ei isnt artnet a areer:Arepserisasuenil Hie STSUY swith. functions: sh rete ‘Classification of shift 2 ; ‘Genifiation based onthe dretin of data movement: i Shite register. 4 Shiftrightrexiter i Bidirectional shift registers. Classifeation based on the mode of input and output Serial in serial out shift register (SISO) ‘i Serialin peralel out shift register (SIPO) ‘i Parllelin eral out shift register (PISO) Parallel in parallel out shift register (PIPO) ‘Universal shit register. on of shift registers, fe ime called shift registers, ro, ‘TAIT Write ashort note on different types of shift registe [Raswer 1 2 ‘Serial in serial out shift register (SISO) : ‘The seralin serial out shift register accepts the data serially ona? input ine, Kaleo produces the stored information on its output in serial foro? ‘can shift the data from ef side or right side. Based on the shiing of data the register iscalled shift left or: 2 sine "register. Fig. 3.17.1 shows the block diagram of serial in serial o™ register ($180) Digital Logie Design S-21A(BCICSIT-Sem3) ee (a) Shift right () Shift left . Pig. S171. bit tit Svat out shit resister Shift right register 1. _Inthis ester while secepting data serially, the groupof bias sited ‘towards the right side, ae 2 Hence the serial data is entered onto the left side of register and it leaves from the right side serially. Fig. 8.17.2 showsthe logicireuit for ‘ad-bit shift right register. [Ps a By @}—fP. by, Ds a ® © ® ® ig 3172 Vagina rw it HN Shift ett register: 1. Thogroup oie is sifted towards tho eft sid in serial form. Hence the Serial date is entered fom right and the Binary data at the ootputis taken from the Tet mos Hipp. 2 Fig. 8.17.9 shows the logiecireit fora bit shi let register. FRO FFs FF) [@s Da} 422 Ds}—f%_Dy ® © ® ‘Fig: 317.91 Lowe dee ea ee eA FER 3. Tho binary data is entered into right most Mip-Nop (FF) and output is taken from the left most ip-op (FF,)in serial form. Serial in parallel out shift registe 1. This is one type of shift register form and oxtpat isin parallel form. 2 Hence it is necessary tohave all the databits available as outputs tthe same time. 8. This type of shift register operation is same as the serial in serial out shit riser. 44. Thedifference between serial out and parallel out shift registers is the way in which the data bits are taken out ofthe register. Scanned with CamScannersequential Lorie & its APpticy = sara cecrost pallout if oyster, pe tit A Fig. ntTshonsne cout sesilin i parallel ot ARAM oj cocktail eit, pA a Q », ria ut sift rine -amofaparalleLin serial out shit reg, tered in parallel, -e, simultaneously, ean on Liat ik ra , In this typo, the bits are ent Digital Logie Design 3.29 A (ECICST-Sem-2) A crc8T Sem-3) Que 48;] With the help of diagram, explain the operation of [ATU 2O1E15, Marks 06 register, (ARTU 901516) MarkeT0] mboth the directions shift right called asa universal shift register. ‘This shift registers capable of performing the fallowing operations: i. Parallel loading (parallel input parallel output) fi Loft shitting. fil Right shifting ‘The block diagram of a 4-bit universal shift register is shown in Fig. 9.18.1. It consists of four D ip-Nop and four 41 multiplexers universal shift register. oR Draw and explain 4-bit universal shift register that can shift the d aswell as loa it parallely iti, 3 ‘inaparalll ine 4 utplexershave wr common select ines, and S,Inpat Ukr resp pon on ts ouput in seal form, iinover elected whew Sec OD nate hee a. ttyrtucatho stored information on ts ou pore i 89 = 00, opt 5. Theselectio inputs (SS) control the made ofperationaf th ester r according tothe function table shown intable 3 181 + seriat out Paral output (gis: Paranoia al ait rowiten) 5 Ay a allel in parallel out shift register : - 7, 7 9) | 1. Athodateappenrsinultancousy alongwith allthe Mip-opinpsts Clear-—d FFs r r 3 oof r D nlp 1 oe sdewinhaneo ita ntinraetiens Ba cay Parallel outputs: Sif ea ee Dap ete ay atin | — right for shift || |e te te aun fe |r é b % . Palliat - ‘HAR St Loge agra fe bi parallel in parallel But shin Scanned with CamScannersabe reed sie sah onthe vats tenn roam ip hope TS Career ce aight se Act operation wat 1 Ne ; sam TP a rr gan seni, wt the ober 8 a nce np each main int wine ep Tala ith, poems eH nario nthe poral npn en 510 the es ceamultancoaly during the next lg. Tae] Wat are t applications of shift resister ? ane) Shit cepleteraplications 1 Time delays The eri out shi regiter canbe used to provideate daly ram ipo outpt that in fancton of both the aunts: toes athe reer andthe lok reeney. 1k Bera toparalel data converter Sera data transmission rome digital tem to anather in commonly sed ta reduce the numb ‘riresinthe transmis line. We enn convert the received serial {opera datay wing seri in parallel out shi register. ‘M, Paral to eral data converter Serial data transmission reg A tream a serial dat obo Wanafered fom one digital #2 Sone cnet te rl taser daa ‘Anserial out shift reginter. a eet ‘46320, ] Design abit serial in werial out er usiat! — twhift regis 225A ECICSIT-Sem-2) Serial in-rerial out shift register using D flip-flop : Serial in cu DB, a4 a Pz}, 3} —JD, a] — Serial or utp [ wr a a] Conversion table and Fig3.2051) map: Ors =r eels] -o~ ofp] reroll ery | Logie diagram : Serial in oF cs lor cu. Quesate ‘Sera Fig-3.202 Design a 3-bit binary up/down counter with a direction control M. Use JE Mip-flops. Ana 1. The counter sequence for -bit binary upldown counter is: Direction | Counter Flip-flop inputs control state Mw | KK ° 0 ooo» 0 = ax ° © 0 4 fo ek te we GT o o 1 0 fo e+ « oa ° oor ttt oe ew te GT ° 1 0 o |x 0 Oo « a x ° 1 0 1 |e 0 t ew eG ° 1 1 of 0 « O14 % ° tor ade toe tad 1 oo oft « Tei Scanned with CamScannerTSCM RET ne HERE Digital Logie Design 3-27 \ RCICSAT-Sem-2) renee Ser ocstr ema) ‘Anewer | 1. The number of Mipop tobe used is three. We shall use three tog ‘ip op, Let, up counting takes place with M's Gand tose eeoee take place for M = 1, P ih M= Oand down counting 2 First, we write the circuit excitation table, eeedsen ‘Table 9.22.1: Excitation table for a2-bit upldown synchronous counter 2, Reap fOr Iyp Ky J “ww wi, = B= . Mode | Present state. [Next state | Fip-fiop Inpata From abe or aly C8, gt ak wo eemtrolae| Oe TQ [Qs [Qa] Ql |e] Q% Gy eM 0 ofolo}oyo oy td 1 el IA o Jofo}lifola afi ‘ d —| o fofilololy ofa ty) al TET o fed ftyc te tft ol « 4+¥—* 4 o 1 ojo 1 o o}a [4 rl ol o fijfofijafa ria ulm ‘ul 3 45} ad 0 rfafofaila ofa x [x |x o Jr faitifolo ria 1 —2|_al_w 1 Jolofloli|i ria ae MGA + AQ a Jofolilolo ofa Jee MR He For Ky 1 o}i}olo]o afa Ford, 1 fo}alijofa ofa a ao Mas wn or 10 1 1 o}o o 5 ray. ol Ital « dl 1 rlofaililo ofa 1 5 r Jaltafofilo ada aft IT J ay* Jet) 1 rtirtirdida o}a 4 = i 9 1] Next, let us obtain the K-maps and si ssions. The uly 7 3 * Ino} as] aol | ‘K-maps and simplified expressions for T, ave shown in Iat_ walls 1a [ob Fig. 3221. 10) «tLe ay ror’ Pl “a4 2] 292 Forte 80% TaN HQ, Sea Ky = MQ +H MQ\ 00 or 11 10 Mad 10 eae ooo Jo Io 00) 3. Theminimizedexpresionsare: alo doubled o oil + Qt 11d Of oul ir I= K,= HQQ+ MOQ 20 fF gf of Out Oy 10 ee or a Design a bit serchronous up-down connie = Te = Hp Q, + MT, TARTU 2016-16, Marks Scanned with CamScannerSequential Lage is APDlcotig, $-28A (ECICSIT:Sem-3) For, 2% Qe oo_ on 10 ola al jodta4 14. Finaly et usdraw the oie diagram. ite, sect Boi er J] Draw the logic diagram of a 4bit binary counter wid parallel load, ia] 1 Tho operation ofthe counter is sunmarized i Table 3.23.1. The fe control inputs-Clear, CLK, lod, and coun, determine the next stale 2 Thedesrinputisarynchonousand when equal (20, cates the cout tobe cleared regarilessof the pretence of lock pulses or other inp Twbleasns. eiear [OER teed | Coua]| | Fanaien «ee Ls [ons Yea | a ed epee re eg ier tiny mtr wt parle ona” igtal Logie Design 8-204 (BCICSIT-Som.8) oat st bs i (res Draw diagram of a 4-bit binary ripple down counter using fip-lops that trigger on negative edge transition, Also draw ‘timing diagram of the counter. ‘¢bit binary ripple down counter: 1. Te +i asynchronous counter Is constructed hy using JK fip-lop (asynchronous counter are als called ripple canter. 2 ‘Theoutput @, must be externally connected to clock input of ip-opB. The input count pulses are applied to clock input of fino A ‘Simultaneous evita of 2,48 and 1 are performed athe Qy,Qy eacdgostrats Scanned with CamScanner Tees_ sequel oi ite Apt 00a GOST Sem9) Timing dram: Dig Logi Desien SSA EoCsITsems) pe7 89 WH I gy crn Sem a4 owes PEEPLES LPL a | So Teer [ FipFiop apa rate sate pe ee OL OZR | oO 9f8 6 foe ge ae oo 1}o 1-0fo 3 § Ply are ol1 0 oft an - 7 ee jectea aia ee ela te ete atm et ab ge) tat lie tpg tee a fos ifa a oft 4b a ne 1aeleo ols i x ioe mame a |e re ee Kmape: ae Ford, Fork, © oo wo a uw ee + 4 TW ~| +] : 7 ~|-IE =[a | ‘itiplecunter needs Mipop To work indown mode M7 dei : so tehigh TG Kee 986325; ] Design a synchronous counter using JK flip-flop ford MQ For J, Qe FoR folowing input sequences ‘i Aa To topo (ast | olofr . elifo } ePs[s = eg ilo]? Rae ifalo stale 5 a _ Scanned with CamScannerDigital Lase Design SSSA (ECICSTT Sem-8) For, fe Fort, eo 5 Se he Oem nw | Io) Tp Yt od off af a 1 uP aff aa 10) rs aL tty tf ee ig. 8882, wee sas counter with T ip-flop - : esi of i binary syochronous count ee [Neate Flipflop tapaa Tf ls(epolay a, elo tm a] J Ley Lama ofepete foie} eo] sls rP® | po tjo| a sfols} ofelolsis|o % plolajar}o;ajyo;o}eo o}elej ole} ifols|o Sfife]ifo}afajelo sfaft]ofey rasa Design S-it synchronous counter using JK fp-ops. Shilips|sfe| ofo]s gl efopofije| ofa lo ARTO MART] tfele|alalelrlo]o tlefifalilelafifo Tae Tlelifi]ifilefoloe eres ; Posy aay i peles (s it synchronous counter tlije] lata] sfo|]s Fora dit synchronous ennter sing JK fpop, need pop Peete tbalatale 7 Excitation table and state diagram of JK flip-flop: rfititefefefoli map simplifeation oa EEE Pet Forty Fetata | ate. | input AN Mw SP oo o_o Tee 00) 00} 0 otf a} ie of 4 fi | 0 "aL APY oy i <4 4 ‘Excitation table of JK flip-flop "iY ag] | dul : J Tay Scanned with CamScanner