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  • Btech Ec 7 Sem Vlsi Design Eec 703 2016

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    Abhimanyu Yadav
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    This document is a 4 page exam paper on VLSI design for a B.Tech course. It contains 3 sections with a total of 100 marks. Section A contains 10 short answer questions worth 2 marks each on topics like leakage power, latch up, CMOS vs SOI technology, body effect, scaling techniques, transmission gates, reducing inverter delay, ROM vs PLA implementations, and dynamic CMOS circuits. Section B contains 5 long answer questions worth 10 marks each, including questions on the WSI design process, CMOS inverter analysis, flip flops, domino logic, DRAM cells, CMOS logic families, latches, multiplexers, testability concepts. Section C contains 2 long answer questions

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    This document is a 4 page exam paper on VLSI design for a B.Tech course. It contains 3 sections with a total of 100 marks. Section A contains 10 short answer questions worth 2 marks each on topics like leakage power, latch up, CMOS vs SOI technology, body effect, scaling techniques, transmission gates, reducing inverter delay, ROM vs PLA implementations, and dynamic CMOS circuits. Section B contains 5 long answer questions worth 10 marks each, including questions on the WSI design process, CMOS inverter analysis, flip flops, domino logic, DRAM cells, CMOS logic families, latches, multiplexers, testability concepts. Section C contains 2 long answer questions

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    4 views4 pages

    Btech Ec 7 Sem Vlsi Design Eec 703 2016

    Uploaded by

    Abhimanyu Yadav
    This document is a 4 page exam paper on VLSI design for a B.Tech course. It contains 3 sections with a total of 100 marks. Section A contains 10 short answer questions worth 2 marks each on topics like leakage power, latch up, CMOS vs SOI technology, body effect, scaling techniques, transmission gates, reducing inverter delay, ROM vs PLA implementations, and dynamic CMOS circuits. Section B contains 5 long answer questions worth 10 marks each, including questions on the WSI design process, CMOS inverter analysis, flip flops, domino logic, DRAM cells, CMOS logic families, latches, multiplexers, testability concepts. Section C contains 2 long answer questions

    Copyright:

    © All Rights Reserved
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    of 4

    r-

    www.aktuonline.com

    Printed Pages: 4 EEC.7O3

    (Foltowing Paper ID and Roll hlo. to be filled in your


    Answer Book)
    RollNo.
    B.Tech.

    (sEM. VIr) THEORY EXAMIT{ATIOhI, 2015- 1 6

    VL$ DESIGN
    hours]
    www.aktuonline.com

    [Time:3 [Total Marks:l00J

    Section-A

    1. Atternpt all parts. All parts carry equal marks. Write


    answer of each partin short. (2xl 0:20)

    (a) Why leakage power dissipation has become an


    important issue in deep submicron technology in
    deep submicron technology?

    (b) How the latch up problem can be overcome?

    (c) Distinguish between the bulk CMOS technology


    _
    with the SoI technology fabrications

    (d) What is body effect? How does it influence the


    threshold voltage of a MOS transistor?

    14300 (1) www.aktuonline.com


    P.T.O
    r www.aktuonline.com

    (e) Distinguish between constant field and const ant


    voltage feature size scaling? Compare their
    advantages and disadvantages.

    (f) How does the ON-resistance of a transmission gate


    changes as the input varies from 0 V to Vno, when
    the output has a light capacitive load.

    (g) What arethe various ways to reduce the delay time


    ofa CMOS inverter ?
    www.aktuonline.com

    (h) How the lirnitations of a ROM based realization is


    overcome in a PlA-based realtzation.

    (i) Explain the basic operation of a Z-phase dynamic


    circuit?

    0) Whatis charge leakageproblem ofdynamic CMOS


    circuits? How is it overcome?

    Section-B

    Attempt any five Questions from this section. (10x5:50)


    2. .Draw the Y-Chart and explain the WSI design process.

    3. Derive and explain the working of CMOS inverterwith


    V,r,
    its VTC characteristics. Also calculate the Vor, Vo", r
    V,, andVo forthe CMOS inverter.

    1 4300 (2) www.aktuonline.com


    EEC-703
    www.aktuonline.com

    4. Draw and explain the working of CMOS negative edge


    triggered Master slave D-flip flop.

    5. Compare the performance ofDomino CMOS logic and


    NP-Domino CMOS logic with suitable example.

    6. Explain the working of Three - transistor D-RAM cell


    with concept of leakage currents and refresh operation.
    What are the features required to select a proper RAM.

    7. Discuss the classification of CMOS digital logic


    www.aktuonline.com

    families.

    8. Explainthe following :

    a) Explain the behavior ofbistable elements. Explain


    the working of CMOS NOR based clocked JK
    latch.

    b) Draw a4xlMultiplexerusingtransmission gate.

    9. Explainthe following :

    a) Controllabilityandobservability.

    bl Explain the implementation of Built-In SelfTest


    (BIST) design techniques for VL SI circuit testing.

    www.aktuonline.com
    I 4300 (3) P.T.O
    4
    r':
    r"
    I www.aktuonline.com

    Section-C

    Attempt any two questions from this section. ( 15x2:30)


    10. Derive the expression for fall time and rise time for
    CMOS inverter.

    I 1. Explain the working of pass transistor circuit. Also


    explain how the charge stored affects the transfer of
    logic 66J" and logic 660" in NMOS pass transistor circuits.
    www.aktuonline.com

    12. Explain the techniques used in designing the low power


    CMOS logic circuits.

    x_

    (4) www.aktuonline.com
    r 4300 EEC-703

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