Printed Page: | of 2 AMAT Ad Subject Code: REC702 PAPER ID-310615, ET \ Roll No: [ J B.TECH (SEM-VII) THEORY EXAMINATION 2020-21 VLSI Desi Time: 3 Hours enien Total Marks: 70 Note: Attempt all Sections. If require any missing data; then choose suitably. SECTION A 1, Attempt aff questions in brief. —_———- Question a State Moore's law in reference to VLSI design. 2 1 _7[___ [implement EX-OR gate using CMOS logic. 2 ! e Differentiate between Static power and Dynamic power. 2 2 4. _| Define the term Interconnect impact in brief 2 3 fe. Mention the advantages of dynamic logic circuits over static | 2 4 logic circuits? | Comment on overview of power consumption in CMOS logic | 2 5 | circuits. g Define the term interconnect delay. 2 2) SECTION 2. Attempt any zhree of the following: Qo Ques 1 yw Explain the CMOS fabrication si ~ _{weil process. - _ b.__| Explain RC delay model eggiesonmes ~ : | ¢__| Implement the Boolean ekpression Y=AB+(C+D)(E+F)+(G+H) 4 ra Mention the advantages of interconnect modeling. Desszbe the | a | L interconnect modefin? to calculate R and C. @. [Discuss the varibus design techniques involved in lowpower [7 |S CMOS VLSI Eircuits. | AS SECTION C fe 3. Attempt any one part of the following: : Tx1=7 [ Qno. — ‘Question [Marks | CO} 4m | Draw the Y chart and explain the’ VLSI design process. |7 | Mention its advantages, | ! Explain symbol, different iad lines used for drawing)? |? | stick diagram, Draw the St gram of CMOS inverter. | __} % 4. Attempt any oze part of the following: Txte Qn0. Question “Marks | CO | Define the term Logical effoit & Electrical effort. Explain |7 2 | Linear RC delay model. Mention the limitation of this model. b. [Explain the Elmore delay model with suitable RC networks. |7 2 Mention its merits, t | https://www.aktuonline.comAum wag gg Attempt any one part of the follow inted Page: 20f2 PAPER 10-3106 RollNo | fort Subject Code: REC7O2 :| 1 — — Tute7 Qutiting ane - = - | Marks | CO a. | Define the term Bnergy delay Product (EDP) and Power delay [73 product (PDP). Describe different low power architectures with suitable diagrams._ oe { i {eT epln he inteconnee aging mew mh Attempt any one part of the following: Txl=7 [Qn0. Question Marks | CO \_| What is SRAM? Explain CMOS SRAM cell design strategy. 7 [4 | >. | Explain the behavior of Pass transistor in dynamic CMOS logic 7 4 implementation. \ 7. Attempt any one part of the following: Tx1=7 Qno. ‘Question | Marks | CO | a, __| Explain the term Controllability and Observability indetail. [7 _|$__| Z 3 ¥ With the help of suitable diagram, Explain Scan based | 7 technique. ; https:/‘www.aktuonline.com Whatsapp @ 9300930012 Send your old paper & get 10/- weet geet edt srr ste 10 eat ore, Paytm or Google Pay & https://www.aktuonline.com