IEEE Computer Society Annual Symposium on VLSI

GePaRD - a High-Level Generation Flow for Partially Reconfigurable Designs

Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke

Fraunhofer IIS / EAS Dresden

Zeunerstr. 38, 01069 Dresden, Germany
{boden|fiebig|ruelke}@eas.iis.fraunhofer.de
Abstract
This paper presents GePaRD, a novel approach to
High-Level Synthesis of self-adaptive systems based on
Partially Reconfigurable (PR) FPGAs. GePaRD combines
Temporal Modularization and Temporal Placement in
order to reduce the reconfiguration overhead at runtime by
extracting Temporal Reusable Modules. We introduce the
basics of High-Level PR design as well as the GePaRD
design steps (transformations) and GePaRD descriptions
(models). Moreover, we describe our approach to Temporal
Modularization using Greedy Clique Partitioning and
Temporal Placement using Simulated Annealing.
1. Motivation and introduction
Innovative applications in ubiquitous computing (such
as mobile embedded and multimedia systems) require a
high performance at a reasonable power consumption.
State-of-the-art programmable devices (such as FPGAs)
are capable to meet this requirements using Run-Time
Reconfiguration (RTR) [11]. RTR enables to exchange the
functionality of HW partitions while the remaining HW
partitions continue processing without interruption.
Several approaches deal with the FPGA-based
implementation of RTR systems and the use of high-level
design entries [1][7]. Using FPGA architectures, the
overhead to reconfigure at runtime affects the system
performance significantly.
To overcome this limitation, an application-specific
design has to adapt to the target-specific reconfiguration
mechanisms. For this reason, we present GePaRD (a
Generation Flow for Partially Reconfigurable Designs) for
Partially Reconfigurable (PR) FPGAs using High-Level
Synthesis (HLS).
In order to reduce the reconfiguration overhead at run-
time we developed a novel approach to temporal resource
sharing of called Temporal Modularization. It extracts
Temporal Reusable Modules (TRMs). These modules are
. reason, we use HLS to generate an application-specific
reused by several tasks and do have to be reconfigured
during a task switch. Raje et al. [6] consider resource shar-
ing in HLS as a clique partitioning problem and propose to
use a global cost function. Thus our approach uses Greedy
Clique Partitioning (GCP).
After Temporal Modularization the TRMs has to be
placed on the target architecture using Temporal Place-
ment. We apply a probabilistic optimization heuristic (Sim-
ulated Annealing) on a hierarchical layout model that
considers temporal sharings.
This paper is structured as follows: Section 2 introduces
partially reconfigurable architectures and related design
flows. An overview of the GePaRD approach is given in
Section 3. In Section 4 we explain the GePaRD approach
to Temporal Modularization and Temporal Placement in
detail. Section 5 summarizes the presented approach and
points out future work.
2. Background of High-Level PR Design
The first section gives an overview of state-of-the-art
partially reconfigurable architectures and related design
flows. In terms of the GePaRD approach, we also introduce
the basics of HLS.
2.1. Partially Reconfigurable (PR) FPGAs
In the last decade, a certain number of reconfigurable
computing architectures has been introduced [3]. But none
of these architectures is provided commercially. Nowa-
days, common FPGA architectures enable the implementa-
tion of adaptive systems.
Xilinx [9] introduced Virtex series FPGAs that provide
Partial Reconfiguration (PR) capabilities. Modern Virtex-4
FPGAs also support 2D reconfiguration which increases
the flexibility in PR system design. Moreover, PR-FPGAs
are hyper-programmable, that means they can implement
coarse-grained architectures too.
The GePaRD approach uses the hyper-programmability
in order to create an optimized architecture to implement
adaptive systems based on PR-FPGAs efficiently. For this

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DOI 10.1109/ISVLSI.2008.21
virtual architecture that adapts to the reconfiguration specification) to a structural description (i.e., a netlist) [5].
mechanisms of a dedicated target device. In the context of PR-FPGA design, HLS is used to generate
both the top-level architecture and the structural descrip-
2.2. Basic PR-FPGA Design Flows tion of the PR modules for the EAPR flow.
As shown in Figure 1, regarding PR-FPGA design we
can distinguish three different classes of HLS steps:
Xilinx, a vendor of PR-FPGAs, provides three basic
design flows in order to use the feature of dynamic partial • Compilation and Scheduling: Compilation transforms
reconfiguration of modern Virtex FPGAs: the behavioral description to an intermediate model
(i.e., a Control Data Flow Graph, CDFG). Scheduling
• Small-Bit Manipulations: The first PR design flow [8]
commits resources for the realization of operations at a
is a difference-based design flow. It is appropriate if
dedicated time. Regarding the realization of an adaptive
two distinct configurations differ marginally and does
PR system consisting of a set of HW tasks, the schedule
not require design restrictions because it is applied after
is explicitly given by the executable specification.
all configurations of the PR system have been com-
pletely designed and the bitstreams are available. Then • Resource Allocation and Binding: Allocation selects
partial bitstreams for the reconfiguration at runtime are design elements for realizing operation using a design
generated using BitGen or the FPGA Editor. library. Binding assigns the selected design elements to
dedicated resources on the target device. Regarding PR
• Module-based Partial Reconfiguration: The second design, allocation and binding enable an approach to
PR design flow [8] is based on the Xilinx Modular temporal resource sharing between HW tasks.
Design Flow (XMDF). According to Xilinx [10], the
XMDF is preferred for designing dynamically reconfig- • Connection Allocation and Architecture Generation:
urable embedded systems using Virtex FPGAs. This In the EAPR design flow, the top-level architecture
flow is characterized by dividing the design in a certain depends on the timing-dependent placement of the
number of distinct portions, called reconfigurable mod- modules on the target device. Thus, Temporal
ules, whose height is always the full height of the Placement has to be applied in order to determine the
device. Consequentially, a PR system is composed of a structure and the layout of the PR system including the
set of reconfigurable modules. If a module is not module-interconnections.
involved in the reconfiguration task, it does not have to
stop during the reconfiguration process. Modules are Behavioral Description
z = (x+y) * (e-f)
interlinked using dedicated routing resources, called Resource Binding
Bus Macros (BMs). BMs are place on the border of two
Compilation ALU + Reg
modules and represent a fixed communication interface
- ALU
in order to ensure a correct interconnection even if the + - * MULT
Connection Allocation
x y e f
configuration of modules varies at runtime. * ALU + Reg
a
• Early Access Partial Reconfiguration (EAPR): The Resource Allocation b - ALU
* MULT
most recent PR design flow proposed by Xilinx [11] z
Scheduling Add + Reg
introduces a novel approach to modular PR design. In
- Sub
contrast to the XMDF, a reconfigurable module (in the + s1
* Mult Architecture Generation
EAPR flow, called PR module) can assume an arbitrary - s2 s1 e
x
s2
s1
MULT
height. But this feature requires a device that supports * f s2 b
s2 a
y s1 z
ALU
2D reconfiguration such as a Virtex-4 FPGA.
Figure 1. High-level synthesis steps
In conclusion, the EAPR flow enables flexible, modular
design of PR systems using the advantages of modern PR-
FPGAs. Moreover, 2D reconfiguration allows an efficient 3. The GePaRD Approach
design partitioning in common and distinct PR modules in
This section gives an overview of the GePaRD approach
order to reduce the reconfiguration overhead at runtime.
which focusses on the reduction of the overhead when
reconfiguring PR-FPGA partially at runtime. It is based on
2.3. High-Level Synthesis (HLS) a previous work on HLS of HW tasks targeting run-time
reconfigurable FPGAs [2].
In general, High-Level Synthesis (HLS) transforms the Firstly, we introduce a temporal resource sharing
behavioral description of an IC design (i.e., an executable approach using temporal reusable modules. Then applying

299
the Y-diagram [4], the related design steps in HLS are
pointed out. Lastly, we itemize the models used to describe
a PR-FPGA system in all three design domains.
3.1. Temporal Reusable Modules (TRMs)
The most significant drawback of FPGA-based adaptive
PR systems is the reconfiguration overhead at runtime.
GePaRD addresses the reduction of the reconfiguration
overhead by extracting Temporal Reusable Modules
(TRMs) in order to enable temporal resource sharing
between sequentially executed HW tasks.
According to the modular EAPR design flow, a TRM
has to be placed on a fixed area on the FPGA. Furthermore,
it has to provide a common interface that fits all tasks
which are composed of this TRM.
Consequentially, the GePaRD approach combines the
extraction of Common Temporal Modules (CTMs), called
Temporal Modularization, and Temporal Placement.
3.2. Design Steps and Transformations
The GePaRD Flow enhances the EAPR design flow by
a high-level synthesis framework to enable model-based
design of PR systems using PR-FPGAs.
The flow uses an executable specification (i.e. high-
level notation of the PR system) as input and generates
both a system model for simulation and a physically-aware
architecture description as input for the implementation on
the target device using the modular EAPR design flow.
This is done by the four following design steps:
1. Template Abstraction: Firstly, the design library (LIB)
is created by abstracting templates from the target
architecture. Templates associate high-level notations
(i.e. control statements, called patterns, and operations)
with the related implementation (called macro). The
compiler uses these templates to refine a given algo-
rithm-level description to an intermediate RT-level
description called Binary Macro Tree (BMT, see
Section 3.3) as input for HLS.
2. High-Level Synthesis: According to Section 2.3, HLS
starts with a pre-scheduled behavioral description (rep-
resented by the BMT) and generates the structural PR
system description, the Pattern Macro Netlist (PMN,
see Section 3.3), which is used as model for simulating
the PR system on RT-level and as architecture template
to implement the PR system using the EAPR flow.
3. Temporal Modularization: The extraction of CTMs is
done at RT-level using the PMNs provided by HLS. A
CTM encapsulates an application-specific set of com-
mon macros in a reusable design element. Each CTM
300
substitutes a common set of macros in the PMNs of
sequentially executed tasks.
4. Temporal Placement: To generate a physically-aware
top-level architecture for the modular EAPR design
flow, Temporal Placement is used in order to pre-place
the unitized PMNs on the target-device.
Figure 2 depicts the design steps in the GePaRD flow
using the Y-diagram.
High-Level Modelling
Executable
Specification High-Level System Model
Prozessor, Memory
System Algorithm Synthesis
2
3 Temporal
RTL CDFG Modularization
Netlist ALU,MUX,
Registers
LIB
4 Temporal
Template 1 Placement
Abstraction Macro
Layout Physically-aware
Module Implementation
Target Architecture
Figure 2. Design Steps and transformations
3.3. Design Descriptions and Models
GePaRD comprises three interdepending intermediate
models to describe a PR design in all design domains
according to the Y-diagram shown in Figure 2:
• Binary Macro Tree (BMT): The BMT is a hierarchical
CDFG that represents the behavior of the PR system. It
is organized as a binary tree and consists of leaves and
branches. Leaves represent operations on the data flow.
Branches represent patterns or hierarchical nodes (e.g.,
to distinguish between system and the task behavior).
• Pattern Macro Netlist (PMN): The PMN is a netlist the
represents the hierarchical structure of the PR system.
It consists of macros and CTMs. A CTM comprises a
set of macros. Macros are provided by the design
library and implement patterns and operations.
• Binary Layout Tree (BLT): The BLT is a hierarchical
representation of an PR-FPGA layout. It segments the
CLB array using nested containers by splitting the chip
area represented by a container in half. Hence, each
container contains two sub-containers. At bottom-level
each container represents a CLB. The BLT comprises
multiple configurations per container in order to enable
Temporal Placement of multiple PMNs (one for each
task or configuration respectively).
 Figure 3 illustrates the descriptions and models (BMT, Sample Mean Sample Variance
PMN, BLT) used by GePaRD. n = read(); n = read();
c = n; c = n;
while ( c > 0 ) a = read();
Binary Macro Tree
{ while ( c > 0 )
t s p x = read(); {
Reconfiguration Schedule a = a + x; x = read();
Operation Sequence r r c = c - 1; s = x - a;
} s2 = s2 + (s * s);
r l s c s
a = a / n; c = c - 1;
write( a ); }
!= % / * + s2 = s2 / (n - 1);
Design (r,a,0) (s,a,2) (a,a,2) (t,a,3) (a,t,1) write( s2 );
l c
Library
(r) (s)

Figure 4. High-level notation (C code) of examples

REG
MUX Binary Layout Tree Sample Mean Sample Variance

run run
Pattern Macro Netlist
Figure 3. Descriptions and Models n n
a

c c
4. Physically-aware HLS for PR-FPGAs true
> -
true
> -

This section explains the GePaRD approach to HLS of
physically-aware optimized implementations of adaptive
PR systems using Temporal Modularization and Temporal
Placement in order to extract TRMs.
4.1. Example: Statistical Calculations
To explain the GePaRD approach, we introduce simple
design example for a PR system: an adaptive accelerator
for statistical calculations. This accelerator provides two
statistic function:
• Sample Mean: In statistics, the mean (or average) of a
list of numbers (x1, .., xn) is the sum of all the members
of the list divided by the number of items in the list.
l n l In the first step of physically-aware PR optimization,
x = --- ∑ x = --- 〈 x l + … + x n〉
n i=l i n
• Sample Variance: In statistics, the variance of a list of
numbers (x1, .., xn) is one measure of the statistical dis-
persion. It averages the squared distance of the possible
values from the expected value.
n l
δ = n∑
2 2
( x i – x ) = --- ( ( x l – x ) + … + ( x n – x ) )
i=l n
Figure 4 shows implementation examples for these two
algorithms using a High-Level Language (HLL) such as C.
In the GePaRD flow, optimizations (such as Temporal
Modularization and Temporal Placement) are performed
during HLS. Thus, we transform the source code to an
abstract CDFG for representing the intermediate formats of
the GePaRD flow, see Figure 5.
It’s obvious that the CDFGs of both algorithms are quite
false false
x - x
- / /
s + s2 + a
*
rdy rdy
Figure 5. Control Data Flow Graph of examples
similar. Consequentially, the task is to extract CTMs from
the related implementations in order to compose the PR
system using TRMs. The next two sections explain our
approach to extract CTMs using Temporal Modularization
and to form TRMs using Temporal Placement.
4.2. Temporal Modularization
GePaRD uses Temporal Modularization to extract CTMs
from sequentially executed HW tasks.
Using PMN, the structural description D of a PR system
is defined as a 5-tuple D = (H, P, t, L, a), whereby
• H = {h1, h2, .., hh} is the finite set of HW tasks.
2 2
• P = {p1, p2, .., pp} is a finite set of PMN nodes.
• t: P → H is a relation that assigns a PMN node a task.
• L = {l1, l2, .., ll} is a finite set of LIB macros.
• a: P → L is the allocation relation which assigns a PMN
node a dedicated LIB macro.
Valid combinations Cu of interconnected PMN nodes of
a HW task hu, called (PMN) tuples, are defined as a 4-tuple
Cu = (T, i, t2, tn), whereby

301
• Tuc = {tuc1, tuc2, .., tuct} is a finite set of c-tuples tuci that best combination of sharings svk ∀v∀k(v,k ∈ N ∧ v → Sv
comprises a set of PMN nodes {pi1, pi2, .., pic} of a task ≠ ∅ ∧ k < card(Sv)). Figure 6 illustrates the result of Tem-
hu, i.e. ∀pi∀hu(pi ∈ tuci ∧ hu ∈ H → t(pi) = hu). poral Modularization with example (see Section 4.1).

• i: P × P → {true, false} is the input condition of a pair Sample Mean Sample Variance
of nodes (pi, pj) that holds if pj gets an input from pi.
run run

• t2: P × P → Tu2 is a relation that forms a 2-tuple by

n n
joining two PMN nodes (pi, pj) of HW task hu, a
if i(pi, pj) = true. c
> c - > -
true true
• tn: Tu2 × Tui → Tu(i+1) is a relation that merges i-tuples false false
x x -
and 2-tuples to form (i+1)-tuples of HW task hu, / - /

if ∃px∃py(px ∈ Tu2 ∧ py ∈ Tui → i(px, py) = true). + a s + s2

*
rdy rdy
All (2..m)-tuples of a task hu can be derived iteratively
by merging i-tuples and 2-tuples to form (i+1)-tuples with
i,m ∈ N ∧ 2 < i < m, i.e. Figure 6. Temporal Modularization

• ∀hu∀pki∀pkj(hu ∈ H ∧ pki ∈ P ∧ pkj ∈ P 4.3. Temporal Placement

→ t2(pki, pkj) ∈ Tu2)
• ∀hu∀n∀tki∀tkj(hu∈H∧n∈N∧n>1∧tki∈Tkn∧tkj∈Tk2
→ tn(tun, tuj) ∈ Tu(n+1))
Valid mergings Mv of temporal PMN v-tuples sharings
according to a given task schedule are defined as a 4-tuple
Mv = (F, e, Sv, s), whereby
• F = {f1, f2, .., fts} is a finite set of task pairs (hi, hj)
where hj is valid a successors of hi in a given schedule.
• e: Tqv x Trv → {true, false} is the equivalent condition
of two v-tuples (ti, tj) that holds if ti ≡ tj.
The GePaRD approach to Temporal Placement uses a
hierarchical binary tree representation of the PR-FPGA
layout (the BLT, see Section 3.3) as model, that is defined
as a X-tuple, whereby
• B = {b1, b2, .., bb} is a finite set of BLT nodes that
represent a dedicated area on the PR-FPGA.
• v = [v1, v2, .., vv] is a vector that represents the path to a
BLT node in the tree related to the root node, i.e. the
layout position on the PR-FPGA.
• p: B → v is a relation that assigns a BLT node a path.

• Sv = {sv1, sv2, .., svs} is a finite set of v-tuples sharings
svi represents a set of equal tuples (tav, tbv, .., tcv) of dis-
joint tasks, i.e. ∀tqv∀trv(tqv ∈ svi ∧ trv ∈ svi ∧ hq,hr ∈ H
→ (hq,hr) ∈ F ∧ e(tqv, trv) = true).
• s: Tqv → Sv is a relation that assigns equal v-tuples tqvi
and trvj in succeeding tasks hq and hr an unique sharing
svk, i.e. ∀tqvi∀trvj∃1svk(tqvi ∈ Tqv ∧ trvj ∈ Trv ∧ e(tqvi,
trvj) = true ∧ svk ∈ Sv → s(tqvi) = svk ∧ s(tqvj) = svk).
A sharing svk is characterized by the required chip area
costa(svk), the number of I/O ports costp(svk), and the
number of task transitions costs(svk) where the runtime
reconfiguration overhead is reduced when applying svk.
Thus, a weighted cost function can be deduced:
• cost(svk) = α • costs(svk) • costa(svk) + β • costp(svk)
with α,β ∈ R+ ∧ α,β ≤ 1
The CTMs are extracted using GCP, i.e. by selecting the
• D = {d1, d2, .., dd} is a finite set of dimensions for valid
BLT paths representing multiple configurations for the
related chip area on the PR-FPGA.
• d: D → B is a relation that assigns a BLT node a
dimension.
• c: Sv → B is a relation that assigns a CTM svk (selected
sharing Sv) a BLT node.
• u: P → B is a relation that assigns a PMN node a BLT
node bi within the sub-tree of the related CTM svk in
the same dimension, i.e. ∀bi∀svk(bi ∈ B ∧ svk ∈ Sv →
p(svk) ⊂ p(bi) ∧ d(bi) = d(c(svk))).
In consequence, the BLT fulfills the requirements in
order to apply a probabilistic optimization heuristic (such
as Simulated Annealing):
• An initial start layout of the CTMs can be generated
using a deterministic placement algorithm by assign
any CTM and any PMN node a BLT node.

302
• Exchanging two BLT nodes bi and bj enables to move 6. References
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All registered or unregistered trademarks referenced are the property of

We proposed GePaRD, a Generation Flow for Partially their respective owners and no trademark rights to the same is claimed.
Reconfigurable Designs. GePaRD enhances the EAPR
flow by a High-Level Synthesis approach to optimized
design of adaptive PR systems that implement a certain
number of HW tasks.
In order to reduce the reconfiguration overhead when
tasks switches occur at runtime, GePaRD combines
Temporal Modularization and Temporal Placement.
Temporal Modularization is considered as a Greedy Clique
Partitioning problem. It extracts Temporal Reusable
Modules. These modules are reused by several tasks and do
have to been reconfigured during a task switch. For
Temporal Placement, we apply a probabilistic optimization
heuristic (Simulated Annealing) on a hierarchical layout
model that considers temporal sharings.
This paper introduces the GePaRD approach and gives
an example. The next step in future work is to add the
described optimization steps in our synthesis framework
for adaptive PR systems [2] in order to get experimental
results.

303