Sph434 Microprocessor Applications I - Int - Mod

KENYATTA UNIVERSITY
DIGITAL SCHOOL OF VIRTUAL AND OPEN LEARNING

IN COLLABORATION WITH
SCHOOL OF PURE AND APPLIED SCIENCES

DEPARTMENT OF PHYSICS
SPH 434: MICROPROCESSOR APPLICATIONS I
AUTHOR VETTED BY
DR. MK MUNJI DR. RL NYENGE
Copyright © 2020
All Rights Reserved.
INTRODUCTION
Welcome to this module. You probably have heard about the term microprocessor. You could
have formed and developed your own versions of what the term constitutes. In this module,
we will introduce you to the basic concepts in microprocessors and why you should study it.
This is an interactive instructional module that uses both action and collaborative learning
styles that provide you with diverse online learning experiences and effective learning
processes. The key purpose of this module is to expose you theoretically to the various types
of microprocessors in use, how they were developed, designed and applied to computers and
other microprocessor-based systems. This should hopefully equip you with the necessary
attitudes, knowledge and skills crucial in developing microprocessor systems to those who
would like to major in electronics.
Computing digital systems are designed to store, process, and communicate information in
digital form. They are found in a wide range of applications, including process control,
communication systems, digital instruments, and consumer products. A digital computer,
more commonly called simply a computer, is an example of a typical digital system.
A computer manipulates information in digital or more precisely, binary form. A binary

number has only two discrete values: zero or one. Each discrete value is represented by the
OFF and ON status of an electronic switch called a transistor. All computers understand only
binary numbers. Any decimal number (base 10, with ten digits from 0 to 9) can be
represented by a binary number (base 2, with digits 0 and 1).
The basic blocks of a computer are the central processing unit (CPU), the memory, and the
input/output (I/O). The CPU of a computer is basically the same as the brain of a human
being; so computer memory is conceptually similar to human memory. A question asked of a
human being is analogous to entering a program into a computer using an input device such
as a keyboard, and a person answering a question is similar in concept to outputting the
program result to a computer output device such as a printer. The main difference is that
human beings can think independently, whereas computers can only answer questions for
which they are programmed. Computer hardware includes such components as memory,
CPU, transistors, etc
We hope that you will find this module exciting, educative, and engaging. We also hope that
it stimulates your mind so that you can think of microprocessors in computing regardless of
your academic pursuits. After all, computing cuts across all fields of study and should be
exploited if motivation allows.
MICROPROCESSOR AND APPLICATION 1 FLOW CHART

Week Topic and/or Sub topic
1 Introduction
2 History of microprocessor
3 Architecture and overview of microprocessors
4 Microprocessor-based systems
5 Intel 8085 microprocessor architecture
6 Intel 8085 microprocessor organization
7 Intel 8085 microprocessor instruction sets and assembly language programs
8 Intel 8086/8088 microprocessor architecture
9 Intel 8086/8088 microprocessor organization
10 Intel 8086/8088 microprocessor instruction sets and assembly language programs
11 Examination
12 Examination
OVERVIEW OF THE COURSE
Week 1: Introduction
This lesson is intended to help you get used to the blended learning and to create a
community of learners who will motivate each other during the course. You are required to
introduce yourself to both your lecturer and colleagues online before other academic
interactions start. It will be important for us to go through the entire course to highlight the
context and goals as well as what learners think about microprocessors. Learners are
encouraged to share their experience regarding microprocessors.
Week 2: History of Microprocessors

In this first lesson, we lay the foundation for the entire course by defining the concept
microprocessor, computers and other related terms. The purpose of this lesson is to enable
you understand fundamental concepts, history and development of microprocessors.
Week 3: Overview and Architecture of Microprocessors

In this lesson, we introduce you to the components inside a microprocessor, types of registers
used in microprocessors/computers, and function of these processor registers. Both von
Neumann and Harvard architecture designs and associated components is discussed. The
purpose of this lesson is to inspire learners towards understanding the architecture and the
components used to design microprocessors.
Week 4: Microprocessor-based systems

This lesson focuses on microprocessor based designs and is intended to train learners to
appreciate all systems that are designed to use microprocessors. The purpose of this lesson is
to help learners understand the role played by microprocessors in digital systems.
Week 5: Intel 8085 architecture

This lesson builds on the lesson 3 architecture of microprocessor. Here emphasis will be on
the functional units and architecture of Intel 8085 microprocessor. Addressing modes and
Formats-immediate, direct, indirect, register, register indirect, displacement and stack,
Instruction Cycle machine cycle and Data flow, 8085 instruction set shall be discussed. The
purpose of this lesson is to learn the architecture and operation of Intel 8085 microprocessor.
Week 6: Intel 8085 Microcomputer Organization

These lessons describe Intel 8085 instruction sets, stacks and subroutine structures with basic
registers. The purpose is to understand the instructional organization of Intel 8085
microprocessor.
Week 7 Intel 8085Assembly Language and Machine Language programming

This lesson is will discuss machine and assembly language programming in Intel 8085
microprocessor, Instruction Cycle, machine cycle and Data flow, 8085 instruction set and
assembly programming. The purpose of this lesson is to help learners design and write
assembly language programs for Intel 8085 microprocessor.
Week 8: Intel 8086/8088 architecture

This lesson builds on the lesson 3 and 5 architecture of microprocessor. Here emphasis will
be on the functional units and architecture of Intel 8086/8088 microprocessor. Addressing
modes and Formats, Instruction Cycle machine cycle and Data flow, 8086/8988 instruction
set shall be discussed. The purpose of this lesson is to learn the architecture and operation of
Intel 8086/8088 microprocessor.
.
Week 9: Intel 8086/8088 Microcomputer Organization

These lessons describe Intel 8086/8088 instruction sets, stacks and subroutine structures with
basic registers. The purpose is to understand the instructional organization of Intel 8086/8088
microprocessor.
Week 10: 7 Intel 8086/8088 Assembly Language and Machine Language programming
This lesson is will discuss machine and assembly language programming in Intel 8086/8088
microprocessor, Instruction Cycle, machine cycle and Data flow, 8086/8088 instruction set
and assembly programming. The purpose of this lesson is to help learners design and write
assembly language programs for Intel 8086/8088 microprocessor
Week 11&12: Examination

These two weeks bring together the work you have been doing to an end. This course unit
will be examined and will partially contribute to the award of the degree in the program that
you are undertaking.
Troubleshooting
o If you have problems accessing or logging into the system (LMS):
1. Go to the Student Help Desk -https://support.ku.ac.ke/
2. Chat with us at http://chat.ku.ac.ke/
3. Call the Digital school offices at (See our Contacts here)-

http://www.ku.ac.ke/dsvol/contact-us
4. Guides about how to use Moodle are available athttp://www.ku.ac.ke/dsvol/students-

resources
5. Also use our social media huddles:
Twitter: @KUDigitalSchool
Facebook: @KUDSVOL
Table of Contents
Inside a microprocessor ..................................................................................................... 10
1.1Introduction ......................................................................................................................... 10
1.2 Lesson Learning Outcomes................................................................................................ 10
1.2.1 History of Microprocessors......................................................................................... 10
Table:1-1 Important Intel Microprocessors ......................................................................... 12
Lesson 2 ............................................................................................................................... 15
Microprocessor Architecture ............................................................................................ 15
2.1 Introduction ........................................................................................................................ 15
2.2.1 Von Neumann Architecture ........................................................................................ 15
2.2.2 Parallel processing schemes ........................................................................................ 19
Lesson 3 ............................................................................................................................... 24
Microprocessor Overview ................................................................................................. 24
3.1 Introduction ........................................................................................................................ 24
3.2.1 Difference between Microprocessor and Microcontroller .......................................... 24
3.2.2 Organization of a Microprocessor .............................................................................. 29
Lesson four ......................................................................................................................... 37
Microprocessor based systems .......................................................................................... 37
4.1 Introduction ........................................................................................................................ 37
4.2.1 Microprocessor based systems .................................................................................... 37
Lesson 5 ............................................................................................................................... 43
The 8085 Microprocessor Architecture ........................................................................... 43
5.1 Introduction ........................................................................................................................ 43
5.2.1 PIN arrangement of the 8085 microprocessor. ........................................................... 43
5.2.2 The Internal Organization the 8085 ............................................................................ 44
Lesson 6 ............................................................................................................................... 48
The 8085 Instructions ........................................................................................................ 48
6.1 Introduction ........................................................................................................................ 48
6.2.1 Addressing modes of the 8085 .................................................................................... 48
6.2.2 Classification of 8085 microprocessor Instructions .................................................... 49
Lesson 7 ............................................................................................................................... 53
The Stack and Subroutines ............................................................................................... 53
7.1 Introduction ................................................................................................................... 53
7.2.1 The Stack and Subroutines.......................................................................................... 53
7.2.2 Movement of data in stacks ........................................................................................ 55
Lesson 8 ............................................................................................................................... 58
Introduction to 8085 Programs......................................................................................... 58
8.1 Introduction ........................................................................................................................ 58
8.2.1 Write and Hand Assemble Programs .......................................................................... 58
Lesson 9 ............................................................................................................................... 62
Introduction to 8088/8086 ................................................................................................. 62
9.1 Introduction ........................................................................................................................ 62
9.2.1 Intel 8088/8086 Microprocessor Fundamentals.......................................................... 62
The 8086/8088 Instructions ............................................................................................... 74
10.1 Introduction ...................................................................................................................... 74
10.2 Lesson Learning Outcomes.............................................................................................. 74
10.2.1 Addressing modes of the 8086/8088......................................................................... 74
1. Purpose
This course is prepared for fourth year B.Sc. (TIT) students at Kenyatta University. The
course is based on the Intel 8088/8086 microprocessor, and prepares students to solve
practical problems using a microprocessor.
2. Description
Inside the microprocessor: Microprocessor architecture, microprocessor word lengths, types
of memory addressing, internal microprocessor buses, microprocessor registers and the
arithmetic and logic unit.
Microprocessor: Accumulator, status register, program counter, instruction register and
stack pointers.
Features of real microprocessors: data control logic, address control logic, data address
control bus buffers, microprocessor fetch-decode-execute cycle, instruction execution by
microprocessor and arithmetic operation by ALU.
Microprocessor systems: Basic units and application of 8088/8086 microprocessor.
3. Module Learning Outcomes

By the end of this course, the learners should be able to:-
1. Synthesize and implement digital circuits using programmable logic
2. Describe components of a CPU
3. Describe how a microprocessor is built and how its functions
4. Explain what goes on in a typical microprocessor system
5. Write simple programs in assembler:
6. Hand assembles mnemonics using instruction set
4. Course Requirements
This is a blended learning course that will utilize the flex model. This means that learning
materials and instructions will be given online and the lessons will be self-guided with the
lecturer being available briefly for face to face sessions and support and also on-site (online)
most of the time. Your lecturer will be meeting you face to face to introduce a lesson and put
it into perspective and you will actively participate in your search for knowledge by
undertaking several online activities. This means that some of the 35 instructional hours of
the course will be delivered face to face while other lessons will be taught online through
various learner and lecturer activities. It is important for you to note that one instructional
hour is equivalent to two online hours. Three instructional hours will be needed per week.
Out of these, one will be used for face to face contact with your lecturer (also referred as e-
moderator in the online activities) while the other two instructional hours (translating to four
online hours) will be used for online activities otherwise referred to as e-tivities in the
lessons.
You will be required to participate and interact online with your peers and the e-moderator
who in this case is your lecturer. Guidelines for the online activities (which we shall keep
referring to as e-tivities) will be provided whenever there is an e-tivity. Please note that since
the online e-tivities are part of the learning process, they may be graded at the discretion of
your e-moderator. Such grading will however be communicated in the e-tivity guidelines and
feedback given as soon as possible after the e-tivity. The e-tivities will include but will not be
limited to online assessment quizzes, assignments and discussions. There are also assessment
questions that you can attempt at the end of every lesson to test your understanding of the
lesson. The answers to all the assessment questions are at the end of each lesson.
5. Assessment
The tools include online collaborative discussions forums that focus on team learning and
personal mastery and will therefore provide you with peer feedback, lecturer assessment and
self- reflection. You will also be required to do one major assignment that is meant to assess
the application of the skills and knowledge gained during the course. The project score in
combination with scores for e-tivities (where graded) will account for 30% of your final
examination score with the remaining 70% coming from a face to face sit-in final written
examination that will be guided by your university examination policy and procedures
Continuous assessment Tests 30%

 Online Tests 15%
 Assignments and Practices 15%
End of semester examination 70%
Total 100%
Lesson 1
Inside a microprocessor
1.1 Introduction
This lesson is recommended as the starting point for microprocessors and provides a
foundation on which the rest of the units build. The online lessons with readings, video
demonstrations, and activities introduce students to:
 A brief history of computers, from ENIAC to modern computers

 The four basic components of a computer: input, storage, processing, and output
 The differences between the capabilities of an electronic brain and the human brain
1.2 Lesson Learning Outcomes
By the end of the lesson, you will be able to:
 Understand events that led to the development of the microprocessors

 Learn terminology for parts of the microprocessor
 Create a mental model of microprocessor as information-processing machines
 Understand differences between the human brain and the electronic brain
1.2.1 History of Microprocessors
Computer's Central Processing Unit (CPU) built on a single Integrated Circuit (IC) is called
a microprocessor.
A digital computer with one microprocessor which acts as a CPU is called microcomputer.
It is a programmable, multipurpose, clock -driven, register-based electronic device that reads

binary instructions from a storage device called memory, accepts binary data as input and
processes data according to those instructions and provides results as output.
The microprocessor contains millions of tiny components like transistors, registers, and
diodes that work together.
Block Diagram of a Microcomputer

A microprocessor consists of an ALU, control unit and register array. Where ALU performs
arithmetic and logical operations on the data received from an input device or memory.
Control unit controls the instructions and flow of data within the computer. And, register
array consists of registers identified by letters like B, C, D, E, H, L, and accumulator.
Fair child semiconductors (founded in 1957) invented the first Integrated Circuit in 1959 that
marked the microprocessor history. In 1968, Gordan Moore, Robert Noyce and Andrew
Grove resigned from the Fair child semiconductors and started their own company: Integrated
Electronics (Intel). In 1971, the first microprocessor Intel 4004 was invented. A
microprocessor is also known as a central processing unit in which numbers of peripherals’
are fabricated on a single chip. It has ALU (arithmetic and logic unit), a control unit,
registers, bus systems and a clock to perform computational tasks.
Generation of Microprocessor
1st Generation
This was the period during 1971 to 1973 of microprocessor’s history. In 1971, INTEL created
the first microprocessor 4004 that would run at a clock speed of 108 KHz.With only 4 bits as
the word size, the 4004 could only represent signed numbers in the range -8 to +7, which is
indeed very small. So, it was not really of practical use for arithmetic calculations. However,
it found applications in controlling devices.
2nd Generation
Intel 8008 was the next in the evolution, the first 8-bit microprocessor. This was in the year
1972. This was soon followed by Intel 8080, also an 8-bit microprocessor. Intel 8080 was the
first commercially popular 8bit microprocessor. With 8 bits as the word size, it could
represent signed numbers in the range of −128 to +127. This is also not a good enough range
for performing arithmetic calculations. Thus, the 8080 also was used only for control
applications.
Some other microprocessors like 6800 from Motorola, Z-80 from Zilog were also popular at
this time.
They were costly as they were based on NMOS technology fabrication and also for their
superfast speed.
3rd Generation
Around 1978, Intel released 8086, the first 16-bit microprocessor. With 16-bit word size, it
was possible to represent signed numbers in the range of −32,768 to +32,767, which is quite a
decent range for performing arithmetic calculations. As such, this processor became very
popular not only for control applications, but also for number crunching operations. Speeds
of those processors were four times better than the 2nd generation processors. Not to be
outdone, Motorola came out with 68000, their 16-bit processor. Zilog released Z-8000, again
a 16-bit processor. These are the most popular 16-bit processors.
4th Generation
In the early 80s, Intel released the 32-bit processor, the Intel 80386, by using HCMOS
fabrication. With 32-bit word size, it was possible to represent signed numbers in the range
±2×109, which is quite a large range for performing arithmetic calculations. If floating point
notation is used, it can represent much larger numbers. As such, this processor became very
popular as the CPU in computers for number crunching operations. At this time, Motorola
came out with 68020, their 32-bit processor. Intel released 80486, which was basically an
80386 processor with an 80387 numeric co-processor on a single chip. Motorola released
68030. In the early 90s, Intel released 80586 by the name Pentium processor. It is extremely
fast in performing arithmetic calculations and executing instructions. The Pentium 4 released
in 2000 has 42 Million transistors worked with a clock frequency of 1.5 GHz and is rated for
1500 MIPS (Million instructions per second).
5th Generation
From 1995 to until now this generation has been bringing out high-performance and high-
speed processors that make use of 64-bit processors. The present-day computers based on
microprocessors are already faster than the mini computers and sometimes the main frame
computers of yesteryear, and they are available at a small fraction of the cost of such main
frame computers.
Table:1-1 Important Intel Microprocessors
Microprocessor Year of Word Memory Pins Clock Remarks

Invention Length addressing
Capacity
4004 1971 4-bit 1 KB 16 750 First
KHz Microprocessor
8085 1976 8-bit 64 KB 40 3-6 Popular 8-bit
MHz Microprocessor
8086 1978 16-bit 1MB 40 5-8 Widely used in
MHz PC/XT
80286 1982 16-bit 16MB real, 68 6-12.5 Widely used in
4 GB virtual MHz PC/AT
80386 1985 32-bit 4GB real, 132 20-33 Contains MMU
64TB 14X14 MHz on chip
virtual PGA
80486 1989 32-bit 4GB real, 168 25- Contains MMU,
64TB 17X17 100 cache and FPU,
virtual PGA MHz 1.2 million
transistors
Pentium 1993 32-bit 4GB 237 60- Contains 2
real,32-bit PGA 200 ALUs,2 Caches,
address,64- FPU, 3.3 Million
bit data bus transistors, 3.3 V,
7.5 million
transistors
Pentium Pro 1995 32-bit 64GB real, 387 150- It is a data flow
36-bit PGA 200 processor. It
address bus MHz contains second
level cache
also,3.3 V
Pentium II 1997 32-bit - - 233- All features
400 Pentium pro plus
MHz MMX
technology,3.3 V,
7.5 million
transistors
Pentium III 1999 32-bit 64GB 370 600- Improved version
PGA 1.3 of Pentium II; 70
MHz new SIMD
instructions
Pentium 4 2000 32-bit 64GB 423 600- Improved version
PGA 1.3 of Pentium III
GHz
Itanium 2001 64-bit 64 address 423 733 64-bit EPIC
lines PGA MHz- Processor
1.3
GHz
Where,
 PGA - Pin Grid Array

 MMX - MultiMedia eXtensions
 EPIC - Explicitly Parallel Instruction Computing
 SIMD - Single Instruction Multiple Data
 ALU - Arithmetic and Logic Unit
 MMU - Memory Management Unit
 FPU - Floating Point Unit
Basic Terms used in Microprocessor
Here is a list of some basic terms used in microprocessor:

Instruction Set - The group of commands that the microprocessor can understand is called
Instruction set. It is an interface between hardware and software.
Bus - Set of conductors intended to transmit data, address or control information to different
elements in a microprocessor. A microprocessor will have three types of buses, i.e., data bus,
address bus, and control bus.
IPC (Instructions Per Cycle) - It is a measure of how many instructions a CPU is capable of
executing in a single clock.
Clock Speed - It is the number of operations per second the processor can perform. It can be
expressed in megahertz (MHz) or gigahertz (GHz). It is also called the Clock Rate.
Bandwidth - The number of bits processed in a single instruction is called Bandwidth.
Word Length - The number of bits the processor can process at a time is called the word
length of the processor. 8-bit Microprocessor may process 8 -bit data at a time. The range of
word length is from 4 bits to 64 bits depending upon the type of the microcomputer.
Data Types - The microprocessor supports multiple data type formats like binary, ASCII,
signed and unsigned numbers.
Lesson 2
Microprocessor Architecture
2.1 Introduction
The microprocessor follows a sequence to execute the instruction: Fetch, Decode, and then
Execute.
Initially, the instructions are stored in the storage memory of the computer in sequential
order. The microprocessor fetches those instructions from the stored area (memory), then
decodes it and executes those instructions till STOP instruction is met. Then, it sends the
result in binary form to the output port. Between these processes, the register stores the
temporary data and ALU (Arithmetic and Logic Unit) performs the computing functions.

2.2.1 Understand the von Neumann Architecture
2.2.2 Describe parallel processor systems
2.2.1 Von Neumann Architecture
The phrase Von Neumann architecture derives from a paper written by computer scientist
John von Neumann in1945. This describes design architecture for an electronic digital
computer with subdivisions of a central arithmetic part, a central control part, a memory to
store both data and instructions, external storage, and input and output mechanisms. The
meaning of the phrase has evolved to mean a stored-program computer. A stored-program
digital computer is one that keeps its programmed instructions, as well as its data, in read-
write, random-access memory (RAM). So John Von Neumann introduced the idea of the
stored program. Previously data and programs were stored in separate memories. Von
Neumann realised that data and programs are indistinguishable and can, therefore, use the
same memory. On a large scale, the ability to treat instructions as data is what makes
assemblers, compilers and other automated programming tools possible. One can "write
programs which write programs". This led to the introduction of compilers which accepted
high level language source code as input and produced binary code as output.
The Von Neumann architecture uses a single processor which follows a linear sequence of
fetch-decode-execute. In order to do this, the processor has to use some special registers,
which are discrete memory locations with special purposes attached. These are:
These are
(i) PC Program Counter
(ii) CIR Current Instruction Register
(iii)MAR Memory Address Register
(iv) MDR Memory Data Register
(v) IR Index Register
(vi) Accumulator Holds results
(i) The program Counter: The program counter keeps track of where to find the next
instruction so that a copy of the instruction can be placed in the current instruction register.
Sometimes the program counter is called the Sequence Control Register (SCR) as it controls
the sequence in which instructions are execute
(ii) The current instruction register holds the instruction that is to be executed.
(iii) The memory address register is used to hold the memory address that contains either
the next piece of data or an instruction that is to be used.
(iv) The memory data register acts like a buffer and holds anything that is copied from the
memory ready for the processor to use it.
The central processor contains the arithmetic-logic unit (also known as the arithmetic unit)
and the control unit. The arithmetic-logic unit (ALU) is where data is processed. This
involves arithmetic and logical operations. Arithmetic operations are those that add and
subtract numbers, and so on. Logical operations involve comparing binary patterns and
making decisions.
The control unit fetches instructions from memory, decodes them and synchronizes the
operations before sending signals to other parts of the computer.
(v) The accumulator is in the arithmetic unit, the program counter and the instruction
registers are in the control unit and the memory data register and memory address register are
in the processor.
(vi) An index register is a microprocessor register used for modifying operand addresses
during the run of a program, typically for doing vector/array operations. Index registers are
used for a special kind of indirect addressing where an immediate constant (i.e. which is part
of the instruction itself) is added to the contents of the index register to form the address to
the actual operand or data.
A typical layout is shown in Fig. 2.1 which also shows the data path
Fig. 2.1 typical microprocessor layout

The Fetch-Decode-Execute-Reset Cycle
The following is an algorithm that shows the steps in the cycle. At the end the cycle is reset
and the algorithm repeated.
1. Load the address that is in the program counter (PC) into the memory address register
(MAR).
2. Increment the PC by 1.
3. Load the instruction that is in the memory address given by the MAR into the
memory data register (MDR).
4. Load the instruction that is now in the MDR into the current instruction register
(CIR).
5. Decode the instruction that is in the CIR.
6. If the instruction is a jump instruction then
a. Load the address part of the instruction into the PC
b. Reset by going to step 1.
7. Execute the instruction.
8. Reset by going to step 1.
Steps 1 to 4 are the fetch part of the cycle. Steps 5, 6a and 7 are the execute part of the cycle
and steps 6b and 8 are the reset part.
Step 1 simply places the address of the next instruction into the memory address register so
that the control unit can fetch the instruction from the right part of the memory. The program
counter is then incremented by 1 so that it contains the address of the next instruction,
assuming that the instructions are in consecutive locations.
The memory data register is used whenever anything is to go from the central processing unit
to main memory, or vice versa. Thus the next instruction is copied from memory into the
MDR and is then copied into the current instruction register.
Now that the instruction has been fetched the control unit can decode it and decide what has
to be done. This is the execute part of the cycle. If it is an arithmetic instruction, this can be
executed and the cycle restarted as the PC contains the address of the next instruction in
order.
However, if the instruction involves jumping to an instruction that is not the next one in
order, the PC has to be loaded with the address of the instruction that is to be executed next.
This address is in the address part of the current instruction, hence the address part is loaded
into the PC before the cycle is reset and starts all over again.
A CPU cannot do math on data registers, although it can do it indirectly with an index
register. The index register works with the data registers, allowing a program to process
strings of data efficiently. To process your first name, for example, a program move 300 to
MAR and zero to the index register. An indexed operation adds the index value to the MDR,
retrieving the letter at location 300. Next, the program increments the index by one and gets
the next letter. It repeats this process until it has moved the whole name. By itself, the index
register does little; its value is that it gives greater speed and convenience to address registers.
The need for and the use of buses to convey data (Data, Address and Control Buses)
A bus is a set of parallel wires connecting two or more components of the computer.
The CPU is connected to main memory by three separate buses. When the CPU wishes to
access a particular memory location, it sends this address to memory on the address bus. The
data in that location is then returned to the CPU on the data bus. Control signals are sent
along the control bus.
The data, address and control buses connect the processor, memory and I/O controllers.
These are all system buses. Each bus is a shared transmission medium, so that only one
device can transmit along a bus at any one time.
Data and control signals travel in both directions between the processor, memory and I/O
controllers. Address, on the other hand, travel only one way along the address bus: the
processor sends the address of an instruction, or of data to be stored or retrieved, to memory
to an I/O controller.
The control bus is a bi-directional bus meaning that signals can be carried in both directions.
The data and address buses are shared by all components of the system. Control lines must
therefore be provided to ensure that access to and use of the data and address buses by the
different components of the system does not lead to conflict. The purpose of the control bus
is to transmit command, timing and specific status information between system components.
Timing signals indicate the validity of data and address information. Command signals
specify operations to be performed. Specific status signals indicate the state of a data transfer
request, or the status of request by a components to gain control of the system bus.
The data bus, typically consisting of 8, 16, or 32 separate lines provides a bi-directional path
for moving data and instructions between system components. The width of the data bus is a
key factor in determining overall system performance. For example, if the data bus is 8 bits
wide, and each instruction is 16 bits long, then the processor must access the main memory
twice during each instruction cycle.
Address bus: When the processor wishes to read a word (say 8, 16, or 32 bits) of data from
memory, it first puts the address of the desired word on the address bus. The width of the
address bus determines the maximum possible memory capacity of the system. For example,
if the address bus consisted of only 8 lines, then the maximum address it could transmit
would be (in binary) 11111111 or 255 – giving a maximum memory capacity of 256
(including address 0). A more realistic minimum bus width would be 20 lines, giving a
memory capacity of 220, i.e. 1Mb.
Von Neumann is a very successful architecture, but it has its problems.

First problem is that every piece of data and instruction has to pass across the data bus in
order to move from main memory into the CPU (and back again). This is a problem because
the data bus is a lot slower than the rate at which the CPU can carry out instructions. This is
called the 'Von Neumann bottleneck'. If nothing were done, the CPU would spend most of its
time waiting around for instructions. A special kind of memory called a 'Cache' (pronounced
'cash') is used to tackle with this problem. OS tries to fetch block of memory to cache, in a
wake to fetch further required instruction or data beforehand.
Second problem is both data and programs share the same memory space.
This is a problem because it is quite easy for a poorly written or faulty piece of code to write
data into an area holding other instructions, so trashing that program.
Another problem is that the rate at which data needs to be fetched and the rate at which
instructions need to be fetched are often very different. And yet they share the same
bottlenecked data bus. To solve the problem idea of the Harvard Architecture is considered
that to split the memory into two parts: One part for data and another part for programs. Each
part is accessed with a different bus. This means the CPU can be fetching both data and
instructions at the same time. There is also less chance of program corruption. This
architecture is sometimes used within the CPU to handle its caches, but it is less used with
RAM because of complexity and cost.
2.2.2 Parallel processing schemes
Von Neumann architecture is a sequential processing machine but if we could process more
than one piece of data at the same time? This would dramatically speed up the rate at which
processing could occur. This is the idea behind 'parallel processing'. Parallel processing is the
simultaneous processing of data. There are a number of ways to carry out parallel processing;
the table below shows each one of them and how they are applied in real life.
Parallel Processing Systems are designed to speed up the execution of programs by dividing
the program into multiple fragments and processing these fragments simultaneously.
Flynn's Classification
In 1966, Michael Flynn proposed a classification for computer architectures based on the
number of instruction steams and data streams (Flynn’s Taxonomy). Flynn uses the stream
concept for describing a machine's structure. A stream simply means a sequence of items
(data or instructions).
 SISD (Singe-Instruction stream, Singe-Data stream):- SISD corresponds to the

traditional mono-processor (von Neumann computer). A single data stream is being
processed by one instruction stream A single-processor computer (uni-processor) in
which a single stream of instructions is generated from the program.
 SIMD (Single-Instruction stream, Multiple-Data streams):- Each instruction is
executed on a different set of data by different processors i.e multiple processing units
of the same type process on multiple-data streams. This group is dedicated to array
processing machines. Sometimes, vector processors can also be seen as a part of this
group.
 MISD (Multiple-Instruction streams, Singe-Data stream):- Each processor
executes a different sequence of instructions. In case of MISD computers, multiple
processing units operate on one single-data stream. In practice, this kind of
organization has never been used.
 MIMD (Multiple-Instruction streams, Multiple-Data streams):- Each processor
has a separate program. An instruction stream is generated from each program. Each
instruction operates on different data. This last machine type builds the group for the
traditional multi-processors. Several processing units operate on multiple-data streams
Types of parallel processing schemes
Type Class of computers Application

Pipeline Single Instruction Single Inside a CPU
Data (SISD)
Array Processor Single Instruction Graphics cards, games
Multiple Data SIMD consoles
Multi-Core Multiple Instruction Super computers, modern

Multiple Data MIMD multi-core chips
Advantages of parallel processing over the Von Neumann architecture

• Faster when handling large amounts of data, with each data set requiring the same
processing (array and multi-core methods)
• Is not limited by the bus transfer rate (the Von Neumann bottleneck)
• Can make maximum use of the CPU (pipeline method) in spite of the bottleneck
Disadvantages
• Only certain types of data are suitable for parallel processing. Data that relies on the result
of a previous operation cannot be made parallel. For parallel processing, each data set must
be independent of each other.
• More costly in terms of hardware - multiple processing blocks needed, this applies to all
three methods
1. Pipelining
Using the Von Neumann architecture for a microprocessor illustrates that basically an
instruction can be in one of three phases. It could be being fetched (from memory), decoded
(by the control unit) or being executed (by the control unit). An alternative is to split the
processor up into three parts, each of which handles one of the three stages. This would result
in the situation shown in Fig. 2.2, which shows how this process, known as pipelining, works
with each single line is a pipeline: Fetch, Decode, Execute.
Fig 2.2 Pipelining scheme
This helps with the speed of throughput unless the next instruction in the pipe is not the next
one that is needed. Suppose Instruction 2 is a jump to Instruction 10. Then Instructions 3, 4
and 5 need to be removed from the pipe and Instruction 10 needs to be loaded into the fetch
part of the pipe. Thus, the pipe will have to be cleared and the cycle restarted in this case. The
result is shown in Fig. 2.3
Fig 2.3 Pipelining cycle

The effect of pipe lining is that there are three instructions being dealt with at the same time.
This SHOULD reduce the execution times considerably (to approximately 1/3 of the standard
times), however, this would only be true for a very linear program. Once jump instructions
are introduced the problem arises that the wrong instructions are in the pipe line waiting to be
executed, so every time the sequence of instructions changes, the pipe line has to be cleared
and the process started again.
2 Array/Vector processing scheme

Some types of data can be processed independently of one another. A good example of this is
the simple processing of pixels on a screen. If you wanted to make each coloured pixel a
different colour according to what it currently holds. For example "Make all Red Pixels
Blue", "Make Blue Pixels Red", "Leave Green pixels alone".
A sequential processor would examine each pixel one at a time and apply the processing
instruction. But you can also arrange for data such as this to be an array. The simplest array is
called a '1 dimensional array' or a 'vector'. A slightly more complicated array would have
rows and columns. This is called a '2 dimensional' array or 'matrix'. The matrix is
fundamental to graphics work.
An array processor (or vector processor) has a number of Arithmetic Logic Units (ALU) that
allows all the elements of an array to be processed at the same time. The illustration Fig. 2.4
below shows the architecture of an array or vector processor
Fig. 2.4 Array or Vector processing scheme
With an array processor, a single instruction is issued by a control unit and that instruction is
applied to a number of data sets at the same time. An array processor is a Single Instruction
Multiple Data computer or SIMD. You will find games consoles and graphics cards making
heavy use of array processors to shift those pixels about.
Limitations
This architecture relies on the fact that all data sets are acting on a single instruction.
However, if these data sets somehow rely on each other then you cannot apply parallel
processing. For example, if data A has to be processed before data B then you cannot do A
and B simultaneously. This dependency is what makes parallel processing difficult to
implement. And it is why sequential machines are still extremely common
3 Multiple Processor Schemes

Moving on from an array processor, where a single instruction acts upon multiple data sets
and the next level of parallel processing is to have multiple instructions acting upon multiple
data sets. This is achieved by having a number of CPUs being applied to a single problem,
with each CPU carrying out only part of the overall problem.
Fig 2.5 Multiple processor schemes
A good example of this architecture is a supercomputer. For example the massively parallel
IBM Blue Gene supercomputer that has 4,098 processors, allowing for 560 Tera-Flops of
processing. This is applied to problems such as predicting climate change or running new
drug simulations. This is where larger problems that can be broken down into smaller chunks
and processed separately.
But even the humble CPU chip in your personal computers is likely to have multiple cores.
For example the Intel Core Duo has two CPUs (called 'cores') inside the chip, whilst the Quad
core has four. A multi-core computer is a 'Multiple Instruction Multiple Data' computer or
MIMD.
Limitations of multi-core processing:

This architecture is dependent on being able to cut a problem down into chunks, each chunk
can then be processed independently. But not many problems can be broken down in this way
and so it remains a less used architecture.
Furthermore, the software programmer has to write the code to take advantage of the multi-
core CPUs. This is actually quite difficult and even now most applications running on a
multi-core CPU such as the Intel 2 Duo will not be making use of both cores most of the
time.
Math co-processor
So far, we have discussed parallel processing as a means of speeding up data processing. This
is fine but it does make an assumption that the Arithmetic Logic Unit (ALU) within the CPU
is perfect for handling all kinds of data. And this is not always true. There are two basic ways
of doing calculations within a CPU that is integer math which only deal with whole numbers
and floating point math which can deal with decimal or fractional numbers.
Large-number ranges are best handled as 'floating-point'. Handling floating point numbers
efficiently requires wide registers to deal with a calculation in one go. And the CPU architect
may not want to dedicate precious hardware space in his CPU for these wider registers So the
idea of a 'Math co-processor' came about. A co-processor is especially designed to carry out
floating point calculation extremely quickly. It co-exists with the CPU on the motherboard.
Whenever a floating point calculation needs to be done, the CPU hands the task over to the
co-processor then carries on with doing something else until the task is complete. The
advantage of having a co-processor is that calculation (and hence performance) is much
faster. The disadvantage is that it is more expensive, requires more motherboard space and
takes more power.
But if the computer is dedicated to handling heavy floating point work then it may be worth
it. For instance a computer within a signal processing card in a communication system may
include a math co-processor to process the incoming data as quickly as possible.
Lesson 3
Microprocessor Overview
3.1 Introduction
Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable
of performing ALU (Arithmetic Logical Unit) operations and communicating with the other
devices connected to it.
Microprocessor consists of an ALU, register array, and a control unit. ALU performs
arithmetical and logical operations on the data received from the memory or an input device.
Register array consists of registers identified by letters like B, C, D, E, H, L and accumulator.
The control unit controls the flow of data and instructions within the compute
The term microprocessor came into existence in 1971, when the Intel Corporation developed
the first microprocessor (Intel-4004) which is a 4-bit microprocessor. The 4004 was not very
powerful; it was primarily used to perform simple mathematical operations in a calculator.
An 8-bit processor followed in 1972 and the development has progressed up to the present
64-bit microprocessors. The modern microprocessors can perform extremely sophisticated
operations, and take up much less space as well as delivering superior performance.

3.2.1 Differentiate between microprocessor and microcontroller.
3.2.2 Give an overview of the organization of microprocessor.
3.2.1 Difference between Microprocessor and Microcontroller

The terms microprocessor and microcontroller have always been confused with each other.
Both of them have been designed for real time application. They share many common
features and at the same time they have significant differences. Both the IC’s i.e., the
microprocessor and microcontroller cannot be distinguished by looking at them.
Microprocessor find applications where tasks are unspecific like developing software, games,
websites, photo editing, creating documents etc. In such cases the relationship between input
and output is not defined. They need high amount of resources like RAM, ROM, I/O ports
etc. The clock speed of the microprocessor is quite high as compared to the microcontroller.
Whereas the microcontrollers operate from a few MHz to 30 to 50 MHz, today’s
microprocessor operate above 1GHz as they perform complex tasks.
Microprocessor
Microprocessor (Fig 3.1 (a)) is an IC which has only the CPU inside them i.e. only the
processing powers such as Intel’s Pentium 1, 2, 3, 4, core 2 duo, i3, i5, i7 etc. A more formal
definition is: a microprocessor is a multipurpose, programmable, clock-driven, register-based
electronic device that reads binary instructions from a storage device called memory, accepts
binary data as input and processes the data according to those instructions, and provides
results as output. These microprocessors don’t have RAM, ROM, and other peripheral on the
chip. A system designer has to add them externally to make them functional.
Microprocessor Microcontroller
(a) (b)
Fig.3.1: (a) A Microprocessor and (b) a Microcontroller
A microprocessor is specified by its word size, e.g. 4-bit, 8-bit, 16-bit etc. The term word size
means the number of bits of data that can be processed by the microprocessor as a unit. It also
specifies the width of the data bus. Thus a 4-bit microprocessor has a word length of 4 bits
and so forth. Application of microprocessor includes:
Microcontroller
Microcontroller has a CPU, in addition to a fixed amount of RAM, ROM and other
peripherals all embedded on a single chip, as shown in Fig 6.1 (b). At times it is also termed
as a mini computer or a computer on a single chip. Unlike a general-purpose computer, which
also includes all of these components, a microcontroller is designed for a very specific task -
to control a particular system. Specific means applications where the relationship of input and
output is defined. Depending on the input, some processing needs to be done and output is
delivered.
How does a Microprocessor Work?
The microprocessor follows a sequence: Fetch, Decode, and then Execute. Initially, the
instructions are stored in the memory in a sequential order. The microprocessor fetches those
instructions from the memory, then decodes it and executes those instructions till STOP
instruction is reached. Later, it sends the result in binary to the output port. Between these
processes, the register stores the temporarily data and ALU performs the computing
functions.
Terms Used in a Microprocessor
Here is a list of some of the frequently used terms in a microprocessor −
 Instruction Set − It is the set of instructions that the microprocessor can understand.
 Bandwidth − It is the number of bits processed in a single instruction.
 Clock Speed − It determines the number of operations per second the processor can
perform. It is expressed in megahertz (MHz) or gigahertz (GHz).It is also known as
Clock Rate.
 Word Length − It depends upon the width of internal data bus, registers, ALU, etc.
An 8-bit microprocessor can process 8-bit data at a time. The word length ranges from
4 bits to 64 bits depending upon the type of the microcomputer.
 Data Types − The microprocessor has multiple data type formats like binary, BCD,
ASCII, signed and unsigned numbers.
Salient features of a Microprocessor
Here is a list of some of the most prominent features of any microprocessor −
 Cost-effective − The microprocessor chips are available at low prices and results its
low cost.
 Size − The microprocessor is of small size chip, hence is portable.
 Low Power Consumption − Microprocessors are manufactured by using metaloxide
semiconductor technology, which has low power consumption.
 Versatility − The microprocessors are versatile as we can use the same chip in a
number of applications by configuring the software program.
 Reliability − The failure rate of an IC in microprocessors is very low, hence it is
reliable.
A microprocessor can be classified into three categories −
1. RISC Processor
RISC stands for Reduced Instruction Set Computer. It is designed to reduce the execution
time by simplifying the instruction set of the computer. Using RISC processors, each
instruction requires only one clock cycle to execute results in uniform execution time. This
reduces the efficiency as there are more lines of code, hence more RAM is needed to store the
instructions. The compiler also has to work more to convert high-level language instructions
into machine code.
Some of the RISC processors are −
 Power PC: 601, 604, 615, 620

 DEC Alpha: 210642, 211066, 21068, 21164
 MIPS: TS (R10000) RISC Processor
 PA-RISC: HP 7100LC
Architecture of RISC
RISC microprocessor architecture uses highly-optimized set of instructions. It is used in
portable devices like Apple iPod due to its power efficiency.
Characteristics of RISC
The major characteristics of a RISC processor are as follows −
 It consists of simple instructions.

 It supports various data-type formats.
 It utilizes simple addressing modes and fixed length instructions for pipelining.
 It supports register to use in any context.
 One cycle execution time.
 “LOAD” and “STORE” instructions are used to access the memory location.
 It consists of larger number of registers.
 It consists of less number of transistors.
2. CISC Processor
CISC stands for Complex Instruction Set Computer. It is designed to minimize the number
of instructions per program, ignoring the number of cycles per instruction. The emphasis is
on building complex instructions directly into the hardware.
The compiler has to do very little work to translate a high-level language into assembly level
language/machine code because the length of the code is relatively short, so very little RAM
is required to store the instructions.
Some of the CISC Processors are −
 IBM 370/168
 VAX 11/780
 Intel 80486
Architecture of CISC
Its architecture is designed to decrease the memory cost because more storage is needed in
larger programs resulting in higher memory cost. To resolve this, the number of instructions
per program can be reduced by embedding the number of operations in a single instruction.
Characteristics of CISC
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 Variety of addressing modes.
 Larger number of instructions.
 Variable length of instruction formats.
 Several cycles may be required to execute one instruction.
 Instruction-decoding logic is complex.
 One instruction is required to support multiple addressing modes.
3. Special Processors
These are the processors which are designed for some special purposes. Few of the special
processors are briefly discussed −
Coprocessor
A coprocessor is a specially designed microprocessor, which can handle its particular

function many times faster than the ordinary microprocessor.
For example − Math Coprocessor.
Some Intel math-coprocessors are −
 8087-used with 8086

 80287-used with 80286
 80387-used with 80386
Input/Output Processor
It is a specially designed microprocessor having a local memory of its own, which is used to
control I/O devices with minimum CPU involvement.
For example −
 DMA (direct Memory Access) controller

 Keyboard/mouse controller
 Graphic display controller
 SCSI port controller
Transputer (Transistor Computer)
A transputer is a specially designed microprocessor with its own local memory and having
links to connect one transputer to another transputer for inter-processor communications. It
was first designed in 1980 by Inmos and is targeted to the utilization of VLSI technology.
A transputer can be used as a single processor system or can be connected to external links,
which reduces the construction cost and increases the performance.
For example − 16-bit T212, 32-bit T425, the floating point (T800, T805 & T9000)
processors.
DSP (Digital Signal Processor)
This processor is specially designed to process the analog signals into a digital form. This is
done by sampling the voltage level at regular time intervals and converting the voltage at that
instant into a digital form. This process is performed by a circuit called an analogue to digital
converter, A to D converter or ADC.
A DSP contains the following components −
 Program Memory − It stores the programs that DSP will use to process data.
 Data Memory − It stores the information to be processed.
 Compute Engine − It performs the mathematical processing, accessing the program
from the program memory and the data from the data memory.
 Input/Output − It connects to the outside world.
Its applications are −
 Sound and music synthesis

 Audio and video compression
 Video signal processing
 2D and 3d graphics acceleration.
3.2.2 Organization of a Microprocessor
A computer, large or small, can be represented functionally (in a simplified form) by the
block diagram in Figure. 3.2. As shown, it comprises of three basic parts or sub-systems:
1. Microprocessor/processing unit
2. Storage/Memory
3. Input/output devices
Fig 3.2 Block diagram of microprocessor
1. Central Processing Unit (CPU)

It performs the necessary arithmetic and logic operations and controls the timing and general
operation of the complete system.
2. Input/Output (I/O) Devices

Input devices are used for feeding data into the CPU, examples of these devices are toggle
switches, analog-to-digital converters, paper tape readers, card readers, keyboards, disk etc.
The output devices are used for delivering the results of computations to the outside world;
examples are light emitting diodes, cathode ray tube (CRT) displays, digital-to-analog
converters, card and paper-tape punches, character printers, plotters, communication lines etc.
The input-output subsystem thus allows the computer to usefully communicate with the
outside world.
Input-output devices are also called as peripherals.

3. Memory
It stores both the instructions to be executed (i.e., the program) and the data involved. It
usually consists of both RAMs (random-access memories) and ROMS (read-only memories).
A microprocessor is an integrated circuit designed to function as the CPU of a
microcomputer.
What is inside a microprocessor?

The microprocessor or CPU reads each instruction from the memory decodes it and executes
it. It processes the data as required in the instructions. The processing is in the form of
arithmetic and logical operations. The data is retrieved from memory or taken from an input
device and the result of processing is stored in the memory or delivered to an appropriate
output device, all as per the instructions.
To perform all these functions, the µP (microprocessor) incorporates various functional units
in an appropriate manner. Such an internal structure or organizational structure of µP, which
determines how it operates, is known as its architecture.
Typical microprocessor architecture is shown in Figure 3.3. The various functional units are
as follows:
Fig 3.3 Microprocessor Architecture
Busses
Microcomputer, like all computers, manipulates binary information. The binary information
is represented by binary digits, called bits. µC operates on a group of bits which are referred
to as a word. The number of bits making-µP a word varies with the µP. Common word sizes
are: 4, 8, 12 and 16 bits (µPs with 32 bit-word have also of late entered the market). Another
binary terms that will be of interest in subsequent discussions are the byte and the nibble,
which represent a set of 8 bits and 4 bits, respectively.
Figure 3.3 shows busses interconnecting various blocks. These busses allow exchange of
words between the blocks. A bus has a wire or line for each bit and thus allows exchange of
all bits of a word in parallel. The processing of bits in the µP is also in parallel. The busses
can thus be viewed as data highways. The width of a bus is the number of signal lines that
constitute the bus.
The figure shows for simplicity three busses for distinct functions. Over the address bus, the
µP transmits the address of that I/O device or memory locations which it desires to access.
This address is received by all the devices connected to the processor, but only the device
which has been addressed responds. The data bus is used by the µP to send and receive data
to and from different devices (I/O and memory) including instructions stored in memory.
Obviously the address bus is unidirectional and the data bus is bi-directional. The control bus
is used for transmitting and receiving control signals between the µP and various devices in
the system.
Arithmetic-Logic Unit (ALU)

The arithmetic-logic unit is a combinational network that performs arithmetic and logical
operations on the data.
Internal Registers
A number of registers are normally included in the microprocessor. These are used for
temporary storage of data, instructions and addresses during execution of a program. Those in
the Intel 8085 microprocessor are typical and are described below:
(i) Accumulator (Acc) or Result Register
This is an 8-bit register used in various arithmetic and logical operations. Out of the two
operands to be operated upon, one comes from accumulator (Acc), whilst the other one may
be in another internal register or may be brought in by the data bus from the main memory.
Upon completion of the arithmetic/logical operation, the result is placed in the accumulator
(replacing the earlier operand). Because of the later function, this register is also called as
result register.
(ii) General Purpose Registers or Scratch Pad Memory

There are six general purpose 8-bit registers that can be used by the programmer for a variety
of purposes. These registers, labelled as B, C, D, E, H and L, can be used individually (e.g.
when operation on 8-bit data is desired) or in pairs (e.g., when a 16-bit address is to be
stored). Only B-C, D-E and H-L pairs are allowed.
(iii) Instruction Register (IR)

This 8-bit register stores the next instruction to be executed. At the proper time this stored
word (instruction) is fed to an instruction decoder which decodes it and supplied appropriate
signals to the control unit. When the execution has been accomplished the new word in the
instruction register is processed.
(iv) Program Counter (PC)

This is a 16-bit register which holds the address of the next instruction that has to be fetched
from the main memory and loaded into the instruction register. The program controlling the
operation is stored in the main memory and instructions are retrieved from this memory
normally in order. Therefore, normally the address contained in the PC is incremented after
each instruction is fetched. However, certain classes of instruction can modify the PC so that
the programmer can provide for branching away from the normal program flow. Examples
are instructions in the “jump” and ‘call subroutine’ groups.
(v) Stack Pointer (SP)

This is also a 16-bit register and is used by the programmer to maintain a stack in the memory
while using subroutines.
(vi) Status Register or Condition Flags

A status register consisting of a few flip-flops, called as condition flags (in 8085 the number
of flags is five) is used to provide indication of certain conditions that arise during arithmetic
and logical operations. These are:
 ZF ‘zero’ Flag is set if result of instruction is 0.
 SF ‘sign’ Set if MSB of result is 1.
 PF ‘parity’ Set if result has even parity.
 CF ‘carry’ Set if carry or borrow resulted.
 AF ‘auxiliary carry’ Set if instruction caused a carry out of bit 3 and into bit 4 of the
resulting value.
(vii) Dedicated Registers
Several other registers are incorporated in the µP for its internal operation. They cannot be
accessed by the programmer and hence do not concern much a µP user.
Instruction Decoder and Control Unit

It decodes each instruction and under the supervision of a clock controls the external and
internal units ensuring correct logical operation of the system.
Memories
As mentioned earlier, memories are required in a microprocessor for storing information
which may comprise of:
(a) the data to be used for computation,
(b) instructions and
(c) computational results.
A program starts as a set of instructions on a paper, and then this is transferred to a set of
cards with the instructions punched in code on them. These instructions also can be
transferred to magnetic tape, paper tape or directly into semiconductor memory which is the
eventual storage space for a program. The semiconductor memory chips are connected to the
µP through the address bus, data bus and control bus. (This is also the way that I/O devices
are connected to the µP). See Figure 3.4
Fig 3.4 Connection of I/O Devices and Memory
Memory Classes
Memories may be broadly divided into two classes:
(a) Random Access Memory (RAM) or Read/Write Memory (RWM)
(b) Read only Memory (ROM)
Random Access Memory (RAM) or Read/Write Memory (RWM)

There is provision in RAMs (RWMs) for writing information into the memory and reading it
when the microcomputer is in operation. It is, therefore, used to store information which
changes or may change during the operation of the system, viz. data for calculations and
results of calculations. It is also used to store the programs which are to be changed
frequently. Semiconductor RAM is a volatile memory.
A RAM can be of static or dynamic type. Dynamic RAMs have higher packing densities, are
faster and consume less power in the quiescent state. However, because of external refreshing
circuitry requirement, the dynamic RAMs are profitable only in large sizes.
Read-Only Memory (ROM)

The ROM functions as a memory array whose contents once programmed, is permanently
fixed and cannot be altered by the microprocessor while the system is operating. It is non-
volatile. ROMs exist in many forms.
(i) Mask ROM : It is custom programmed or mask programmed when manufactured and
cannot be altered thereafter. The cost of a custom built mask for programming is so high that
thousands of ROMs storing the same information must be produced to pay for the mask.
(ii) Programmable ROM (PROM): This type is programmable by the user (typically by
electrically overheating fusible links in selected manner). Once programmed, the contents
cannot be altered. The memory may be programmed one at a time by the user and is thus
suitable for the cases where small quantities of a ROM are needed.
(iii) Electrically Alterable ROM (EAROM): In this type of memory, the contents can be
electrically erased (by applying a large negative voltage to control gates of memory cells) and
the memory can be then reprogrammed (by applying a large positive voltage to control
gates). This type is convenient when the user is not sure of the program and may wish to
modify it. This is a typical requirement in prototype development.
(iv) Erasable Programmable ROM (EPROM): Like EAROM, this type of memory can
also be erased and reprogrammed. However, erasing is by exposing the memory chips to high
intensity ultra-violet light of a wavelength close to 2537 Å. It has the same application filed
as the EAROM.
Peripheral interfacing
Functions
When one or more I/O devices (peripherals) are to be connected to a microprocessor, an
interface network for each device, called peripheral interface, is required.
The interface incorporates commonly the following four functions:
(a) Buffering: Which is necessary to take care of incompatibility between the µP and the
peripheral.
(b) Address Decoding: Which is required to select one of the several peripherals connected in
the system.
(c) Command Decoding: Required for peripherals that perform actions other than of data
transfers.
(d) Timing and Control: All the above functions require timing and control.
Data Transfer
Data exchange or transfers which occur between a peripheral device and the µC fall into one
of the following two broad categories:
(i)Programmed Data Transfer

A software routine residing in memory requests the peripheral device for data transfer to or
from the µP. Generally, the data is transferred to or from the accumulator though in some
µPs, others internal registers may also participate in the transfer.
Programmed data transfers are generally used when a small amount of data is transferred with
relatively slow I/O devices, e.g., A/D and D/A converters, peripheral multiplier, peripheral
floating point arithmetic unit etc. In these cases, usually one word of data is transferred at a
time.
(ii)Direct Memory Access (DMA) Transfer or Cycle Stealing Transfer

In this mode, the data transfer is controlled by the peripheral device. The µP is forced to hold
on by an I/O device until the data transfer between the device and the memory is complete.
Since the data control transfer is controlled entirely by hardware, the interface is more
complex than that required for a programmed data transfer. DMA transfer is used when a
large block of data is to be transferred, for example, for transferring data from peripheral
mass storage devices like the floppy disk and high-speed card reader.
Microprocessor software and program languages

The foregoing was a brief account of the µC hardware and now follows a concise picture of
the µC software. A sequence of instructions designed to perform a particular task in a
computer is known as the program and a set of programs written for a computer-based system
is called software for that system.
Programming Languages
(i)Machine Language (ML)

Since a machine (computer) can handle (i.e., store and process) information in binary form
only, the instruction (program) must be finally encoded in binary for feeding to the machine.
A program in this form is thus in machine language.
(ii)Assembly Language (AL)

In an assembly language programme, the instructions including the storage locations are
represented by alphanumeric symbols, called mnemonics. It is relatively easier to write a
programme in assembly language than in machine language. However, if written in AL, it
must be translated to ML before it can be stored and executed in µC. Mostly one statement in
AL translates to one instruction in ML.
(iii)High-Level Language (HLL)

Programming in AL is very tedious and time consuming. High Level languages like Fortran,
Cobol, Algol, Pascal and PL/M can be used for programming and then the program translated
into ML program. One statement in HL generally corresponds to several ML instructions.
Software Tools
(i) Assembler
It is a computer program that translates an AL program to ML program (also called object
code). A cross assembler is an assembler that is executed on a machine other than the one for
which it is producing the ML program. A self-assembler or resident assembler, on the other
hand, is meant to be run on the machine for which ML program is required to be produced.
(ii) Compiler
A compiler is a computer program that translates a HLL program to ML program (object
code). Like the assembler, the compiler can be a cross compiler or a self (resident) compiler.
(iii) Editor
During the process of program entry into the memory or debugging, it may be necessary to
make changes in the program text in order to correct any errors or modify the logic. An editor
helps the programmer to do this.
(iv) System Monitor

All single board microprocessors, design kits and µP development systems have system
monitor as an integrated component. The monitor (a ML program) resides in ROM. It helps a
programmer in performing such functions as entering a program into memory, getting a
program executed, modifying contents of one or more memory locations or µP registers,
displaying the contents of any memory location of a register in the µP, entering ML program
in convenient hexadecimal format, etc.
Microcomputer instruction set

The instruction set of a microprocessor will typically comprise of five groups of instructions:
(i) Data Transfer Group

These instructions help to move data between registers within the microprocessor, between a
register and a memory location or between memory locations.
(ii) Arithmetic Group

Instructions in this group adds, subtract increment or decrement data in registers or in
memory (e.g., an instruction to add the contents of two registers within the microprocessor).
(iii) Logical Group

These are used to AND, OR, EXCLUSIVE-OR, Compare, rotate or complement data in
registers or in memory (e.g., OR the contents of two registers within the microprocessor).
(iv) Branch Group

This group includes conditional and unconditional jump instructions, subroutine-call
instructions and return-from-subroutine instructions. A conditional instruction specifies that a
certain operation be performed only if a certain condition has been met (e.g., jump to a
particular instruction if the result of the last operation was zero). Conditional instructions
provide decision making capability in programs.
(v) Stack, I/O and Machine Control Group

This group of instructions performs data transfer between the microprocessor and I/O
devices, manipulates the stack and alters internal control flags. These instructions make it
possible for the programmer to halt the microprocessor, put it in a “no operation” state,
enable/disable its interrupt system and so on.
Instructions, which are stored along with data in the memory, may be one or more bytes in
length. Multiple byte instructions are stored in successive memory locations: the address of
the first byte is always used as the address of the instruction. Also, the first byte is always the
operation code (abbreviated as OPCODE).
Lesson four
Microprocessor based systems
4.1 Introduction
Computer systems have undergone many changes recently. Machines that once filled large
areas have been reduced to small desktop computer systems because of the microprocessor
they possess computing power that was only dreamed of a few years ago. Million-dollar
mainframe computer systems, developed in the earlier are not as powerful as the Pentium
icore-based computers of today
The Microprocessor based system (single board microcomputer) consists of microprocessor

as CPU, semiconductor memories like EPROM and RAM, input device, output device and
interfacing devices. The memories, input device, output device and interfacing devices are
called peripherals. In the microprocessor-based system, the microprocessor is the master and
all other peripherals are slaves. The master controls all the peripherals and initiates all
operations. To perform a specific job or task, the microprocessor has to execute a program
stored in memory. The program consists of a set of instructions. It issues address and control
signals and fetches the instruction and data from memory. The instruction is executed one by
one internal to the processor and based on the result it takes appropriate action.

 Describe the major functional units of a microprocessor-based system
4.2.1 Microprocessor based systems

Fig.4.1 shows a simplified but formal structure of a microprocessor-based system. The main
parts of this system are memory and the processor. In subsection, we will discuss the memory
and the paths witch the processor uses to communicate with devices connected to it. It will be
left as an e-tivity to the student to explain the functions of the constituent parts of the
processor.
Fig. 4.1: A microprocessor-based system
Components of Microprocessor-based systems
1. Register Array:
Register array is group of registers. Register array contains general purpose registers and
special purpose registers. It is used for temporary storage of data.
2. Instruction Decoding Unit:
Instruction decoding unit decodes the instruction. In order to execute (perform) the operation,
all data should be decoded. The processor cannot perform the execution, if data are not
decoded.
3. Arithmetic and Logic unit
All the arithmetic and logic operations are performed with respect to ALU. The execution is
taken inside the ALU.
4. Timing and Control Unit:
In order to perform all the operations, some predefined timing period is required. That is,
with respect to the time period, the processor will works. The control unit releases the control
signal. Control Signal provides control to both the processor and to the peripheral devices.
5. Flag Register:
Flag register is very near to ALU. “Flag register keeps the status of the last operation”. That
is, by the help of flag register, the processor can understand the status of the last operation.
Processor cannot access the data directly from the flag register.
In 8086 Processor, all the general purpose and special purpose registers except decoding
registers are 16 bit registers.
Program Counter (PC)/ Instruction Pointer (IP):
Instruction pointer will store the address of the next instruction to be executed. That is, the
address of the next instruction to be executed is stored in PC.
In 8086, PC is a 16 bit register. This means that, in 8086, 20 address lines are used. So the
8086 has 16-bit registers and 20 address lines.
6. System bus
System bus – It is a communication path between the microprocessor and peripherals. The
microprocessor communicates with only one peripheral at a time. The timing is provided by
the control unit of the microprocessor.
7. Memory and Address/ Data Lines
Memory
Memory stores such binary information as instructions and data, and provides that
information to the processor whenever necessary. There are two types of memory; Read-Only
memory (ROM) and Read/Write memory (R/WM) or Random Access Memory (RAM).
ROM is used to store programs that do not need alterations. The RAM is used to store user
programs and data.
Memory Terminology
a) Memory Cell: A device or an electrical circuit used to store a single bit (0 or 1).
Examples of memory cells include flip-flop, a charged capacitor, and a single spot on
a magnetic tape or disk.
b) Bit: Abbreviation for binary digit, e.g. 1001 is a binary number with 4 bits.
c) Memory word: A group of bits (cells) in a memory that represents instructions or
data of some type.
d) Byte: A group of eight bits
e) Capacity: the total number of data units that can be stored. Consider the diagram of
Fig.6.3
Fig.4.2: A 64-cell memory array

This memory stores 8 words each of 8 bits; therefore it is an 8 x 8 memory array. So the
capacity of this memory is 8 x 8 = 64 bits. Suppose we have a memory that can store 4096
20-bit words, this represents a total of 4096 x 20 = 81920 bits. We could express this memory
capacity as 4096 x 20. When expressed like this, 4096 is the number of words and 20 is the
number of bits per word.
Some Prefixes used with Memory

1. 210 = 1024: kilo K
2. 220 = 1048576: mega M
3. 230 = 1073741824: giga G
4. 240 = 1099511627776 tera T
5. ……………etc.
Thus a 4K x 20 is (4 x 1024) words x 20, i.e. 4096 x 20, which means 4096 words each of 20
bits. A memory of 2M x 8 is actually (2 x 1048576) x 8 = 2097152 x 8 or 2097152 words
each of 8 bits.
Address and Data Lines

An address is a pattern of 0’s and 1’s that represents a specific location in memory or a
particular I/O device. Recalling that a bit can have a value of 0 or 1, two address lines can
produce a pattern from 00 to 11, shown as follows:
00 0
01 1
10 2
11 3
2
Thus, there are 4 (2 = 4) locations which can be identified by two address lines, as illustrated
in Fig 6.4. Each of the 4 locations can store 8 bits; hence 8 data lines are required.
Fig.4.3: A 2-address line memory registers with input and output buffers
Three address lines can be used to address 8 (23) memory locations as follows:
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Fig. 6.5 shows a memory with 3 address lines; which can address 8 memory locations
(registers, Rn). The RD/ and the WR/ lines determine whether the memory performs a read or
a write operation, respectively.
Fig.4.4: Memory of 3 address lines, 8 data lines and 8 registers
The 8085 microprocessor has 16 address lines. If all these lines are connected to a single
memory device, it will decode these 16 address lines internally and produce different
addresses from 0000H to FFFFH so that each location in the memory will have a unique
address. The unique patterns from 00000000000000000 to 111111111111111111, represent
65536 different address combinations, or 64K memory locations.
Example 4.1
How many address lines are required to address a memory chip of 256 registers (Locations)?
Solution
2 x  256
By taking logs of both sides
x log 2 2  log 256
log 2 256
x 8
log 2 2
Example 4.2
Calculate the number of address lines required for an 8K-byte memory. How many data lines
does this memory have?
Solution
Memory locations = 8 x 1024 = 8192
Therefore 2  8192
x
Taking logs (base 2) of both gives 13 address lines

Since it is organized as a byte memory, it has 8 data lines
Lesson 5
The 8085 Microprocessor Architecture
5.1 Introduction

5.2.1 Explain the functions of various pins of the 8085.
5.2.2 Describe the internal organization the 8085 and be able to draw the functional block
diagram of the 8085.
5.2.1 PIN arrangement of the 8085 microprocessor.
The 8085A (popularly known as 8085) is a conventional von Neumann design based on the
Intel 8080. It is designed by using nMOS technology, and includes on its chip most of the
logic circuitry for performing computing tasks and for communicating with peripherals. It has
an 8-bit data bus and a 16-bit address bus. The device has 40 pins, a +5V power supply, and
operates on a 3 to 5 MHz frequency single phase clock. The "5" in the model number came
from the fact that the 8085 requires only a +5-V power supply, rather than requiring the +5 V,
−5 V and +12 V supplies the 8080 needed.
The 8085A uses a multiplexed data bus. The address is split between the 8-bit address bus
and the 8-bit data bus. It is capable of decimal, binary, and double precision arithmetic. It has
a direct addressing capability to 64K bytes of memory.
Fig.5.1: (a) The 8085 Microprocessor pin-out diagram (b) the Intel 8085 chip
Fig. 5.1 shows the logic pin-out and chip of the 8085 microprocessor. To use the 8085 in a
microprocessor-based system, it is useful to know what each pin does. The pins in the 8085
microprocessor pin diagram can be grouped into 6 categories:
1. Power supply & frequency
2. Serial I/O ports
3. Externally initiated & acknowledgement signals
4. Data bus
5. Address bus
6. Control & Status bus
The functions of each pin in these broad categories will be left to the student as an e-tivity
exercise.
5.2.2 The Internal Organization the 8085

Fig. 7.2 shows the internal architecture of the 8085 microprocessor which consists of five
functional units:
 Arithmetic and logic Unit
 General purpose registers
 Special Purpose Registers
 Instruction register and decoder,
 Timing and control unit.
Arithmetic and Logic Unit

As has already explained in lesson 4, the ALU carries out arithmetic and logic operations.
The ALU also handles all data manipulation, such as shift left/right, rotate, and the 2’s
complement operations. The contents of the accumulator and the temporary register are the
inputs to the ALU. Thus, the ALU of the 8085 is called an accumulator-oriented ALU as one
of the data for arithmetic and logic operations must be stored in the accumulator.
Temporary Register
This 8-bit register stores the operands of arithmetic-logic operations. For instance, during an
ADD C the contents of the C register are copied in the temporary register during one T state
and added during another T state. This register is one of the inputs of the ALU.
Fig.5.2: The 8085 Microprocessor: Functional Block Diagram
General Purpose Registers
The general purpose registers are used to store only the data that is used by the currently
running program or the results obtained from the currently running program. These general
purpose registers are user accessible by programs. Registers B, C, D, E, H and L are the
general purpose registers of 8085 as shown in Fig 5.3. They can be combined as register
pairs: BC, DE, and HL to perform some 16-bit operations. When used as a pair the C, E and
L registers contain the low-order byte. Among these pairs, HL has a special significance. A
few memory related instructions of 8085 (refer instruction set) use the HL pair as a memory
pointer. For example, the instruction “MOV A, M” transfers the content of memory location
pointed by the HL pair to accumulator. The HL pair is pre-loaded with the memory address in
which data is available.
Special Purpose Registers

As shown in Fig. 5.3, there are also special purpose registers that are dedicated to a specific
function. The Accumulator, flag register, Program Counter (PC) and Stack Pointer (SP)
constitute the special registers in the 8085 Microprocessor.
Fig.5.3: General purpose registers and special purpose registers
Accumulator
It is an 8 bit register which stores the results of arithmetical and logical operations. It is also
used to receive data from input port to microprocessor and to send data to output port from
microprocessor. The accumulator, which is a part of the ALU, is referred to as register A in a
program. The result of an arithmetic operation is stored in the accumulator.
Flags
The ALU includes five flip-flops, which keep track of the changing conditions during a
microprocessor run. Each bit of the flag register is quite independent of each other, unlike in
all other registers, where each bit is just part of a single binary byte value and hence each bit
would have a numerical value. They are set or reset according to data conditions of the result
in the accumulator and other registers. They are called Zero (Z), carry (CY), Sign (S), Parity
(P), and Auxiliary carry (AC) flags. The bit positions reserved for these five flags, in the flag
register are shown in Fig.5.4.
Fig.5.4: 8085 flag register
S: S is set to 1 when the accumulator contents become negative during the execution
of some instructions, otherwise reset to zero. (Also, after an ALU operation, if the
most significant bit of the result is 1, then sign flag is set).
Z: The zero flag is set to 1, if the ALU or logic operation result in a zero and it is reset if
the result is non-zero.
AC: When an instruction causes a carry or carry is generated by digit D3 and passed on
to digit D4 the AC flag is set to 1, otherwise it remains reset to 0.This flag has
critical importance in the decision-making process of the microprocessor. This highly
specialized flag bit is tested by the DAA instruction to adjust the value of AL after a
BCD addition or subtraction. The auxiliary carry flag is, not free to the programmer.
P: Parity is logic 0 for odd parity and logic 1 for even parity. Parity is the count
of 1s in a number, and is expressed as even or odd. The flag is set to 1 if the result of
an arithmetic or logical operation has an even number of 1s. If it has an odd number
of 1s, the flag is reset to 0.
CY: When the result of an arithmetic operation results in a carry or a borrow out of the
higher order bit, the CY flag is set to 1, otherwise remains 0.
Program Counter (PC)

It is a16-bit register which contains the 16-bit address of the memory location of the next
instruction. The function of the program counter is to point to the memory address from
which the next byte is to be fetched. When a byte (machine code) is being fetched, the
program counter is incremented by one to point to the next memory location.
Memory Address Register (Address Buffer and Address/Data Buffer)
Holds address, received from PC, of next program instruction. It feeds the address bus with
addresses of location of the program under execution.
Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in the R/W memory, called the stack. The beginning of the stack is defined by
loading a 16-bit address in the stack pointer. Stack is a part of memory which is used to store
data temporarily, especially in the execution of subroutines or functions.
Instruction Register/Decoder
It is an 8-bit register which usually offers a temporary store for the current instruction of a
program. Latest instruction sent here from memory prior to execution. The content of the
register is decoded by the decoder circuitry, where the nature of the operation to be
performed is decided (interpreted). The internal machine command is interpreted to decide
the next course of action. Decoded instruction is then passed to next stage. In addition, there
are two temporary registers W and Z which are controlled internally and not available for
user access. These registers are used to hold 8-bit data during execution of some instructions.
Timing and Control

Generates signals within the microprocessor to carry out the instruction, which has been
decoded. In reality causes certain connections between blocks of the microprocessor to be
opened or closed, so that data goes where it is required, and so that ALU operations occur.
The timing and control section includes an oscillator and a controller-sequencer.
Lesson 6
The 8085 Instructions
6.1 Introduction
Efficient software development for the microprocessor requires a complete familiarity with
the addressing modes employed by each instruction. A set of instructions make a program,
whereby the instructions are commands to the microprocessor to perform an operation. The
addressing modes and instruction classification for the 8085 microprocessor will be
discussed.

6.2.1 State the different addressing modes of the 8085.
6.2.2 Explain the classification of instructions according to their operation and size
6.2.1 Addressing modes of the 8085

An instruction in the 8085 microprocessor will have the format shown in Fig 8.1.
Fig.6.1: Instruction format
Op Code (Operation Code) is the operation to be performed, while the operand is the data or
memory location. The operand can be specified in various ways, which may include:
 8-bit or 16-bit data
 An internal register
 Memory location
 8-bit (or 16-bit) address
The various formats for specifying operands are called the addressing modes. The 8085 has
five addressing modes which will be discussed in the following subsections:
Register Addressing
Data is provided through the registers.
Example 6.1
MOV Rd, Rs
MOV B, A; copy contents of A to B
ADD B; Add B to A
Indirect Addressing
Whenever an instruction uses the HL pointer, the addressing is called indirect addressing.
The address is stored in the HL register pair.
Example 6.2
MOV reg, M, where reg = A, B, C, D, E, H, or L and M = MHL. The instruction says to load
the specified register with the data addressed by HL. For example, MOV B, M; load register
B with the data found in the address in MHL.
Direct Addressing
This addressing mode is used to accept data from external devices and store it in the
accumulator or send the data stored in the accumulator to the outside device. In this
addressing mode, address of the operand is specified in the instruction itself.
Example 6.3
OUT 01H ; send from acc to port 01
IN 00H ; Accept from port 00 and load into acc
Immediate Addressing
Data is present in the instruction and is loaded to the destination provided. In this mode of
addressing, the data follows the op-code and is part of the instruction itself.
Example 6.4
MVI A, 09H, the 8-bit data 09H in the instruction is moved to register A.
Implied Addressing
The location of the data is contained within the op-code itself. For instance, RAL tells us to
rotate the accumulator bits left. The data is in the accumulator; this is why no operand is
needed with implied addressing.
6.2.2 Classification of 8085 microprocessor Instructions
An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The 8085 has 246 instructions with each instruction represented by an 8-bit binary
value, called Op-Code or Instruction Byte. The entire group of instructions is called an
instruction set. The instructions are classified according to what they do or according to their
word size. We discuss classification in the following subsections:
Data Transfer (copy) Instructions

These operations simply copy the data from the source to the destination.
The instructions perform the following six operations.
 Load an 8-bit number in a register
 Load a16-bit number in a register pair
 Copy from register to register
 Copy between register and memory
 Copy between I/O and accumulator
 Copy registers and stack memory
The 8085 provides an instruction to place a 16-bit data into a register pair in one step.
LXI Rp, <16-bit address> (Load eXtended Immediate).
For example, the instruction LXI B 4000H will place the 16-bit number 4000 into the register
pair B, C. The upper two digits are placed in the 1st register of the pair and the lower two
digits in the 2nd.
Other instructions such as: MOV, MVI, LDA, and STA are illustrated by example 6.5.
Examples 6.5
MOV A,B
MOV is the mnemonic for move. It tells the computer to move data from one register to
another. The operation is nondestructive, meaning that the data in B is copied but not erased.
Arithmetic Instructions
These instructions perform mathematical operations like add, subtract, increment, and
decrement.
Addition (ADD, ADI): Any 8-bit number, the contents of a register, or the contents of a
memory location can be added to the contents of the accumulator and the result is stored in
the accumulator. No two other 8-bit registers can be added directly.
Example 6.6
Suppose register A = 04H and register B = 02H, what are the contents of the accumulator
after the execution of ADD B
Solution This instruction adds the contents of B to the contents of the accumulator and stores
the answer in the accumulator, therefore A = 06H
Arithmetic Operations Related to Memory

These instructions perform an arithmetic operation using the contents of a memory location
while they are still in memory. For example, ADDM adds the contents of M to the
Accumulator.
SUBM subtracts the contents of M from the contents of the Accumulator
INR M / DCR M increment/decrement the contents of the memory location in place. All of
these use the contents of the HL register pair to identify the memory location being used.
Increment (INR) and decrement (DCR): The 8-bit contents of any memory location or any
register can be directly incremented or decremented by 1.
Examples 6.7
ADD B or ADD M; Add register or memory to accumulator
The contents of register or memory are added to the contents of accumulator.
 The result is stored in accumulator.
 If the operand is a memory location, its address is specified by H-L pair.
 All flags are modified to reflect the result of the addition.
Example 6.8
ADD B means to add contents of the register B to the accumulator. If A = 04H and B = 02H,
then the execution of ADD B results in A = 06H
Logical Instructions
These instructions perform logical operations on the contents of the accumulator. Some of the
logical operations are:
 AND
 OR
Source: Accumulator and An 8-bit number, or the contents of a register, or the contents of a
memory location
Destination: Accumulator
Example 6.9
ANA B or ANA M; Logical AND register or memory with accumulator
 The contents of the accumulator are logically ANDed with the contents of register or
memory.
 The result is placed in the accumulator.
 If the operand is a memory location, its address is specified by the contents of H-L
pair.
 S, Z, P are modified to reflect the result of the operation.
 CY is reset and AC is set.
ANA B means to AND the contents of the accumulator with the contents of the register B.
Example 6.10
Suppose the two registers contain: A = 1100 1100 and B = 1111 0001, what are the contents
of A after the execution of the instruction ANA B?
Solution: A = 1100 0000

Notice that the ANDing is bitwise.
Branching Instructions
The branching instruction alters the normal sequential flow either unconditionally or
conditionally.
(a) Unconditional branch; Go to a new location irrespective of the outcome of an
operation.
JMP Address; Jump to the address specified (Go to).
CALL Address; Jump to the address specified but treat it as a subroutine.
RET; Return from a subroutine.
The addresses supplied to all branch operations must be 16-bits.
(b) Conditional branch; Go to a new location if a specified condition is met.
Examples 6.11
The following are some conditional instructions
 JZ Address; (Jump on Zero): Go to address specified if the Zero flag is set.
 JC Address; (Jump on Carry): Go to the address specified if the Carry flag is set.
 JP Address; (Jump on Plus): Go to the address specified if the Sign flag is not set
Example 6.12
This example demonstrates an unconditional instruction
JMP 3000H tells the microprocessor to get the next instruction from memory location
30000H. Suppose this instruction is stored at 2005H; at the end of the fetch cycle, the
program counter contains 2006H, i.e. PC = 2006H
2005H JMP 3000H
3000H
During the execution cycle, the JMP 3000H loads the program counter with PC = 3000H. At
the beginning of the next fetch cycle, the next instructions comes from 3000H (and not
2006H)
Machine Control Instructions

These instructions control the operation of the microprocessor. Some examples are: NOP; the
instruction is fetched and decoded but no operation is executed (Exactly as it says, do
nothing). Usually used for delay or to replace instructions during debugging.
HLT; The CPU finishes executing the current instruction and halts any further execution. An
interrupt or reset is necessary to exit from the halt state.
Classification of an Instruction According to the Word Size

One-byte Instruction
A 1-byte instruction includes the opcode and the operand in the same byte.
Example 6.13
Op Code Operand Hex Code Comment
MOV C, A 4FH Copy contents of A into C
ADD B 80H Add contents of B to the
contents of A
In the first instruction, both operand register are specified while in the second, the operand B
is specified and the accumulator is assumed.
Two-byte Instruction
The first byte specifies the opcode while the second byte specifies the operand.
Example 6.14
Op Code Operand Hex Code Comments
MVI A, 32H 3E Load an 8-bit byte into A
32 Two memory locations required
Three-byte Instructions
The first byte specifies the opcode, and the next two bytes specify the 16-bit address.
Example 6.15
Op Code Operand Hex Code Comment
LDA 2050H 3A load contents of memory location
50 2050H into A
20
These instructions would require three memory locations each to store the binary codes.
Lesson 7
The Stack and Subroutines
7.1 Introduction
The stack holds data temporarily and stores the return addresses used by subroutines. The
stack memory is a last-in, first-out (LIFO) memory, which describes the way that data are
stored and removed from the stack. Data are placed onto the stack with a PUSH instruction
and removed with a POP instruction. The CALL instruction also uses the stack to hold the
return address for subroutines and a RET (return) instruction to remove the return address
from the stack.

7.2.1 Define the stack and subroutines and explain their uses.
7.2.2 Describe the sequence of events that place data onto the stack or remove data from the
stack.
7.2.1 The Stack and Subroutines

The stack is a group of memory locations in the R/W memory that is used for temporary
storage of binary information during the execution of a program. The starting memory
location of the stack is defined in the main program, and space is reserved, usually at the high
end of the memory. Given that the stack grows backwards (or upwards like a stack of plates,
on reducing memory) into memory, that it is why it is usual to place the bottom of the stack at
the end of memory to keep it as far away from user programs as possible.
The instructions that read and write into the stack are called stack instructions; they include
PUSH, POP, and CALL. Stack instructions use indirect addressing because a 16-bit register
holds the address of the desired memory address.
The beginning of the stack is defined in the program by using the immediate load instruction
LXI SP, data, which loads a 16-bit memory address in the stack pointer register of the
microprocessor. Once the stack location is defined, storing of data bytes begins at the
memory address that is one less than the address in the stack pointer register.
Example 7.1
Where will the storing of data start when stack pointer is loaded with memory address
2500H, using the instruction: LXI SP, 2500H?
Solution
The storing of data bytes begins at 24FFH and continues in decreasing order as shown in
Fig. 7.1 As a general practice, the stack is initialized at the highest available memory
location.
Stack Instructions
The instructions that read and write into the stack are called stack instructions. They include
PUSH and POP which are important instructions that store and retrieve data from the LIFO
stack memory. Data can be stored (written) on the stack using the instruction PUSH, while
the instruction POP transfers (reads) data from the stack.
Fig.7.1: Stack area as defined by LXI SP, 2500H
Example 7.2
Suppose SP = 2500 H and HL = 5678H, illustrate the state of the stack after the execution of
PUSH H
Solution 56 H will be loaded to memory location 24FF H and 78 H will be loaded to 24FE H
memory location as shown in Fig. 9.2. At the end of this instruction the stack pointer, SP
contains 24FE H.
Fig.7.2: Contents of the stack after the PUSH H instruction
Subroutine
A subroutine is a group of instructions that will be used repeatedly in different locations of a
program to perform a function that occurs in the main program. Rather than repeat the same
instructions several times, they can be grouped into a subroutine that is called from the
different locations. In Assembly language, a subroutine can exist anywhere in the code.
However, it is customary to place subroutines separately from the main program.
Subroutine Instructions
The 8085 microprocessor has two instructions to implement subroutines: CALL (call a
subroutine), and RET (return to main program from subroutine). The CALL is in the main
program, and RET at the end of a subroutine. The address of the subroutine program is
specified with the CALL instruction. When a CALL<address> instruction is executed, the
contents of the program counter (PC) are pushed onto the stack. Then the starting address of
the subroutine is loaded into the program counter. The next instruction fetched is the first
instruction of the subroutine. On completion of the subroutine, a RET instruction POPs the
return address off the stack into the program counter and returns control to the instruction that
immediately follows the CALL in a program when a RET instruction executes. Although the
CALL instruction is a branching instruction, it differs from the jump instruction in that a
CALL saves a return address on the stack. A few examples follow:
1. Unconditional Call Instructions

CALL address ; Calls the addressed subroutine program
This is the format for unconditional call instruction which is of three bytes.
2. Conditional Call Instructions

Similar to conditional jump instruction, it has the following conditional instructions.
(i) CNZ address ; Call if not zero
This instruction will call the subroutine program specified by the address provided the zero
flag is reset.
(ii) CZ address ; Call if zero)
It will call the subroutine (specified by the address) if zero fags is set.
7.2.2 Movement of data in stacks
Example 7.3 will be used to illustrate how the stack and the related instructions work.
Example 7.3
Study the following program and explain how it works
Address Instruction
2000H LXI SP, 2100H
2001H
2002H
2003H CALL 8050H
2004H
2005H
2006H MVI A,0EH
.
.
200AH HLT
.
.
8050
.
.
8059 RET
Solution The LXI loads the stack pointer with 2100H. During the execution of CALL 8050H,
the address of the next instruction is saved in the stack. This address (2006H) is pushed into
the stack as shown in Fig 9.3(a)
(a) (b)
Fig. 7.3: (a) Saving a return address during a subroutine call (b) Popping the return address
during a RET
The program counter is then loaded with 8050H, the starting address of the subroutine. When
the subroutine is completed, the RET instruction takes the processor back to the main
program as follows:
i) The low byte is popped from the stack into the lower half of the program
counter; then the high byte is popped from the stack into the upper half of the
program counter (Fig. 9.3b).
ii) After the second increment, the stack pointer is back at 2100H. The process is
summarized in Fig. 9.4
CALL 8050H
2006 MVI A, 0EH
8050H
RET
Fig.7.4: CALL and RET instruction
Note: The stack operation is automatic during a CALL or a RET instruction. All we have to
do is to initialize the setting of the stack pointer; this is the purpose of LXI SP,dble
instruction. It sets the upper boundary of the stack. The CALL automatically pushes the
return address onto the stack, and RET automatically POPs this return address off the stack.
Lesson 8
Introduction to 8085 Programs
8.1 Introduction
Microprocessors recognize and operate on unique mnemonics developed for a given
processor. A program called an assembler translates the mnemonics into the corresponding
binary machine codes of the processor. In this chapter, we put into practice what we have
learnt in the previous chapters so that we write simple 8085-based assembly language
programs.

8.2.1 Design, write and hand assemble programs
8.2.1 Write and Hand Assemble Programs

Depending on the complexity of the problem to be solved, all or part of the following steps
will be useful designing and writing programs:
1. State the problem
2. Divide the problem into small steps
3. Draw a flow chart
4. Write assembly language program
5. Convert assembly language program to Hex Code
A program may contain some or all of the following fields:
 Identifier/Label: name used to reference items in a program
 Operation code: the task to be performed
 Operand: the data (or memory to be accessed) to be operated on
 Comments: they increase readability and help in understanding the program
Example 8.1
Find the Hex code for the following instructions, identify the opcodes, operands, and show
the order of entering the codes in memory.
a) STA 2050H b) JNZ 2070H
Solution
a) Hex code = 32 50 20. Opcode = STA, Operand = 2050H
Hex code = C2 70 20. Opcode = JNZ, Operand = 2070H
Example 8.2
Store the number D5H in register B
Solution
Mnemonics M/C code Operands Comments
MVI B, D5H 06 B, D5H move D5 into reg B
D5
HLT 76 Halt the process
Example 8.3
Write a program to load two hexadecimal numbers 32H and 48H in registers A and B,
respectively. Add the numbers, and display the sum at the LED output port PORT1.
Solution
Problem analysis
1. Load the numbers in the registers
2. Add the numbers
3. Display the sum at the output port PORT1
A suitable flow chart is shown in Fig. 10.1
Fig.8.1: Flow chart for adding two numbers (b) common flow chart symbols
The translation of each block in the flow chart into mnemonics is as follows:
Block1 MVI A, 32H Load register A with 32H
MVI B, 48H Load register B with 48H
Block 2 ADD B Add two bytes and save sum in A
Block 3 OUT 01H Display accumulator contents at port 01H
Block 4 HALT End
Hand Assembling
To convert the mnemonics of example 10.3 into hex code, we need to look up the code in the
8085 instruction set; this is called manual or hand assembly. To hand-assemble means to
translate a source program into machine-language program by hand rather than machine.
Mnemonics Hex Code

MVI A, 32H 3E 2-byte instruction
32
MVI B, 48H 06 2-byte instruction
48
ADD B 80 1-byte instruction
OUT 01H D3 2-byte instruction
01
HLT 76 1-byte instruction
Example 8.4
Hand-assemble the following program starting from 2000H
MVI A, 49H
MVI B, 4AH
MVI C, 4BH
STA 6285H
HLT
Solution
Address Hex code Mnemonics
2000H 3EH MVI A, 49H
2001H 49H
2002H 06H MVI B, 4AH
2003H 4AH
2004H 0EH MVI C, 4BH
2005H 4BH
2006H 32H STA 6285H
2007H 85H
2008H 62H
2009H 76H HLT
Example 8.5
Load the hexadecimal 9BH and A7H into registers D and E, respectively, and add the
numbers. If the sum is greater than FFH, display 01H at output PORT0; otherwise, display
the sum. You are given that the R/W memory begins at 2000H
Solution
The problem can be divided into the following steps (Algorithm):
i) Load the numbers in the registers
ii) Add the numbers
iii) If sum > FFH display 01, otherwise display the sum
iv) End
These steps can be converted into a flow chart, as shown in Fig. 10.2
Fig. 8.2: A flow chart to test the carry flag
Address Hex code Label Mnemonics

2000H 16H START MVI D,9BH
2001H 9BH
2002H 1EH MVI E,A7H
2003H A7H
2004H 7AH MOV A,D
2005H 83H ADD E
2006H D2H JNC DISPLAY
2007H X
2008H X
2009H 3EH MVI A, 01H
200AH 01H
200BH D3H DSPLAY OUT 00H
200CH 00H
200DH 76H HLT
Memory locations 2007H and 2008H have been left blank because the exact location of the
transfer is not known; what is known is that two bytes should be reserved for the 16-bit
address. After completing the straight line sequence, we know the memory address of the
label DSPLAY, as 200BH. This address is placed in the reversed order, i.e.
2007 0B Low-order
2008 20 High-order
Lesson 9
Introduction to 8088/8086
9.1 Introduction
It is a semiconductor device consisting of electronic logic circuits manufactured by using

either a Large Scale Integration (LSI) or Very Large Scale Integration (VLSI) Technique. It
includes the ALU, register arrays and control circuits on a single chip. The microprocessor
has a set of instructions, designed internally, to manipulate data and communicate with
peripherals. The era microprocessors in the year 1971, the Intel introduced the first 4-bit
microprocessor is 4004. Using this the first portable calculator is designed. The 16-bit
Microprocessor families are designed primarily to complete with microcomputers and are
oriented towards high-level languages. They have powerful instruction sets and capable of
addressing megabytes of memory. The era of 16-bit Microprocessors began in 1974 with the
introduction of PACE chip by National Semiconductor. The Texas Instruments TMS9900
was introduced in the year 1976. Intel 8086 was commercially available in the year 1978,
Zilog Z800 in the year 1979, Motorola MC68000 in the year 1980. The 16-bit
Microprocessors are available in different pin packages. Ex: Intel 8086/8088 40 pin package
Zilog Z8001 40 pin package, Digital equipment LSI-II 40 pin package, Motorola MC68000
64 pin package National Semiconductor NS16000 48 pin package.
The primary objectives of this 16-bit Microprocessor can be summarized as follows.

1. Increase memory addressing capability
2. Increase execution speed
3. Provide a powerful instruction set
4. Facilitate programming in high-level languages.

9.2.1 Describe Intel 8088/8086 microprocessor fundamentals and functional units
9.2.1 Intel 8088/8086 Microprocessor Fundamentals
The 8086/8088 refers to microprocessors developed by Intel Corporation, which was used by
IBM personal computers (XT, 1981). 8088 and 8086 are functionally identical (8-bit cpu)
except that 8088 uses 8 dada lines in its data bus while 8086 uses 16 data lines in its data bus.
Fundamental components of 8086/8088

The 8086/8088 microprocessor consists of four functional units.
1) Execution unit (EU): decodes and executes machine instructions.
2) Arithmetic and logic unit (ALU): performs math and logical operations on command
by the EU.
3) Bus interface unit (BIU): handles all communications with the I/O via the system bus
and maintains instruction queue.
4) Internal storage (sometime called registers): is used for internal data storage.
1. Execution Unit (EU)
The Execution Unit controls the activity within the processor. It is responsible for retrieving
binary machine-language instructions from the Instruction Queue maintained by the Bus
Interface Unit deciphering them, and seeing to it that the correct steps are performed within
the processor to carry out each instruction. If an instruction requires the use of data that is
stored internally, in a register, then the Execution Unit retrieves the data from the correct
register; if the instruction requires external data, from memory perhaps, then the EU requests
the data from the Bus Interface Unit.
Whenever an instruction calls for an arithmetic or logical function, the EU passes the data to
Arithmetic and Logic Unit together with a command telling the ALU what to do with the
data. The EU then accepts the resulting data from the ALU and sees to it that it is stored into
correct location (register or memory), as designated by the instruction.
2. Arithmetic and Logic Unit (ALU)

The ALU contains circuitry that is capable to perform arithmetic (+, -, *, /) operations and
logic operations (AND, OR, NOT, XOR) operations. As the ALU completes a requested
operation, it also controls individual bits of Flags register (sometimes called the program
status register). It sets (1) or clear (0) the correct bits to reflect specific characteristics of the
result of the operation, such as whether the result was zero or non-zero, whether it was
positive or negative, or if the result is too big to be stored in a byte or word. The EU checks
the status of those Flag bits whenever executing conditional jump instructions.
3. Bus Interface Unit (BIU)

BIU is a circuitry to response memory access and communicate with I/O devices. In most
microprocessors, these functions are performed by EU, and sometimes the EU has to be idle
due to different speed and serial execution.
In the design of the 8086/8088, Intel introduces BIU in order to avoid idle time and hold an
instruction queue such that instructions can be executed in a pipeline fashion.
System Bus
The System Bus is a series of conductive traces of signal lines on the system board, which is
used to communicate between 8086/8088 (cpu) and all other devices.
The system bus is made up of three functional parts:

1) Data bus
2) Address bus
3) Control bus
In order to build a complete computer, there are a number of other hardware devices (chips in
the computer. Some of them are:
To read from memory, for example, the Bus Interface Unit puts the correct memory address
onto the Address Bus and puts the command to read from memory onto the Control Bus. All
devices connected to the bus see this address and command simultaneously, but only the
memory-control circuitry respond to it. The memory-control circuitry is then responsible for
decoding the address, retrieving the data from the appropriate memory chips, and placing the
data onto the Data Bus for retrieval by the BIU.
To write to memory, the BIU puts the memory address onto the Address Bus, the byte of data
onto the Data Bus, and a command to write data onto memory of the control bus. The
memory-control circuitry decodes the command and the address, retrieves the data from the
Data Bus, and stores it into the correct memory chips. All other circuitry simply ignores the
command.
8086/8088 Memory I/O port1 I/O port N

BIU
System bus
Communication with the many special-purpose microprocessors attached to the System Bus
is accomplished through I/O ports. I/O ports are used for the transfer of data between the
8086/8088 processor and the other support hardware within the system. The In and OUT
instructions tell the processor to input or output data through the I/O ports.
When executing an IN instruction, the BIU puts the I/O port address onto the Address Bus
and puts the command to input data onto the Control Bus. The circuitry on some peripheral
device attached to the bus recognizes the red command and decodes the I/O port as the
address of some register within the peripheral device. It then retrieves the data from the
register and places it onto the Data Bus from which it is retrieved by the BIU and fed to the
Execution Unit within the processor.
To execute an OUT instruction, the BIU puts the command to output data onto the Control
Bus, and I/O address onto the Address Bus, and the data to be output onto the Data Bus. The
circuitry of a peripheral device is then responsible for recognizing the output command and
the I/O address and for retrieving the data from the data bus.
4. Memory and Internal Storage
1. Storage Elements
 Bits: The smallest storage element on any computer is the bit, which can have a value
of 0 or 1.
 Nibbles: A nibble is a sequence of 4 bits.
e.g.
1 1 0 1
bit 3 bit 0
 Bytes: A byte is a sequence of 8 bits.
e.g.
1 0 1 0 1 1 0 1
bit 7 bit 0
 Words: in 8086/8088, a word consists of 16 bits that can be viewed as:
1) A horizontal sequence of 16 bits or.
e.g.
1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1
bit 15 bit 0
2) A vertical sequence of 2 bytes e.g..
1 0 1 0 1 1 0 1
bit 15 bit 8
1 0 1 0 1 1 0 1
bit 7 bit 0
Note: in memory, the least significant bye (bits 0-7) is stored in lower numbered
memory location, and the most significant byte (bits 8-15) is stored in the next
higher numbered location.
 Double words: Two words represents a double word which is viewed as

1) A horizontal sequence of 32 bits or
2) A vertical sequence of 2 words or
3) A vertical sequence of 4 bytes
Note: in memory, its 0-7 bits would come first; bits 8-15 would be in the next higher
numbered byte and so on.
 Quadword: A quadword is 2 double words, hence 4 words or 8 bytes.
 Tenbytes: A tenbyte is a sequence of 10 bytes.
2. Memory
Computer memory consists of an ordered sequence of storage units (8-bits called bytes), each
with its own address.
 8086/8088’s memory is bytes-addressable, which means that each byte has its own
address, e.g. if A is the address of a word (16 bits), then A is actually the address of
the first byte (bits 0-7) of the word, A+1 is the address of the second byte (bits 8-15)
of the word, and A+2 is the address of the next word.
 Memory address space: (MAS): 220= 1,048,576= 1M(bytes) (address space: 0—220- 1,
i.e.00000-fffff: in hexadecimal)
 Map of the memory address space (MAS)
The whole MAS is organized by a 216 * 24 matrix: there are 216 paragraphs, each of
which with 16 (24) bytes.
Paragraph numbers:
0000 0001
0002
FFFE
FFFF
00000 00001 0000E 0000F

… … …
00010 00011 00C1E 0001F
… … …
00020 00021 0002E 0002F
… … …
. . . .
. . . .
. . . .
FFFE0 FFFE1 FFFEE FFFEF
FFFF0 FFFF1 FFFFE FFFFF

…
…
Figure 1: Map of the memory address space (MAS) of the 8086/8088.
 Hexadecimal number system
The hexadecimal number system uses sixteen characters to represent umbers:0
through 9 and A through F; A is worth ten, B is worth eleven, …, and F is fifteen. In
assembly program, the hexadecimal will be indicated by the letter h.
Example: 7Fh is the number 127(7*16+15*1) and its equivalent binary number is
01111111b.
The conversion between binary and hexadecimal is simple. To covert from
hexadecimal to binary: just represent each hexadecimal digit by four binary digits:
Example: 74Dh = 011101001101b
To convert from binary to hexadecimal: break the binary number into groups of four
digits, and convert each group into one hexadecimal digit:
Example: 101001001110b = A4Fh
 Character representation
Each character is represented by a byte or two hexadecimal digits according to ASCII
code.
For example: ASCII code Letter
41h A
42h B
. .
. .
5Ah Z
61h a
62h b
. .
. .
7Ah z
30h 0
. .
. .
39h 9
In assembly the ASCII representation of character can be defined by enclosing the
characters in paired single (‘) or double (“) quotes.
Example: ‘A’ ‘e’ “9”
Note ‘A’ = 41h, ‘a’ = 61h and “9” = 39h
 Segment-relative addresses.
1) There are 16 bits in a segment register. The content of the segment register
represents the paragraph number of the paragraph at which it begins.
2) All memory address are formed by segment-relative format which is computed
as follows:
Absolute address=(segment register)*16 + offset (16-bit) denoted by segment
register: where the offset can be content of a register (16-bit) and a 16-bit
value. e.g. where CS is the code segment register, IP is the instruction pointer
register
CS: 1110000000000000
CS*16: 11100000000000000000 (Beginning of code segment)
IP: 0000000000001101 (offset)
--------------------------------------------------------------------------
CS : IP = 11100000000000001101 (Actual location (absolute
address) in memory)
3. Program stack
A program stack is a region of memory (RAM), which is defined by the assembly program.
The program stack is implemented by setting the SS (stack segment) register and by
initializing the SP (stack pointer) register to the byte immediately above the top of the sack
segment. Data is moved onto the stack in word- sized units by an operation called a push and
retrieved from the stack in word-sized units by an operation called pop in the reversed order
(last in- first out).
A Push operation decrements the SP register twice (-2) and put the word at SS : SP. A Pop
operation retrieves the word at SS: SP and increments the SP register twice (+2)
Figure 2: Stack operations
Example: A program stack is to use 100h bytes and SS= 58A1h, A = 1234h and B = 5678h.
Figure 3 shows the “empty” stock, where the initial value of SP register = 100h and the
stack starts at address of 58A10h and ends at address of 58B0Fh (100 bytes). Figure 4
shows the stack after two Push operations: Push A and Push B, and Figure 5 shows the
stack after two Pushes and one Pop operation (Pop B).
Figure 3: Empty stack

Figure 4: Stack after two Pushes
Figure 5: Stack after two Pushes and one Pop
4. Internal Storage (Registers)

Registers: there are 14 registers, each 16 bits (bits 0-15) in length. 14 registers are divided
into five groups:
1) Four data registers
2) Four segment registers
3) The instruction pointer register
4) Two pointer and two index registers
5) The flag register (status register)
Figure 6: Register Map of 8086/8088
1. Data registers
There are four 16-bit data registers that are used to store data.
1) Accumulator: AX (used for arithmetic and logic instruction).
2) Base register: BX (stored data)
3) Count register: CX (is altered by the loop instruction).
4) Data register: DX (used for multiply and divide instructions).
An “X” register can be subdivided into a high part (H, 8-15 bits) and a low part (L, 0-7bits).
 AX Register: Accumulator register consists of two 8-bit registers AL and AH, which
can be combined together and used as a 16- bit register AX. AL in this case contains
the low-order byte of the word, and AH contains the high-order byte. Accumulator
can be used for I/O operations, rotate and string manipulation.
 BX Register: This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment. It is used as offset storage for
forming physical address in case of certain addressing mode.
 CX Register: It is used as default counter - count register in case of string and loop
instructions.
 DX Register: Data register can be used as a port number in I/O operations and
implicit operand or destination in case of few instructions. In integer 32-bit multiply
and divide instruction the DX register contains high-order word of the initial or
resulting number.
AX AH AL
BX BH BL
CH CL
CX
DH DL
DX
15 8 7 0
2. Segment registers
The 8086/8088 has four separate “work area” for the parts of an assembly language program:
data, instruction, stack and extra data. Each area is called a segment and has a register to
associate with called segment register. Each segment can be up to 65,536 bytes, and two
segments my overlap.
1) Data segment register (DS): indicates the beginning of the data segment.
2) Code segment register (CS): indicates the beginning of the code segment.
3) Stack segment register (SS): the stack is a part of memory. The stack is only word-
addressable.
4) Extra data segment register (ES): points to the beginning of the extra data
3. The instruction pointer (IP)

The instruction pointer (IP) contains the offset address in the code segment of the next
instruction to be executed. The absolute address of the next instruction = CS: IP.
4. Pointer and index registers

The segment registers point to the beginning of the various memory segments. The point
registers are used to calculate offsets (displacements) into these segments. The pointers are
contained within the particular segments.
The pointers IP, BP, SP usually contain offsets within the code, data and stack segments
respectively
A stack is a pile or list of items that can be accessed one at a time and from only one end,
usually the items are removed from the top and added to the top. Thus, the stack is also called
last-in first-out (LIFO) list. In8086/8088, the stack is implemented by a segment of the
memory; each item is a 16-bit word (2 bytes). There are two registers associated with stack:
SS and SP.
There are two pointer registers in a stack:

3) Stack pointer (SP)
4) Base pointer (BP)
Stack Pointer (SP)
Stack pointer (SP) is a 16-bit register pointing to program stack in stack segment. SP is used
to hold the current stack location. SS contains the address of the beginning of the stack
segment and SP contains the offset.
There are two basic stack operations in 8086/8088.
 PUSH (operand) it decreases the SP by 1 word (2 bytes), then stores a word on the
stack e.g. current SP=204. AX=0010. Execution of PUSH AX will result: SP=204-
2=202 and store 0010 at memory location at address 202.
 POP (operand it removes the top word from the stack, and then add 1 word (2 bytes)
to the SP.
Base Pointer (BP)

Base pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing. BP can also be used to point to
offset within stack segment. Primarily it is used for base indexed addressing modes.
Index registers
There are two index registers:
(a) Source index register (SI)
(b) Destination index register (DI)
There is no significance to the words source and destination, and SI and DI can be used
interchangeably. Index registers are used in the same way subscripts that are used in high-
level language. That enables us to access the elements in an array or table.
Destination Index (DI) and/or Source Index (SI) is a 16-bit register. DI/SI is used for
indexed, based indexed and register indirect addressing, as well as a destination data addresses
in string manipulation instructions.
5. Status register
In 8086/8088 the status register is called the flag register. The flag register contains
information about the most recently executed instruction. There are 16 bits in register. But
only bits 0, 2, 4 and 6-11 are used
1) CY (bit 0): the carry flag.

2) PF (bit 2): the parity flag.
3) AF (bit 4): the auxiliary flag.
4) ZF (bit 6): the zero flag.
5) SF (bit 7): the sign flag.
6) TF (bit 8): the trap flag.
7) IF (bit 9): the interrupt flag.
8) DF (bit 10): the direction flag.
9) OF (bit 11): the overflow flag.
Flags Register determines the current state of the processor. They are modified automatically
by CPU after mathematical operations, this allows to determine the type of the result, and to
73
determine conditions to transfer control to other parts of the program. The 8086 flag register
as shown in the fig 1.5. 8086 has 9 active flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
Conditional Flags
 Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.
 Auxiliary Flag (AC): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is not a
general-purpose flag; it is used internally by the Processor to perform
Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If lower
order 8-bits of the result contains even number of 1’s, the Parity Flag is set
and for odd number of 1’s, the Parity flag is reset.
 Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is
zero else it is reset.
 Sign Flag (SF): In sign magnitude format the sign of number is indicated
by MSB bit. If the result of operation is negative, sign flag is set.
Control Flags
Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:
 Trap Flag (TF): It is used for single step control. It allows user to execute
one instruction of a program at a time for debugging. When trap flag is set,
program can be run in single step mode.
 Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the
maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared by
executing CLI instruction.
 Direction Flag (DF): It is used in string operation. If it is set, string bytes are
accessed from higher memory address to lower memory address. When it is reset,
the string bytes are accessed from lower memory address to higher memory
address.
74
Lesson 10
The 8086/8088 Instructions
10.1 Introduction
Efficient software development for the microprocessor requires a complete familiarity with
the addressing modes employed by each instruction. A set of instructions make a program,
whereby the instructions are commands to the microprocessor to perform an operation. The
addressing modes and instruction classification for the 8086/8088 microprocessor will be
discussed.

10.2.1 State the different addressing modes of the 8086/8088.
10.2.2 Explain the classification of instructions according to their operation and size
10.2.1 Addressing modes of the 8086/8088

An instruction in the 8086/8088 microprocessor will have the format shown in Fig 10.1
Fig 10.1 8086/8088 Instruction format
The op-code register direction bit (D) and data size bit (W) in byte 1 are defined by Intel as
follows:
 Op code occupies six bits and it defines the operation to be carried out by the
instruction.
 Register Direction bit (D) occupies one bit. It defines whether the register operand in
byte 2 is the source or destination operand.
o D = 1 specifies that the register operand is the destination operand; on the
other hand,
o D = 0 indicates that the register is a source operand.
75
 Data size bit (W) defines whether the operation to be performed is on 8- or 16- bit
data.
o W = 0 indicates 8-bit operation.
o W = 1 specifies 16-bit operation.
 The second byte of the instruction usually identifies whether one of the operands is in
the memory or the registers; this byte contains three fields.
o The Mode (MOD) field,
o The register (REG) field,
o The Register/Memory (R/M) field.
Types of ddressing modes

Addressing mode indicates a way of locating data or operands. Depending upon the data
types used in the instruction and the memory addressing modes, any instruction may belong
to one or more addressing modes, or some instruction may not belong to any of the
addressing modes. Thus the addressing modes describe the types of operands and the way
they are accessed for executing an instruction. Here, we will present the addressing modes of
the instructions depending upon their types. According to the flow of instruction execution,
the instructions may be categorized as:
a) Sequential control flow instructions and
b) Control transfer instructions.
(a) Sequential control flow instructions

Sequential control flow instructions are the instructions, which after execution, transfer
control to the next instruction appearing immediately after it (in the sequence) in the
program. For example, the arithmetic, logical, data transfer and processor control instructions
are sequential control flow instructions. The control transfer instructions, on the other hand,
transfer control to some predefined address somehow specified in the instruction after their
execution. For example, INT, CALL, RET and JUMP instructions fall under this category.
The addressing modes for sequential control transfer instructions are explained as follows:
1. IMMEDIATE
In this type of addressing, immediate data is a part of instruction, and appears in the form of
successive byte or bytes.
Example 1: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit or 16-
bit in size.
Example 2: MOV CL, 03 H

Moves the 8 bit data 03 H into CL
Example 3: MOV DX, 0525 H

Moves the 16 bit data 0525 H into DX
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In the above examples, the source operand is in immediate mode and the destination operand
is in register mode.
2. DIRECT
In the direct addressing mode, a 16-bit memory address (offset) is directly specified in the
instruction as a part of it.
Example: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address may be
computed using 5000H as the offset address and content of DS as segment address. The
effective address, here, is 10H*DS+5000H.
The instruction Opcode is followed by an affective address, this effective address is directly
used as the 16 bit offset of the storage location of the operand from the location specified by
the current value in the selected segment register.
The default segment is always DS.

The 20 bit physical address of the operand in memory is normally obtained as
PA = DS : EA
But by using a segment override prefix (SOP) in the instruction, any of the four segment
registers can be referenced,
The Execution Unit (EU) has direct access to all registers and data for register and immediate
operands. However the EU cannot directly access the memory operands. It must use the BIU,
in order to access memory operands. In the direct addressing mode, the 16 bit effective
address (EA) is taken directly from the displacement field of the instruction.
Example 1: MOV CX, START:

If the 16 bit value assigned to the offset START by the programmer using an assembler
pseudo instruction such as DW is 0040 and [DS] = 3050. Then BIU generates the 20 bit
physical address 30540 H. The content of 30540 is moved to CL the content of 30541 is
moved to CH
Example 2: MOV CH, START
If [DS] = 3050 and START = 00408 bit content of memory location 30540 is moved to CH.
Example 3: MOV START, BX

With [DS] = 3050, the value of START is 0040.Physical address: 30540
MOV instruction moves (BL) and (BH) to locations 30540 and 30541 respectively.
3. REGISTER:
In register addressing mode, the data is stored in a register and it is referred using the
particular register. All the registers, except IP, may be used in this mode.
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The operand to be accessed is specified as residing in an internal register of 8086. Fig. below
shows internal registers, anyone can be used as a source or destination operand, however only
the data registers can be accessed as either a byte or word.
Example 1: MOV DX (Destination Register), CX (Source Register) which moves 16 bit

content of CS into DX.
Example 2: MOV CL, DL

Moves 8 bit contents of DL into CL
MOV BX, CH is an illegal instruction
* The register sizes must be the same.
4. REGISTER INDIRECT
Sometimes, the address of the memory location, which contains data or operand, is
determined in an indirect way, using the offset registers. This mode of addressing is known as
register indirect mode. In this addressing mode, the offset address of data is in either BX or
SI or DI registers. The default segment is either DS or ES. The data is supposed to be
available at the address pointed to by the content of any of the above registers in the default
data segment.
Example: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset address is in BX. The effective
address of the data is given as 10H*DS+ [BX]. The EA is specified in either pointer (BX)
register or an index (SI or DI) register. The 20 bit physical address is computed using DS and
EA.
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Example: MOV [DI], BX
If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.

The content of BX (2456) is moved to memory locations 50060 H and 50061 H.
5. INDEXED
In this addressing mode, offset of the operand is stored in one of the index registers. DS and
ES are the default segments for index registers SI and DI respectively. This mode is a special
case of the above discussed register indirect addressing mode.
Example: MOV AX, [SI]
Here, data is available at an offset address stored in SI in DS. The effective address, in this
case, is computed as 10H*DS+ [SI].
Example: MOV BH, START [SI]

PA: [SART] + [SI] + [DS]
The content of this memory is moved into BH.
6. REGISTER RELATIVE:
In this addressing mode, the data is available at an effective address formed by adding an 8-
bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in
the default (either DS or ES) segment. The example given before explains this mode.
Example: MOV Ax, 50H [BX]

Here, effective address is given as 10H*DS+50H+ [BX].
7. BASED INDEXED:
The effective address of data is formed, in this addressing mode, by adding content of a base
register (any one of BX or BP) to the content of an index register (any one of SI or DI). The
default segment register may be ES or DS.
Example: MOV AX, [BX] [SI]
Here, BX is the base register and SI is the index register. The effective address is computed
as 10H*DS+ [BX] + [SI].
8. RELATIVE BASED INDEXED:

79
The effective address is formed by adding an 8-bit or 16-bit displacement with the sum of
contents of any one of the bases registers (BX or BP) and any one of the index registers, in a
default segment.
Example: MOV AX, 50H [BX] [SI]
Here, 50H is an immediate displacement, BX is a base register and SI is an index register.

The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H.
(b) Control transfer instructions

For the control transfer instructions, the addressing modes depend upon whether the
destination location is within the same segment or a different one. It also depends upon the
method of passing the destination address to the processor. Basically, there are two
addressing modes for the control transfer instructions, viz. inter-segment and intra-segment
addressing modes
If the location to which the control is to be transferred lies in a different segment other than
the current one, the mode is called inter-segment mode. If the destination location lies in the
same segment, the mode is called intra-segment.
1. INTRA-SEGMENT DIRECT MODE
In this mode, the address to which the control is to be transferred lies in the same segment in
which the control transfers instruction lies and appears directly in the instruction as an
immediate displacement value. In this addressing mode, the displacement is computed
relative to the content of the instruction pointer IP.
The effective address to which the control will be transferred is given by the sum of 8 or 16
bit displacement and current content of IP. In case of jump instruction, if the signed
displacement (d) is of 8 bits (i.e. –128 <d</d16 bits (i.e. –32768<+32768), it is termed as
long jump.
80
2. INTRA-SEGMENT INDIRECT MODE:
In this mode, the displacement to which the control is to be transferred is in the same segment
in which the control transfer instruction lies, but it is passed to the instruction indirectly.
Here, the branch address is found as the content of a register or a memory location. This
addressing mode may be used in unconditional branch instructions.
3. INTER-SEGMENT DIRECT MODE: In this mode, the address to which the control is
to be transferred is in a different segment. This addressing mode provides a means of
branching from one code segment to another code segment. Here, the CS and IP of the
destination address are specified directly in the instruction.
4. INTER-SEGMENT INDIRECT MODE: In this mode, the address to which the control
is to be transferred lies in a different segment and it is passed to the instruction indirectly, i.e.
contents of a memory block containing four bytes, i.e. IP (LSB), IP (MSB), CS (LSB) and CS
(MSB) sequentially. The starting address of the memory block may be referred using any of
the addressing modes, except immediate mode.
10.2.3 Instruction Sets for 8086/8088 microprocessor
The 8086/8088 microprocessor supports 8 types of instructions −
 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions
Let us now discuss these instruction sets in detail.
1. Data Transfer Instructions
These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −
Instruction to transfer a word
 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
 XCHG − Used to exchange the data from two locations.
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 XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.
Following is the list of instructions under this group −
Instructions to perform addition
 ADD − Used to add the provided byte to byte/word to word.

 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
Instruction to perform multiplication
 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.
Instructions to perform division
 DIV − Used to divide the unsigned word by byte or unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
82
 AAD − Used to adjust ASCII codes after division.

 CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower
byte.
 CWD − Used to fill the upper word of the double word with the sign bit of the lower
word.
3. Bit Manipulation Instructions
These instructions are used to perform operations where data bits are involved, i.e. operations
like logical, shift, etc.
Instructions to perform logical operation
 NOT − Used to invert each bit of a byte or word.

 AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with
the corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.
Instructions to perform shift operations
 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into
the new MSB.
Instructions to perform rotate operations
 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to
Carry Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to
Carry Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to
LSB.
4. String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.
 REP − Used to repeat the given instruction till CX ≠ 0.

 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
83
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF

= 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the
provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in
AL or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into
AX.
5. Program Execution Transfer Instructions (Branch and Loop Instructions)
These instructions are used to transfer/branch the instructions during an execution. It includes
the following instructions −
Instructions to transfer the instruction during an execution without any condition −
 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
 JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1
6. Processor Control Instructions
These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −

84
 STC − Used to set carry flag CF to 1

 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
7. Iteration Control Instructions
These instructions are used to execute the given instructions for number of times. Following
is the list of instructions under this group −
 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX
=0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 &
CX = 0
 JCXZ − Used to jump to the provided address if CX = 0
8. Interrupt Instructions
These instructions are used to call the interrupt during program execution.
 INT − Used to interrupt the program during execution and calling service specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program

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KENYATTA UNIVERSITY

DIGITAL SCHOOL OF VIRTUAL AND OPEN LEARNING

SCHOOL OF PURE AND APPLIED SCIENCES

SPH 434: MICROPROCESSOR APPLICATIONS I

A computer manipulates information in digital or more precisely, binary form. A binary

MICROPROCESSOR AND APPLICATION 1 FLOW CHART

Week 2: History of Microprocessors

Week 3: Overview and Architecture of Microprocessors

Week 4: Microprocessor-based systems

Week 5: Intel 8085 architecture

Week 6: Intel 8085 Microcomputer Organization

Week 7 Intel 8085Assembly Language and Machine Language programming

Week 8: Intel 8086/8088 architecture

Week 9: Intel 8086/8088 Microcomputer Organization

Week 11&12: Examination

o If you have problems accessing or logging into the system (LMS):

1. Go to the Student Help Desk -https://support.ku.ac.ke/

2. Chat with us at http://chat.ku.ac.ke/

3. Call the Digital school offices at (See our Contacts here)-

4. Guides about how to use Moodle are available athttp://www.ku.ac.ke/dsvol/students-

5. Also use our social media huddles:

3. Module Learning Outcomes

Continuous assessment Tests 30%

 A brief history of computers, from ENIAC to modern computers

1.2 Lesson Learning Outcomes

By the end of the lesson, you will be able to:

 Understand events that led to the development of the microprocessors

1.2.1 History of Microprocessors

It is a programmable, multipurpose, clock -driven, register-based electronic device that reads

Block Diagram of a Microcomputer

Table:1-1 Important Intel Microprocessors

Microprocessor Year of Word Memory Pins Clock Remarks

 PGA - Pin Grid Array

Basic Terms used in Microprocessor

Here is a list of some basic terms used in microprocessor:

Bandwidth - The number of bits processed in a single instruction is called Bandwidth.

2.2 Lesson Learning Outcomes

2.2.1 Von Neumann Architecture

Fig. 2.1 typical microprocessor layout

Von Neumann is a very successful architecture, but it has its problems.

 SISD (Singe-Instruction stream, Singe-Data stream):- SISD corresponds to the

Types of parallel processing schemes

Type Class of computers Application

Multi-Core Multiple Instruction Super computers, modern

Advantages of parallel processing over the Von Neumann architecture

Fig 2.2 Pipelining scheme

Fig 2.3 Pipelining cycle

2 Array/Vector processing scheme

Fig. 2.4 Array or Vector processing scheme

3 Multiple Processor Schemes

Fig 2.5 Multiple processor schemes

Limitations of multi-core processing:

3.2 Lesson Learning Outcomes

3.2.1 Difference between Microprocessor and Microcontroller

Fig.3.1: (a) A Microprocessor and (b) a Microcontroller

How does a Microprocessor Work?

Terms Used in a Microprocessor

Here is a list of some of the frequently used terms in a microprocessor −

Salient features of a Microprocessor

Here is a list of some of the most prominent features of any microprocessor −

A microprocessor can be classified into three categories −

Some of the RISC processors are −

 Power PC: 601, 604, 615, 620