LABORATORY REPORT BERANANG 43700 BERANANG ‘SELANGOR DARUL EHSAN DPP B20) MARA JAPAN INDUSTRIAL INSTITUTE LOT 2333, JALAN KAJANG-SEREMBAN Jso2 COURSE/CLASS : | DIPLOMA IN ELECTRONICS ENGINEERING. SESSION : APa-Augus 303) | SEMESTER ]3 ; | OFV21113/ELECTRONIC “| Cope/suBJecT:; | DEVat1N SHEET NO: | us 02 NO OF STUDENTS :|F sy -a4q— cera WEEK: DURATION : 3 hour Electronic Devices Lab LECTURER : Maver ncamara TOPI POWER SUPPLIES (VOLTAGE REGULATOR) SUB-TOPIC : VOLTAGE REGULATOR CIRCUIT At the end of the lesson, students should be able to LEARNING | 1. Measure the de output voltages of resistor load OUTCOME : 2. Study the performance of simple series regulator, shunt voltage regulator and IC regulator. INSTRUMENTS : 1. Digital Multimeter 2. Edibon Development Module (M15) TOOLS / 3. Edibon Power Supply Module (M5) EQUIPMENTS/ | COMPONENTS : MATERIALS : 1. 2N3904 - 2 2. 1N5327 8.2 V— Zener diode - 2 3. Resistor 1k0 - 2 4. Resistor 3,3kQ - 2OPP B2(c) PROCEDURE STEP KEY POINT PART 4: 1. Calculate the output voltage and zener current in Figure Series Voltage 1 for input voltage, Vs = 4V, BV, 8V, 10V and 12V regulator. 2. Simulate circuit in Figure 1 using MULTISIM software. 3. Assemble circuit as Figure 1. 4. Vary Vs, measure and record the output voltage Vo in table 1. Qa “Fr “ls |! + $ s f00 | . 5 3.3kQ eR Vs = 1kQ Vo Ve | - , 8V 7 Figure 1.1 RESULT (PART 1) av | ev | BV] tov | 12v ,, | Vo Calculated ( y 3.23] 5. | FB 43 alle | Ealeulated (A) O | 0 [Oo _ |572-5Hyt-FXm Vo Simulated (v)| 3-1 | 5:14 Bos 7.18 | #3 7 Simulated (A) An | 0 [SH | MBA Lem! Vo Measured Iz Measured TABLE 4 Page 2 of 5DPP B2(c) STEP KEY POINT PART 2: 1. Calculate the output voltage and transistor current in ‘Shunt voltage Figure 2 for input voltage, Vs = 4V, 6V, 8V, 10V and 12V tegulator 2. Simulate circuit in Figure 2 using MULTISIM software. circuit. 3. Assemble circuit as Figure 2. 4. Vary Vs, measure and record the output voltage Vo in table 2. | Figure 2 RESULT (PART 2) V. ~T av] ev] ev [ tov | fav Vo Caleulatey y)| 3:04 Evol buy] % 67] 2-4 | Iccalculated(mA) oO | 0 | O 10 lows Vo Simulated v | 3.04] ¢- uy] 6-1¥] F-44| yas} Ic Simulated (hk) -Udun|-@ yO 0 |482-ou Vo Measured Ic Measured Table 2 Page 3 of 5PSF CRI a Smacom [Eo Je (25 : 3 Vins y peed Pd BIA Mota meN HWssAw IS B.3 2 25-44298A 204.4k [Age @rt IE = S-31 wn Vo: Tex RU= 5-214Gy erRe=t {eo\v rma R: 10° 0 a & vin fio a - 5) Vin = 1av Wore Vo -VRE Vout = VreVee 2+3 23:3 Mae irs-Ls Pacts-le Tys= 10-8 = 0blm BHk Tes = 1-8 wy o1mA Bk Te 73mA 7 Xe ges De. Shmik _ i. lie te. atm. aeons Oe er et a3 SWA B =o 2 ANVBSmA “Hae 593-50A t| Biayammap nae BA arctlancd HIE6Ar~ |Fey-319- chip SHIR UNA ED 9s @) Rat 2 | ' | Vin = AW avin bu 2)_vn= Sv | oz a ‘ Vo= Rt Nor 32k y ¢ Lest ee Rstpe Yak = 3.3k = 33k = 61d | 44k Gak Tes O = 3-0Fy) =U b0v le: Ic=0 | Dvn = lv Five? vo= Woz Va + VRE u a oF =. 3% To=8-7= 9-LAmk | yak 3 | =. Is=Vin-\2-Vae Ie=!8-lo Ic 20 Rs = B-bomA + = 33 Ve = 4.bmkM, e DPP B2%c) DISCUSSION = 1. Sketch output voltage, Vo against input voltage, Vs for part 1 and part 2 vow) NOW)” Rave 5 Poe ope were tem Zw rege oO LVS Via VIC Discuss your finding in Part 1 and Part 2 (pee fart, tle output voltoge 1¢ mointouned by 2eney wltge Phate why ue can fing VO by V2~Vew. Part 2 tle zeney Sede will not funchon if te mput is Intutficidne Compare the data using the values obtain in Part 1 and Part 2. Comment the regulation behavior for each circuit, the Senes voltge vegulotey has beHey volige tRulotey sind Shunt veulatyy has poow valige a constant CONCLUSION 1) ewe cones linev reulatov SY lagh tevel per formang, 2) Shunt yulatev uve A congren yo! AFCOSS And Matto, ne Vlite arrose progese by Mointory Ane load,:| @ Multimeter-X.. Xf ® Multimeter-X.. x@ Multimeter-X. XX Multimeter-X.. Xf[rome F S&S PRACTICAL MARKING SCHEME (A1) [PROGRATARE [DPLOWA W ELEGTRONG ENGNEERING (ORE XE DRNDRRDRS) lcourse: DRTC forvai113 ELECTRONS DEVICES HOURS. IRetaTED cLo> [CLO2: Dispiay oslo conduct egariment on Aron Uevces crea Pap TWecwrace “| [STUDENT NAME: muraminn 0 Aa 87% meAmeoo FAK [Sem7 session = 20% ‘SECTION A: CRITICAL ASSESSMENT Mark V for type of crea Hen tobe assessed are = VES Tow ‘.Funetionat | 2. Accuracy 3. Finishing “asi S.enaurance | 6.Satery fark = NO W nt Tao | | YES NO. | 1 Section A marks ALL the ertieal tems are marked (J) in Section A ccle 1.0 [NO erica tems are being assessed in Secion A, cle 10 [WAN othe erica tome is marke (X) in Seetion ce ino oe ‘SECTION B: WORKING PROCESS ASESSMENT [90% @ 100%] Factor] Obtain | Obtain IP | Basie mark | Mark WORK PROCESS BOW] PORNO 1 frates iy Able to read and interpret etecroiccveut thigh components bu hl socardng We CATS i Able to red and interpret electronic crew ght components which occupy to specication, 060 Gateutate parameter valve [t-Nt abe fo doe ane fy Able to caluate and apphingTomuloe Theorem ba al coneTeS fin Abie ocala and applying forruise! tear to prot Wissen Spaced WS Dat cect 2 70 [Able to eluate and applying Trmulae” tere To road earical ‘Sipete vlie Sorely ane [circuit constrocton = Abo fo mount the componenia bul wrong connec, shea] spa B the. components and bu ol ofing Wo speciealoy [i)_ Abie to meunt te components propery actor to spsifcalcn Ale io mount he components propery acorang to specicalin and eaas To neues OR fouput 120 .o2-p a2 [Skls of anding Instrument Tools Poor to hand ons equipment Abs to handle fools equipment Corocy wth guidance i) Ae to use tos! equpment and equpment correctly without pulance TOT THOT 23 Poco apy measurement method [2 Able apply measurement method corecly with guidance eg: wagon paralay Gavan Ur ) |W) Able o apy measurement method coreety wihoa gudance 140 24 [citcuit functionality & Troubleshooting [}_Gteus completely not operate tinction [ar of he creut s nol functioning and not able To Go ToubIaRGOH iy Pan of he eet isnot fancboring bu able to do Troubleshooting fatng equipment and ea 0 bleshooing wih igh eating SqupmenT IM Ciel uncon ncrding to the wpeclicalons