Microprocessors & Microcontrollers

By A.Susmitha

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UNIT-1
•ARCHITECTURE AND PROGRAMMING OF 8085 MICROPROCESSOR
• Architecture of 8085 Microprocessor
• Functional Block Diagram – Registers, ALU, Bus systems,

• Timing and control signals, Machine cycles and timing diagrams.

• Programming of 8085 Instruction formats,
• Addressing modes,

• Instruction set,
• Need for Assembly language
• Development of Assembly language programs
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Features of 8085
• It is a 8-bit, NMOS microprocessor.
• It is a 40 pin IC fabricated on a single LSI chip.
• It operates on +5V dc supply.
• Its clock speed is about 3 MHz, the clock cycle is of 320ns.
• It has 80 basic instructions and 246 opcodes.
• It consists of three main sections: ALU, a timing and control unit and a set of
registers.
• 8 bit data bus.
• Address bus is of 16-bit, which can address up to 64KB
• 16-bit stack pointer
• 16 bit PC (Program Counter)
• Six 8-bit registers are arranged in pairs :BC, DE, HL
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Microprocessor
• The microprocessor follows a sequence to execute the instruction: Fetch, Decode, and then Execute.

• Initially, the instructions are stored in the storage memory of the computer in sequential order.

• The microprocessor fetches those instructions from the stored area (memory), then decodes it and executes
those instructions till STOP instruction is met. Then, it sends the result in binary form to the output port.
Between these processes, the register stores the temporary data and ALU (Arithmetic and Logic Unit)
performs the computing functions.

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ARCHITECTURE

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Architecture
• The Arithmetic and Logic Unit, ALU performs the arithmetic and logical
operations:
• Addition
• Subtraction
• Logical AND
• Logical OR
• Logical EXCLUSIVE OR
• Complement (Logical NOT)
• Increment (add 1)
• Decrement (subtract 1)
• Left shift, Rotate left, Rotate right
• Clear, etc.

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Timing and Control Unit
• The timing and control unit is the section of the CPU.
• It is used to generate timing and control signals which are necessary for the
execution of instructions.
• It is used to control data flow between CPU and peripherals (including
memory).
• It is used to provide status, control and timing signals which are required for
the operation of memory and I/O devices.
• It is used to control the entire operations of the microprocessor and
peripherals connected to it.

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Registers
• These are used by microprocessor for temporary storage and
manipulation of data and instructions. 8085 contains following registers.
• One 8 bit accumulator i.e. register A
• Six 8 bit general purpose registers . These are B,C,D,E,H and L
• One 16 bit stack pointer.
• One 16 bit program counter.
• Instruction Register.
• Temporary Register.
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Accumulator
• Accumulator is a 8 bit register associated with ALU.
• It is used to hold one of the operands of an arithmetic and logic operation.
• The other operand for the arithmetic operation may be stored in the memory
location or any of the general purpose register.
• The accumulator is connected to the internal data bus and the ALU.
• The outcome of the operations carried out by the Arithmetic and Logical unit ( ALU )
is stored into the accumulator. The processed data is then transferred to the RAM
• The final result is stored in the accumulator (except for single operand instruction
or DAD rp instruction)

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General Purpose Registers
• The 8085 contains six 8-bit general purpose registers: B,C,D,E,H,L

• To hold 16 bit data a combination of two 8-bit registers is employed.

• The combination of two registers is called register pair.

• The valid register pairs are B-C, D-E, H-L. The programmer cannot form a register
pair of his own choice.

• The H-L pair is used to act as memory pointer so it holds the address of the 16 bit
memory location.

• The general purpose registers and accumulator are accessible to programmer.

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Program Counter
• Program Counter is a 16 bit special register.

• It is used to hold the memory address of the next instruction to be

executed.

• It keep tracks of the memory addresses of the instructions in a program

while they are executed.

• The microprocessor increments the content of the program counter during

the execution of the instruction so that it points to the address of the next
instruction to be executed.
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Stack Pointer
• Stack is a sequence of memory locations set aside by the programmer to store/retrieve the
contents of accumulator, general purpose registers, flags, program counter.

• During the execution of the program sometimes it becomes necessary to save the contents of
registers which are needed for some other subsequent steps of the program.

• The contents of such registers are saved in the stack.

• After completing the needed operations the contents are saved back to the registers.

• Stack Pointer is a special purpose 16 bit register that stores the address of the top element of the
stack.

• The stack is defined and the stack pointer is initialized by the programmer at the beginning of the
program that needs stack.

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Instruction and Temporary Register
• Instruction Register holds the opcode (operation code) of the instruction
which is being decoded and executed.

• Temporary Register: It is an 8 bit register associated to ALU.

• It holds data during an arithmetic or logic unit.
• It is used by the microprocessor and not accessible by the programmer.

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Flag Register
• The main function of the flag register is to indicate the status of the processor after the ALU operation. The
Flag register is also alternately referred to as program status word (PSW ).
• A flag register is a 8 bit special purpose register used in 8085 architecture to indicate the CPU status after each
arithmetic and logical operation.

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Status Flags
• Intel 8085 consists of five flip-flops to serve as status flags. The flip-flops are set or reset according to the
conditions which arise during an arithmetic or logical operation. If a flip-flop for a particular flag is set, it
indicates 1. When it is reset, it indicates 0.

• Carry Status Flag (CS): If in the result of the arithmetic operation carry is produced then this flag is set to 1
otherwise it is set to 0.

• Parity Flag (P): If the result of the arithmetic or logical operation contains even number of one then this
flag is set to 1 otherwise it is set to zero.

• Auxiliary Carry Flag (AC): It holds carry out of the bit number 3 to bit number 4 resulting out of the
arithmetic operation.

• Zero Flag (Z): If the result of the arithmetic and logical operation is zero, then it is set to 1, otherwise it is
set to 0.

• Sign Flag (S): If the result of the arithmetic operation is negative then it is set to 1, otherwise 0.
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Data and Address Bus
• Intel 8085 has 8 bit data bus. So 8 bits can be transferred in parallel from or
to the microprocessor.

• It requires 16 bits wide address bus to address 64 K of memory locations.

• The 8 most significant bits of the address are transmitted by the Address bus
(A8 to A15).

• The 8 least significant bits of address are transferred through address/data

bus (AD0 –AD7).

• The AD bus works in time shared mode. This process is called multiplexing.
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Program Status Word (PSW)
• The combination of five status bits and three undefined bits is called
Program Status Word.

• PSW and accumulator are treated as 16 bit unit for stack operation.

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Interrupt control
• As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt
occurs, the microprocessor shifts the control from the main program to
process the incoming request.

• After the request is completed, the control goes back to the main program.

• There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5,
RST 5.5, TRAP.

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PIN CONFIGURATION

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1. Address Bus and Data Bus:
The address bus is a group of sixteen lines i.e A0-A15. The address bus is unidirectional, i.e., bits
flow in one direction from the microprocessor unit to the peripheral devices and uses the high
order address bus.

2. Control and Status Signals:

•ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine cycle and
enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.
IO/MI – It is a status signal which determines whether the address is for input-output or memory.
When it is high(1) the address on the address bus is for input-output devices. When it is low(0) the
address on the address bus is for the memory.
•SO, S1 – These are status signals. They distinguish the various types of operations such as halt,
reading, instruction fetching or writing.

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 I Data Bus
IO/M S1 S0
Status

0 1 1 Opcode fetch

0 1 0 Memory read

0 0 1 Memory write

1 1 0 I/O read
1 0 1 I/O write
Interrupt
1 1 1
acknowledge
0 0 0 Halt

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• RDI– It is a signal to control READ operation. When it is low the selected
memory or input-output device is read.

• WRI – It is a signal to control WRITE operation. When it goes low the

data on the data bus is written into the selected memory or I/O location.

• READY – It senses whether a peripheral is ready to transfer data or not.

If READY is high(1) the peripheral is ready. If it is low(0) the
microprocessor waits till it goes high. It is useful for interfacing low
speed devices.

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3. Power Supply and Clock Frequency:

•Vcc – +5v power supply

•Vss – Ground Reference

•XI, X2 – A crystal is connected at these two pins. The frequency is

internally divided by two, therefore, to operate a system at 3MHZ
the crystal should have frequency of 6MHZ.
•CLK (OUT) – This signal can be used as the system clock for other
devices.

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4. Interrupts and Peripheral Initiated Signals:
The 8085 has five interrupt signals that can be used to interrupt a program
execution.
(i) INTR
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP
The microprocessor acknowledges Interrupt Request by INTAI signal. In addition to
Interrupts, there are three externally initiated signals namely RESET, HOLD and
READY. To respond to HOLD request, it has one signal called HLDA.

•INTR – It is an interrupt request signal.

• INTAI– It is an interrupt acknowledgement sent by the microprocessor after INTR
is received.

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5. Reset Signals:

• RESET INI– When the signal on this pin is low(0), the program-counter is set to
zero, the buses are tristate and the microprocessor unit is reset.
• RESET OUT – This signal indicates that the MPU is being reset. The signal can
be used to reset other devices.

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6. DMA Signals:

•HOLD – It indicates that another device is requesting the use of the address and data
bus. Having received HOLD request the microprocessor relinquishes the use of the
buses as soon as the current machine cycle is completed. Internal processing may
continue. After the removal of the HOLD signal the processor regains the bus.

•HLDA – It is a signal which indicates that the hold request has been received after the
removal of a HOLD request, the HLDA goes low

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7. Serial I/O Ports:
Serial transmission in 8085 is implemented by the two signals,

•SID and SOD – SID is a data line for serial input where as SOD is a data
line for serial output.

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 Bus Structure in 8085
There are three buses in Microprocessor:

1.Address Bus
2.Data Bus
3.Control Bus

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 Bus Structure

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 1.Address Bus

▪ Generally, Microprocessor has 16 bit address bus. The bus over which the
CPU sends out the address of the memory location is known as Address bus.
▪ The address bus carries the address of memory location to be written or to be
read from.
The address bus is unidirectional. It means bits flowing occurs only in one
direction, only from microprocessor to peripheral devices.
▪ We can find that how much memory location it can using the formula 2^N.
where N is the number of bits used for address lines.

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Q.>If a processor has 4 GB memory then how
many address lines are required to access this
memory?

Ans:
4GB= 4 * 1GB
4 = 2^2
1GB = 2^30
4GB = 2^2 * 2^30 = 2^32
So 32 address lines are required to access the
4 GB memory.
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 2. Data Bus

▪ 8085 Microprocessor has 8 bit data bus. So it can be used to

carry the 8 bit data starting from 00000000H(00H) to
11111111H(FFH). Here 'H' tells the Hexadecimal Number.
▪ It is bidirectional. These lines are used for data flowing in
both direction means data can be transferred or can be
received through these lines. The data bus also connects the
I/O ports and CPU. The largest number that can appear on
the data bus is 11111111.
It has 8 parallel lines of data bus. So it can access up to 2^8
= 256 data bus lines.

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 3. Control Bus
1.The control bus is used for sending control signals to the memory and
I/O devices. The CPU sends control signal on the control bus to enable
the outputs of addressed memory devices or I/O port devices.
Some of the control bus signals are as follows:
1.Memory read
2.Memory write
3.I/O read
4.I/O write

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 Addressing Modes

The way of specifying data to be operated by an instruction is called addressing

mode.
Types of addressing modes –
In 8085 microprocessor there are 5 types of addressing modes:

1. Immediate Addressing Mode

2. Register Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Implied/Implicit Addressing Mode

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1. Immediate Addressing Mode –

In immediate addressing mode the source operand is always data. If the data is 8-bit,
then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will
be of 3 bytes.
Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)

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2. Register Addressing Mode –

In register addressing mode, the data to be operated is available inside the

register(s) and register(s) is(are) operands. Therefore the operation is performed
within various registers of the microprocessor.

Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)

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3. Direct Addressing Mode –

In direct addressing mode, the data to be operated is available inside a memory

location and that memory location is directly specified as an operand. The operand
is directly available in the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)

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4. Direct Addressing Mode –

In register indirect addressing mode, the data to be operated is available inside a memory
location and that memory location is indirectly specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contents of B-C register to the accumulator)
LXIH 9570 (load immediate the H-L pair with the address of the location 9570)

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5. Implied/Implicit Addressing Mode –

In implied/implicit addressing mode the operand is hidden and the data to be

operated is available in the instruction itself.

Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)

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 Grouping of Instructions of 8085 according
to Length

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 T-States and Machine Cycles of 8085

• The time needed for completing one operation of accessing memory, I/O or
acknowledging an external request is termed as Machine cycle. It is
comprised of T-states.
• One subdivision of the operation completed in one clock period is termed as
T-state.
The following are the various machine cycles of 8085 microprocessor.

1. Opcode Fetch (OF)

2. Memory Read (MR)
3. Memory Write (MW)
4. I/O Read (IOR)
5. I/O Write (IOW)
6. Interrupt Acknowledge (IA)
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Bus Idle (BI) 44
 All instructions have at least one Opcode Fetch machine cycle. Depending on the
type of instruction one or more other machine cycles are required to complete the
execution of the instruction.
The number and type of machine cycles for different instructions are shown in
table.
S No Instruction No: of Machine Machine Machine Machine
machine cycle - 1 cycle - 2 cycle - 3 cycle - 4
cycles
1 MOV A,B 1 OF - - -
2 MVI A, 50H 2 OF MR - -
3 LDA 5000H 4 OF MR MR MR
4 STA 5000H 4 OF MR MR MW
5 IN 80H 3 OF MR IOR -
6 OUT 80H 3 OF MR IOW -

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1. Opcode Fetch (OF) machine cycle of 8085:

▪ Each instruction of the microprocessor has one byte Opcode. The Opcode is stored
in memory.
▪ In order to fetch the Opcode from memory, processor executes the Opcode Fetch
machine cycle. So, every instruction starts with Opcode Fetch machine (OFM)
cycle. The time taken by the microprocessor to execute the Opcode Fetch cycle is
4T (T- states).
▪ In order to fetch the Opcode from memory, the first 3 T-states are used. The
remaining T-state is used for internal operations by the microprocessor.

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State T1 -
• PC Content to Address Bus
• ALE IS Activated ( to store the lower order byte of the address in external latch before it disappears)
• Sends Status Signals : IO/ M1 = 0, S1 = 1, S0 = 1. (OPCODE FETCH)

State T2 –
• Lower Order Address disappears from AD0 – AD7
• Send Read Signal to the contents of memory location
• Memory device places Contents of addressed memory location on AD0 – AD7

State T3 –
• 8085 loads the data from the data bus in its Instruction Register
• Raises RD to high which disables the memory device

State T4-
Decodes the opcode, and on the basis of the instruction received, it decides whether to enter state T5 or
to enter state T1 of the next Machine Cycle of 8085 Microprocessor.

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2. Memory Read (MR) Machine Cycle of 8085:

• Single byte instructions require only Opcode Fetch machine cycles.

• But, 2-byte and 3-byte instructions require additional machine cycles to read the
operands from memory.
• The additional machine cycle is called Memory Read machine cycle.
• For example, the instruction MVI A, 50H requires one OF machine cycle to fetch
the operand from memory and one MR machine cycle to read the operand (50H)
from memory.
• The MR machine cycle takes 3 T-states.

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State T1 -
• PC or SP or RP Content to Address Bus
• ALE IS Activated ( to store the lower order byte of the address in external latch
before it disappears)
• Sends Status Signals : IO/ M1 = 0, S1 = 1, S0 = 0. (MEMORY READ)

State T2 –
• Lower Order Address disappears from AD0 – AD7
• Send Read Signal to the contents of memory location
• Memory device places Contents of addressed memory location on AD0 – AD7

State T3 –
• 8085 loads the data from the data bus into Specified Register (F,A,B,C,D,E,H &L)
• Raises RD to high which disables the memory device

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 3. Memory Write(MW) Machine Cycle of 8085:

• The 8085 executes the memory write cycle to store the data into data
memory or stack memory.
• The length of this machine cycle is 3T states. (T1 – T3).
• In this Machine Cycle of 8085 Microprocessor, processor places the
address on the address lines from the stack pointer or general purpose
register pair and through the write process, stores the data into the
addressed memory location.
• The memory write timing diagram is similar to the memory read timing
diagram, except that instead of RD, WR signal goes low during T2 and
T3. The status signals for memory write cycle are : IO/ M1 = 0, S1 = 0,
S0 = 1.
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3/15/2022 53
 State T1 -
• SP or RP or PC Content to Address Bus
• ALE IS Activated ( to store the lower order byte of the address in
external latch before it disappears)
• Sends Status Signals : IO/ M1 = 0, S1 = 1, S0 = 0. (MEMORY READ)

State T2 –
• Lower Order Address disappears from AD0 – AD7
• Send WRITE Signal for writing into addressed memory location
• Memory device places Contents of addressed memory location on
AD0 – AD7

State T3 –
• Raises WR to high which disables the memory device and terminates
write operation.
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 4. I/O Read (IOR)Machine Cycle of 8085

• The I/O read machine cycle is similar to the memory read machine
cycle, except that the 10/ M1 signal is high for I/O read machine
cycle.
• High IO/ M1 signal indicates that it is an I/O operation.
• The I/O machine cycle takes 3 T-states.

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 5. I/O Write (IOW) Machine Cycle of 8085

• The I/O write machine cycle is similar to the memory write machine
cycle, except that the 10/ M1 signal is high for I/O write machine
cycle.
• High IO/ M1 signal indicates that it is an I/O operation.
• The I/O machine cycle takes 3 T-states.

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 6. Interrupt Acknowledge (IA) Cycle of 8085

In response to INTR signal, 8085 executes interrupt acknowledge machine

cycle to read an instruction from the external device. Theoretically, the
external device can place any instruction on the data bus in response to INTA.
However, only RST and CALL, save the PC contents (return address) before
transferring control to the interrupt service routine. The next sections explain
Interrupt Acknowledge Cycle of 8085 for RST and CALL instructions.

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 7. Bus Idle(BI) Cycle of 8085 :
There are few situations where the machine cycles are neither Read nor Write.
These situations are:
1.For execution of DAD instruction (this instruction adds the contents of a specified register pair to the
contents of HL register pair) ten T states are required. This means that after execution of opcode fetch
machine cycle, DAD instruction requires 6 extra T-states to add 16 bit contents of a specified register
pair to the contents of HL register pair. These extra T-states which are divided into two machine cycles
do not involve any memory or I/O operation. These Machine Cycle in 8085 are called BUS IDLE
machine cycles.
In the case of DAD, these Bus Idle cycles are similar to memory read cycles, except RD and ALE
signals are not activated.
2.During internal opcode generations, for TRAP and RST interrupts, 8085 executes Bus Idle Machine
Cycles. Fig. 1.23 shows the Bus Idle Machine Cycle of 8085 Microprocessor for TRAP. In response to
TRAP interrupt, 8085 enters into a Bus Idle Machine Cycle during which it invokes restart instruction,
stores the contents of PC onto the stack and places 0024H (Vector address of TRAP) onto the program
counter.

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 Assignment Question 1

Draw the timing diagrams for Interrupt

Acknowledgement (IA) Cycle & Bus Idle (BI)
Cycle of 8085.

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 Instruction Set of 8085
Instruction and Data Formats
The various techniques to specify data for instructions are:
1.8-bit or 16-bit data may be directly given in the instruction itself.
2.The address of the memory location, I/O port or I/O device, where data resides,
may be given in the instruction itself.
3.In some instructions, only one register is specified. The content of the specified
register is one of the operands.
4.Some instructions specify two registers. The contents of the registers are the
required data.
5.In some instructions, data is implied. The most instructions of this type operate
on the content of the accumulator.
Due to different ways of specifying data for instructions, the machine codes of
all instructions are not of the same length. It may 1-byte, 2-byte or 3-byte
instruction.

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 Symbol/Abbreviations Meaning
Addr 16-bit address of the memory location.
Data 8-bit data
data 16 16-bit data
r, r1, r2 One of the registers A, B, C, D, E, H or L
A, B, C, D, H, L 8-bit register
A Accumulator
H-L Register pair H-L
B-C Register pair B-C
D-E Register pair D-E
PSW Program Status Word
M Memory whose address is in H-L pair
H Appearing at the end of the group of digits specifies hexadecimal, e.g. 2500H
Rp One of the register pairs.
Rh The high order register of a register pair
Rl The low order register of a register pair
PC 16 bit program counter, PCH is high order 8 bits and PCL low order 8 bits of register PC.
CS Carry Status
[] The contents of the register identified within bracket
[ [] ] The content of the memory location whose address is in the register pair identified within brackets
^ AND operation
∨ OR operation
⊕ or ∀ Exclusive OR
← Move data in the direction of arrow
⇔ 3/15/2022 Exchange contents 66
 Intel 8085 Instructions

An instruction of a computer is a command given to the computer to perform

a specified operation on given data. In microprocessor, the instruction set is
the collection of the instructions that the microprocessor is designed to
execute.
The programmer writes a program in assembly language using these
instructions. These instructions have been classified into the following groups:

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1. Data Transfer Group
Instructions which are used to transfer the data from a register to another register from memory to register or
register to memory come under this group.
Instruction Set Explanation States Flags Addressing Machine Example
Cycles
MOV r1, r2 Move the content of the 4 None Register 1 MOV A, B
[r1] ← [r2] one register to another

MOV r, M Move the content of 7 None Register Indirect 2 MOV B, M

[r]←[[H-L]] memory to register

MOV M, r Move the content of 7 None Register Indirect 2 MOV M, C

[[H-L]]←[r] register to memory

MVI r, data Move immediate data to 7 None Immediate 3 MVI B, 08

[r] ←data register Register

LXI rp, data 16 Load Register pair 10 None Immediate 3 LXI H, 2500H
[rp] ←data 16 bits, immediate
[rh] ←8 MSBs,
[rl] ←8 LSBs of data

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1. Data Transfer Group

Instruction Set Explanation States Flags Addressing Machine Cycles Example

LDA addr Load Accumulator 13 None Direct 4 LDA 2400 H
[A] ←[addr] direct

STA Addr Store accumulator direct 13 None Direct 4 STA 2000H

[addr] ←[A]

LHLD addr Load H-L pair direct 16 None Direct 5 LHLD 2500H
[L] ←[addr],
[H] ← [addr + 1 ]
SHLD addr Store H-L pair direct 16 None Direct 5 SHLD 2500 H
[addr] ←[L],
[addr +1] ← [H]

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1. Data Transfer Group

Instruction Set Explanation States Flags Addressing Machine Example

Cycles
LDAX rp Load accumulator 7 None Register 2 LDAX B
[A] ←[[rp]] indirect Indirect

STAX rp Store accumulator 7 None Register 2 STAX D

[[rp]] ←[A] indirect Indirect

XCHG Change the contents 4 None Register 1

[H-L] ↔[D-E] of H-L with D-E pair

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 Arithmetic Group

The instructions of this group perform arithmetic operations

such as addition, subtraction, increment or decrement of the
content of a register or a memory.
Instruction Set Explanation States Flags Addre-ssing Machine Cycles Example

ADD r Add register to 4 All Register 1 ADD K

[A] ←[A]+[r] accumulator

ADD M Add memory 7 All Register 2 ADD K

[A] ← [A] + to accumulator indirect
[[H-L]]
ACC r Add register 4 All Register 1 ACC K
[A] ← [A] + [r] with carry to
accumulator
+ [CS]
ADC M Add memory 7 All Register 2 ADC K
[A] ← [A] + with carry to indirect
accumulator
[[H-L]] [CS]
ADI data Add immediate 7 All Immediate 2 ADI 55K
[A] ← [A] + data to
accumulator
data
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 Instruction Set Explanation States Flags Addre-ssing Machine Cycles Example

ACI data Add with carry 7 All Immediate 2 ACI 55K

[A] ← [A] + data + immediate data
[CS] to accumulator
DAD rp Add register 10 CS Register 3 DAD K
[H-L] ←[H-L] + [rp] paid to H-L
pair
SUB r Subtract 4 All Register 1 SUB K
[A] ←[A]-[r] register from
accumulator

SUB M Subtract 7 ALL Register 2 SUB K

[A] ← [A] - [[H-L]] memory from indirect
accumulator

SBB r Subtract 7 All Register 2 SBB K

[A] ←[A]-[H-L]] - memory from indirect
[CS] accumulator
with borrow

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 Instruction Set Explanation States Flags Addressing Machine Cycles Example

SUI data Subtract 7 All Immediate 2 SUI 55K

[A] ←[A]-data immediate
data from
accumulator
SBI data Subtract 7 All Immediate 2 XCHG
[A] ←[A]-data-[CS] immediate
data from
accumulator
with borrow
INR r Increment 4 All except Register 1 INR K
[r] ←[r]+1 register carry flag
content

INR M Increment 10 All except Register 3 INR K

[[H-L]] ←[[H-L]]+1 memory carry flag indirect
content

DCR r Decrement 4 All except Register 1 DCR K

[r] ←[r] -1 register carry flag
content
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Instruction Set Explanation States Flags Addre-ssing Machine Cycles Example

DCR M Decrement 10 All except carry Register indirect 3 DCR K

[[H-L]] ← [[H-L]]-1 memory content flag

INX rp Increment 6 None Register 1 INX K

[rp] ←[rp]+1 memory content

DCX rp Decrement 6 None Register 1 DCX K

[rp] ←[rp]-1 register pair

DAA Decimal adjust 4 1 DAA

accumulator

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 2. Logical Group
The instructions in this group perform logical operation such as AND, OR, compare, rotate, etc.

Instruction Set Explanation States Flags Addressing Machine Cycles

ANA r AND register with 4 All Register 1

[A] ←[A]∧[r] accumulator

ANA M AND memory with 4 All Register indirect 2

[A] ←[A]∧[[H-]] accumulator

ANI data AND immediate data 7 All Immediate 2

[A] ← [A] ∧ with accumulator
[data]

ORA r OR-register with 4 All Register 1

[A] ←[A]∨[r] accumulator

ORA M OR-memory with 7 All Register indirect 2

[A] ←[A]∨[[H-L]] accumulator

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 Instruction Set Explanation States Flags Addressing Machine Cycles

ORI data OR -immediate 7 All Immediate 2

[A] ← [A] ∨ data with
[data] accumulator
XRA r [A] ← XOR register 4 All Register 1
[A]∀[r] with
accumulator
XRA M XOR memory 7 All Register indirect 2
[A] ← [A] ∀ with
[[H-L]] accumulator
XRI data XOR immediate 7 All Immediate 2
[A] ←[A] ∀ data with
[data] accumulator
CMA [A] ←[A] Complement the 4 None Implicit 1
accumulator

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 Instruction Set Explanation States Flags Addressing Machine Cycles

CMC Complement the 4 CS 1

[CS] ←[CS] carry status
STC Set carry status 4 CS 1
[CS] ← 1

CMP r Compare register 4 All Register 1

[A]-[r] with
accumulator
CMP M Compare 7 All Register indirect 2
[A] - [[H-L]] memory with
accumulator
CPI data Compare 7 All Immediate 2
[A] - data immediate data
with
accumulator

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 Instruction Set Explanation States Flags Addressing Machine Cycles

RLC Rotate 4 Cs Implicit 1

[An+1] ←[An], accumulator left
[A0] ←[A7], [CS]
←[A7]
RRC Rotate CS Implicit 1
[A7] ←[A0], [CS] accumulator
←[A0], [An] ← right
[An+1]
RAL Rotate CS Implicit 1
[An+1] ←[An], accumulator left
[CS] ←[A7], [A0] through carry
←[CS]
RAR Rotate CS Implicit 1
[An] ←[An+1], accumulator
[CS] ←[A0], [A7] right through
←[CS]
carry

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Branch Control Group
This group contains the instructions for conditional and unconditional jump,
subroutine call and return, and restart.
Unconditional Jump
Instruction Set Explanation States Machine Cycles
Jump addr (label) Conditional jump: jump 10, if true and 3, if true and
[PC] ← Label to the instruction 7, if not true 2, if not true
specified by the address
if the specified condition
is fulfilled

Instruction Set Explanation States Flags Addressing Machine Cycles

JMP addr(label) Unconditional 10 None Immediate 3

[PC] ← Label jump: jump to the
instruction
specified by the
address
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 Instruction Set Explanation Status States Flags Addressing Machine
Cycles
JZ addr (label) [PC] ←Jump, if the result is zero Jump if Z=1 7/10 None Immediate 2/3
address (label)
JNZ addr (label)Jump if the result is notJump if Z=0 7/10 None Immediate 2/3
[PC] ← address (label) zero
JC addr (label)Jump if there is a carry Jump if CS =1 7/10 None Immediate 2/3
[PC] ← address (label)
JNC addr (label)Jump if there is no carry Jump if CS =0 7/10 None Immediate 2/3
[PC] ← address (label)
JP addr (label)Jump if result is plus Jump if S=0 7/10 None Immediate 2/3
[PC] ← address (label)
JM addr (label)Jump if result is minus Jump if S=1 7/10 None Immediate 2/3
[PC] ← address (label)
JPE addr (label)Jump if even parity The parity status P =1 7/10 None Immediate 2/3
[PC] ← address (label)
JPO addr (label)Jump if odd parity The parity status P =0 7/10 None Immediate 2/3
[PC] ← address (label)

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 Unconditional CALL
Instruction Set Explanation States Machine Cycles
CALL addr (label) Unconditional CALL: 18, if true and 5, if true and
[SP]-1] ← [PCH] , Call the subroutine 9, if not true 2, if not true
[[SP-2] ← [PCL], [PC] identified by the address
← addr (label), [SP] ← if the specified
[SP]-2 condition is fulfilled

Conditional CALL

Instruction Set Explanation States Flags Addressing Machine

Cycles
CALL addr Unconditional 18 None Immediate 5
(label) CALL: Call the /register
[SP]-1] ← subroutine
[PCH] ,[[SP-2] identified by
← [PCL], [SP] the address
← [SP]-2, [PC]
← addr(label)
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Instruction Set Explanation Status States Flags Addressing Machine Cycles
CC addr(label) Call subroutine if CS =1 9/18 None Immediate 2/5
carry status CS=1 /register
CNC addr Call subroutine if CS =0 9/18 None Immediate 2/5
(label) carry status CS=0 /register
CZ addr (label) Call Subroutine if Zero status 9/18 None Immediate 2/5
the result is zero Z=1 /register
CNZ addr Call Subroutine if Zero status 9/18 None Immediate 2/5
(label) the result is not zero Z=0 /register

CP addr (label) Call Subroutine if Sign status 9/18 None Immediate 2/5
the result is plus S=0 /register
CM addr (label) Call Subroutine if Sign status 9/18 None Immediate 2/5
the result is minus S= 1 /register

CPE addr(label) Call subroutine if Parity 9/18 None Immediate 2/5

even parity Status P=1 /register
CPO addr(label) Call subroutine if Parity 9/18 None Immediate 2/5
odd parity Status P= 0 /register

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Unconditional Return

Instruction Set Explanation States Flags Addressing Machine

Cycles
RET Unconditional 10 None Indirect 3
[PCL] ← RET: Return
[[SP]], [PCH] from subroutine
← [[SP] + 1],
[SP] ← [SP] +
2

Conditional Return

Instruction Set Explanation States Machine Cycles

RET Conditional RET: Return 12, if true and 6, if not 3, if true and 1, if not
[PCL] ← [[SP]], from subroutine true true
[PCH] ← [[SP] + 1],
[SP] ← [SP] + 2

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Instruction Set Explanation Status States Flags Addressing Machine Cycles
RC Return from subroutine ifCS =1 6/12 None Register indirect 1/3
carry status is zero.
RNC Return from subroutine ifCS = 0 6/12 None Register indirect 1/3
carry status is not zero.
RZ Return from subroutine ifZero status6/12 None Register indirect 1/3
result is zero. Z=1
RNZ Return from subroutine ifZero status6/12 None Register indirect 1/3
result is not zero. Z= 0
RP Return from subroutine ifSign Status6/12 None Register indirect 1/3
result is not plus. S= 0
RM Return from subroutine ifSign Status6/12 None Register indirect 1/3
result is not minus. S= 0
RPE Return from subroutine ifParity Status6/12 None Register indirect 1/3
even parity. P= 1
RPO Return from subroutine ifParity Status6/12 None Register indirect 1/3
odd parity. P= 1

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 Restart
Instruction Set Explanation States Flags Addressing Machine Cycles
RST Restart is a one 12 None Register Indirect 3
[[SP]-1] ← [PCH], word CALL
[[SP]-2] ← [PCL], instruction.
[SP] ← [SP] - 2,
[PC] ← 8 times n

The restart instructions and locations are as follows

Instruction Opcode Restart Locations

RST 0 C7 0000
RST 1 CF 0008
RST 2 D7 0010
RST 3 DF 0018
RST 4 E7 0020
RST 5 EF 0028
RST 6 F7 0030
RST 7 FF 0038
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 PCHL

Instruction Explanation States Flags Addressing Machine

Set Cycles
PCHL Jump address 6 None Register 1
[PC] ← [H-L], specified by
[PCH] ← H-L pair
[H], [PCL] ←
[L]

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Stack, I/O and Machine Control Group
This group contains the instructions for input/output ports, stack and machine control.
Instruction Set Explanation States Flags Addressing Machine Cycles
IN port - addressInput to10 None Direct 3
[A] ← [Port] accumulator from
I/O port
OUT port-addressOutput from10 None Direct 3
[Port] ← [A] accumulator to I/O
port
PUSH rpPush the content of12 None Register(source)/re 3
[[SP] - 1] ← [rh],register pair to gister
[[SP] - 2] ← [rh],stack Indirect(destinatio
[SP] ← [SP] - 2 n)
PUSH PSWPush processor12 None Register(source)/re 3
[SP]-1] ← [A],word gister
[[SP] -2] ← PSW, Indirect(destinatio
[SP] ← [SP] - 2 n)
POP rpPop the content of10 None Register(source)/re 3
[rl] ← [ [ SP ] ],register pair, gister
[rh] ← [[SP]+1],which was saved, Indirect(destinatio
[SP] ← [SP] + 2 from the stack n)
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 Instruction Set Explanation States Flags Addressing Machine Cycles
HLT Halt 5 None 1
XTHL Exchange top16 None Register indirect 5
[L] ↔ [[SP]],stack with H-L
[H] ↔ [[SP] +
1]

SPHL Moves the6 None Register 1

[H-L] → [SP] contents of H-L
pair to stack
pointer
EI Enable 4 None 1
Interrupts
SIM Set Interrupts4 None 1
Masks
RIM Read Interrupts4 None 1
Masks
NOP No Operation 4 None 1

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Resources
• https://learning-microprocessors.sourceforge.io/8085-simulator.html

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